Method for forming contact structure, and its semiconductor device

Abstract

To provide a contact structure and a method for forming its semiconductor device.SOLUTION: There are disclosed a contact structure and an embodiment of a method for forming its semiconductor device. As one example, the method for forming the semiconductor device includes: forming a spacer structure in a base structure from a first surface of the base structure; forming a first contact part enclosed with the spacer structure; and forming a second contact part contacting the first contact part. The second contact extends into the base structure from a second surface of the base structure.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to methods for forming contact structures and semiconductor devices thereof. [Background technology]

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit designs, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become more difficult and costly. As a result, memory density for planar memory cells approaches an upper limit.

[0003] 3D memory architectures can address the density limitations of planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention [Means for solving the problem]

[0004] Methods for forming contact structures and semiconductor device embodiments thereof are disclosed herein.

[0005] In one example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

[0006] In another example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. The contact structure also includes a lower surface of the first contact portion in contact with an upper surface of the second contact portion at a contact interface below the upper surface of the conductive layer.

[0007] In yet another example, a method for forming a semiconductor device includes forming a spacer structure into a base structure from a first surface of the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion, the second contact portion extending into the base structure from a second surface of the base structure.

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of an existing contact structure in a semiconductor device. [Figure 2A] 1 is a cross-sectional view of an exemplary contact structure in a semiconductor device according to some embodiments of the present disclosure. [Figure 2B] 2B is a top view of the contact structure of FIG. 2A according to some embodiments of the present disclosure. [Figure 3A] 4 is a cross-sectional view of another exemplary contact structure in a semiconductor device according to some embodiments of the present disclosure. [Figure 3B] FIG. 3B is a top view of the contact structure of FIG. 3A according to some embodiments of the present disclosure. [Figure 4A] 1A-1D illustrate an exemplary fabrication process for forming a contact structure according to some embodiments of the present disclosure. [Figure 4B] 1A-1D illustrate an exemplary fabrication process for forming a contact structure according to some embodiments of the present disclosure. [Figure 4C] 1A-1D illustrate an exemplary fabrication process for forming a contact structure according to some embodiments of the present disclosure. [Figure 4D] 1A-1D illustrate an exemplary fabrication process for forming a contact structure according to some embodiments of the present disclosure. [Figure 5A] 1A-1C illustrate an exemplary fabrication process for forming another contact structure according to some embodiments of the present disclosure. [Figure 5B] 1A-1C illustrate an exemplary fabrication process for forming another contact structure according to some embodiments of the present disclosure. [Figure 5C] 1A-1C illustrate an exemplary fabrication process for forming another contact structure according to some embodiments of the present disclosure. [Figure 5D] 1A-1C illustrate an exemplary fabrication process for forming another contact structure according to some embodiments of the present disclosure. [Figure 6] 1 illustrates a portion of an exemplary semiconductor device in accordance with various embodiments of the present disclosure. [Figure 7] 4 is a flow chart of an exemplary method for forming a contact structure according to some embodiments of the present disclosure. [Figure 8] 4 is a flow chart of an exemplary method for forming another contact structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in a variety of other applications.

[0012] It should be noted that references herein to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like, indicate that the embodiment being described may include a particular feature, structure, or characteristic, but that all embodiments may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one of ordinary skill in the art to implement such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0013] Generally, terminology may be understood, at least in part, from usage in context. For example, the term "one or more" as used herein may be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, at least in part depending on the context. Similarly, terms such as "a," "an," or "the," etc., may be understood to convey singular usage or plural usage, again, at least in part depending on the context. In addition, the term "based on" may be understood not necessarily intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly recited, again, at least in part depending on the context.

[0014] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in the broadest manner, such that "on" not only means "directly on" something, but also includes meaning "on" something with an intermediate feature or layer between them, and that "above" or "over" can not only mean "above" or "over" something, but also include meaning it is "above" or "over" something (i.e., directly on) with no intermediate features or layers between them.

[0015] Additionally, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself may be patterned. Materials added onto the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0017] As used herein, the term "layer" refers to a material portion that includes a region having a predetermined thickness. A layer can extend throughout an underlying or overlying structure, or can have an extension that is less than the extension of the underlying or overlying structure. Furthermore, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between the upper and lower surfaces (or at the upper and lower surfaces) of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (with interconnect lines and / or vertical interconnect access (VIA) contacts formed therein) and one or more dielectric layers.

[0018] As used herein, the term "nominal / nominal" refers to a desired (or target) value of a characteristic or parameter for a component or process operation that is set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of interest. Based on a particular technology node, the term "about" can refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, a staircase structure refers to a set of surfaces including at least two horizontal surfaces (e.g., along the xy plane) and at least two (e.g., first and second) vertical surfaces (e.g., along the z axis), each of which is adjacent to a first vertical surface extending upward from a first edge of the horizontal surfaces and adjacent to a second vertical surface extending downward from a second edge of the horizontal surfaces. A "step" or "stair" refers to a vertical shift in height of a set of adjacent surfaces. In this disclosure, the terms "step" and "step" refer to one level of a staircase structure and are used interchangeably. In this disclosure, a horizontal direction can refer to a direction parallel to a top surface of a substrate (e.g., a substrate providing a fabrication platform for the formation of structures on the substrate) (e.g., an x-direction or a y-direction), and a vertical direction can refer to a direction perpendicular to the top surface of the structure (e.g., a z-direction).

[0020] As used herein, the term "3D NAND memory device" refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) on a substrate that is laterally oriented such that the memory strings extend perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0021] In some 3D NAND memory devices, a semiconductor plug is selectively grown to surround the sidewall of the channel structure (e.g., known as sidewall selective epitaxial growth (SEG)). Compared with another type of semiconductor plug (e.g., bottom SEG) formed at the lower end of the channel structure, the formation of sidewall SEG avoids etching of the memory film and semiconductor channel at the lower surface of the channel hole (also known as "SONO" punch), thereby increasing the process window, especially when fabricating 3D NAND memory devices with advanced technology, such as having 96 or more levels with multi-deck architecture. Moreover, the sidewall SEG structure can be combined with a backside process to form a source contact from the backside of the substrate, avoiding leakage current and parasitic capacitance between the frontside source contact and the word line, and increasing the effective device area.

[0022] Peripheral contacts (e.g., through-silicon contacts (TSVs) and the like), which are formed in peripheral regions and facilitate electrical contact between memory cells and peripheral circuits, may also be formed using backside processes in these 3D NAND memory devices. However, due to the increasing levels of 3D NAND memory devices, fabrication of peripheral contacts faces challenges. For example, forming peripheral contacts using backside processes often involves a two-step etching process (e.g., a first etching process to form a first opening above a substrate for a first contact portion, and a second etching process to form a second opening from the backside for a second contact portion). A conductive material is deposited to fill the second opening, and a dielectric spacer is often deposited in the second opening before forming the second contact portion. The two-step etching and deposition process may be undesirably long and complicated.

[0023] FIG. 1 illustrates a cross-sectional view of an existing contact structure in a semiconductor device 100. The semiconductor device 100 includes a base structure 104, an insulating structure 118 on the base structure 104, and a memory stack 106 on the base structure 104 and in the insulating structure 118. The base structure 104 includes an insulating layer 102 and a polysilicon layer 108 on the insulating layer 102. The memory stack 106 has a multi-step staircase structure and includes a plurality of interleaved conductor layers 110 and a dielectric layer 112. The semiconductor device 100 also includes a plurality of channel structures (not shown in FIG. 1 ) that extend into and are electrically connected to the polysilicon layer 108. The intersections of the channel structures and the conductor layer 110 form a plurality of memory cells. The semiconductor device 100 also includes a source contact 126 that extends into the insulating layer 102 and the polysilicon layer 108. A source contact 126 is in contact with the polysilicon layer 108 and is electrically connected to the channel structure for applying a source voltage. The semiconductor device 100 also includes word line contacts 114 that extend into the insulating structure 118 and contact the conductor layer 110 of each level.

[0024] The semiconductor device 100 also includes a spacer 120 in the polysilicon layer 108 and a peripheral contact 116, the peripheral contact 116 extending into the insulating structure 118, the spacer 120, and the insulating layer 102. The peripheral contact 116 includes a first contact portion 116-1 extending into the insulating structure 118 and a second contact portion 116-2 extending into the base structure 104. The first and second contact portions 116-1 and 116-2 are cooperatively connected to each other away from the memory stack 106. The second contact portion 116-2 and the source contact 126 are formed by a backside process. The spacer 120 insulates the second contact portion 116-2 from the polysilicon layer 108.

[0025] To form the spacer 120 and the second contact portion 116-2, a hole is formed by removing a portion of the base structure 104 from the backside (e.g., lower surface) after the first contact portion 116-1 is formed. The hole extends into the insulating layer 102 and the polysilicon layer 108 until it contacts the first contact portion 116-1. A dielectric material is then deposited into the hole. After a recess etch to remove a portion of the dielectric material to expose the first contact portion 116-1, a conductive material is deposited over the dielectric layer to fill the hole and form the second contact portion 116-2. The portion of the dielectric material in the polysilicon layer 108 forms the spacer 120. Often, the hole is over-etched into the insulating structure 118 to ensure that the second contact portion 116-2 can make the desired contact with the first contact portion 116-1. The upper surface of the hole (i.e., the upper surface of the second contact portion 116-2) is often not flat, e.g., not coplanar with the upper surface of the polysilicon layer 108. For example, a raised structure may be formed on the upper surface of the second contact portion 116-2, as shown in FIG. 1. As described above, the formation of the peripheral contacts 116 (especially the second contact portion 116-2) may be long and complicated. Existing fabrication processes for forming peripheral contacts (e.g., TSVs) need to be improved.

[0026] Various embodiments according to the present disclosure provide an improved semiconductor device and a method for fabricating the same. According to the disclosed fabrication method, a spacer structure is formed on the front side of a base structure to form a contact structure. The spacer structure can be formed by an etching process, followed by a deposition process to fill the opening structure formed by the etching process. Although the etching process and the deposition process can be performed separately, they can be incorporated into the current process flow without additional fabrication steps. For example, the etching process can be performed in any suitable etching / patterning process for forming another structure in a semiconductor device before the formation of the first contact portion, and the deposition process can be any suitable deposition process for forming another structure in a semiconductor device before the formation of the first contact portion. In some embodiments, the etching process is performed using a zero mask, which is used to pattern a structure in a substrate before any structure is formed on the base structure. In some embodiments, the etching process is the same patterning process that patterns a structure on the base structure (e.g., a bottom-select-gate cut structure in a memory stack). In some embodiments, the deposition process can be the same deposition process that forms the insulating structure in which the memory stack is located, thus simplifying the fabrication process.

[0027] The spacer structure may be formed from a trench structure or from a hole in the polysilicon layer. The second contact portion is positioned in the spacer structure and is insulated from the polysilicon layer. In some embodiments, forming the spacer structure from a hole in the conductive layer allows the lower surface of the first contact portion to be closer to the insulating layer, reducing the etching required to form the hole that forms the second conductor portion, further simplifying the fabrication process.

[0028] Figure 2A illustrates a cross-sectional view of an exemplary contact structure in a semiconductor device 200, according to some embodiments. Figure 2B illustrates a top view of a contact structure in a semiconductor device 200, according to some embodiments. For ease of illustration, Figures 2A and 2B are described together.

[0029] As shown in FIG. 2A , the semiconductor device 200 includes a base structure 204, an insulating structure 218 on the base structure 204, and a contact structure 216 extending into the insulating structure 218 and the base structure 204. The semiconductor device 200 may also include a substrate, with the base structure 204 positioned on the substrate. In some embodiments, the semiconductor device 200 includes a memory stack 206 on the base structure 204 and in the insulating structure 218. The semiconductor device 200 may include a word line contact 214 in the insulating structure 218 and in contact with and conductively connected to the memory stack 206. In some embodiments, the semiconductor device 200 includes a source contact structure 226 in contact with and conductively connected to the base structure 204. In some embodiments, the contact structure 216 is positioned in a peripheral region of the semiconductor device 200. The memory stack 206 may be located in a core region and / or a staircase region of the semiconductor device 200. By way of example, in this disclosure, the semiconductor device is represented by a 3D NAND memory device, and the contact structures (e.g., 216) are described as peripheral contacts in the 3D NAND memory device. In some embodiments, the contact structures 216 electrically connect peripheral circuitry and contact pads (not shown) on the opposite side of the base structure 204 of the semiconductor device 200, such that the peripheral circuitry can be electrically connected to external circuitry through the contact pads. In some embodiments, the contact structures 216 are electrically connected to peripheral circuitry and source contact structures 226 on the opposite side of the base structure 204 of the semiconductor device 200, such that the peripheral circuitry can be electrically connected to the source contact structures 226 to control operation of the source of the 3D NAND memory device.It should be understood that the structures and fabrication methods for forming these contact structures may be used to form contact structures in any other suitable structures / devices as well.

[0030] The substrate of the semiconductor device 200 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, the substrate is a thinned substrate (e.g., a semiconductor layer) that has been thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, the substrate is removed and is not included in the semiconductor device 200. It should be noted that x-, y-, and z-axes are included in the figures of the present disclosure to further illustrate the spatial relationships of components in a semiconductor device. By way of example, the substrate of the semiconductor device 200 includes two lateral surfaces (e.g., upper and lower surfaces) that extend laterally in the x- and y-directions (i.e., laterally). The z-direction represents a direction perpendicular to the xy-plane (i.e., the plane formed by the x- and y-directions). As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., semiconductor device 200) is determined in the z-direction (i.e., vertical direction) relative to the substrate of the semiconductor device when the substrate is positioned within the lowest plane of the semiconductor device in the z-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0031] In some embodiments, the semiconductor device 200 is part of a non-monolithic 3D NAND memory device, where components are formed separately on different substrates and then bonded in a face-to-face, face-to-back, or back-to-back manner. Peripheral devices (not shown), such as any suitable digital, analog, and / or mixed-signal peripheral circuitry used to facilitate the operation of the semiconductor device 200, may be formed on a separate peripheral device substrate that is different from the memory array substrate on which the components shown in FIG. 2A are formed. It should be understood that the memory array substrate may be removed from the semiconductor device 200, as described in detail below, and the peripheral device substrate may become the substrate of the semiconductor device 200. It should be further understood that depending on the manner in which the peripheral device substrate and the memory array device substrate are bonded, the memory array device (e.g., as shown in FIG. 2A) may be in its original position or may be flipped upside down within the semiconductor device 200. For ease of reference, Figure 2A illustrates the semiconductor device 200 with the memory array devices in their original positions (i.e., not flipped upside down). However, it should be understood that in some examples, the memory array devices illustrated in Figure 2A may be flipped upside down within the semiconductor device 200 and their relative positions may be changed accordingly. The same concepts for describing spatial relationships apply throughout this disclosure.

[0032] As shown in FIG. 2A, the base structure 204 can include an insulating layer 202 and a polysilicon layer 208 on the insulating layer 202. Optionally, the base structure 204 can include a stop layer 224 between the insulating layer 202 and the polysilicon layer 208. The insulating layer 202 can include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and via contacts can be formed. The ILD layers of the insulating layer 202 can include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, the insulating layer 202 includes silicon oxide. The stop layer 224, if any, can be disposed directly on the insulating layer 202. The stop layer 224 can be a single layer structure or a multi-layer structure. In some embodiments, the stop layer 224 is a single layer structure and includes a high dielectric constant (high-k) dielectric layer. In some embodiments, the stop layer 224 is a dual layer structure and includes a first stop layer on top of a second stop layer. The first stop layer can include silicon nitride and the second stop layer can include a high-k dielectric. The high-k dielectric layer can include, for example, aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide, to name a few. In one example, the stop layer 224 can include aluminum oxide. It should be understood that since the function of the stop layer 224 is to stop the etching of the channel holes, as described in more detail below, the stop layer 224 can include any other suitable material that has a relatively high etch selectivity (e.g., greater than about 5) with respect to the material in the layer above it. In some embodiments, in addition to functioning as an etch stop layer, the stop layer 224 also functions as a backside substrate thinning stop layer.

[0033] The polysilicon layer 208 may be disposed directly on the stop layer 224. In some embodiments, a pad oxide layer (e.g., a silicon oxide layer) is disposed between the stop layer 224 and the polysilicon layer 208 to relieve stress between the polysilicon layer 208 and the stop layer 224 (e.g., an aluminum oxide layer). The polysilicon layer 208 includes an N-type doped polysilicon layer according to some embodiments. That is, the polysilicon layer 208 may be doped with any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb), etc.), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. The polysilicon layer 208 may include a polysilicon sublayer 208-1 between the upper and lower surfaces of the polysilicon layer 108, which may be conductively connected to the semiconductor channels of the 3D NAND memory strings and source contact structures of the semiconductor device 200. Due to the diffusion process, as described in detail below, the polysilicon layer 208 may have a fairly uniform doping concentration profile in the vertical direction. It should be understood that the sublayer 208-1 of the polysilicon layer 208 may have the same polysilicon material as the rest of the polysilicon layer 208, and the doping concentration may be uniform within the polysilicon layer 208 after diffusion, so that the sublayer 208-1 may not be distinguishable from the rest of the polysilicon layer 208 in the semiconductor device 200. Nevertheless, the sublayer 208-1 refers to a portion of the polysilicon layer 208 that is in contact with the semiconductor channel, instead of the memory film, at the lower portion of the channel structure.

[0034] 2A shows the polysilicon layer 208 above the stop layer 224 as described above, it should be understood that the stop layer 224 may be above the polysilicon layer 208 in some examples because the memory array device shown in FIG. 2A may be flipped upside down and their relative positions within the semiconductor device 200 may be changed accordingly. In some embodiments, the memory array device shown in FIG. 2A is flipped upside down (at the top) within the semiconductor device 200 and coupled to a peripheral device (at the bottom) such that the stop layer 224 is above the polysilicon layer 208. In this disclosure, the polysilicon layer 208 is described as a conductive layer for facilitating electrical coupling between the source contacts of the semiconductor device 200 and the memory stack 206, but in various embodiments, any other suitable conductive material may be formed between the memory stack 206 and the insulating layer 202 to perform a similar / same function as the polysilicon layer 208.

[0035] The memory stack 206 may include multiple interleaved conductor layers 210 and dielectric layers 212 on the polysilicon layer 208. The conductor layers 210 and dielectric layers 212 in the memory stack 206 may alternate vertically. In other words, each conductor layer 210, except for the one at the top or bottom of the memory stack 206, may be flanked by two dielectric layers 212 on both sides, and each dielectric layer 212 may be flanked by two conductor layers 210 on both sides. The conductor layers 210 may include conductive materials, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductor layer 210 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductor layer 210 may extend laterally as a word line and terminate at one or more staircase structures of the memory stack 206. The dielectric layer 212 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The memory stack 206 may have a staircase structure, which includes multiple steps (e.g., extending laterally along the x / y direction). Each step may include one or more pairs of conductor layer 210 and dielectric layer 212 (referred to as a conductor / dielectric layer pair). A word line contact 214 (extending into the insulating structure 218) may be in contact with and conductively connected to the top conductor layer 210 of each step, as shown in FIG. 2A. The word line contact 214 may include a conductive material, including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. The insulating structure 218 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0036] In some embodiments, the semiconductor device 200 is a 3D NAND memory device and includes a plurality of memory cells formed in a memory stack 206. The memory cells may be formed by the intersections of 3D NAND memory strings in the memory stack 206 with the conductor layer 210. Figure 6 illustrates a cross-sectional view of a channel structure in the memory stack 206.

[0037] 6, the channel structure 612 extends vertically through the memory stack 206 and the polysilicon layer 208, stopping (if any) at the stop layer 224. That is, the channel structure 612 can include two portions: a lower portion surrounded by the polysilicon layer 208 (i.e., below the interface between the polysilicon layer 208 and the memory stack 206), and an upper portion surrounded by the memory stack 206 (i.e., above the interface between the polysilicon layer 208 and the memory stack 206). As used herein, an "upper portion / end" of a component (e.g., the channel structure 612) is the portion / end that is farther away from the substrate in the z-direction when the substrate is positioned in the lowest plane of the semiconductor device 200, and a "lower portion / end" of a component (e.g., the channel structure 612) is the portion / end that is closer to the substrate in the z-direction. In some embodiments, each channel structure 612 does not extend beyond the stop layer 224 because etching of the channel holes is stopped by the stop layer 224. For example, the lower end of the channel structure 612 can be nominally flush with the upper surface of the stop layer 224.

[0038] The channel structure 612 can include a channel hole filled with a semiconductor material (e.g., as the semiconductor channel 616) and a dielectric material (e.g., as the memory film 614). In some embodiments, the semiconductor channel 616 includes silicon (e.g., amorphous silicon, polysilicon, or single crystal silicon). In one example, the semiconductor channel 616 includes polysilicon. In some embodiments, the memory film 614 is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of the channel hole can be partially or completely filled with a capping layer 618 including a dielectric material (e.g., silicon oxide) and / or an air gap. The channel structure 612 can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the capping layer 618, the semiconductor channel 616, the tunneling layer, the storage layer, and the blocking layer of the memory film 614 are arranged in this order radially from the center to the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory film 614 can include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer. In some embodiments, the channel structure 612 further includes a channel plug 620 at the top of the upper portion of the channel structure 612. The channel plug 620 can include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 620 functions as a drain of the NAND memory string.

[0039] 6, a portion of the semiconductor channel 616 along the sidewall of the channel structure 612 (e.g., at the lower portion of the channel structure 612) is in contact with the polysilicon sublayer 208-1 according to some embodiments. That is, the memory film 614 is separated at the lower portion of the channel structure 612 abutting the sublayer 208-1 of the polysilicon layer 208, exposing the semiconductor channel 616 to contact the surrounding polysilicon sublayer 208-1 according to some embodiments. As a result, the polysilicon sublayer 208-1 surrounding and contacting the semiconductor channel 616 can act as a "sidewall SEG" of the channel structure 612. In some embodiments, the source contact structure 226 is in contact with the polysilicon layer 208 and is electrically connected to the semiconductor channel 616 through the polysilicon layer 208.

[0040] As shown in FIG. 6, in some embodiments, the semiconductor device 200 further includes an insulating spacer 622 that extends vertically through the interleaved conductor layers 210 and the dielectric layers 212 of the memory stack 206. In some embodiments, the insulating spacer 622 extends into the polysilicon layer 208 and stops at the polysilicon sublayer 208-1 according to some embodiments. In some embodiments, the lower end of the insulating spacer 622 is nominally flush with the upper surface of the polysilicon sublayer 208-1. Each insulating spacer 622 can also extend laterally to separate the channel structure 612 into multiple blocks. Unlike the slit structures in some 3D NAND memory devices, the insulating spacer 622 does not include any contact therein (i.e., does not function as a source contact) according to some embodiments. In some embodiments, each insulating spacer 622 includes an opening (e.g., a slit) that is filled with one or more dielectric materials (including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof). In one example, each insulating spacer 622 can be filled with silicon oxide as the insulator core 626 and a high-k dielectric in contact with the gate dielectric layer.

[0041] The source contact structures 226 may extend vertically through the insulating layer 202 and the stop layer 224 (if any) from the opposite side (i.e., backside) of the polysilicon layer 208 with respect to the stop layer 224, and be in contact with the polysilicon layer 208. It should be understood that the depth to which the source contact structures 226 extend into the polysilicon layer 208 may vary in different examples. The source contact structures 226 may electrically connect the sources of the NAND memory strings of the semiconductor device 200 to the peripheral devices from the backside of the memory array substrate (removed) through the polysilicon layer 208, and thus may also be referred to herein as "backside source pickup". The source contact structures 226 may include any suitable type of contact. In some embodiments, the source contact structures 226 include via contacts. In some embodiments, the source contact structures 226 include laterally extending wall-shaped contacts. The source contact structure 226 can include one or more conductive layers (e.g., a metal layer, such as tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al), or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0042] 2A and 2B, the contact structure 216 may extend into the insulating structure 218 and the base structure 204 and may be conductively connected to any peripheral circuitry for operation of the memory cell. In some embodiments, the contact structure 216 extends through the polysilicon layer 208 and the insulating layer 202. The contact structure 216 may include a first contact portion 216-1 that extends into the insulating structure 218 and a second contact portion 216-2 that extends into the base structure 204 (e.g., the polysilicon layer 208 and the insulating layer 202, and the stop layer 224, if present). The first and second contact portions 216-1 and 216-2 are in contact with each other at a contact interface and may be conductively connected to each other. The semiconductor device 200 may also include a spacer structure 220 in the polysilicon layer 208 and surrounding the second contact portion 216-2 such that the second contact portion 216-2 is insulated from the polysilicon layer 208.

[0043] In some embodiments, as shown in FIG. 2B, the lateral cross-sectional area of ​​the second contact portion 216-2 is equal to or greater than the lateral cross-sectional area of ​​the first contact portion 216-1 such that the first contact portion 216-1 is completely overlapped with the second contact portion 216-2. The lateral cross-sections of the first and second contact portions 216-1 and 216-2, respectively, can have any suitable shape (e.g., elliptical, square, rectangular, and circular, etc.). For example, the lateral cross-sections of the first and second contact portions 216-1 and 216-2 may be nominally circular and square, respectively. The upper surface of the second contact portion 216-2 can be sufficiently flat, e.g., nominally level / coplanar with the upper surface of the polysilicon layer 208. The contact interface between the first contact portion 216-1 and the second contact portion 216-2 can be coplanar (or at least nominally coplanar) with the upper surface of the polysilicon layer 208. That is, the lower surface of the first contact portion 216-1 and the upper surface of the second contact portion 216-2 can be coplanar (or at least nominally coplanar), respectively, with the upper surface of the polysilicon layer 208. In some embodiments, the first and second contact portions 216-1 and 216-2 can each be made of tungsten, cobalt, copper, or aluminum, and / or a silicide.

[0044] The spacer structure 220 is in the polysilicon layer 208 and in contact with and may surround the second contact portion 216-2 such that the second contact portion 216-2 (or the contact structure 216) is insulated from the polysilicon layer 208. The lateral dimension (e.g., in the xy plane) of the spacer structure 220 may be large enough to insulate the second contact portion 216-2 from the polysilicon layer 208 in all directions. The upper surface of the spacer structure 220 in contact with the insulating structure 218 may be coplanar with the upper surface of the polysilicon layer 208. The lower surface of the spacer structure 220 may be in contact with the insulating layer 202 (or the stop layer 224, if present) such that the second contact portion 216-2 is completely insulated from the polysilicon layer 208. In various embodiments, the lower surface of the spacer structure 220 can be flush with or below the lower surface of the polysilicon layer 208. For example, the lower surface of the spacer structure 220 can be in the stop layer 224 or in the insulating layer 202. In some embodiments, the spacer structure 220 comprises a dielectric material (such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof). It should be understood that if the spacer structure 220 comprises the same material as the insulating structure 218 and / or the spacer structure 220, the upper and / or lower surfaces of the spacer structure 220 may not be distinguishable.

[0045] Figure 3A illustrates a cross-sectional view of another exemplary contact structure in a semiconductor device 300, according to some embodiments. Figure 3B illustrates a top view of a contact structure in a semiconductor device 300, according to some embodiments. For ease of illustration, Figures 3A and 3B are described together, and details of other identical structures in both semiconductor devices 200 and 300 are not repeated for ease of explanation.

[0046] As shown in FIG. 3A, the semiconductor device 300 includes a contact structure 316 and a spacer structure 320. The contact structure 316 can include a first contact portion 316-1 and a second contact portion 316-2, which are in contact with each other and are conductively connected to each other. The contact structure 316 can extend through the spacer structure 320, such that the spacer structure 320 insulates the contact structure 316 from the polysilicon layer 208. Unlike the contact structure 216, the contact interface between the first contact portion 316-1 and the second contact portion 316-2 can be below the upper surface of the polysilicon layer 208. For example, the contact interface (e.g., the lower surface of the first contact portion 316-1 and the upper surface of the second contact portion 316-2) can be between the upper and lower surfaces of the polysilicon layer 208. In some embodiments, the contact interface may be flush (or at least nominally flush) with the lower surface of the polysilicon layer 208. That is, the first contact portion 316-1 may extend into (e.g., extend through) the polysilicon layer 208. Thus, the second contact portion 316-2 may have a reduced thickness within the spacer structure 320.

[0047] Unlike the spacer structure 220, the spacer structure 320 surrounds at least a portion of the first contact portion 316-1 such that the first contact portion 316-1 is insulated from the polysilicon layer 208. If the contact interface between the first contact portion 316-1 and the second contact portion 316-2 is between the upper and lower surfaces of the polysilicon layer 208, the spacer structure 320 can also insulate a portion of the second contact portion 316-2 from the polysilicon layer 208. In some embodiments, as shown in FIG. 3B, the lateral cross-sectional area of ​​the second contact portion 316-2 is equal to or greater than the lateral cross-sectional area of ​​the first contact portion 316-1 such that the first contact portion 316-1 is completely overlapped with the second contact portion 316-2. The materials and shapes of the first and second contact portions 316-1 and 316-2 and the spacer structure 320 may be similar or the same as those of the first and second contact portions 216-1 and 216-2 and the spacer structure 220, respectively, and detailed descriptions will not be repeated here.

[0048] 4A-4D illustrate a fabrication process for forming a semiconductor device according to some embodiments of the present disclosure. FIG. 7 illustrates a flowchart of a method 700 for forming a semiconductor device according to some embodiments of the present disclosure. Examples of semiconductor devices illustrated in FIGS. 4A-4D and 7 include the semiconductor devices illustrated in FIGS. 2A and 2B. FIGS. 4A-4D and 7 are described together. It should be understood that the operations illustrated in method 700 are not exhaustive, and that other operations may be performed before, after, or during any of the illustrated operations as well. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 7.

[0049] 7, the method 700 begins with operations 702 and 704, where a trench structure is formed in a base structure and a spacer structure is formed in the trench structure. FIG 4A illustrates the corresponding structure.

[0050] As shown in FIG. 4A, at the beginning of the fabrication process, a trench structure may be formed in a base structure 404. The shape and depth of the trench structure may correspond to that of a spacer structure to be subsequently formed. The base structure 404 may include a polysilicon layer 408 on a stop layer 424, which in turn is on an insulating layer 402. The polysilicon layer 408 may include a sacrificial sublayer, which subsequently forms a polysilicon sublayer in the polysilicon layer 408. A detailed description of the polysilicon layer 408, the stop layer 424, and the insulating layer 402 may be referred to the description of the polysilicon layer 208, the stop layer 224, and the insulating layer 202, and will not be repeated here.

[0051] The trench structure may surround an area (e.g., polysilicon layer 408) in the peripheral region of the base structure 404 such that the surrounded area (e.g., in the polysilicon layer 408) may be insulated from a portion of the polysilicon layer 408 outside the trench structure. In some embodiments, the trench structure may extend from an upper surface of the polysilicon layer 408 to at least a lower surface of the polysilicon layer 408. For example, the lower surface of the trench structure may stop on or in the stop layer 424. In some embodiments, the lower surface of the polysilicon layer 408 stops at the stop layer 424. The thickness / depth of the trench structure may be at least the thickness of the polysilicon layer 408 along the z-direction. The trench structure may be formed by a photolithography process followed by any suitable patterning process (e.g., dry etching and / or wet etching, etc.).

[0052] The base structure 404 may be formed on one side (e.g., a first side) of the substrate. The substrate can be a silicon substrate or a carrier substrate made of any suitable material (e.g., semiconductor, glass, sapphire, plastic, etc., to name a few). In some embodiments, the insulating layer 402 includes a dielectric material (e.g., silicon oxide, etc.). In some embodiments, the stop layer 424 includes a high-k dielectric material (e.g., aluminum oxide, etc.). In some embodiments, the polysilicon layer 408 includes polysilicon having a uniform doping profile. In some embodiments, the insulating layer 402, the stop layer 424, and the polysilicon layer 408 are sequentially formed on the substrate by any suitable film deposition method (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless deposition, and combinations thereof, etc.). Thereafter, the substrate may be removed or thinned to form various structures (e.g., contact vias, etc.). In some embodiments, the substrate is removed or thinned at an appropriate time in the fabrication process so that contact vias can be formed from the lower surface of base structure 404 .

[0053] A dielectric stack (which subsequently forms a memory stack) may be formed on the base structure 404 over the substrate. The dielectric stack may include multiple interleaved sacrificial and dielectric layers. In some embodiments, the dielectric stack (having multiple pairs of sacrificial and dielectric layers) is formed over the polysilicon layer 408. The interleaved sacrificial and dielectric layers may be alternately deposited over the polysilicon layer 408 to form the dielectric stack. In some embodiments, each dielectric layer includes a layer of silicon oxide and each sacrificial layer includes a layer of silicon nitride. In some embodiments, a pad oxide layer (e.g., a silicon oxide layer (not shown)) is formed between the polysilicon layer 408 and the dielectric stack. An insulating structure 418 (having a suitable dielectric material such as silicon oxide) may be deposited over the dielectric stack and the base structure 404 at a suitable time during the fabrication process such that the dielectric stack is positioned in the insulating structure 418. The dielectric stack, the insulating structure 418, and the pad oxide layer (if present) may be formed by one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof).

[0054] At any suitable time during the fabrication process, before the first contact portion of the contact structure is formed, a trench structure may be formed in the peripheral region of the semiconductor device. In some embodiments, the trench structure is formed by patterning the base structure 404 (e.g., polysilicon layer 408) using a "zero mask" that is used to pattern the base structure 404 before any structures are formed thereon. In some embodiments, the trench structure is formed by patterning a dielectric stack to form a bottom-select-gate cut structure, for example, after one or more pairs of sacrificial and dielectric layers are formed on the base structure 404. Thus, the pattern for forming the trench structure may be incorporated into an existing patterning mask such that etching of the base structure 404 to form the trench structure may be performed along with other existing etching operations, reducing the number of total etching operations. In various embodiments, the trench structure may also be formed by a separate patterning / etching process or simultaneously with other suitable structures, depending on the fabrication process.

[0055] A spacer structure 420 may be formed in the trench structure. A dielectric material (e.g., silicon oxide) may be deposited to fill the trench structure to form the spacer structure 420. The dielectric material may be deposited by any suitable film deposition method (e.g., CVD, PVD, ALD, and combinations thereof, etc.) and may be deposited at any suitable time during the fabrication process before the first contact portion of the contact structure is formed. In some embodiments, the spacer structure 420 may be formed by the same deposition process that forms the insulating structure 418 after the formation of the dielectric stack. In some embodiments, the spacer structure 420 may be formed by the same deposition process that forms the bottom-select-gate cut structure in the dielectric stack after one or more pairs of sacrificial and dielectric layers are formed on the base structure 404 and before the entire dielectric stack is formed. In various embodiments, the spacer structure 420 may also be formed by a separate deposition process or filled with the dielectric material simultaneously with other suitable structures, depending on the fabrication process.

[0056] Prior to the formation of the contact structure, other structures (not shown in FIGS. 4A-4D ) may be formed in the semiconductor device (e.g., a dielectric stack). In some embodiments, a channel structure is formed that extends vertically through the dielectric stack, the polysilicon layer 408, and stops at the stop layer 424. In some embodiments, to form the channel structure, a channel hole (e.g., an opening) is formed that extends vertically through the dielectric stack and the polysilicon layer 408, and memory films (e.g., blocking layers, storage layers, and tunneling layers) and a semiconductor channel are sequentially formed along the sidewalls of the channel hole. The deposition of the films and layers in the channel hole can include ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a channel plug is formed above and in contact with the semiconductor channel. In some embodiments, the fabrication process for forming the channel hole includes a wet etching process and / or a dry etching process (e.g., deep ion reactive etching (DRIE), etc.). According to some embodiments, etching of the channel holes continues until it is stopped by the stop layer 424 due to the etch selectivity between the materials of the stop layer 424 and the polysilicon layer 408 .

[0057] To conductively connect the polysilicon layer 408 and the channel structure, a polysilicon sublayer 408-1 (contacting and conductively connected to the semiconductor channel) is formed in the polysilicon layer 408. In some embodiments, a lower portion of the memory film is removed so that the memory film becomes disconnected. The polysilicon sublayer 408-1 in contact with the semiconductor channel can be formed by replacing a sacrificial sublayer with a sublayer of polysilicon. The formation of the polysilicon sublayer 408-1 can include suitable dry and / or wet etching processes, CVD, PVD, ALD, and combinations thereof. An insulating spacer (dividing the memory cell into multiple blocks) can also be formed. The formation of the insulating spacer can include suitable dry and / or wet etching processes, CVD, PVD, ALD, and combinations thereof. A gate exchange process can be performed to replace the sacrificial layer in the dielectric stack and form multiple conductor layers. A memory stack 406 (having multiple interleaved conductor layers 410 and dielectric layers 412) can be formed on the polysilicon layer 408. The gate replacement process can include a suitable isotropic etching process, CVD, PVD, ALD, and combinations thereof. The channel structure (extending through the memory stack 406) can be in contact with and conductively connected to the polysilicon layer 408 through a semiconductor channel. In some embodiments, the memory stack 406 can be repetitively patterned to form a staircase structure, which includes multiple steps extending laterally (e.g., along the x / y direction). The patterning process of the memory stack 406 can include repetitive photolithography processes and recess etching (e.g., isotropic etching processes).

[0058] 7, the method 700 proceeds to operation 706 where a first contact portion is formed on an upper surface of the base structure and surrounded by a spacer structure. FIG. 4B illustrates the corresponding structure.

[0059] As shown in FIG. 4B, the first contact portion 416-1 may be formed in the insulating structure 418 and land on the upper surface of the base structure 404. The lower surface of the first contact portion 416-1 may be in an enclosed area in the polysilicon layer 408 defined by the spacer structure 420 such that laterally, the first contact portion 416-1 is surrounded by the spacer structure 420. In some embodiments, the lower surface of the first contact portion 416-1 extends below the upper surface of the polysilicon layer 408. In some embodiments, the first contact portion 416-1 is formed by the same process that forms the word line contacts 414, which land on the respective steps and form a conductive connection with the conductor layer 410 in the steps. The first contact portion 416-1 and the word line contacts 414 may each include a suitable conductive material (e.g., tungsten, etc.).

[0060] Formation of the first contact portion 416-1 and the word line contact 414 can include a patterning process followed by a suitable film deposition process. The patterning process can remove a portion of the insulating structure 418 and form openings corresponding to the location and position of the first contact portion 416-1 and the word line contact 414. In some embodiments, the opening for the first contact portion 416-1 extends into the insulating structure 418 to expose an enclosed area in the polysilicon layer 408. In some embodiments, the opening for the word line contact 414 extends into the insulating structure 418 to expose the conductor layer 410 in a corresponding step. Deposition of the conductive material can include CVD, PVD, ALD, electroplating, electroless plating, and combinations thereof.

[0061] 7, the method 700 proceeds to operation 708 where a hole is formed extending from a lower surface of the base structure to the first contact portion, the hole being surrounded by a spacer structure. Figure 4C illustrates the corresponding structure.

[0062] As shown in FIG. 4C, a hole 415 may be formed that extends from a lower surface of the base structure 404 to the first contact portion 416-1. The hole 415 may be surrounded by a spacer structure 420. A portion of the base structure 404 (i.e., the insulating layer 402, the stop layer 424, and a portion of the polysilicon layer 408) may be removed to form a hole 415, which extends from the lower surface of the base structure 404 (e.g., the lower surface of the insulating layer 402) to the first contact portion 416-1. The hole 415 may be in contact with and expose the first contact portion 416-1. As shown in FIG. 4C, a portion of the hole 415 in the polysilicon layer 408 may be positioned within an enclosed area defined by the spacer structure 420. The lateral dimensions of the hole 415 can be large enough to completely contact the first contact portion 416-1 and small enough not to extend beyond the enclosed area surrounded by the spacer structure 420. In some embodiments, the hole 415 is isolated from the polysilicon layer 408 outside the spacer structure 420. In some embodiments, the lateral dimensions of the hole 415 can be equal to or smaller than the lateral dimensions of the enclosed area.

[0063] In some embodiments, another hole 425 for forming a source contact structure may be formed in the same patterning process that forms hole 415. Hole 425 may extend from a lower surface of base structure 404 (e.g., insulating layer 402) to polysilicon layer 408. The patterning process may include a suitable etching process (e.g., a dry etching process and / or a wet etching process).

[0064] In various embodiments, the substrate (on which base structure 404 is formed) is removed prior to the formation of hole 415. The substrate may be removed at any suitable time during the fabrication process by a grinding process, CMP, recess etching, or combinations thereof. In some embodiments, the lower surface of base structure 404 is the lower surface of insulating layer 402.

[0065] 7, the method 700 proceeds to operation 710 where a second contact portion is formed in the hole in contact with the first contact portion. Figure 4D illustrates the corresponding structure.

[0066] As shown in FIG. 4D, a second contact portion 416-2 may be formed in the hole 415 in contact with the first contact portion 416-1. A conductive material (e.g., tungsten, etc.) may be deposited to fill the hole 415 and the other hole 425. Any suitable film deposition method may be performed to deposit the conductive material. For example, the deposition method may include CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. In some embodiments, the source contact structure 426 may be formed by the same deposition process that forms the second contact portion 416-2. The contact structure 416 (having first and second contact portions 416-1 and 416-2 in contact with each other) may be formed and extend through the insulating structure 418 and the base structure 404 (e.g., the spacer structure 420) to connect peripheral circuits of the semiconductor device. On the one hand, a source contact structure 426 may be formed in the base structure 404 in contact with and conductively connected to the polysilicon layer 408. A channel structure may then be conductively connected to the source through the polysilicon layer 408 and the source contact structure 426.

[0067] 5A-5D illustrate a fabrication process for forming a semiconductor device according to some embodiments of the present disclosure. FIG. 8 illustrates a flowchart of a method 800 for forming a semiconductor device according to some embodiments of the present disclosure. Examples of semiconductor devices illustrated in FIGS. 5A-5D and 8 include the semiconductor devices illustrated in FIGS. 3A and 3B. FIGS. 5A-5D and 8 are described together. It should be understood that the operations illustrated in method 800 are not exhaustive, and that other operations may similarly be performed before, after, or during any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 8. For ease of illustration, parts in FIGS. 5A-5D similar to those in FIGS. 4A-4D are indicated using the same numerals, and detailed descriptions of these parts will not be repeated here.

[0068] 8, the method 800 begins at operations 802 and 804, where a first hole is formed in a base structure and a well structure is formed in the first hole. FIG. 5A illustrates the corresponding structure.

[0069] As shown in FIG. 5A, at the beginning of the fabrication process, a first hole may be formed in the base structure 404. The shape and depth of the first hole may correspond to that of the subsequently formed spacer structure. In some embodiments, the lower surface of the first hole may expose the stop layer 424. In some embodiments, the depth of the first hole may be equal to or greater than the thickness of the polysilicon layer 408, such that the subsequently formed spacer structure may insulate the contact structure from the polysilicon layer 408. The first hole may be formed at any suitable time during the fabrication process, and may be formed together with other structures or in a separate process. A suitable etching process (e.g., wet etching and / or dry etching) may be performed as a patterning process to form the first hole. A detailed description of the location and timing for forming the first hole may be referred to that of the trench structure described in FIGS. 4A-4D and will not be repeated here.

[0070] A well structure 519 may be formed in the base structure 404 by filling the first hole with a dielectric material. The lower surface of the well structure 519 may be in contact with the stop layer 424. In some embodiments, the lower surface of the well structure 519 may be on or below the upper surface of the stop layer 424. The upper surface of the well structure 519 may be defined as a surface that is coplanar with the upper surface of the polysilicon layer 408 for ease of illustration. In some embodiments, the dielectric material includes silicon oxide and may be formed by a suitable film deposition method (e.g., CVD, PVD, ALD, or a combination thereof). A detailed description of the location and timing for forming the well structure 519 may be referred to that of the spacer structure 420 described in FIGS. 4A-4D and will not be repeated here.

[0071] 8, the method 800 proceeds to operation 806 where a first contact portion is formed in the well structure. Figure 5B illustrates the corresponding structure.

[0072] As shown in FIG. 5B, the first contact portion 516-1 may be formed in the well structure 519. The first contact portion 516-1 may be formed in the insulating structure 418 and land on the lower surface of the well structure 519. The first contact portion 516-1 may be surrounded by the well structure 519. In some embodiments, the first contact portion 516-1 is formed by the same process that forms the word line contacts 414, which land on the respective steps and form a conductive connection with the conductor layer 410 in the steps. The first contact portion 516-1 and the word line contacts 414 may each include a suitable conductive material (e.g., tungsten, etc.). In some embodiments, the lower surface of the first contact portion 516-1 does not reach the lower surface of the well structure 519, but is below the upper surface of the polysilicon layer 408, such that etching from the lower surface of the base structure 404 may be reduced when the second contact portion is formed. That is, the second hole for forming the second contact portion does not need to reach from the lower surface of the base structure 404 (ie, the insulating layer 402 ) to the upper surface of the polysilicon layer 408 .

[0073] Formation of the first contact portion 516-1 and the word line contact 414 can include a patterning process followed by a suitable film deposition process. The patterning process can remove a portion of the insulating structure 418 at a desired depth and form an opening corresponding to the location and position of the first contact portion 516-1 and the word line contact 414. In some embodiments, the opening for the first contact portion 516-1 extends into the insulating structure 418 to expose an enclosed area in the polysilicon layer 408. In some embodiments, the opening for the word line contact 414 extends into the insulating structure 418 to expose the conductor layer 410 in a corresponding step. Deposition of the conductive material can include CVD, PVD, ALD, electroplating, electroless plating, and combinations thereof.

[0074] 8, the method 800 proceeds to operation 808, where a second hole is formed extending from the lower surface of the base structure to the first contact portion. A spacer structure is formed. FIG. 5C illustrates the corresponding structure.

[0075] As shown in FIG. 5C, a second hole 515 may be formed extending from a lower surface of the base structure 404 to the first contact portion 516-1. A spacer structure 520 may be formed from the remaining portion of the well structure 519. The second hole 515 may be surrounded by the spacer structure 520 in the polysilicon layer 408. A portion of the base structure 404 (i.e., the insulating layer 402, the stop layer 424, and a portion of the polysilicon layer 408 (if any)) may be removed to form a second hole 515, the second hole 515 extending from a lower surface of the base structure 404 (e.g., the lower surface of the insulating layer 402) to the first contact portion 516-1. The second hole 515 may be in contact with the first contact portion 516-1 and expose the first contact portion 516-1. In various embodiments, the upper surface of the second hole 515 can be flush with or above the upper surface of the stop layer 424 to ensure sufficient contact between the first contact portion 516-1 and the second hole 515 (or a second contact portion formed subsequently). As shown in FIG. 5C, the lateral dimension of the hole 415 can be large enough to fully contact the first contact portion 516-1 and small enough not to extend beyond the spacer structure 420. In some embodiments, the second hole 515 is isolated from the polysilicon layer 408 outside the spacer structure 520. In some embodiments, the lateral dimension of the second hole 515 can be equal to or smaller than the lateral dimension of the well structure 519 (or the spacer structure 520). In some embodiments, another hole 425 for forming the source contact structure 426 can be formed in the same patterning process that forms the hole 415. The patterning process may include a suitable etching process (eg, a dry etching process and / or a wet etching process).

[0076] 8, the method 800 proceeds to operation 810, where a second contact portion is formed in the second hole and in contact with the first contact portion. Figure 5D illustrates the corresponding structure.

[0077] As shown in FIG. 5D, a second contact portion 516-2 may be formed in the second hole 515 in contact with the first contact portion 516-1. A conductive material (e.g., tungsten, etc.) may be deposited to fill the second hole 515 and the other holes 425. Any suitable film deposition method may be performed to deposit the conductive material. For example, the deposition method may include CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. In some embodiments, the source contact structure 426 may be formed by the same deposition process that forms the second contact portion 516-2. The contact structure 516 (having first and second contact portions 516-1 and 516-2 in contact with each other) may be formed and extend through the insulating structure 418 and the base structure 404 (e.g., spacer structure 520) to connect peripheral circuits of the semiconductor device. A lower surface of the first conductor portion 516-1 may be below an upper surface of the spacer structure 520. The upper surface of the second conductor portion 516-2 may be a flat / leveled surface.

[0078] An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

[0079] In some embodiments, the conductive layer comprises polysilicon.

[0080] In some embodiments, the lateral cross-sectional area of ​​the second contact portion is greater than or equal to the lateral cross-sectional area of ​​the first contact portion.

[0081] In some embodiments, the semiconductor device further includes a memory stack including alternating conductive and dielectric layers over the conductive layer and away from the contact structure. In some embodiments, the semiconductor device also includes a channel structure within the memory stack and into the conductive layer. The channel structure includes a semiconducting channel. A lower portion of the semiconducting channel is in contact with the conductive layer. A second contact structure extends vertically into the insulating layer and in contact with the conductive layer.

[0082] In some embodiments, the channel structure further includes a memory layer in contact with and surrounding the semiconductor channel, hi some embodiments, a lower portion of the memory layer is released to expose the semiconductor channel such that the semiconductor channel is in contact with the conductive layer.

[0083] In some embodiments, the spacer structure comprises a dielectric material.

[0084] In some embodiments, the first contact structure electrically connects the peripheral circuitry and the contact pads on opposite sides of the insulating layer and the conductive layer.

[0085] In some embodiments, the first contact structure is electrically connected to the second contact structure.

[0086] An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. The contact structure also includes a lower surface of the first contact portion in contact with an upper surface of the second contact portion at a contact interface below the upper surface of the conductive layer.

[0087] In some embodiments, the contact interface is flush with the lower surface of the conductive layer.

[0088] In some embodiments, the conductive layer comprises polysilicon.

[0089] In some embodiments, the lateral cross-sectional area of ​​the second contact portion is greater than or equal to the lateral cross-sectional area of ​​the first contact portion.

[0090] In some embodiments, the semiconductor device further includes a memory stack including alternating conductive and dielectric layers above the conductive layer and away from the contact structure, and a channel structure within the memory stack and into the conductive layer. The channel structure includes a semiconductor channel. A lower portion of the semiconductor channel is in contact with the conductive layer. A second contact structure extends vertically into the insulating layer and in contact with the conductive layer.

[0091] In some embodiments, the channel structure further includes a memory layer in contact with and surrounding the semiconductor channel, hi some embodiments, a lower portion of the memory layer is released to expose the semiconductor channel such that the semiconductor channel is in contact with the conductive layer.

[0092] In some embodiments, the spacer structure comprises a dielectric material.

[0093] In some embodiments, the first contact structure electrically connects the peripheral circuitry and the contact pads on opposite sides of the insulating layer and the conductive layer.

[0094] In some embodiments, the first contact structure is electrically connected to the second contact structure.

[0095] An embodiment of the present disclosure provides a method for forming a semiconductor device, the method including forming a spacer structure into a base structure from a first surface of the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion, the second contact portion extending into the base structure from a second surface of the base structure.

[0096] In some embodiments, forming the spacer structure includes removing a portion of the base structure above the first surface to form an aperture structure extending from the first surface into the base structure, In some embodiments, forming the spacer structure includes filling the aperture structure with an insulating material.

[0097] In some embodiments, the lower surface of the aperture structure is between the first surface and the second surface of the base structure.

[0098] In some embodiments, the base structure includes an insulating layer and a conductive layer over the insulating layer. In some embodiments, forming the opening structure includes forming a trench structure in the conductive layer and forming a first portion of the conductive layer surrounded by the trench structure and a second portion of the conductive layer outside the trench structure.

[0099] In some embodiments, a first portion of the conductive layer is separated from a second portion of the conductive layer by a trench structure, a lower surface of the trench structure being in contact with the insulating layer.

[0100] In some embodiments, forming a first contact portion surrounded by the spacer structure includes forming a first contact portion in contact with a first portion of the conductive layer and surrounded by an insulating material.

[0101] In some embodiments, forming the second contact portion includes forming a hole extending from the second surface of the base structure into the base structure and in contact with the first contact portion. The hole is insulated from the second portion of the conductive layer by a spacer structure. In some embodiments, forming the second contact portion includes filling the hole with a conductive material.

[0102] In some embodiments, the base structure includes an insulating layer and a conductive layer over the insulating layer, In some embodiments, forming the aperture structure includes forming a hole in the conductive layer, a lower surface of the hole in contact with the insulating layer.

[0103] In some embodiments, forming a first contact portion surrounded by the spacer structure includes forming the first contact portion extending into the insulating material, a lower surface of the first contact portion below an upper surface of the spacer structure.

[0104] In some embodiments, the lower surface of the first contact portion is in contact with the insulating layer.

[0105] In some embodiments, forming the second contact portion includes forming another hole extending from the second surface of the base structure into the base structure and in contact with the first contact portion. The hole is insulated from the conductive layer by an insulating material. In some embodiments, forming the second contact portion includes filling the hole with the conductive material.

[0106] In some embodiments, the base structure includes an insulating layer, an etch stop layer over the insulating layer, and a conductive layer over the etch stop layer, In some embodiments, forming the aperture structure includes removing a portion of the conductive layer until a lower surface of the aperture structure stops on the etch stop layer.

[0107] In some embodiments, the method further includes forming a memory stack over the base structure spaced from the contact structure, the insulating material being deposited prior to formation of the memory stack.

[0108] In some embodiments, the method further includes forming a memory stack over the base structure spaced from the contact structure. The insulating material is deposited after formation of the memory stack.

[0109] In some embodiments, the method further includes forming a channel structure in the memory stack that includes a semiconductor channel. A lower portion of the semiconductor channel is in contact with the conductive layer. In some embodiments, the method further includes forming a contact structure extending from a second surface of the base structure into the base structure and in contact with the conductive layer. The contact structure is formed in the same process that forms the second contact portion.

[0110] Thus, the foregoing description of specific embodiments will reveal the general nature of the disclosure such that others may easily modify and / or adapt such specific embodiments for various applications without undue experimentation by applying knowledge within the scope of those skilled in the art without departing from the general concept of the disclosure. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for purposes of description and not limitation, and that the terminology or terminology herein is intended to be interpreted by those skilled in the art in light of the teaching and guidance.

[0111] The embodiments of the present disclosure have been described above with the help of functional building blocks illustrating the implementation of certain functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of description. Alternative boundaries may be defined so long as the certain functions and relationships thereof are appropriately implemented.

[0112] The Summary and Abstract sections may describe one or more (but not all) exemplary embodiments of the disclosure contemplated by the inventors and are therefore not intended to be in any way limiting of the scope of the disclosure and the appended claims.

[0113] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0114] 100 Semiconductor Devices 102 Insulating layer 104 Base Structure 106 Memory Stack 108 Polysilicon layer 110 Conductor layer 112 Dielectric layer 114 Word Line Contact 116 Peripheral Contacts 116-1 First contact part 116-2 Second contact part 118 Insulating Structure 120 Spacer 126 Source Contact 200 Semiconductor Devices 202 Insulating layer 204 Base Structure 206 Memory Stack 208 Polysilicon layer 208-1 Polysilicon sublayer 210 Conductor layer 212 Dielectric layer 214 Word Line Contact 216 Contact structure 216-1 First contact part 216-2 Second contact part 218 Insulating Structure 220 Spacer structure 224 Stop Layer 226 Source Contact Structure 300 Semiconductor Devices 316 Contact structure 316-1 First contact part 316-2 Second contact part 320 Spacer structure 402 Insulating layer 404 Base Structure 406 Memory Stack 408 Polysilicon layer 408-1 Polysilicon Sublayer 410 Conductor layer 412 Dielectric layer 414 Word Line Contact 415 Hole 416 Contact structure 416-1 First contact part 416-2 Second contact part 418 Insulating Structure 420 Spacer structure 424 Stop Layer 425 Another hole 426 Source Contact Structure 515 Second hole 516-1 First contact part 516-2 Second contact part 519 Well Structure 520 Spacer structure 612 Channel Structure 614 Memory Film 616 Semiconductor Channel 618 Capping Layer 620 Channel Plug 622 Insulating spacer 626 Insulating Core

Claims

1. An insulating layer; a conductive layer laminated with the insulating layer, the conductive layer including a first conductive sublayer and a second conductive sublayer; a memory stack disposed on a side of the conductive layer away from the insulating layer; a spacer structure extending through the conductive layer; a contact structure within the spacer structure and extending vertically through the insulating layer, the contact structure including a first contact portion and a second contact portion in contact with one another; a channel structure including a semiconductor channel; Equipped with a lateral cross-sectional area of ​​the second contact portion greater than a lateral cross-sectional area of ​​the first contact portion; a portion of the semiconductor channel contacting the first conductive sublayer, and the second conductive sublayer being disposed between the first conductive sublayer and the memory stack; Semiconductor device.

2. The semiconductor device of claim 1 , wherein the first conductive sublayer and the second conductive sublayer comprise the same material.

3. an insulating spacer extending vertically through the memory stack to the conductive layer; a source contact structure extending vertically through the insulating layer to the conductive layer; Further equipped with 2. The semiconductor device of claim 1, wherein a distance between the source contact structure and the memory stack is greater than a distance between an end of the insulating spacer and the memory stack.

4. 2. The semiconductor device of claim 1 , wherein the memory stack includes alternating stacked conductive and stacked dielectric layers over the conductive layer and away from the contact structure, and the channel structure extends through the memory stack to the conductive layer.

5. The semiconductor device of claim 1 , wherein the channel structure further comprises a memory layer in contact with and surrounding the semiconductor channel.

6. 6. The semiconductor device of claim 5, wherein the memory layer includes a first portion and a second portion, the first conductive sublayer being disposed between the first portion and the second portion.

7. The semiconductor device of claim 1 , wherein the spacer structure comprises a dielectric material.

8. 2. The semiconductor device of claim 1, wherein the first contact portion comprises tungsten and the second contact portion comprises aluminum.

9. An insulating layer; a conductive layer laminated with the insulating layer; a memory stack disposed on a side of the conductive layer away from the insulating layer; a spacer structure extending through the conductive layer; a contact structure within the spacer structure and extending vertically through the insulating layer; an insulating spacer extending through the memory stack perpendicular to the conductive layer; a source contact structure extending vertically through the insulating layer and contacting the conductive layer; Equipped with A semiconductor device, wherein a distance between the source contact structure and the memory stack is greater than a distance between an end of the insulating spacer and the memory stack.

10. 10. The semiconductor device of claim 9, wherein the source contact structures electrically connect sources of memory strings of the semiconductor device.

11. The semiconductor device of claim 9 , wherein the contact structure comprises a first contact portion and a second contact portion in contact with each other.

12. The semiconductor device of claim 11 , wherein a lateral cross-sectional area of ​​the second contact portion is greater than or equal to a lateral cross-sectional area of ​​the first contact portion.

13. 12. The semiconductor device of claim 11, wherein the first contact portion comprises tungsten and the second contact portion comprises aluminum.

14. 12. The semiconductor device of claim 11, wherein the second contact portion of the contact structure and the source contact structure comprise the same material.

15. 10. The semiconductor device of claim 9, further comprising a channel structure including a semiconductor channel, a portion of the semiconductor channel in contact with the conductive layer.

16. An insulating layer; a conductive layer laminated with the insulating layer; a spacer structure extending through the conductive layer; a contact structure within the spacer structure and extending vertically through the insulating layer; a source contact structure extending vertically through the insulating layer and in contact with the conductive layer; Equipped with The spacer structure comprises a dielectric material.

17. 17. The semiconductor device of claim 16, wherein the contact structure comprises a first contact portion and a second contact portion in contact with each other.

18. 20. The semiconductor device of claim 17, wherein a lateral cross-sectional area of ​​the second contact portion is greater than or equal to a lateral cross-sectional area of ​​the first contact portion.

19. 20. The semiconductor device of claim 17, wherein the first contact portion comprises tungsten and the second contact portion comprises aluminum.

20. 20. The semiconductor device of claim 17, wherein the second contact portion of the contact structure and the source contact structure comprise the same material.

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