Semiconductor device and method for manufacturing semiconductor device

Abstract

To reduce the occurrence of defects.SOLUTION: A semiconductor device according to one embodiment includes: a substrate; a first semiconductor chip; an adhesive layer; a second semiconductor chip; a first joint part; and a second joint part. The adhesive layer fixes the substrate to the first semiconductor chip. The second semiconductor chip includes a first region which overlaps with the first semiconductor chip in the first direction being the thickness direction of the substrate, and a second region outside the first region. The first joint part is positioned between the first semiconductor chip and the first region of the second semiconductor chip, and electrically connects the first semiconductor chip to the second semiconductor chip. The second joint part is positioned between the substrate and the second region of the second semiconductor chip, and electrically connects the substrate to the second semiconductor chip. A melting point of the first joint part is lower than a melting point of the second joint part.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor device is known that includes a substrate, a first semiconductor chip, and a second semiconductor chip connected to the substrate and the first semiconductor chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,740,980 Summary of the Invention [Problem to be solved by the invention]

[0004] In one embodiment, the occurrence of defects is reduced. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a substrate, a first semiconductor chip, an adhesive layer, a second semiconductor chip, a first bonding portion, and a second bonding portion. The adhesive layer is provided between the substrate and the first semiconductor chip, and fixes the substrate and the first semiconductor chip. The second semiconductor chip is disposed on the opposite side of the substrate to the substrate, and includes a first region overlapping the first semiconductor chip in a first direction, which is a thickness direction of the substrate, and a second region outside the first region. The first bonding portion is disposed between the first semiconductor chip and the first region of the second semiconductor chip, and electrically connects the first semiconductor chip and the second semiconductor chip. The second bonding portion is disposed between the substrate and the second region of the second semiconductor chip, and electrically connects the substrate and the second semiconductor chip. The melting point of the first bonding portion is lower than the melting point of the second bonding portion. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 2] 1 is an enlarged cross-sectional view showing a portion of the semiconductor device according to the first embodiment; [Diagram 3] 3 is an exploded cross-sectional view showing a part of the semiconductor device shown in FIG. 2. [Figure 4] 3 is an enlarged cross-sectional view showing the area surrounded by line F4 shown in FIG. 2. [Diagram 5] FIG. 4 is a diagram for explaining the melting points of the first bonding portion and the second bonding portion in the first embodiment. [Figure 6] 2A to 2C are diagrams showing the flow of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 6A to 6C are cross-sectional views illustrating a manufacturing method of a modified example of the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a part of a semiconductor device according to a second embodiment. [Figure 12] 6A to 6C are diagrams for explaining a manufacturing method according to a second embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing a part of a semiconductor device according to a third embodiment. [Figure 14] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modified example of the first to third embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to the embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Furthermore, duplicated descriptions of those components may be omitted.

[0008] In this application, the terms are defined as follows: "Parallel", "orthogonal", or "same" may include "substantially parallel", "substantially orthogonal", or "substantially the same", respectively. "Connection" is not limited to mechanical connection, but may include electrical connection. That is, "connection" is not limited to direct connection between two elements to be connected, but may include connection between two elements to be connected via another element. In this application, "width" means "maximum width" when the width varies depending on the position.

[0009] The +X direction, the -X direction, the Y direction, the +Z direction, and the -Z direction are defined as follows. The +X direction, the -X direction, and the Y direction are directions along the first surface 10a of the package substrate 10 described later (see FIG. 2). The +X direction is a direction from a first end 40e1 to a second end 40e2 of the first semiconductor chip 40 described later (see FIG. 2). The -X direction is a direction opposite to the +X direction. When the +X direction and the -X direction are not distinguished, they are simply referred to as the "X direction". The Y direction is a direction intersecting (for example, perpendicular to) the X direction. The +Z direction and the -Z direction are directions intersecting (for example, perpendicular to) the X direction and the Y direction. The +Z direction is the thickness direction of the package substrate 10, and is a direction from the package substrate 10 toward the first semiconductor chip 40 (see FIG. 2). The -Z direction is a direction opposite to the +Z direction. When the +Z direction and the -Z direction are not distinguished, they are simply referred to as the "Z direction". The Z direction is an example of a "first direction." The X direction is an example of a "second direction." The -X direction is an example of a "first side." The +X direction is an example of a "second side."

[0010] (First embodiment) <1. Configuration of semiconductor device> First, a configuration common to the first to third embodiments will be described with reference to FIGS. 1 to 4. FIG. 1 is a cross-sectional view showing a semiconductor device 1A according to a first embodiment. In the following, an example will be described in which the semiconductor device 1A is a semiconductor memory device including a plurality of semiconductor memory components 61. However, the following description does not limit the configuration of the embodiment.

[0011] As shown in FIG. 1, the semiconductor device 1A has, for example, a package substrate 10, a plurality of connection terminals 30, a first semiconductor chip 40, an adhesive layer 50, a second semiconductor chip 60, a plurality of first bonding portions 71, a plurality of second bonding portions 72, an insulating layer 80, and a sealing resin portion 90.

[0012] <1.1 Package substrate> The package substrate 10 is a member forming a base of the semiconductor device 1A. The package substrate 10 is an example of a "substrate." The package substrate 10 has a first surface 10a and a second surface 10b located on the opposite side to the first surface 10a. The first surface 10a faces in the +Z direction. The second surface 10b faces in the -Z direction. The package substrate 10 is a printed circuit board. The package substrate 10 includes, for example, an insulating base material 11, a conductive pattern 12, and a solder resist layer 13.

[0013] The insulating base material 11 is an insulating hard member made of an insulating material such as glass epoxy resin or polyimide, etc. The insulating base material 11 forms the main portion of the package substrate 10.

[0014] The conductive pattern 12 is a conductive portion provided on the surface or inside of the insulating base material 11. The conductive pattern 12 forms wiring of the printed circuit board. The conductive pattern 12 includes a plurality of pads 21 located on the first surface 10a and a plurality of pads 22 located on the second surface 10b. Each of the plurality of pads 21 is an example of a "first pad."

[0015] The solder resist layer 13 is an insulating layer provided on the surface of the package substrate 10. The solder resist layer 13 has a plurality of openings 25 (see FIG. 2). The plurality of openings 25 are provided on the first surface 10a of the package substrate 10, and expose the plurality of pads 21 to the outside of the package substrate 10. The plurality of openings 25 are provided in a one-to-one relationship with the plurality of pads 21. In this application, "exposing the pads" means exposing at least a portion of the pads. In other words, "exposing the pads" may also refer to a case where the central portion of the pads is exposed through the openings while the peripheral edge of the pads is covered with the solder resist layer.

[0016] <1.2 Connection terminal> The multiple connection terminals 30 are terminals exposed to the outside of the semiconductor device 1A. The multiple connection terminals 30 are electrically connected to an external device (not shown) (hereinafter referred to as a "host device") located outside the semiconductor device 1A. The multiple connection terminals 30 are provided on the second surface 10b of the package substrate 10 and bonded to the multiple pads 22. The semiconductor device 1A is, for example, a BGA (Ball Grid Array) type semiconductor package. The multiple connection terminals 30 are multiple solder joints (for example, solder bumps) arranged in the X direction and the Y direction on the second surface 10b of the package substrate 10.

[0017] <1.3 First semiconductor chip> The first semiconductor chip 40 is a semiconductor chip including one or more circuits. The first semiconductor chip 40 includes, for example, at least one of a control circuit for controlling the second semiconductor chip 60 and an interface circuit provided between the package substrate 10 and the second semiconductor chip 60.

[0018] Fig. 2 is an enlarged cross-sectional view showing a part of the semiconductor device 1A. For convenience of explanation, the connection terminals 30, the insulating layer 80, and the sealing resin part 90 are omitted in Fig. 2. Fig. 3 is an exploded cross-sectional view showing a part of the semiconductor device 1A shown in Fig. 2.

[0019] 3, the first semiconductor chip 40 has a first surface 40a and a second surface 40b located on the opposite side to the first surface 40a. The first surface 40a faces in the +Z direction. The second surface 40b faces in the -Z direction. The first semiconductor chip 40 also has a first end 40e1 located on the -X direction side and a second end 40e2 located on the +X direction side.

[0020] The first semiconductor chip 40 also has, for example, an insulating section 41 (see FIG. 4), a wiring layer 42 (see FIG. 4), and a plurality of pads 43. The insulating section 41 is provided, for example, at an end of the first semiconductor chip 40 on the +Z direction side. The wiring layer 42 is provided within the insulating section 41. The plurality of pads 43 are provided on the first surface 40a and are electrically connected to a circuit within the first semiconductor chip 40 via the wiring layer 42. The plurality of pads 43 are arranged side by side in the X direction and the Y direction.

[0021] <1.4 Adhesive layer> Returning to FIG. 2, the adhesive layer 50 will be described. The adhesive layer 50 is an adhesive portion that fixes the package substrate 10 and the first semiconductor chip 40. The adhesive layer 50 is provided, for example, along the second surface 40b of the first semiconductor chip 40. The adhesive layer 50 is provided between the first surface 10a of the package substrate 10 and the second surface 40b of the first semiconductor chip 40, and fixes the first surface 10a of the package substrate 10 and the second surface 40b of the first semiconductor chip 40. The adhesive layer 50 is provided, for example, in an area of ​​more than half of the second surface 40b of the first semiconductor chip 40. For example, the adhesive layer 50 is provided across the first end 40e1 and the second end 40e2 of the first semiconductor chip 40. The adhesive layer 50 is formed, for example, by an adhesive such as a die attach film. The thickness of the adhesive layer 50 in the Z direction is, for example, 10 μm.

[0022] In the following, an example will be described in which a thermosetting adhesive (for example, a thermosetting die attach film) is used as the adhesive layer 50. However, the adhesive layer 50 is not limited to a thermosetting adhesive, and may be formed of a thermosoftening adhesive (for example, a thermosoftening die attach film), etc. In this application, "hardening" is not limited to hardening a thermosetting adhesive by heating it to a predetermined temperature (cure temperature) or higher, but may also include hardening a thermosoftening adhesive by heating it to a predetermined temperature (softening temperature) or higher to soften it, and then cooling it.

[0023] <1.5 Second semiconductor chip> The second semiconductor chip 60 is a semiconductor chip including one or more semiconductor components. The second semiconductor chip 60 includes, for example, one or more semiconductor memory components 61 as the one or more semiconductor components. The semiconductor memory components 61 are an example of a "semiconductor component." The semiconductor memory components 61 may be, for example, a non-volatile semiconductor memory component such as a NAND memory, or a volatile semiconductor memory component such as a DRAM (Dynamic Random Access Memory).

[0024] 2, the second semiconductor chip 60 has a first surface 60a and a second surface 60b located on the opposite side to the first surface 60a. The first surface 60a faces the +Z direction. The second surface 60b faces the -Z direction. The second semiconductor chip 60 also has, for example, a plurality of semiconductor memory components 61, an insulating portion 62, a wiring layer 63 (see FIG. 4), a plurality of small pads 64, and a plurality of large pads 65.

[0025] The semiconductor memory components 61 are arranged, for example, stacked in the Z direction. Each semiconductor memory component 61 has a plurality of electrical connection parts 66a provided separately in the X direction. Each electrical connection part 66a penetrates the semiconductor memory component 61 in the Z direction. The electrical connection part 66a provided on one semiconductor memory component 61 is connected to the electrical connection part 66a provided on another semiconductor memory component 61 adjacent thereto in the Z direction. This forms a plurality of through electrodes (TSV: Through-Silicon Via) 66 that penetrate the semiconductor memory components 61 in the Z direction. The semiconductor memory components 61 are electrically connected to the wiring layer 63 of the second semiconductor chip 60 through the plurality of through electrodes 66.

[0026] The insulating section 62 is a sealing resin section that seals the multiple semiconductor memory components 61. The insulating section 62 forms the outer shape of the second semiconductor chip 60. The wiring layer 63 is provided in the insulating section 62 at the end of the second semiconductor chip 60 on the -Z direction side (see FIG. 4). The multiple small pads 64 and the multiple large pads 65 are provided on the second surface 60b and are electrically connected to the wiring layer 63. The small pads 64 and the large pads 65 will be described in detail later.

[0027] As shown in FIG. 2, the second semiconductor chip 60 is disposed on the opposite side of the package substrate 10 with respect to the first semiconductor chip 40. The width of the second semiconductor chip 60 in the X direction is larger than the width of the first semiconductor chip 40 in the X direction. The second semiconductor chip 60 includes a first region R1 and a second region R2. The first region R1 is a region that overlaps with the first semiconductor chip 40 in the Z direction. The second region R2 is a region outside the first region R1.

[0028] The multiple small pads 64 are provided in the first region R1 of the second semiconductor chip 60, and are arranged side by side in the X and Y directions. The multiple small pads 64 face the multiple pads 43 of the first semiconductor chip 40 one-to-one in the Z direction. The size of the small pads 64 is, for example, the same as the size of the pads 43 of the first semiconductor chip 40. Each of the multiple small pads 64 is an example of a "third pad."

[0029] The multiple large pads 65 are provided in the second region R2 of the second semiconductor chip 60, and are arranged side by side in the X and Y directions. The multiple large pads 65 face the multiple pads 21 of the package substrate 10 in a one-to-one relationship in the Z direction. The large pads 65 are larger than the small pads 64. Each of the multiple large pads 65 is an example of a "second pad."

[0030] <1.6 1st joint> The multiple first bonding portions 71 are electrical connection portions that electrically connect the first semiconductor chip 40 and the second semiconductor chip 60. The multiple first bonding portions 71 are arranged between the first semiconductor chip 40 and the first region R1 of the second semiconductor chip 60. The multiple first bonding portions 71 are arranged side by side in the X direction and the Y direction. Each first bonding portion 71 is connected (joined) to a pad 43 of the first semiconductor chip 40, and is also connected (joined) to a small pad 64 of the second semiconductor chip 60. Each first bonding portion 71 is, for example, a solder bonding portion (for example, a solder bump).

[0031] <1.7 Second joint> The second bonding portions 72 are electrical connection portions that electrically connect the package substrate 10 and the second semiconductor chip 60. The second bonding portions 72 are arranged between the package substrate 10 and the second region R2 of the second semiconductor chip 60. The second bonding portions 72 are arranged side by side in the X direction and the Y direction. The second bonding portions 72 are larger than the first bonding portions 71. Each of the second bonding portions 72 is connected (joined) to a pad 21 of the package substrate 10 and is connected (joined) to a large pad 65 of the second semiconductor chip 60. Each of the second bonding portions 72 is, for example, a solder bonding portion (for example, a solder bump).

[0032] Fig. 4 is an enlarged cross-sectional view of the area surrounded by line F4 in Fig. 2. In this embodiment, pad 21 of package substrate 10 is slightly larger than opening 25 of package substrate 10. Pad 21 has exposed portion 21a exposed in opening 25. A part of second bonding portion 72 is located in opening 25 of package substrate 10 and bonded to exposed portion 21a of pad 21.

[0033] <1.8 Insulating layer> Returning now to FIG. 1, the insulating layer 80 will be described. The insulating layer 80 is an underfill layer provided between the package substrate 10 and the second semiconductor chip 60. The insulating layer 80 is provided, for example, between the first surface 10a of the package substrate 10 and the second surface 60b of the second semiconductor chip 60, and between the first surface 40a of the first semiconductor chip 40 and the second surface 60b of the second semiconductor chip 60. The insulating layer 80 electrically insulates the multiple first bonding portions 71 and electrically insulates the multiple second bonding portions 72.

[0034] <1.9 Sealing resin part> The sealing resin part 90 is a sealing resin part that seals the second semiconductor chip 60 and the insulating layer 80. The sealing resin part 90 integrally covers a part of the first surface 10a of the package substrate 10, the second semiconductor chip 60, and the insulating layer 80. The sealing resin part 90 forms part of the outer shape of the semiconductor device 1A.

[0035] 2. Configuration of the First Embodiment Next, the configuration of the first embodiment will be described. In the first embodiment, the melting point of the first bonding portion 71 is different from the melting point of the second bonding portion 72. This will be described in detail below.

[0036] 5 is a diagram for explaining the melting points of the first bonding portion 71 and the second bonding portion 72. In this embodiment, the material of the first bonding portion 71 is different from the material of the second bonding portion 72, and the melting point of the first bonding portion 71 is lower than the melting point of the second bonding portion 72. For example, the melting point of the first bonding portion 71 is lower than the melting point of the second bonding portion 72 by 5° C. or more. In this embodiment, the melting point of the first bonding portion 71 is lower than the melting point of the second bonding portion 72 by 10° C. or more.

[0037] The material of the first bonding portion 71 is, for example, Sn-Ag (tin-silver alloy). One example of the material of the first bonding portion 71 is Sn-1.8Ag (tin-silver alloy with a tin content of 98.2% and a silver content of 1.8%). The melting point of the first bonding portion 71 is, for example, 227°C. However, the material of the first bonding portion 71 is not limited to the above example.

[0038] The material of the second bonding portion 72 is, for example, Sn-Sb (tin-antimony alloy). One example of the material of the second bonding portion 72 is Sn-10Sb (tin-antimony alloy with a tin content of 90% and an antimony content of 10%). The melting point of the second bonding portion 72 is, for example, 245°C. However, the material of the second bonding portion 72 is not limited to the above example.

[0039] <3. Manufacturing method of semiconductor device> Next, a method for manufacturing the semiconductor device 1A will be described. First, with reference to FIG. 6 to FIG. 8, the common parts between the first to third embodiments will be described. Fig. 6 is a diagram showing a flow of a method for manufacturing the semiconductor device 1A of the embodiment. Fig. 7 and Fig. 8 are cross-sectional views for explaining the method for manufacturing the semiconductor device 1A of the embodiment.

[0040] First, the first semiconductor chip 40 is prepared (S101). The second semiconductor chip 60 is also prepared by manufacturing the first semiconductor chip 40 (S102). For example, the second semiconductor chip 60 is manufactured by stacking a plurality of semiconductor memory components 61, sealing them with an insulating part 62, and providing small pads 64 and large pads 65.

[0041] Next, a step of mounting the first bonding portion 71 and the second bonding portion 72 is performed (S103). In this embodiment, a plurality of first bonding portions 71 are mounted on a plurality of pads 43 of the first semiconductor chip 40. Also, a plurality of second bonding portions 72 are mounted on a plurality of large pads 65 of the second semiconductor chip 60. Note that the plurality of first bonding portions 71 may be mounted on a plurality of small pads 64 of the second semiconductor chip 60 instead of being mounted on the plurality of pads 43 of the first semiconductor chip 40.

[0042] Next, the first semiconductor chip 40 is attached to the package substrate 10 (S104). For example, an adhesive layer (adhesive) 50 is used to fix the second surface 40b of the first semiconductor chip 40 to the first surface 10a of the package substrate 10 (see FIG. 7). Note that the adhesive layer 50 is attached to the package substrate 10 together with the first semiconductor chip 40, for example, in a state in which the adhesive layer 50 is provided first on the second surface 40b of the first semiconductor chip 40. Alternatively, the adhesive layer 50 may be provided on the package substrate 10, and then the first semiconductor chip 40 may be attached to the adhesive layer 50 on the package substrate 10.

[0043] Next, the second semiconductor chip 60 is attached to the package substrate 10 and the first semiconductor chip 40 (S105). For example, in a state where a plurality of first bonding portions 71 are arranged between the first region R1 of the second semiconductor chip 60 and the first semiconductor chip 40, and a plurality of second bonding portions 72 are arranged between the second region R2 of the second semiconductor chip 60 and the package substrate 10, the second semiconductor chip 60 is placed on the first semiconductor chip 40 and the package substrate 10 via the plurality of first bonding portions 71 and the plurality of second bonding portions 72 (see FIG. 8).

[0044] Next, a reflow process is performed (S106). As a result, the small pads 64 of the second semiconductor chip 60 are connected (joined) to the pads 43 of the first semiconductor chip 40 by the first bonding portions 71. Also, the large pads 65 of the second semiconductor chip 60 are connected (joined) to the package substrate 10 by the second bonding portions 72.

[0045] Next, a cleaning process is performed (S107). Next, an insulating material for the insulating layer 80 is supplied to form the insulating layer 80 (S108). Next, an insulating material for the sealing resin portion 90 is supplied to form the sealing resin portion 90 (S109). This completes a series of manufacturing processes.

[0046] <4. Manufacturing method of the first embodiment> FIG. 9 is a cross-sectional view for explaining the manufacturing method of the first embodiment. In the first embodiment, the melting point of the first bonding portions 71 is lower than the melting point of the second bonding portions 72. Therefore, in the reflow process, after the first bonding portions 71 and the second bonding portions 72 are melted, the temperature is gradually lowered to proceed with solidification of the second bonding portions 72 while the first bonding portions 71 remain in a molten state.

[0047] Then, after completing solidification of the plurality of second bonding portions 72, solidification is completed of the plurality of first bonding portions 71. In this application, "completing solidification of the first bonding portions after completing solidification of the second bonding portions" is not limited to the case where solidification of the first bonding portions 71 starts after solidification of the second bonding portions 72 is completed, but may also include the case where solidification of the first bonding portions 71 starts before solidification of the second bonding portions 72 is completed.

[0048] 5. Advantages of the First Embodiment As a first comparative example, a configuration is considered in which the first semiconductor chip 40 is first fixed to the back surface of the second semiconductor chip 60 via a plurality of first bonding parts 71, and after the first semiconductor chip 40 and the second semiconductor chip 60 are integrated, the second semiconductor chip 60 is fixed to the package substrate 10 via a plurality of second bonding parts 72. In such a configuration, a gap of about 30 μm is required as a gap for injecting an insulating material that forms an underfill layer between the first semiconductor chip 40 and the package substrate 10. This makes it difficult to thin the semiconductor device. In addition, a reflow process is required for each of the process of fixing the first semiconductor chip 40 to the back surface of the second semiconductor chip 60 via the plurality of first bonding parts 71 and the process of fixing the second semiconductor chip 60 to the package substrate 10 via the plurality of second bonding parts 72, making it difficult to reduce the manufacturing process.

[0049] On the other hand, in this embodiment, the semiconductor device 1A includes a package substrate 10, a first semiconductor chip 40, an adhesive layer 50, a second semiconductor chip 60, a first bonding portion 71, and a second bonding portion 72. The adhesive layer 50 is provided between the package substrate 10 and the first semiconductor chip 40, and fixes the package substrate 10 and the first semiconductor chip 40. The second semiconductor chip 60 is disposed on the opposite side of the package substrate 10 with respect to the first semiconductor chip 40, and includes a first region R1 that overlaps with the first semiconductor chip 40 in the Z direction, and a second region R2 that is outside the first region R1. The first bonding portion 71 is disposed between the first semiconductor chip 40 and the first region R1 of the second semiconductor chip 60, and electrically connects the first semiconductor chip 40 and the second semiconductor chip 60. The second bonding portion 72 is disposed between the package substrate 10 and the second region R2 of the second semiconductor chip 60, is larger than the first bonding portion 71, and electrically connects the package substrate 10 and the second semiconductor chip 60.

[0050] According to this configuration, the distance in the Z direction between the first semiconductor chip 40 and the package substrate 10 can be reduced to the thickness of the adhesive layer 50 (for example, about 10 μm). This allows the semiconductor device 1A to be made thinner. Furthermore, according to the above configuration, the step of fixing the second semiconductor chip 60 to the first semiconductor chip 40 via the first bonding portion 71 and the step of fixing the second semiconductor chip 60 to the package substrate 10 via the second bonding portion 72 can be performed in a single reflow step. This allows the manufacturing process to be shortened.

[0051] Here, as a second comparative example, a case where the step of fixing the second semiconductor chip 60 and the first semiconductor chip 40 via the first bonding portion 71 and the step of fixing the second semiconductor chip 60 and the package substrate 10 via the second bonding portion 72 are performed in one reflow step as in the present embodiment, and the first bonding portion 71 and the second bonding portion 72 are solidified at the same time will be considered. In this case, if the mounting position of the first semiconductor chip 40 is misaligned with respect to the package substrate 10, a connection failure of the first bonding portion 71 may occur due to a volume difference between the first bonding portion 71 and the second bonding portion 72. That is, the second bonding portion 72 is larger than the first bonding portion 71. Therefore, when the first bonding portion 71 and the second bonding portion 72 are solidified in the reflow step, the tension of the second bonding portion 72 becomes dominant compared to the first bonding portion 71, and a shear force acts to move the second semiconductor chip 60 in the X direction or Y direction relative to the first semiconductor chip 40. Therefore, if the first bonded portion 71 solidifies before the second bonded portion 72, the first bonded portion 71 may break due to the shear force.

[0052] Therefore, in this embodiment, the melting point of the first bonding portion 71 is set lower than the melting point of the second bonding portion 72. With this configuration, the first bonding portion 71 is prevented from solidifying before the second bonding portion 72, and when the shear force acts on the first bonding portion 71 due to the tension of the second bonding portion 72, the first bonding portion 71 can deform in response to the shear force. Therefore, the first bonding portion 71 can be prevented from breaking due to the shear force. This can reduce the occurrence of defects in the semiconductor device 1A.

[0053] In this embodiment, the melting point of the first bonding portion 71 is 5° C. or more lower than the melting point of the second bonding portion 72. With this configuration, even if temperature variations occur within the semiconductor device 1A, it is possible to more reliably prevent the first bonding portion 71 from solidifying before the second bonding portion 72. Note that experiments by the present inventors have confirmed that the temperature variations occurring within the semiconductor device 1A are less than 5° C.

[0054] (Modification of the first embodiment) Next, a modification of the first embodiment will be described. 10 is a cross-sectional view for explaining a manufacturing method of a modified example of the first embodiment. In the above-described embodiment, the melting point of the first bonding portion 71 is lower than the melting point of the second bonding portion 72, so that the solidification of the first bonding portion 71 is completed after the solidification of the second bonding portion 72 is completed.

[0055] Alternatively / in addition to this, in this modification, a heating device HD (e.g., a laser reflow device) is used to create a temperature difference between the second bonding portion 72 and the first bonding portion 71. That is, while the heating device HD maintains the temperature of the first bonding portion 71 or suppresses a decrease in temperature, the temperature of the second bonding portion 72 is lowered to complete the solidification of the second bonding portion 72. With this configuration, the solidification of the first bonding portion 71 can be completed after the solidification of the second bonding portion 72 is completed. Note that in this modification, the melting point of the first bonding portion 71 and the melting point of the second bonding portion 72 may be the same. That is, the material of the first bonding portion 71 and the material of the second bonding portion 72 may be the same.

[0056] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that the adhesive layer 50 allows the first semiconductor chip 40 to tilt in accordance with the second semiconductor chip 60. Note that the configuration other than that described below is the same as the first embodiment.

[0057] <Configuration of the second embodiment> 11 is a cross-sectional view showing a portion of a semiconductor device 1B of the second embodiment. In this embodiment, the second semiconductor chip 60 is disposed at an angle with respect to the package substrate 10. The second semiconductor chip 60 has an end 60e1 on the -X direction side and an end 60e2 on the +X direction side. The distance between the end 60e2 on the +X direction side of the second semiconductor chip 60 and the package substrate 10 is greater than the distance between the end 60e1 on the -X direction side of the second semiconductor chip 60 and the package substrate 10.

[0058] The first semiconductor chip 40 is disposed at an angle with respect to the package substrate 10. The first semiconductor chip 40 has an end 40e1 on the -X direction side and an end 40e2 on the +X direction side. The distance between the end 40e2 on the +X direction side of the first semiconductor chip 40 and the package substrate 10 is greater than the distance between the end 40e1 on the -X direction side of the first semiconductor chip 40 and the package substrate 10. The first semiconductor chip 40 is disposed at an angle of 0.01° or more and 1.00° or less with respect to the package substrate 10 by being supported at an angle by, for example, an adhesive layer 50 described later.

[0059] The adhesive layer 50 has an end 50e1 on the -X direction side and an end 50e2 on the +X direction side. The Z-direction thickness t2 of the end 50e2 on the +X direction side of the adhesive layer 50 is greater than the Z-direction thickness t1 of the end 50e1 on the -X direction side of the adhesive layer 50. The Z-direction thickness t2 of the end 50e2 on the +X direction side of the adhesive layer 50 is 1.1 times or more and 3.0 times or less than the Z-direction thickness t1 of the end 50e1 on the -X direction side of the adhesive layer 50.

[0060] For example, when the thickness in the Z direction of the adhesive layer 50 before deformation is 10 μm, the thickness in the Z direction of the end 50e1 on the -X direction side of the adhesive layer 50 after deformation is 5 μm or more and 7.5 μm or less, and the thickness in the Z direction of the end 50e2 on the +X direction side of the adhesive layer 50 after deformation is 12.5 μm or more and 15 μm or less. Note that "the thickness in the Z direction of the adhesive layer 50 before deformation" may be read as "the thickness in the Z direction at the center in the X direction of the adhesive layer 50 after deformation".

[0061] <Manufacturing method of the second embodiment> In this embodiment, the second semiconductor chip 60 is placed on the package substrate 10 and the first semiconductor chip 40 before the adhesive layer 50 is cured. For example, when the adhesive layer 50 is a thermosetting adhesive, the second semiconductor chip 60 is placed on the first semiconductor chip 40 and the package substrate 10 before the adhesive layer 50 is heated to a cure temperature. As a result, by placing the second semiconductor chip 60 on the first semiconductor chip 40 and the package substrate 10 while the adhesive layer 50 is flexible, the adhesive layer 50 deforms in accordance with the inclination of the second semiconductor chip 60, and the first semiconductor chip 40 tilts in accordance with the inclination of the second semiconductor chip 60.

[0062] 12 is a diagram for explaining the manufacturing method of this embodiment. The second semiconductor chip 60 is placed on the first semiconductor chip 40 and the package substrate 10 in a state where the elastic modulus of the adhesive layer 50 is 1 MPa or less. For example, the second semiconductor chip 60 is placed on the first semiconductor chip 40 and the package substrate 10 in a state where the adhesive layer 50 is heated to a temperature equal to or lower than the cure temperature thereof and within a predetermined temperature range (indicated by a dashed line TR in FIG. 12, for example, 60° C. or more and 100° C. or less) where the elastic modulus of the adhesive layer 50 is 1 MPa or less.

[0063] An example of a method for measuring the elastic modulus (storage elastic modulus) shown in FIG. 12 is as follows. Method: Dynamic viscoelasticity method Equipment: Viscoelasticity measuring equipment Geometry: Parallel disc, diameter 8mm Distortion: 0.1~1.4% Temperature range: Room temperature to 170℃ Heating rate: 10℃ / min Frequency: 1Hz Measurement atmosphere: Nitrogen gas flow

[0064] <Advantages of the second embodiment> As a third comparative example, consider a case where the adhesive layer 50 does not have flexibility when the second semiconductor chip 60 is placed on the first semiconductor chip 40 and the package substrate 10. In this case, when the second semiconductor chip 60 is attached at an angle to the package substrate 10, the gap between the first semiconductor chip 40 and the second semiconductor chip 60 also tilts, and the first semiconductor chip 40 and the second semiconductor chip 60 are close to each other in one part of the gap, and are far apart from each other in another part of the gap. As a result, a connection failure such as a short circuit or an open circuit may occur in the first joint 71.

[0065] Therefore, in this embodiment, the second semiconductor chip 60 is placed on the first semiconductor chip 40 and the package substrate 10 before the adhesive layer 50 is hardened. With this configuration, when the second semiconductor chip 60 is attached at an angle to the package substrate 10, the first semiconductor chip 40 can be allowed to tilt in accordance with the angle of the second semiconductor chip 60. Therefore, in the gap between the first semiconductor chip 40 and the second semiconductor chip 60, it is possible to prevent the first semiconductor chip 40 and the second semiconductor chip 60 from being too close to each other or from being far apart from each other. As a result, it is possible to prevent the first bonding portion 71 from having a connection failure. This makes it possible to reduce the occurrence of defects in the semiconductor device 1B.

[0066] In this embodiment, the second semiconductor chip 60 is placed on the first semiconductor chip 40 and the package substrate 10 in a state where the elastic modulus of the adhesive layer 50 is 1 MPa or less. With such a configuration, the adhesive layer 50 deforms sufficiently greatly, and the first semiconductor chip 40 is likely to tilt significantly following the tilt of the second semiconductor chip 60.

[0067] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment in that the opening 25 of the solder resist layer 13 is formed large so as to allow for misalignment of the second bonding portion 72. Note that the configuration other than that described below is the same as that of the first embodiment.

[0068] <Configuration of the third embodiment> 13 is a cross-sectional view showing a part of a semiconductor device 1C of the third embodiment. In this embodiment, the width W1 in the X direction of the opening 25 of the solder resist layer 13 (the width in the X direction of the exposed portion 21a of the pad 21) is larger than the width W2 in the X direction of the large pad 65 of the second semiconductor chip 60 by 10 μm or more. Furthermore, the width W1 in the X direction of the opening 25 is larger than the width W2 in the X direction of the large pad 65 by, for example, 20 μm or more.

[0069] From another perspective, in the second semiconductor chip 60, the center-to-center distance in the X direction of the multiple small pads 64 is a first distance P1. The first distance P1 is, for example, not less than 10 μm and not more than 70 μm. In one example, the first distance P1 is not less than 30 μm and not more than 50 μm. However, the specific value of the center-to-center distance is not limited to the above example. The width W1 in the X direction of the opening 25 is larger than the width W2 in the X direction of the large pad 65 by at least the first distance P1.

[0070] From another perspective, when the allowable tolerances in the +X and -X directions of the mounting position of the first semiconductor chip 40 on the package substrate 10 are each a deviation S, the width W1 in the X direction of the opening 25 is greater than the width W2 in the X direction of the large pad 65 by more than twice the deviation S. For example, when the deviation S, which is the allowable tolerance in the +X and -X directions, is each 15 μm, the width W1 in the X direction of the opening 25 is greater than the width W2 in the X direction of the large pad 65 by more than 30 μm. An example of the diameter of the solder ball mounted on the large pad 65 to become the second bonding portion 72 is 160 μm.

[0071] In this embodiment, when viewed from the Z direction, the distance D1 in the X direction between the center C1 in the X direction of the opening 25 (the center in the X direction of the exposed portion 21a of the pad 21) and the center C2 in the X direction of the large pad 65 of the second semiconductor chip 60 is greater than the distance D2 in the X direction between the center C3 in the X direction of the pad 43 of the first semiconductor chip 40 and the center C4 in the X direction of the small pad 64 of the second semiconductor chip 60. Note that Fig. 13 illustrates an example in which the distance D2 is zero.

[0072] On the other hand, the width W3 in the X direction of the pad 43 of the first semiconductor chip 40 is the same as the width W4 in the X direction of the small pad 64 of the second semiconductor chip 60. Alternatively, the difference between the width W3 in the X direction of the pad 43 and the width W4 in the X direction of the small pad 64 is less than 10 μm.

[0073] <Manufacturing method of the third embodiment> In this embodiment, the reflow process is performed in a state where the large openings 25 are present in the solder resist layer 13, allowing the second bonding portion 72 to move significantly in the X and Y directions compared to the first bonding portion 71. This allows the second semiconductor chip 60 to be aligned with the package substrate 10 and the first semiconductor chip 40 by self-alignment based on the first bonding portion 71.

[0074] <Advantages of the third embodiment> Here, as a fourth comparative example, a case where the opening 25 of the solder resist layer 13 is not large will be described. In this case, as described above in the second comparative example, when the first bonding portion 71 and the second bonding portion 72 are solidified in the reflow process, the tension of the second bonding portion 72 becomes dominant compared to the first bonding portion 71, and the position of the second semiconductor chip 60 is determined by self-alignment based on the second bonding portion 72. As a result, there is a possibility that a connection failure of the first bonding portion 71 or a short circuit between a plurality of first bonding portions 71 may occur.

[0075] Therefore, in this embodiment, the width W1 in the X direction of the opening 25 of the solder resist layer 13 is greater than the width W2 in the X direction of the large pad 65 of the second semiconductor chip 60 by 10 μm or more. With this configuration, the self-alignment force based on the second bonding portion 72 is weakened, and the positions of the pad 43 of the first semiconductor chip 40 and the small pad 64 of the second semiconductor chip 60 are less likely to shift. As a result, it is possible to suppress the occurrence of connection failures of the first bonding portions 71 or short circuits between a plurality of first bonding portions 71. This makes it possible to reduce the occurrence of defects in the semiconductor device 1C.

[0076] (Modifications of the first to third embodiments) FIG. 14 is a cross-sectional view showing semiconductor devices 1A, 1B, and 1C according to modified examples of the first to third embodiments. As shown in FIG. 14, in this modified example, an insulating layer 80, which is an underfill layer, is not provided. In this modified example, instead of the insulating layer 80, a part of a sealing resin portion 90 is present between the second surface 60b of the second semiconductor chip 60 and the first surface 10a of the package substrate 10, and between the second surface 60b of the second semiconductor chip 60 and the first surface 40a of the first semiconductor chip 40. Even with this configuration, the semiconductor devices 1A, 1B, and 1C similar to those of the first to third embodiments can be obtained.

[0077] The first to third embodiments and their modified examples have been described above. However, the embodiments and modified examples are not limited to the above examples. For example, any two of the first to third embodiments may be combined to realize the present invention, or all of the first to third embodiments may be combined to realize the present invention.

[0078] On the other hand, in the second embodiment, the melting points of the first and second bonding portions 71 and 72 do not have to be different as in the first embodiment, and the opening 25 does not have to be large so as to allow misalignment of the second bonding portion 72 as in the third embodiment. Also, in the third embodiment, the melting points of the first and second bonding portions 71 and 72 do not have to be different as in the first embodiment, and the first semiconductor chip 40 does not have to be arranged at an angle as in the second embodiment.

[0079] In the above-described embodiment, an example has been described in which the second semiconductor chip 60 has a plurality of semiconductor memory components 61. Note that, instead of the above example, the second semiconductor chip 60 may have only one semiconductor memory component 61. Furthermore, the semiconductor components included in the second semiconductor chip 60 are not limited to semiconductor memory components, and may be semiconductor components other than semiconductor memory components. In other words, the configurations of the semiconductor devices 1A, 1B, and 1C are not limited to semiconductor memory devices, and may be widely applicable to various semiconductor devices.

[0080] According to at least one of the above-described embodiments, the semiconductor device of the embodiment includes a substrate, a first semiconductor chip, an adhesive layer, a second semiconductor chip, a first bonding portion, and a second bonding portion. The adhesive layer fixes the substrate and the first semiconductor chip. The second semiconductor chip is disposed on the opposite side of the substrate with respect to the first semiconductor chip, and includes a first region overlapping the first semiconductor chip in the thickness direction of the substrate and a second region outside the first region. The first bonding portion is disposed between the first semiconductor chip and the first region of the second semiconductor chip, and electrically connects the first semiconductor chip and the second semiconductor chip. The second bonding portion is disposed between the substrate and the second region of the second semiconductor chip, and electrically connects the substrate and the second semiconductor chip. The melting point of the first bonding portion is lower than the melting point of the second bonding portion. According to such a configuration, it is possible to reduce the occurrence of defects.

[0081] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0082] 1A, 1B, 1C...semiconductor device, 10...package substrate (substrate), 21...pad (first pad), 25...opening, 40...first semiconductor chip, 43...pad, 50...adhesive layer (adhesive), 60...second semiconductor chip, 61...semiconductor memory component (semiconductor component), 64...small pad (second pad), 65...large pad (first pad), 71...first bonding portion, 72...second bonding portion, R1...first region, R2...second region.

Claims

1. A substrate; A first semiconductor chip; an adhesive layer provided between the substrate and the first semiconductor chip and fixing the substrate and the first semiconductor chip; a second semiconductor chip disposed on the opposite side of the substrate with respect to the first semiconductor chip, the second semiconductor chip including a first region overlapping with the first semiconductor chip in a first direction that is a thickness direction of the substrate, and a second region outside the first region; a first joint portion disposed between the first semiconductor chip and the first region of the second semiconductor chip, the first joint portion electrically connecting the first semiconductor chip and the second semiconductor chip; a second bonding portion that is disposed between the substrate and the second region of the second semiconductor chip, the second bonding portion being larger than the first bonding portion and electrically connecting the substrate and the second semiconductor chip; Equipped with The melting point of the first bonding portion is lower than the melting point of the second bonding portion. Semiconductor device.

2. The melting point of the first bonding portion is lower than the melting point of the second bonding portion by 5° C. or more. The semiconductor device according to claim 1 .

3. When one side in a second direction intersecting the first direction is defined as a first side, and the opposite side to the first side in the second direction is defined as a second side, the second semiconductor chip is disposed at an angle with respect to the substrate, and a distance between an end of the second semiconductor chip on the second side and the substrate is greater than a distance between an end of the second semiconductor chip on the first side and the substrate; the first semiconductor chip is disposed at an angle with respect to the substrate, and a distance between an end of the first semiconductor chip on the second side and the substrate is greater than a distance between an end of the first semiconductor chip on the first side and the substrate; The adhesive layer has a thickness in the first direction at an end on the second side that is greater than a thickness in the first direction at an end on the first side of the adhesive layer.

3. The semiconductor device according to claim 1 or 2.

4. The first semiconductor chip is disposed at an angle of 0.01° or more and 1.00° or less with respect to the substrate. The semiconductor device according to claim 3 .

5. The thickness of the adhesive layer in the first direction at the end of the second side is 1.1 times or more and 3.0 times or less than the thickness of the adhesive layer in the first direction at the end of the first side. The semiconductor device according to claim 3 .

6. the substrate has a first pad and an insulating layer provided on a surface of the substrate and having an opening for exposing the first pad; the second semiconductor chip has a second pad; the second bonding portion is bonded to the first pad and the second pad, When a direction intersecting the first direction is defined as a second direction, The width of the opening in the second direction is greater than the width of the second pad in the second direction by 10 μm or more.

3. The semiconductor device according to claim 1 or 2.

7. a plurality of first bonding portions including the first bonding portion and disposed between the first semiconductor chip and the first region of the second semiconductor chip; the substrate has a first pad and an insulating layer provided on a surface of the substrate and having an opening for exposing the first pad; the second semiconductor chip has a second pad and a plurality of third pads; the second bonding portion is bonded to the first pad and the second pad, the first bonding portions are bonded to the third pads; When a direction intersecting the first direction is defined as a second direction, and a center-to-center distance in the second direction of the third pads is defined as a first distance, The width of the opening in the second direction is greater than the width of the second pad in the second direction by at least the first distance.

3. The semiconductor device according to claim 1 or 2.

8. Fixing the first semiconductor chip to the substrate using an adhesive; a second semiconductor chip is disposed on the opposite side of the substrate from the first semiconductor chip, the second semiconductor chip including a first region overlapping the first semiconductor chip in a first direction that is a thickness direction of the substrate and a second region outside the first region, a first bonding portion is disposed between the first semiconductor chip and the first region, and a second bonding portion larger than the first bonding portion is disposed between the substrate and the second region, and the second semiconductor chip is placed on the first semiconductor chip and the substrate via the first bonding portion and the second bonding portion; a reflow process is performed to connect the first semiconductor chip and the second semiconductor chip by the first bonding portion, and to connect the substrate and the second semiconductor chip by the second bonding portion; Including, In the reflow process, after the second bonding portion is solidified, the first bonding portion is solidified. A method for manufacturing a semiconductor device.

9. The completion of solidification of the first bonding portion after the completion of solidification of the second bonding portion is performed by a melting point of the first bonding portion being lower than a melting point of the second bonding portion. The method for manufacturing a semiconductor device according to claim 8 .

10. Completing the solidification of the first bonded portion after completing the solidification of the second bonded portion is performed by creating a temperature difference between the second bonded portion and the first bonded portion using a heating device. The method for manufacturing a semiconductor device according to claim 8 or 9.

11. placing the second semiconductor chip on the first semiconductor chip and on the substrate before hardening the adhesive; The method for manufacturing a semiconductor device according to claim 8 or 9.

12. The second semiconductor chip is placed on the first semiconductor chip and on the substrate in a heated state so that the adhesive has an elastic modulus of 1 MPa or less. The method for manufacturing a semiconductor device according to claim 8 or 9.

13. the substrate includes a pad to which the second bonding portion is bonded, and an insulating layer provided on a surface of the substrate and having an opening for exposing the pad; When a direction intersecting the first direction is defined as a second direction, the reflow process is performed in a state in which the second bonding portion is allowed to move significantly in the second direction compared to the first bonding portion due to the presence of the opening. The method for manufacturing a semiconductor device according to claim 8 or 9.

14. A substrate; A first semiconductor chip; an adhesive layer provided between the substrate and the first semiconductor chip and fixing the substrate and the first semiconductor chip; a second semiconductor chip disposed on the opposite side of the substrate with respect to the first semiconductor chip, the second semiconductor chip including a first region overlapping with the first semiconductor chip in a first direction that is a thickness direction of the substrate and a second region outside the first region; a first joint portion disposed between the first semiconductor chip and the first region of the second semiconductor chip, the first joint portion electrically connecting the first semiconductor chip and the second semiconductor chip; a second bonding portion that is disposed between the substrate and the second region of the second semiconductor chip, the second bonding portion being larger than the first bonding portion and electrically connecting the substrate and the second semiconductor chip; Equipped with When one side in a second direction intersecting the first direction is defined as a first side, and the opposite side to the first side in the second direction is defined as a second side, the second semiconductor chip is disposed at an angle with respect to the substrate, and a distance between an end of the second semiconductor chip on the second side and the substrate is greater than a distance between an end of the second semiconductor chip on the first side and the substrate; the first semiconductor chip is disposed at an angle with respect to the substrate, and a distance between an end of the first semiconductor chip on the second side and the substrate is greater than a distance between an end of the first semiconductor chip on the first side and the substrate; The adhesive layer has a thickness in the first direction at an end on the second side that is greater than a thickness in the first direction at an end on the first side of the adhesive layer. Semiconductor device.

15. Fixing the first semiconductor chip to the substrate using an adhesive; a second semiconductor chip is disposed on the opposite side of the substrate from the first semiconductor chip, the second semiconductor chip including a first region overlapping the first semiconductor chip in a thickness direction of the substrate and a second region outside the first region, a first bonding portion is disposed between the first semiconductor chip and the first region, and a second bonding portion larger than the first bonding portion is disposed between the substrate and the second region, and the second semiconductor chip is placed on the first semiconductor chip and the substrate via the first bonding portion and the second bonding portion; a reflow process is performed to connect the first semiconductor chip and the second semiconductor chip by the first bonding portion, and to connect the substrate and the second semiconductor chip by the second bonding portion; Including, hardening the adhesive is performed after placing the second semiconductor chip on the substrate and the first semiconductor chip. A method for manufacturing a semiconductor device.

16. A substrate; A first semiconductor chip; an adhesive layer disposed on the opposite side of the first semiconductor chip from the substrate, the adhesive layer fixing the substrate and the first semiconductor chip; a second semiconductor chip disposed on the opposite side of the substrate with respect to the first semiconductor chip, the second semiconductor chip including a first region overlapping with the first semiconductor chip in a first direction that is a thickness direction of the substrate and a second region outside the first region; a first joint portion disposed between the first semiconductor chip and the first region of the second semiconductor chip, the first joint portion electrically connecting the first semiconductor chip and the second semiconductor chip; a second bonding portion that is disposed between the substrate and the second region of the second semiconductor chip, is larger than the first bonding portion, and electrically connects the substrate and the second semiconductor chip; Equipped with the substrate has a first pad and an insulating layer provided on a surface of the substrate and having an opening for exposing the first pad; the second semiconductor chip has a second pad; the second bonding portion is bonded to the first pad and the second pad, When a direction intersecting the first direction is defined as a second direction, The width of the opening in the second direction is greater than the width of the second pad in the second direction by 10 μm or more. Semiconductor device.

17. Fixing the first semiconductor chip to the substrate using an adhesive; a second semiconductor chip is disposed on the opposite side of the substrate from the first semiconductor chip, the second semiconductor chip including a first region overlapping the first semiconductor chip in a first direction that is a thickness direction of the substrate and a second region outside the first region, a first bonding portion is disposed between the first semiconductor chip and the first region, and a second bonding portion larger than the first bonding portion is disposed between the substrate and the second region, and the second semiconductor chip is placed on the first semiconductor chip and the substrate via the first bonding portion and the second bonding portion; a reflow process is performed to connect the first semiconductor chip and the second semiconductor chip by the first bonding portion, and to connect the substrate and the second semiconductor chip by the second bonding portion; Including, the substrate includes a pad to which the second bonding portion is bonded, and an insulating layer provided on a surface of the substrate and having an opening for exposing the pad; When a direction intersecting the first direction is defined as a second direction, the reflow process is performed in a state in which the second bonding portion is allowed to move significantly in the second direction compared to the first bonding portion due to the presence of the opening. A method for manufacturing a semiconductor device.

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