3D bit cost scalable memory

Abstract

To provide a 3D bit cost scalable memory device.SOLUTION: A 3D bit cost scalable memory device includes a stack of layers and a via electrode 150 extending vertically through the stack of layers. The layers include a separator layer 110, a controllable conductivity layer 120 and an electrode layer. The electrode layer has an electrode conductor portion 130 and a separator portion 140 that separates the via electrode from the electrode conductor portion of the electrode layer. At least one storage portion of the controllable conductivity layer is in electrical series between the via electrode and the electrode conductor portion of the electrode layer. The via electrode comprises, for example, tungsten (W). The controllable conductivity layer comprises, for example, an ovonic threshold switch material. The electrode conductor portion of the electrode layer comprises, for example, carbon (C).SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] This disclosure relates to memory cells, including memory cells used in integrated circuits. [Background technology]

[0002] Memory cells (such as those used in integrated circuits) benefit from performance improvements, such as reduced latency, increased bandwidth, and / or reduced power consumption. Memory cells further benefit from cost improvements, such as increased density. For example, scaling of DRAM has slowed, resulting in stalled performance and / or cost improvements. Summary of the Invention

[0003] One or more computer systems can be configured to perform particular operations or actions by having installed thereon software, firmware, hardware, or a combination thereof that causes the system to perform and / or control such actions in operation. One or more computer programs can be configured to perform particular operations or actions by containing instructions that, when executed by a data processing device, cause the device to perform such actions.

[0004] A first aspect includes a memory device comprising a stack of layers, the layers optionally having a controllably conductive layer and an electrode layer adjacent the controllably conductive layer; and a via electrode extending vertically through the stack, the electrode layer optionally including a conductor portion and a separator portion separating the via electrode from the conductor portion, and at least one storage portion of the controllably conductive layer being electrically continuous between the via electrode and the conductor portion.

[0005] Variations optionally include one or more of the following features, alone or in any combination: the stack of layers has an internal sidewall defining a hole for accommodating the via electrode; the controllable conductive layer comprises an Ovonic Threshold Switch (OTS) material; the conductor portion optionally comprises carbon (C) in combination with a metallic material; the conductor portion optionally comprises a material selected from the group of materials consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co) and ruthenium (Ru); the via electrode optionally comprises tungsten (W); the via electrode optionally comprises titanium nitride (TiN); the separator portion optionally comprises a dielectric material; the via electrode is one of a plurality of via electrodes each extending vertically through the stack, and the stack has a plurality of internal sidewalls defining a hole for accommodating each of the plurality of via electrodes. The controllable conductive layer is one of a plurality of controllable conductive layers, the electrode layer is one of a plurality of electrode layers, each controllable conductive layer of the plurality of controllable conductive layers being adjacent to a respective one of the plurality of electrode layers, the layer optionally having an isolation layer, at least one of the isolation layers separating each controllable conductive layer of the plurality of controllable conductive layers from other controllable conductive layers of the plurality of controllable conductive layers, and at least one of the isolation layers separating each electrode layer of the plurality of electrode layers from other electrode layers of the plurality of electrode layers, the conductor portion is one of a plurality of conductor portions, the separator portion is one of a plurality of separator portions, each electrode layer of the plurality of electrode layers optionally including a respective one of the plurality of conductor portions and optionally including a respective separator portion of the plurality of separator portions corresponding to each via electrode of the plurality of via electrodes, the plurality of separator portions separating the via electrodes from the plurality of conductor portions.The memory portion is a specific memory portion, and each memory portion of at least one of the controllable conductive layers adjacent to each electrode layer corresponding to each via electrode of the plurality of via electrodes and each electrode layer of the plurality of electrode layers is electrically continuous between the conductor portion of each via electrode and each electrode layer, and the specific memory portion is one of the memory portions. Each conductor portion of the plurality of conductor portions is operable as a respective word line of a memory array, and each via electrode of the plurality of via electrodes is operable as a respective bit line of the memory array, and each memory portion is usable as a non-volatile storage for storing a portion of information of the memory array, the information being decomposable into one or more bits of binary information accessible using the word lines and bit lines between which the memory portions are electrically continuous. The memory device is suitable for implementing non-volatile storage in a solid state disk (SSD), implementing storage class memory (SCM), and / or implementing a memory compatible with Compute Express Link (CXL).

[0006] A second aspect includes a method of forming a memory device comprising forming a stack of layers, the layers having a controllably conductive layer and an electrode layer adjacent the controllably conductive layer; and forming a via electrode extending vertically through the stack, the electrode layer optionally including a conductor portion and a separator portion, the separator portion separating the via electrode from the conductor portion, and at least one storage portion of the controllably conductive layer being electrically continuous between the via electrode and the conductor portion.

[0007] Variations optionally include one or more of the following features, alone or in any combination: The method, wherein the forming the via electrode optionally comprises forming a hole through the stack, the hole defining a dimension of the via electrode through the layer; The electrode layer is formed by forming an undercut in the electrode layer, the undercut surrounding the hole, the undercut defining a volume for the separator portion; The electrode layer is formed by forming the separator portion in the undercut; The controllable conductive layer optionally comprises an Ovonic Threshold Switch (OTS) material, and the conductor portion optionally comprises Carbon (C).

[0008] A third aspect comprises a method comprising a processor and a memory enabled to store instructions executable by the processor that, when executed by the processor, cause the processor to perform operations to form a memory device.

[0009] Variations of the above-described aspects optionally include hardware, methods or processes, or computer software on a computer-accessible medium.

[0010] Other aspects and advantages of the disclosure will become apparent from the drawings, detailed description, and claims. [Brief description of the drawings]

[0011] [Figure 1A] 3D diagrams of various aspects of memory cells of a 3D bit-cost scalable memory are shown. [Figure 1B] 1A-1D show cross-sectional views of various embodiments of memory cells of a 3D bit-cost scalable memory. [Figure 1C] 1A-1D show top views of various embodiments of memory cells of a 3D bit-cost scalable memory.

[0012] [Diagram 2] 1A-1D show schematic diagrams of various embodiments of memory cells of a 3D bit-cost scalable memory.

[0013] [Diagram 3] 1A-1D show 3D views of various aspects of memory arrays of a 3D bit-cost scalable memory.

[0014] [Figure 4] 1 shows a time sequence snapshot of an example of the fabrication of 3D bit-cost scalable memory. [Diagram 5] 1 shows a time sequence snapshot of an example of the fabrication of 3D bit-cost scalable memory. [Figure 6] 1 shows a time sequence snapshot of an example of the fabrication of 3D bit-cost scalable memory. [Figure 7] 1 shows a time sequence snapshot of an example of the fabrication of 3D bit-cost scalable memory. [Figure 8] 1 shows a time sequence snapshot of an example of the fabrication of 3D bit-cost scalable memory.

[0015] [Figure 9] 1 shows a flow diagram for a technique for fabricating one or more regions of a 3D bit-cost scalable memory. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] With reference to FIGS. 1A-1C and 2-9, a detailed description of the technology for 3D bit-cost scalable memory is provided.

[0017] One or more flow diagrams are described herein. The processes described by these flow diagrams can be implemented and / or instructed using a processor, which is programmed using a computer program stored in a memory accessible to a computer system and executable by the processor, using dedicated logic hardware (including field programmable integrated circuits), and various combinations thereof. Various actions can be combined, performed in parallel, and / or performed in different sequences without affecting the process performed. In some cases, rearranging the actions achieves the same result only if certain other changes are made in addition. In other cases, rearranging the actions achieves the same result only if certain conditions are met. Furthermore, for clarity, some of the flow diagrams herein omit certain actions that are not necessary to understand the disclosed technology. Various additional actions can be performed before, after, and / or between the actions illustrated.

[0018] Below are examples of selected acronyms, mnemonics, and abbreviations used within the description. [Table 1] 3D bit-cost scalable memory concept

[0019] The 3D bit-cost scalable memory described herein comprises structures for forming non-volatile memory cells. These memory cells are enabled to store information, such as one or more bits of information per memory cell. The memory cells are formed at the intersections of vertical bit lines and horizontal word planes, providing information storage at these intersections. Each memory cell is formed by an active layer pair. An isolation layer separates the memory cells in the vertical dimension.

[0020] The wordline plane is formed from thin film layers deposited in the wafer plane, with the vertical bitlines perpendicular to the wafer plane.

[0021] To fabricate electronic devices comprising one or more of the 3D bit-cost scalable memories described herein, integrated circuit fabrication techniques such as those based on planar processing of silicon wafers can be used.

[0022] Some 3D bit-cost scalable memories described herein enable DRAM-comparable access latencies (e.g., faster than 3D NAND-based memories) and densities (e.g., higher density than DRAM) that are comparable to 3D NAND-based memories. Some 3D bit-cost scalable memories described herein enable reduced costs of memory fabrication compared to other memory fabrication techniques.

[0023] Throughout the description and associated drawings herein, like numbered elements correspond to identical elements, substantially similar elements, and / or examples thereof. For example, via electrode 150 in FIG. 1A is identical to via electrode 150 in FIG. 1B. For another example, completed separator layer 510 in FIG. 5 is identical to completed separator layer 510 in FIG. 6.

[0024] Throughout the figures, unless otherwise indicated, similarly stippled elements correspond to elements that include the same or substantially the same type of material (such as the same or substantially similar chemical composition and / or structure). For example, the stipples of controllably conductive layer 420 in Figure 4 are identical to those of completed controllably conductive layer 520 in Figure 5, indicating that controllably conductive layer 420 and completed controllably conductive layer 520 are made of substantially similar materials, such as OTS materials.

[0025] 1A to 1C show various embodiments of memory cells of a 3D bit-cost scalable memory. FIG. 1A shows a 3D view of a portion of the 3D bit-cost scalable memory. There are six instances of via electrodes 150. There are five instances of separator layers 110, four instances of controllably conductive layers 120, and four instances of electrode layers including electrode conductor portions 130 and separator portions 140. At each intersection between instances of via electrodes 150 and electrode conductor portions 130, there is one instance of a separator portion 140.

[0026] FIG. 1B shows a side view of a portion of a 3D bit-cost scalable memory. This view corresponds to cross section BB of FIG. 1C. The top and bottom layers of the stack are instances of separator layers 110. Each instance of a controllable conductive layer 120 is adjacent to a corresponding layer comprising an instance of an electrode conductor portion 130 and an instance of a separator portion 140. Each instance of a separator portion 140 surrounds a portion of one of the instances of a via electrode 150. The instances of separator layers 110 form the top and bottom layers, and further instances of separator layers 110 form separators between the layer formed from the electrode conductor portion 130 in combination with the separator portion 140 and the controllable conductive layer 120. Brackets 199 indicate that any number of repetitions of the three-layer stack of (1) the controllable conductive layer 120, (2) the electrode layer formed from the electrode conductor portion 130 in combination with the separator portion 140, and (3) the separator layer 110 are possible. For example, the electrically continuous (memory) portions of the example controllably conductive layer 120 between the example via electrodes 150 and the example electrode conductor portions 130 each provide information storage.

[0027] 1C shows a top view of a portion of a 3D bit-cost scalable memory, which corresponds to cross section AA of FIG. 1B. An example of a via electrode 150 surrounded by an example of a separator portion 140 is disposed within an example of an electrode conductor portion 130.

[0028] FIG. 2 shows a schematic diagram of various aspects of a memory cell of a 3D bit-cost scalable memory. For clarity, structures associated with two bit lines (bit lines 250 and 251) are shown. Bit line 250 is coupled to multiple memory cells in parallel. An exemplary memory cell is shown as memory cell 280. Bit line 250 is coupled to a source line selector (not shown) via To source line selector (SLS) 290. Bit line 251 is coupled to a source line selector (not shown) via To source line selector (SLS) 291. Any number of memory cells may be implemented, as indicated by bracket 299. Bracket 299 conceptually corresponds to bracket 199 of FIG. 1B.

[0029] 1B , such as a two-layer stack of electrode layers formed from (1) controllably conductive layer 120 and (2) electrode conductor portion 130 in combination with separator portion 140. As a specific example, memory cell 280 is implemented by a portion of an instance of controllably conductive layer 120 that is electrically continuous between an instance of via electrode 150 and an instance of electrode conductor portion 130.

[0030] A word plane is associated with each memory cell. The word planes are shown as word planes 260, 261, 268, and 269. Each word plane corresponds to an example of the electrode conductor portion 130 of FIG. 1B. Each word plane is associated with a number of bit lines, as shown, for example, by word plane 260 being coupled to memory cells of bit lines 250 and 251. Each of bit lines 250 and 251 corresponds to an example of the via electrode 150 of FIG. 1B.

[0031] Bracket 299 indicates that any number of repetitions of the three-layer stack of (1) controllably conductive layer 120, (2) electrode layer formed from electrode conductor portion 130 in combination with separator portion 140, and (3) separator layer 110 are possible.

[0032] FIG. 3 shows a 3D view of various aspects of a memory array of a 3D bit-cost scalable memory. Bit line (BL) 350 is an exemplary implementation of via electrode 150 of FIG. 1B and is also an example of bit line 250 of FIG. 2, for example. Bit line selector (BLS) connection 370 is an implementation of connections for bit line (BL) 350. OTS layer 320 is an exemplary implementation of controllable conductive layers 120 of FIG. 1B. Source line selector (SLS) 392 is an example of a source line selector coupled, for example, to source line selector (SLS) 290 of FIG. 2. Source line (SL) 391 is coupled to source line selector (SLS) 392. OTS and SL connection 321 are an example of connections to other elements (e.g., drivers, not shown). Contact 398 is an example of a contact between source line (SL) 391 and other elements (e.g., source ground, not shown). Exemplary Fabrication of 3D Bit-Cost Scalable Memory

[0033] Figures 4 through 8 show time-series snapshots of an example of the fabrication of a 3D bit-cost scalable memory. The time-series progresses monotonically in time, beginning with Figure 4 and ending with Figure 8. Each of the snapshots is a cross-sectional view.

[0034] FIG. 4 shows a first of a time series of snapshots. A fabrication process equipment performs thin film deposition of three alternating planar material layers. Two of the layers are active layer pairs. One of the layers is a separator layer. The first layer of the active layer pair is represented by a controllable conductive layer 420. The second layer of the active layer pair is represented by an electrode conductor layer 430. The separator layer is represented by separator layer 410. The separator layer separates each active layer pair from the other active layer pairs.

[0035] The thin film deposition begins with the fabrication processing equipment depositing a first layer (e.g., a base layer) as a separator layer 410, such as on a top portion of a substrate (e.g., on a top portion of a silicon-based wafer). Continuing in the thin film deposition, the fabrication processing equipment deposits a second layer as a controllably conductive layer 420, such that the controllably conductive layer 420 is adjacent to and coplanar with the separator layer 410. Continuing in the thin film deposition, the fabrication processing equipment deposits a third layer as an electrode conductor layer 430, such that the electrode conductor layer 430 is adjacent to and coplanar with the controllably conductive layer 420.

[0036] Continuing with the thin film deposition, fabrication processing equipment deposits further instances of separator layers 410, controllably conductive layers 420, and electrode conductor layers 430 until a predetermined number of layers have been deposited. In various exemplary 3D bit-cost scalable memories, there are various examples of numbers of layers, such as 300 layers (e.g., 100 active layer pairs and 100 separator layers) or 3000 layers.

[0037] After thin film deposition, fabrication processing equipment performs further processing on the material layers to form a plurality of 3D bit-cost scalable memory cells (as shown in Figures 4 through 8).

[0038] In some exemplary fabrications of 3D bit-cost scalable memories, the first instance of the separator layer 410 is omitted and a first instance of the controllably conductive layer 420 is deposited directly on the substrate. As shown, the last layer deposited is an instance of the separator layer 410. Alternatively, the last layer deposited can be an instance of the controllably conductive layer 420 or an instance of the electrode conductor layer 430, among other variations.

[0039] In various constructions, the materials used and / or their thicknesses may vary, such as (a) being the same for all instances of separator layer 410, (b) being the same for all but the first instance of separator layer 410, (c) being the same for all but the last instance of separator layer 410, or (d) being the same for all but the first and last instances of separator layer 410.

[0040] Please refer to thin film deposition 904 in FIG. 9 and the associated discussion paragraphs regarding FIG. 4 for additional explanation.

[0041] FIG. 5 shows a second of the time series snapshots. The fabrication process equipment performs an etch to form a plurality of parallel holes perpendicular to the planar material layer. The holes extend through the layer. Each hole establishes a respective internal sidewall that extends through the layer. The holes are represented by respective instances of holes 550 (for via electrodes 850). Etching the example holes 550 transforms the examples of separator layer 410, controllable conductive layer 420, and electrode conductor layer 430 shown in FIG. 4 into the examples of completed separator layer 510, completed controllable conductive layer 520, and electrode conductor layer 530 shown in FIG. 5, respectively. In some variations, the holes extend through all layers except the first example of separator layer 410. In some variations, the holes extend through all layers including the first example of separator layer 410.

[0042] Please refer to hole opening etch 905 in FIG. 9 and the associated description paragraph regarding FIG. 5 for additional explanation.

[0043] FIG. 6 shows a third of the time series snapshots. The fabrication process equipment performs an etch to form undercuts in the instance of electrode conductor layer 530 to form an instance of completed electrode conductor portion 630 and a corresponding instance of electrode separator undercut 640. Within each instance of electrode conductor layer 530, there is an instance of electrode separator undercut 640 for each instance of hole 550. At this stage of fabrication, the instances of hole 550 and electrode separator undercut 640 are conceptual. They are conceptual in that for each instance of hole 550, the adjacent instances of electrode separator undercut 640 form a single 3D void in conjunction with the respective instance of hole 550. In the drawing, the adjacentness of the instances of hole 550 and electrode separator undercut 640 is indicated by dashed lines.

[0044] As one specific example, in the context of a circular hole 550, each instance of electrode separator undercut 640 is a ring-shaped volume of material that is further removed from electrode conductor layer 530 to form a completed electrode conductor portion 630.

[0045] The holes 550, the completed separator layer 510, and the completed controllable conductive layer 520 are not affected by the undercut etch.

[0046] Please refer to undercut etching 906 in FIG. 9 and the associated discussion paragraph regarding FIG. 6 for additional explanation.

[0047] 7 shows a fourth of the time series snapshots. The fabrication process equipment performs a deposition of separator material into the example electrode separator undercuts 640 and holes 550, and then etches back the separator material to form an example completed separator portion 740. Thus, after the deposition of the separator material, the respective interior sidewalls established by the hole opening etch (e.g., as shown and described with respect to FIG. 5) are effectively restored.

[0048] The completed electrode conductor portion 630, the holes 550, the completed separator layer 510, and the completed controllably conductive layer 520 examples are not affected by the deposition of separator material.

[0049] See deposition and etch back 907 in FIG. 9 and the associated description paragraph for additional explanation regarding FIG.

[0050] 8 shows the fifth of the time series snapshots: Fabrication processing equipment performs deposition of via electrode material (e.g., via metal deposition) to (globally) fill the example hole 550, and then performs CMP to form the example via electrode 850.

[0051] The examples of completed separator layer 510, completed controllable conductive layer 520, completed electrode conductor portion 630, and completed separator portion 740 are not affected by the deposition of via electrode material.

[0052] Thus, Fig. 8 shows a completed portion of the 3D bit-cost scalable memory. Figs. 4 to 8 show an example of the fabrication of the 3D bit-cost scalable memory shown in Figs. 1A to 1C. The examples of completed separator layer 510, completed controllable conductive layer 520, completed electrode conductor portion 630, completed separator portion 740, and via electrode 850 in Fig. 8 correspond to the examples of separator layer 110, controllable conductive layer 120, electrode conductor portion 130, separator portion 140, and via electrode 150 in Figs. 1A to 1C, respectively.

[0053] Please refer to via deposition and CMP run 908 in FIG. 9 and the associated description paragraph for additional explanation regarding FIG. Exemplary Fabrication Flow for 3D Bit-Cost Scalable Memory

[0054] A device comprising a 3D bit-cost scalable memory is fabricated from a wafer, such as, for example, a semiconductor (e.g., silicon) wafer. The wafer has a top surface that is compatible with fabrication by processing across the top surface of the wafer. This fabrication can be performed in a semiconductor manufacturing facility. This processing results in one or more regions of the 3D bit-cost scalable memory element, and optionally other regions. These other regions optionally include circuitry for using the 3D bit-cost scalable memory element as a memory device, such as one or more processors, interfaces, and / or circuits enabled to interoperate with the memory. These other regions optionally include circuitry for using the 3D bit-cost scalable memory device within a system and / or elements of the system itself.

[0055] FIG. 9 shows a flow diagram for a technique for fabricating one or more regions of a 3D bit-cost scalable memory element such as those shown in any of the previous figures.

[0056] The operations comprise deposition and etching of materials to form a 3D bit-cost scalable memory. The etching is guided using one or more masks, such as, for example, photomasks. The etching optionally has an intermediate action of depositing a layer of photosensitive material, which is selectively removed (or retained) based on selectively exposing the photosensitive material to electromagnetic radiation (e.g., ultraviolet light) through the photomask. Different photomasks are used for the different actions shown in the figures. For clarity, specific references to photomasks are omitted in the following description of the figures.

[0057] The fabrication processing equipment first deposits three alternating multi-planar thin film layers (thin film deposition 904), such as the example separator layer 410, controllably conductive layer 420, and electrode conductor layer 430 of Figure 4. The thin film layers are alternated such that an active layer pair is formed, followed by an isolation layer, which separates the next active layer pair formed, and so on until the desired number of layers is formed.

[0058] A first deposit (e.g., the first instance of the separator layer 410) covers at least substantially the entire area of ​​the top surface of the wafer that will become the vertical 3D bit-cost scalable memory elements. A second deposit (e.g., the controllable conductive layer 420 adjacent to the separator layer 410) covers at least substantially the entire top surface of the first deposit. A third deposit (e.g., the electrode conductor layer 430 adjacent to the controllable conductive layer 420) covers at least substantially the entire top surface of the second deposit, and so on. The isolation layers (corresponding to the first deposit, the fourth deposit, etc.) serve to isolate (e.g., electrically and / or thermally) the active layer pairs from other ones of the active layer pairs. The isolation layers (e.g., the separator layer 410) optionally comprise the same material, e.g., a specific dielectric (e.g., silicon nitride or silicon oxide). The active layer pairs (corresponding to the second and third stacks, the fifth and sixth stacks, etc.) serve to form a portion of the active circuitry of the 3D bit-cost-scalable memory element. The first of the active layer pairs (e.g., the controllable conductive layer 420) comprises a controllable conductive material, such as a specific OTS material. The second of the active layer pairs (e.g., the electrode conductor layer 430) comprises a conductive material, such as a material having carbon (C). The deposition continues until a target number of layers are deposited, for example, a total of 3*8, 3*32, 3*64, 3*1024 layers (corresponding to 8, 32, 64, and 1024 active layer pairs) are formed.

[0059] Thin film deposition can be carried out using CVD.

[0060] The fabrication processing equipment then forms holes for the next material deposition to form (deep) via electrodes, such as the example of holes 550 in FIG. 5 (hole open etch 905). These holes are for the next material deposition for the central electrode. The hole formation can be performed by etching, for example using RIE techniques. In some variations, an etch stop layer is used to determine the depth of the hole etching, for example to prevent etching too deep.

[0061] The fabrication processing equipment then forms conductor portions (of the electrode conductor layers), such as that shown by finished electrode conductor portion 630 in Figure 6, by etching undercuts (such as that shown by electrode separator undercut 640 in Figure 6) into each of the electrode conductor layers (undercut etch 906).

[0062] The undercut etch can be performed using wet or dry etching techniques. One exemplary etching technique is O2 plasma etching. Another exemplary etching technique is N2 plasma etching. The extent of the undercut can be controlled by controlling the etch time.

[0063] The fabrication processing equipment then forms a separator portion (of the electrode conductor layer), such as that shown by finished separator portion 740 in FIG. 7. This formation is by material deposition and then etching (deposition and etch back 907). In the material deposition, the undercuts and holes are filled with separator material. In the etch, the separator material is then removed (e.g., reduced) to reform the originally formed holes, such as those in hole opening etch 905 (e.g., as shown by finished separator portion 740 in FIG. 7).

[0064] The material deposition can be performed by ALD techniques. In some variations, the etching can be performed by RIE techniques.

[0065] The fabrication processing equipment then forms the (deep) via electrodes by material deposition and then polishing (via deposition and CMP run 908) in which the holes first formed by hole opening etch 905 and then reformed by deposition and etch back 907 are filled with via electrode material. Polishing removes material, for example, thereby exposing the topmost separator layer.

[0066] The material deposition can be performed by CVD techniques. The polishing can be performed by CMP techniques.

[0067] This completes the process for fabricating a 3D bit-cost scalable memory element.

[0068] In some fabrication flows, additional processing occurs before, after, and / or fully or partially concurrently with any one or more of the actions shown in Figure 9. For example, the additional processing is for circuitry related to using the 3D bit-cost scalable memory element as a memory device, using the memory device in a system, and / or forming one or more components of the system. Materials for 3D bit-cost scalable memory

[0069] Suitable materials for the (deep) via electrode include one or more conductive materials such as tungsten (W) and titanium nitride (TiN), either alone, in any combination with each other, or acting as the basis for a material that is combined with one or more other materials.

[0070] Suitable materials for the conductive portions of the electrode layers include one or more conductive materials such as carbon (C), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co), and ruthenium (Ru), either alone, in any combination with each other, or acting as the basis of a material made up of one or more other materials. Some conductive portions include carbon (C) in combination with metallic materials such as tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), and ruthenium (Ru).

[0071] Suitable materials for the controllably conductive material include arsenic (As), selenium (Se), silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), and indium (In), either alone, in any combination with each other, or acting as the basis of a material made in combination with one or more other materials. For various examples, one or more of the OTS elements are made from chalcogenides including: (i) As, Se, and Ge (e.g., AsSeGe), (ii) AsSeGe and Si (e.g., AsSeGeSi), (iii) AsSeGeSi and In (e.g., AsSeGeSiIn), and (iv) AsSeGeIn.

[0072] Suitable materials for the separation layer and / or for the separator portion of the electrode layer include one or more dielectric materials such as silicon nitride or silicon oxide. 3D bit-cost scalable memory devices and systems

[0073] Some devices (e.g., integrated circuits, one or more system-on-chip dies, and / or packaged dies) comprise one or more arrays of 3D bit-cost scalable memory cells (as described elsewhere herein) with additional circuitry for implementing a memory device that can be used as a standalone device and / or as a component within a system. This additional circuitry provides interface and control functions to allow the 3D bit-cost scalable memory cell array to be realized in various organized ways as one or more planes, each plane comprising one or more blocks, each block having one or more pages.

[0074] The additional circuitry may comprise various hardware circuits such as bit line circuitry, sense amplifiers, page cache / buffers, interface circuits, word line decoders / drivers, controllers, and / or bias circuits (such as voltage and / or current sources).

[0075] In some variations, the additional circuitry enables the array of 3D bit-cost scalable memory cells to be used as DRAM and / or SCM in alternative and / or additional elements in a system, such as packaged in a DIMM or SODIMM. In some variations, the additional circuitry enables the array of 3D bit-cost scalable memory cells to be coupled to a CPU and / or GPU by high performance communication techniques such as CXL. In some variations, the additional circuitry enables the array of 3D bit-cost scalable memory cells to be used in one or more portions of a memory and / or storage hierarchy, such as in components equivalent to SSDs and / or DRAMs.

[0076] In some variations, additional circuitry enables the array of 3D bit-cost scalable memory cells to be used as various alternative and / or additional non-volatile memory elements in a system, such as one packaged within and / or operated as an NVDIMM. More information on 3D bit-cost scalable memory

[0077] 1A-1C and 2-9 disclose various aspects of an exemplary 3D bit-cost scalable memory technology that uses controlled conductive layers, such as those including OTS materials, to provide non-volatile information storage.

[0078] While the present invention has been disclosed with respect to preferred embodiments and examples described above, it should be understood that these examples are intended in an illustrative and not a limiting sense. Modifications and combinations will readily occur to those skilled in the art, and are within the spirit of the invention and the scope of the following claims.

Claims

1. a stack of layers, the layers having a controllably conductive layer and an electrode layer adjacent the controllably conductive layer; and A via electrode extending vertically through the stack Equipped with the electrode layer includes a conductor portion and a separator portion that separates the via electrode from the conductor portion; At least one memory portion of the controllable conductive layer is electrically continuous between the via electrode and the conductor portion. Memory device.

2. The memory device of claim 1 , wherein the stack of layers has interior sidewalls defining holes for accommodating the via electrodes.

3. The memory device of claim 1 , wherein the controllable conductive layer comprises an Ovonic Threshold Switch (OTS) material.

4. The memory device of claim 1 , wherein the conductor portion comprises carbon (C) in combination with a metallic material.

5. 2. The memory device of claim 1, wherein the conductor portion comprises a material selected from the group of materials consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co), and ruthenium (Ru).

6. The memory device of claim 1 , wherein the via electrode comprises tungsten (W).

7. The memory device of claim 1 , wherein the via electrode comprises titanium nitride (TiN).

8. The memory device of claim 1 , wherein the separator portion comprises a dielectric material.

9. the via electrode being one of a plurality of via electrodes each extending vertically through the stack; the stack having a plurality of interior sidewalls defining an aperture for receiving each via electrode of the plurality of via electrodes. A memory device according to any one of claims 1 to 8.

10. the controllably conductive layer is one of a plurality of controllably conductive layers; the electrode layer is one of a plurality of electrode layers, each controllably conductive layer of the plurality of controllably conductive layers being adjacent to a respective one of the plurality of electrode layers; The memory device of claim 9.

11. the layer further comprises a separation layer; at least one of the isolation layers separates each controllably conductive layer of the plurality of controllably conductive layers from other controllably conductive layers of the plurality of controllably conductive layers; at least one of the separation layers separates each electrode layer of the plurality of electrode layers from other electrode layers of the plurality of electrode layers; The memory device of claim 10.

12. the conductor portion is one of a plurality of conductor portions; the separator portion is one of a plurality of separator portions; Each electrode layer of the plurality of electrode layers includes a respective one of the plurality of conductor portions, and includes a respective separator portion of the plurality of separator portions corresponding to each via electrode of the plurality of via electrodes; the separator portion separates the via electrode from the conductor portion; The memory device of claim 10.

13. the storage portion is a specific storage portion, Corresponding to each via electrode of the plurality of via electrodes and each electrode layer of the plurality of electrode layers, at least one memory portion of the controllable conductive layer adjacent to each electrode layer is electrically continuous between each via electrode and the conductor portion of each electrode layer; the particular storage portion being one of the storage portions; The memory device of claim 12.

14. each conductor portion of the plurality of conductor portions operable as a respective word line of a memory array; Each via electrode of the plurality of via electrodes is operable as a respective bit line of the memory array; each memory portion is operable as non-volatile storage for storing a portion of information of said memory array, said information being decomposable into one or more bits of binary information accessible using said word lines and said bit lines between which said memory portions are electrically contiguous; The memory device of claim 13.

15. 15. The memory device of claim 14, wherein the memory device is suitable for implementing non-volatile storage in a solid-state disk (SSD), for implementing storage class memory (SCM), and / or for implementing Compute Express Link (CXL) compliant memory.

16. 1. A method of forming a memory device, comprising: forming a stack of layers, the layers having a controllably conductive layer and an electrode layer adjacent the controllably conductive layer; and forming a via electrode extending vertically through said stack; Equipped with the electrode layer includes a conductor portion and a separator portion; the separator portion separates the via electrode from the conductor portion; At least one memory portion of the controllable conductive layer is electrically continuous between the via electrode and the conductor portion. method.

17. 17. The method of claim 16, wherein the step of forming the via electrode comprises forming a hole through the stack, the hole defining a dimension of the via electrode through the layer.

18. 20. The method of claim 17, wherein the electrode layer is formed by forming an undercut in the electrode layer such that the undercut surrounds the hole, and the undercut defines a volume for the separator portion.

19. The method of claim 18 , wherein the electrode layer is formed by forming the separator portion in the undercut.

20. the controllable conductive layer comprises an Ovonic Threshold Switch (OTS) material; The conductor portion contains carbon (C), 20. The method according to any one of claims 16 to 19.

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