Wiring board and manufacturing method of the same

Abstract

To provide a wiring board capable of improving an insulation reliability between adjacent penetration wirings.SOLUTION: A present wiring board includes: a core substrate having a reinforcement member; a first penetration hole in a rectangular-shape in a cross sectional view that penetrates the core substrate; an insulation layer that is provided on an upper surface and a lower surface of the core substrate and in the first penetration hole, and does not have the reinforcement member; a second penetration hole that passes through the first penetration hole, and penetrates the insulation layer from the upper surface to the lower surface; and a penetration wiring for filling the second penetration hole. The second penetration hole has a shape in the cross sectional view having a width gradually narrow toward a constricted part on a center side in a thickness direction fron an open end on the upper surface side and an open end on the lower surface side of the insulation layer, and an outer wall surface of the penetration wiring is separated from an inner wall surface of the first penetration hole via the insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a manufacturing method thereof. [Background technology]

[0002] Conventionally, there is known a wiring board in which wiring layers and insulating layers are alternately laminated. In such a wiring board, adjacent wiring layers are connected by through-hole wiring that penetrates the insulating layer. The through-hole wiring has, for example, a tapered shape with its tops butted together. The through-hole wiring is formed, for example, by plating (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-46248 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the insulating layer has a reinforcing member such as glass cloth, the reinforcing member may be exposed or protrude from the inner wall of the through hole in which the through wiring is disposed. In this case, during plating to form the through wiring, chloride ions contained in the plating solution penetrate between the reinforcing member and the resin constituting the insulating layer from the vicinity of the end of the reinforcing member. If the penetrated chloride ions reach adjacent through wirings, the resistance value between the through wirings decreases, and the insulation reliability deteriorates.

[0005] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a wiring board capable of improving the insulation reliability between adjacent through-wirings. [Means for solving the problem]

[0006] This wiring board has a core substrate having a reinforcing member, a first through hole having a rectangular shape in cross section that penetrates the core substrate, an insulating layer having no reinforcing member provided on the upper and lower surfaces of the core substrate and within the first through hole, a second through hole that passes through the first through hole and penetrates the insulating layer from the upper surface to the lower surface, and a through wiring that fills the second through hole, wherein the second through hole has a shape that gradually narrows in width from the opening ends on the upper surface and the lower surface of the insulating layer toward a constricted portion at the center in the thickness direction in cross section, and the outer wall surface of the through wiring is separated from the inner wall surface of the first through hole by the insulating layer. Effect of the Invention

[0007] According to the disclosed technique, it is possible to provide a wiring board capable of improving the insulation reliability between adjacent through-wires. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of the wiring board according to the first embodiment (part 1). [Diagram 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 1 is a cross-sectional view illustrating a wiring board according to a first modified example of the first embodiment. [Diagram 5] 11 is a cross-sectional view illustrating a wiring board according to a second modified example of the first embodiment. FIG. [Figure 6] 11 is a cross-sectional view illustrating a wiring board according to a third modified example of the first embodiment. FIG. [Figure 7] 11 is a cross-sectional view illustrating a wiring board according to a fourth modified example of the first embodiment. FIG. [Figure 8] 10A to 10C are diagrams illustrating a manufacturing process of a wiring board according to a fourth modified example of the first embodiment. [Figure 9] 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0010] First embodiment [Wiring board structure] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. Referring to Fig. 1, wiring board 1 is a wiring board in which wiring layers and insulating layers are laminated on both sides of core substrate 10.

[0011] Referring to FIG. 1, the wiring board 1 has a core substrate 10, a wiring layer 11, an insulating layer 12, a wiring layer 13, a through-wire 20, a wiring layer 21, a wiring layer 23, and solder resist layers 19 and 29.

[0012] In this embodiment, for convenience, the solder resist layer 19 side of the wiring board 1 in FIG. 1 is referred to as the upper side or one side, and the solder resist layer 29 side is referred to as the lower side or the other side. Also, the surface of each part facing the solder resist layer 19 is referred to as one side or upper side, and the surface facing the solder resist layer 29 is referred to as the other side or lower side. However, the wiring board 1 can be used upside down or placed at any angle. Also, a planar view refers to a view of an object from the normal direction of one side of the solder resist layer 19, and a planar shape refers to a shape of an object viewed from the normal direction of one side of the solder resist layer 19.

[0013] The core substrate 10 has a reinforcing member 10G. For example, the core substrate 10 may be a substrate in which the reinforcing member 10G is impregnated with a thermosetting insulating resin 10R. For example, the reinforcing member 10G may be a glass cloth using a glass fiber bundle. Instead of the glass cloth, a carbon fiber bundle, a polyester fiber bundle, a nylon (polyamide) fiber bundle, an aramid fiber bundle, or the like may be used. The reinforcing member 10G may be a woven fabric or a nonwoven fabric. For example, the insulating resin 10R may be an epoxy resin, an imide resin, a phenol resin, a cyanate resin, or the like. The insulating resin 10R may contain a filler such as silica (SiO2). The thickness of the core substrate 10 may be, for example, about 80 to 1200 μm.

[0014] The core substrate 10 is provided with first through holes 10x penetrating the core substrate 10 from the upper surface 10a to the lower surface 10b. The first through holes 10x have a rectangular shape with a constant width in a vertical cross section. The vertical cross section is a cross section cut in a direction perpendicular to the upper surface 10a of the core substrate 10. The constant width means that a variation of the order of a manufacturing error occurring when forming the first through holes 10x is allowed. The planar shape of the first through holes 10x can be, for example, a circle with a diameter of about 50 to 100 μm. The pitch of the first through holes 10x can be, for example, about 100 to 1000 μm.

[0015] The wiring layer 11 is a wiring pattern provided on the upper surface 10a of the core substrate 10. The wiring layer 21 is a wiring pattern provided on the lower surface 10b of the core substrate 10. The wiring layer 11 and the wiring layer 21 are made of, for example, a metal foil such as copper foil or a plating layer such as copper plating. The thickness of the wiring layer 11 and the wiring layer 21 can be, for example, about 15 to 35 μm.

[0016] The insulating layer 12 is provided on the upper surface 10a and the lower surface 10b of the core substrate 10 and inside the first through hole 10x. The insulating layer 12 covers the wiring layer 11 on the upper surface 10a side of the core substrate 10, covers the wiring layer 21 on the lower surface 10b side, and further covers the inner wall surface of the first through hole 10x. The insulating layer 12 does not have a reinforcing member.

[0017] The insulating layer 12 is an insulating layer mainly composed of, for example, a non-photosensitive resin. The insulating layer 12 may be mainly composed of, for example, a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenol resin, or a cyanate resin. The thickness of the insulating layer 12 in the portion covering the upper surface 10a may be, for example, about 20 to 40 μm. The thickness of the insulating layer 12 in the portion covering the lower surface 10b may be, for example, about 20 to 40 μm. The insulating layer 12 may contain a filler such as silica (SiO2). The insulating layer 12 may be an insulating layer mainly composed of a photosensitive resin.

[0018] The insulating layer 12 is provided with a second through hole 10y. The second through hole 10y passes through the first through hole 10x and penetrates the insulating layer 12 from the upper surface 12a to the lower surface 12b. The second through hole 10y has a shape in which the width gradually narrows from an opening end 101 on the upper surface 12a side and an opening end 102 on the lower surface 12b side of the insulating layer 12 toward a constricted portion 103 on the center side in the thickness direction in a vertical cross section. That is, the second through hole 10y has an hourglass shape in a vertical cross section. In the illustrated example, the inclined portion of the hourglass shape is linear, but a part or all of the inclined portion of the hourglass shape may be curved.

[0019] The planar shape of the open end 101 may be, for example, a circle with a diameter of about 50 to 100 μm. The planar shape of the open end 102 may be, for example, a circle with substantially the same diameter as the open end 101. The planar shape of the constricted portion 103 may be, for example, a circle with a diameter smaller than those of the open ends 101 and 102 by about 10 to 30 μm. The pitch of the second through holes 10y may be the same as that of the first through holes 10x.

[0020] The opening area of ​​the constricted portion 103 is smaller than the opening area of ​​the first through hole 10x. The opening areas of the opening ends 101 and 102 may be the same as the opening area of ​​the first through hole 10x, may be larger than the opening area of ​​the first through hole 10x, or may be smaller than the opening area of ​​the first through hole 10x. In any case, the second through hole 10y does not contact the first through hole 10x.

[0021] A through wiring 20 is provided in the second through hole 10y. The through wiring 20 fills the second through hole 10y. That is, the through wiring 20 has an hourglass shape similar to the second through hole 10y. An outer wall surface of the through wiring 20 is separated from an inner wall surface of the first through hole 10x via an insulating layer 12. The through wiring 20 can be made of, for example, copper (Cu).

[0022] In order to increase the distance between the outer wall surface of the through wiring 20 and the side surface of the wiring layer 11, it is preferable that the side surface of the wiring layer 11 is located at a position separated from the upper end of the inner wall surface of the first through hole 10x. Similarly, in order to increase the distance between the outer wall surface of the through wiring 20 and the side surface of the wiring layer 21, it is preferable that the side surface of the wiring layer 21 is located at a position separated from the lower end of the inner wall surface of the first through hole 10x. This can improve the insulation reliability between the through wiring 20 and the wiring layers 11 and 21.

[0023] The wiring layer 13 is provided on the insulating layer 12. The wiring layer 13 includes a wiring pattern and a pad provided on the upper surface 12a of the insulating layer 12, and a via wiring filling the via hole 12x. The wiring layer 13 includes a wiring pattern electrically connected to the wiring layer 11 through the via wiring filling the via hole 12x. The via hole 12x can be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the solder resist layer 19 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 11. The diameter of the opening of the via hole 12x can be, for example, about 15 μm or more and 20 μm or less.

[0024] The wiring layer 23 is provided on the insulating layer 12. The wiring layer 23 includes a wiring pattern and a pad provided on the lower surface 12b of the insulating layer 12, and a via wiring filling the via hole 12y. The wiring layer 23 includes a wiring pattern electrically connected to the wiring layer 21 through the via wiring filling the via hole 12y. The via hole 12y can be a truncated cone-shaped recess in which the diameter of the opening opened on the solder resist layer 29 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 21. The diameter of the opening of the via hole 12x can be, for example, about 15 μm or more and 20 μm or less.

[0025] The pads of the wiring layer 13 and the pads of the wiring layer 23 are electrically connected via the through wiring 20. The pads of the wiring layer 13 and the pads of the wiring layer 23 are arranged at positions overlapping with the through wiring 20 in a plan view. The pads of the wiring layers 13 and 23 and the through wiring 20 may be integrally formed. The material of the wiring layers 13 and 23 may be, for example, copper (Cu) or the like. The thickness of the wiring pattern of the wiring layers 13 and 23 may be, for example, approximately the same as that of the wiring layer 11. The wiring layers 13 and 23 may have a structure in which an electrolytic plating layer is laminated on an electroless plating layer, for example.

[0026] The solder resist layer 19 is formed on the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 13. The solder resist layer 29 is formed on the lower surface 12b of the insulating layer 12 so as to cover the wiring layer 23. The solder resist layers 19 and 29 may be formed from, for example, a photosensitive resin. The solder resist layers 19 and 29 may have a thickness of, for example, about 15 to 35 μm.

[0027] The solder resist layer 19 has openings 19x, in which a portion of the wiring layer 13 is exposed. The wiring layer 13 exposed in the openings 19x functions as a pad electrically connected to a semiconductor chip or the like. The solder resist layer 29 has openings 29x, in which a portion of the wiring layer 23 is exposed. The wiring layer 23 exposed in the openings 29x functions as a pad electrically connected to a mounting board such as a motherboard.

[0028] If necessary, a metal layer may be formed on the wiring layer 13 exposed in the opening 19x and the wiring layer 23 exposed in the opening 29x, or an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment may be performed. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), and a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order).

[0029] As shown by the broken line A, the end of the reinforcing member 10G may be exposed or protruded in the first through hole 10x. If the second through hole 10y is not provided, the through wiring 20 is formed to fill the first through hole 10x. The through wiring 20 is formed by plating, and the plating solution contains chloride ions. Therefore, if the end of the reinforcing member 10G is exposed or protruded in the first through hole 10x, chloride ions will soak between the reinforcing member 10G and the insulating resin 10R from near the end of the reinforcing member 10G during plating. If the soaked chloride ions reach the adjacent through wiring 20, the resistance value between the through wiring 20 will decrease, and the insulation reliability will deteriorate.

[0030] However, in the wiring board 1, the first through hole 10x is filled with the insulating layer 12, and the second through hole 10y is formed in the first through hole 10x so as not to contact the first through hole 10x. In this structure, even if the end of the reinforcing member 10G is exposed or protrudes in the first through hole 10x, it is covered by the insulating layer 12 and is not exposed or protrudes in the second through hole 10y. Therefore, when the through wiring 20 is formed by plating, chloride ions are not soaked between the reinforcing member 10G and the insulating resin 10R, so that the insulation reliability between adjacent through wirings 20 can be improved. From the viewpoint of ensuring the insulation reliability between adjacent through wirings 20, the shortest distance between the outer wall surface of the through wiring 20 and the inner wall surface of the first through hole 10x is preferably 2 μm or more.

[0031] Furthermore, in the wiring board 1, the second through hole 10y is hourglass-shaped, which improves the filling of the plating when the through wiring 20 is formed. That is, the opening area of ​​the constricted portion 103 is smaller than the opening area of ​​the opening ends 101 and 102, so that the constricted portion 103 is blocked at an early stage of plating. The depth of the portion where the plating is formed thereafter is the depth from the opening ends 101 and 102 to the constricted portion 103, and the aspect ratio decreases, so that the occurrence of voids and the like can be suppressed and the second through hole 10y can be easily filled.

[0032] [Method of manufacturing wiring board] Next, a method for manufacturing the wiring board according to the first embodiment will be described below. Figures 2 and 3 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment.

[0033] Although an example of the process for producing one wiring board is shown here, the wiring board can be manufactured as a multi-piece board in which multiple wiring board formation areas are provided on a large substrate. By cutting this multi-piece board between the wiring board formation areas, individual wiring boards can be obtained.

[0034] 2(a), a wiring layer 11 is formed on the upper surface 10a of a core substrate 10 having a reinforcing member 10G impregnated with a thermosetting insulating resin 10R, and a wiring layer 21 is formed on the lower surface 10b of the core substrate 10. For example, a laminate having unpatterned plain copper foil formed on the upper surface 10a and the lower surface 10b of the core substrate 10 is prepared. Then, the copper foil on both surfaces is patterned by a subtractive method or the like to form the wiring layer 11 on the upper surface 10a of the core substrate 10 and the wiring layer 21 on the lower surface 10b of the core substrate 10. The wiring layers 11 and 21 may be formed by a semi-additive method.

[0035] Next, in the step shown in FIG. 2(b), a first through hole 10x is formed that is rectangular in cross section and penetrates the core substrate 10 having the reinforcing member 10G. The first through hole 10x is preferably formed so that the upper end of the inner wall surface is separated from the side surface of the wiring layer 11 and the lower end of the inner wall surface is separated from the side surface of the wiring layer 21. The first through hole 10x can be formed, for example, by a drilling method. The planar shape of the first through hole 10x can be, for example, a circle with a diameter of about 50 to 100 μm. The pitch of the first through holes 10x can be, for example, about 100 to 1000 μm. When the first through hole 10x is formed, the end of the reinforcing member 10G may be exposed or protrude into the first through hole 10x. The first through hole 10x may be formed by a laser processing method. When irradiating the laser light, by keeping the laser light nearly parallel using a collimator lens or the like, it is possible to form the first through-hole 10x having a rectangular shape with a constant width in a vertical cross-sectional view.

[0036] 2(c) and 2(d), an insulating layer 12 is formed on the upper surface 10a and the lower surface 10b of the core substrate 10 and in the first through holes 10x. First, in the process shown in Fig. 2(c), a thermosetting insulating film 121 is disposed on the upper surface 10a of the core substrate 10 so as to cover the wiring layer 11, and a thermosetting insulating film 122 is disposed on the lower surface 10b of the core substrate 10. As the insulating films 121 and 122, for example, a film-like epoxy resin in a semi-cured state can be used.

[0037] 2(d), the insulating films 121 and 122 are pressed against the core substrate 10 while being heated in a vacuum atmosphere, and are cured to form the insulating layer 12. The insulating layer 12 is formed so as to cover the wiring layer 11 on the upper surface 10a side of the core substrate 10, cover the wiring layer 21 on the lower surface 10b side of the core substrate 10, and fill the first through holes 10x. The thickness of the insulating layer 12 in the portions covering the upper surface 10a and the lower surface 10b of the core substrate 10 is as described above.

[0038] 3(a), a second through hole 10y is formed through the first through hole 10x, penetrating the insulating layer 12 from the upper surface 12a to the lower surface 12b. A via hole 12x is also formed through the insulating layer 12 to expose the upper surface of the wiring layer 11. A via hole 12y is also formed through the insulating layer 12 to expose the lower surface of the wiring layer 21. The second through hole 10y and the via holes 12x and 12y can be formed by, for example, a laser processing method using a CO2 laser or the like.

[0039] To form the second through hole 10y, first, the upper surface 12a side of the insulating layer 12 is irradiated with laser light to form a recess in the shape of an inverted truncated cone that opens to the upper surface 12a side of the insulating layer 12. Next, the lower surface 12b side of the insulating layer 12 is irradiated with laser light to form a recess in the shape of a truncated cone that opens to the lower surface 12b side of the insulating layer 12. As a result, the tops of the recess in the shape of an inverted truncated cone and the recess in the shape of a truncated cone are connected near the center in the thickness direction of the insulating layer 12, and the second through hole 10y is formed in an hourglass shape in a vertical cross section. That is, the second through hole 10y has a shape in which the width gradually narrows from the opening end on the upper surface 12a side and the opening end on the lower surface 12b side of the insulating layer 12 toward the narrowed portion on the center side in the thickness direction in a cross section.

[0040] The via hole 12x can be formed by irradiating the upper surface 12a side of the insulating layer 12 with a laser beam. The via hole 12x can be a recessed portion having an inverted truncated cone shape in which the diameter of the opening portion opened on the upper surface 12a side of the insulating layer 12 is larger than the diameter of the bottom surface of the opening portion formed by the upper surface of the wiring layer 11. The via hole 12y can be formed by irradiating the lower surface 12b side of the insulating layer 12 with a laser beam. The via hole 12y can be a recessed portion having an inverted truncated cone shape in which the diameter of the opening portion opened on the lower surface 12b side of the insulating layer 12 is larger than the diameter of the bottom surface of the opening portion formed by the lower surface of the wiring layer 21.

[0041] After the via holes 12x and 12y and the second through hole 10y are formed, it is preferable to perform a desmear treatment to remove resin residues exposed to the inside of the via holes 12x and 12y and the second through hole 10y.

[0042] Next, in the step shown in FIG. 3(b), the through wiring 20 and the wiring layers 13 and 23 are formed. For example, a seed layer is formed by electroless plating or sputtering to cover the upper surface 12a of the insulating layer 12, the inner wall surface of the via hole 12x, the upper surface of the wiring layer 11 exposed in the via hole 12x, the inner wall surface of the second through hole 10y, the lower surface 12b of the insulating layer 12, the inner wall surface of the via hole 12y, and the lower surface of the wiring layer 21 exposed in the via hole 12y. Next, a plating resist pattern having an opening that matches the shape of the wiring pattern of the wiring layer 13 is formed on the seed layer covering the upper surface 12a of the insulating layer 12. Also, a plating resist pattern having an opening that matches the shape of the wiring pattern of the wiring layer 23 is formed on the seed layer covering the lower surface 12b of the insulating layer 12. Then, the second through hole 10y and the via holes 12x and 12y are filled by electrolytic plating supplied from the seed layer, and an electrolytic plating layer is deposited on the seed layer exposed in the opening of the plating resist pattern. Then, the plating resist pattern is removed using a plating resist remover. Next, etching is performed using the electrolytic plating layer as a mask to remove the seed layer exposed from the electrolytic plating layer. This forms the through wiring 20 and the wiring layers 13 and 23. The outer wall surface of the through wiring 20 is separated from the inner wall surface of the first through hole 10x via the insulating layer 12. For example, copper (Cu) can be used as the material for the seed layer and the electrolytic plating layer.

[0043] 3(c), a solder resist layer 19 is formed on the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 13. Also, a solder resist layer 29 is formed on the lower surface 12b of the insulating layer 12 so as to cover the wiring layer 23. The solder resist layer 19 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin or acrylic insulating resin to the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 13 by a screen printing method, a roll coating method, a spin coating method, or the like. Alternatively, for example, a film-like photosensitive epoxy insulating resin or acrylic insulating resin may be laminated on the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 13. The method of forming the solder resist layer 29 is the same as that of the solder resist layer 19.

[0044] Next, the solder resist layers 19 and 29 are exposed and developed to form openings 19x in the solder resist layer 19, which expose a portion of the upper surface of the wiring layer 13. Also, openings 29x are formed in the solder resist layer 29, which expose a portion of the lower surface of the wiring layer 23. The planar shape of each of the openings 19x and 29x may be, for example, a circular shape. The diameter of each of the openings 19x and 29x may be designed arbitrarily in accordance with the connection target (such as a semiconductor chip or a motherboard).

[0045] In this step, the above-mentioned metal layer may be formed by, for example, electroless plating on the upper surface of the wiring layer 13 exposed at the bottom of the opening 19x and the lower surface of the wiring layer 23 exposed at the bottom of the opening 29x. Alternatively, instead of forming a metal layer, an anti-oxidation treatment such as OSP treatment may be performed. Through the above steps, the wiring board 1 is completed.

[0046] Modification of the First Embodiment In the modified example of the first embodiment, an example of a wiring board having a shape different from that of the first embodiment is shown. Note that in the modified example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0047] Fig. 4 is a cross-sectional view illustrating a wiring board according to Modification 1 of the first embodiment. Referring to Fig. 4, wiring board 1A differs from wiring board 1 in that wiring board 1A does not have wiring layers 11 and 21. In this manner, wiring layers may or may not be provided on upper surface 10a and lower surface 10b of core substrate 10.

[0048] 5 is a cross-sectional view illustrating a wiring board according to Modification 2 of the first embodiment. Referring to Fig. 5, wiring board 1B differs from wiring board 1 in that it has a multilayer wiring structure.

[0049] In the wiring board 1B, an insulating layer 14 covering the wiring layer 13 is provided on the upper surface 12a of the insulating layer 12. A wiring layer 15 is provided on the insulating layer 14. The wiring layer 15 includes a wiring pattern formed on the upper surface of the insulating layer 14 and via wiring filling a via hole 14x that penetrates the insulating layer 14 and exposes the upper surface of the wiring layer 13. An insulating layer 16 covering the wiring layer 15 is provided on the upper surface of the insulating layer 14. A wiring layer 17 is provided on the insulating layer 16. The wiring layer 17 includes a wiring pattern formed on the upper surface of the insulating layer 16 and via wiring filling a via hole 16x that penetrates the insulating layer 16 and exposes the upper surface of the wiring layer 15. A solder resist layer 19 having an opening 19x is provided on the upper surface of the insulating layer 16.

[0050] In the wiring board 1B, an insulating layer 24 is provided on the lower surface 12b of the insulating layer 12 to cover the wiring layer 23. A wiring layer 25 is provided on the insulating layer 24. The wiring layer 25 includes a wiring pattern formed on the lower surface of the insulating layer 24 and via wiring that fills a via hole 24x that penetrates the insulating layer 24 and exposes the lower surface of the wiring layer 23. An insulating layer 26 is provided on the lower surface of the insulating layer 24 to cover the wiring layer 25. A wiring layer 27 is provided on the insulating layer 26. The wiring layer 27 includes a wiring pattern formed on the lower surface of the insulating layer 26 and via wiring that fills a via hole 26x that penetrates the insulating layer 26 and exposes the lower surface of the wiring layer 25. A solder resist layer 29 having an opening 29x is provided on the lower surface of the insulating layer 26.

[0051] In this manner, the wiring layers and the insulating layers may be alternately laminated on the upper surface 10a and the lower surface 10b of the core substrate 10. The number of laminated wiring layers and insulating layers can be set arbitrarily as required.

[0052] Fig. 6 is a cross-sectional view illustrating a wiring board according to Modification 3 of the first embodiment. Referring to Fig. 6, the wiring board 1C differs from the wiring board 1 in that two second through holes 10y are provided in one first through hole 10x. The through wiring 20 fills each of the two second through holes 10y provided in one first through hole 10x.

[0053] Three or more second through holes 10y may be provided in one first through hole 10x. In this manner, the number of second through holes 10y provided in one first through hole 10x is not limited to one, and multiple second through holes 10y may be provided in one first through hole 10x.

[0054] Fig. 7 is a cross-sectional view illustrating a wiring board according to Modification 4 of the first embodiment. Referring to Fig. 7, wiring board 1D differs from wiring board 1 in that wiring layer 13 and wiring layer 23 have a laminated structure of a first metal layer and a second metal layer.

[0055] The wiring layer 13 has a laminated structure of a first metal layer 13a and a second metal layer 13b. The first metal layer 13a is provided on the upper surface 12a of the insulating layer 12 outside the through wiring 20 in a plan view. The second metal layer 13b is laminated on the upper surface of the first metal layer 13a and the upper surface of the through wiring 20. The second metal layer 13b may be formed integrally with the through wiring 20. The first metal layer 13a is also provided on the upper surface 12a of the insulating layer 12 outside the via wiring filling the via hole 12x in a plan view. The second metal layer 13b is laminated on the upper surface of the first metal layer 13a and the upper surface of the via wiring. The second metal layer 13b may be formed integrally with the via wiring. The second metal layer 13b may have a two-layer structure in which an electrolytic plating layer is laminated on a seed layer.

[0056] The wiring layer 23 has a laminated structure of a first metal layer 23a and a second metal layer 23b. The first metal layer 23a is provided on the lower surface 12b of the insulating layer 12 outside the through wiring 20 in a plan view. The second metal layer 23b is laminated on the lower surface of the first metal layer 23a and the lower surface of the through wiring 20. The second metal layer 23b may be formed integrally with the through wiring 20. The first metal layer 23a is also provided on the lower surface 12b of the insulating layer 12 outside the via wiring filling the via hole 12y in a plan view. The second metal layer 23b is laminated on the lower surface of the first metal layer 23a and the lower surface of the via wiring. The second metal layer 23b may be formed integrally with the via wiring. The second metal layer 23b may have a two-layer structure in which an electrolytic plating layer is laminated on a seed layer.

[0057] FIG. 8 is a diagram illustrating a manufacturing process of a wiring board according to the fourth modified example of the first embodiment. First, after performing the same processes as those in FIG. 2(a) and FIG. 2(b), in the process shown in FIG. 8(a), a laminate in which a first metal layer 13a such as copper foil is laminated on a thermosetting insulating film 121 in a semi-cured state, and a laminate in which a first metal layer 23a such as copper foil is laminated on a thermosetting insulating film 122 in a semi-cured state are prepared. The thickness of the first metal layers 13a and 23a can be, for example, about 5 to 15 μm. Then, the laminate is disposed on the upper surface 10a of the core substrate 10 so that the insulating film 121 covers the wiring layer 11. Also, the laminate is disposed on the lower surface 10b of the core substrate 10 so that the insulating film 122 covers the wiring layer 21.

[0058] 8(b), the insulating films 121 and 122 of the laminate are pressed against the core substrate 10 while being heated in a vacuum atmosphere, and are cured to form the insulating layer 12. The insulating layer 12 is formed so as to cover the wiring layer 11 on the upper surface 10a side of the core substrate 10, cover the wiring layer 21 on the lower surface 10b side of the core substrate 10, and further fill the first through holes 10x. The material of the insulating layer 12 and the thickness of the insulating layer 12 in the portions covering the upper surface 10a and the lower surface 10b are as described above.

[0059] 8(c), a second through hole 10y is formed through the first through hole 10x, penetrating the first metal layer 13a, the insulating layer 12, and the first metal layer 23a. A via hole 12x is formed through the first metal layer 13a and the insulating layer 12, exposing the upper surface of the wiring layer 11. A via hole 12y is formed through the first metal layer 23a and the insulating layer 12, exposing the lower surface of the wiring layer 21. The second through hole 10y and the via holes 12x and 12y can be formed by a laser processing method using, for example, a CO2 laser or the like.

[0060] 3(b) and 3(c) are then performed to complete the wiring board 1D. However, when performing etching using the electrolytic plating layer as a mask, the seed layer exposed from the electrolytic plating layer and the first metal layers 13a and 23a exposed from the electrolytic plating layer are removed.

[0061] In addition, when the first metal layers 13a and 23a are laminated on both sides of the insulating layer 12, the following effects can be obtained. In general, when comparing the adhesion (peel strength) of the electroless plating layer to the insulating layer when an electroless plating layer is formed on the surface of the insulating layer with the adhesion (peel strength) of the metal foil to the insulating layer when a metal foil is laminated on the surface of the insulating layer, the adhesion of the metal foil is greater. Therefore, when the first metal layers 13a and 23a are laminated on both sides of the insulating layer 12, when the second metal layers 13b and 23b have a two-layer structure in which an electroless plating layer is laminated on a seed layer, the seed layer, which is an electroless plating layer, adheres firmly to the first metal layers 13a and 23a. As a result, the peel strength of the wiring layers 13 and 23 to the insulating layer 12 can be improved.

[0062] Second Embodiment In the second embodiment, an example of a semiconductor device in which a semiconductor chip is mounted on the wiring substrate according to the first embodiment will be described. Note that in the second embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0063] 9 is a cross-sectional view illustrating a semiconductor device according to the second embodiment. Referring to Fig. 9, the semiconductor device 2 includes the wiring substrate 1 shown in Fig. 1, a semiconductor chip 50, bumps 60, and an underfill resin 70.

[0064] The semiconductor chip 50 has a chip body 51 and electrodes 52. The chip body 51 is, for example, a semiconductor integrated circuit (not shown) and the like formed on a thinned semiconductor substrate (not shown) made of silicon or the like. The semiconductor substrate (not shown) has electrodes 52 formed thereon that are electrically connected to the semiconductor integrated circuit.

[0065] The bump 60 is formed between the electrode 52 of the semiconductor chip 50 and the wiring layer 13 exposed in the opening 19x of the wiring board 1, and electrically connects the electrode 52 and the wiring layer 13. The electrode 52 can be made of, for example, copper. The bump 60 is, for example, a solder bump. Examples of materials that can be used for the solder bump include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu. The underfill resin 70 is filled between the semiconductor chip 50 and the upper surface of the solder resist layer 19 of the wiring board 1.

[0066] In this manner, a semiconductor device can be realized by mounting a semiconductor chip on the wiring board according to the first embodiment.

[0067] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0068] 1,1A,1B,1C,1D Wiring board 2. Semiconductor Devices 10 Core Board 10G Reinforcement material 10R Insulating resin 10a Top 10b Bottom side 10x 1st through hole 10y 2nd through hole 11,13,15,17,21,23,25,27 wiring layer 12,14,16,24,26 Insulating layer 12a Top side 12b Bottom side 12x, 12y, 14x, 16x, 24x, 26x via holes 13a,23a 1st metal layer 13b,23b 2nd metal layer 19,29 Solder resist layer 19x,29x opening 20 Through Wiring 50 Semiconductor Chips 51 Chip body 52 electrodes 60 Bump 70 Underfill resin 101,102 Open end 103 Neck

Claims

1. a core substrate having a reinforcing member; a first through hole having a rectangular shape in cross section, the first through hole penetrating the core substrate; an insulating layer having no reinforcing member provided on an upper surface and a lower surface of the core substrate and in the first through hole; a second through hole passing through the first through hole and penetrating the insulating layer from the upper surface to the lower surface; a through wiring filling the second through hole, the second through hole has a shape in which the width gradually narrows from an opening end on an upper surface side and an opening end on a lower surface side of the insulating layer toward a constricted portion on a center side in a thickness direction, in a cross-sectional view; An outer wall surface of the through wiring is separated from an inner wall surface of the first through hole by the insulating layer.

2. a first wiring layer is provided on the upper surface of the core substrate; a second wiring layer is provided on the lower surface of the core substrate; a side surface of the first wiring layer is located at a position spaced apart from an upper end of an inner wall surface of the first through hole, The wiring board according to claim 1 , wherein a side surface of the second wiring layer is located at a position spaced apart from a lower end of an inner wall surface of the first through hole.

3. The wiring board according to claim 1 , wherein a plurality of the second through holes are provided within one of the first through holes.

4. A first pad is provided on an upper surface of the insulating layer; A second pad is provided on a lower surface of the insulating layer; The wiring board according to claim 1 , wherein the first pad and the second pad are electrically connected to each other via the through-wire.

5. The first pad and the second pad have a laminated structure of a first metal layer and a second metal layer, the first metal layer is provided outside the through-hole wiring in a plan view, The wiring board according to claim 4 , wherein the second metal layer is formed integrally with the through-hole wiring.

6. The wiring board according to claim 1 , wherein a shortest distance between an outer wall surface of the through-wire and an inner wall surface of the first through hole is 2 μm or more.

7. forming a first through hole having a rectangular shape in cross section, penetrating a core substrate having a reinforcing member; forming an insulating layer on the upper and lower surfaces of the core substrate and in the first through hole; forming a second through hole passing through the first through hole and penetrating the insulating layer from the upper surface to the lower surface; forming a through wiring filling the second through hole, the second through hole has a shape in which the width gradually narrows from an opening end on an upper surface side and an opening end on a lower surface side of the insulating layer toward a constricted portion on a center side in a thickness direction, in a cross-sectional view; A method for manufacturing a wiring substrate, wherein an outer wall surface of the through wiring is separated from an inner wall surface of the first through hole by the insulating layer.

8. The first through hole is formed by a drilling method; The method for manufacturing a wiring board according to claim 7 , wherein the second through hole is formed by a laser processing method.

Images