Semiconductor device and semiconductor circuit

Abstract

To provide a semiconductor device capable of suppressing a leakage current from a diode to a deep portion of a substrate.SOLUTION: A semiconductor device includes: a first conductivity type semiconductor substrate 1A; a second conductivity-type semiconductor layer 1B located on the semiconductor substrate 1A; a first conductivity-type first semiconductor region 10 formed in the semiconductor layer 1B; a second conductivity-type second semiconductor region 20 formed in the semiconductor layer 1B; and a second conductivity-type buried layer BLR interposed between the first semiconductor region 10 and the semiconductor substrate 1A. The first semiconductor region 10 and the semiconductor layer 1B form a pn junction, and the second semiconductor region 20 and the semiconductor layer 1B are electrically connected to each other. In plan view, a first interval ΔX1 is provided between a first end position of the buried layer BLR on the second semiconductor region 20 side and a second end position of the second semiconductor region 20 on the first semiconductor region 10 side.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a semiconductor circuit. [Background technology]

[0002] Patent Document 1 discloses a switching circuit including a diode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-063081 A

[0004] [overview] The present disclosure provides a semiconductor device and a semiconductor circuit capable of suppressing leakage current from a diode to a deep portion of a substrate.

[0005] The present disclosure provides a semiconductor device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type located on the semiconductor substrate; a first semiconductor region of the first conductivity type formed in the semiconductor layer; a second semiconductor region of a second conductivity type formed in the semiconductor layer; and a buried layer of a second conductivity type interposed between the first semiconductor region and the semiconductor substrate, wherein the first semiconductor region and the semiconductor layer form a pn junction, the second semiconductor region and the semiconductor layer are electrically connected, and a first distance is provided between a first end position of the buried layer on the second semiconductor region side and a second end position of the second semiconductor region on the first semiconductor region side in a planar view. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor circuit according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing a vertical cross-sectional configuration of the semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a plan view of the semiconductor device according to the embodiment. [Figure 4] 4A to 4F are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention (FIGS. 4A, 4B, 4C, 4D, 4E, and 4F). [Diagram 5] FIG. 5 is a plan view of the buried layer. [Figure 6] FIG. 6 is a plan view of the buried layer. [Figure 7] FIG. 7 is a graph (FIG. 7(a) and FIG. 7(b)) showing the relationship between the depth (Z) and the impurity concentration Cn ( / cm 3 ). [Figure 8] FIG. 8 is a graph showing the relationship between the position (X) in the X-axis direction and the impurity concentration Cn ( / cm 3 ). [Figure 9] FIG. 9 is a graph showing the relationship between the position (X) in the X-axis direction and the impurity concentration Cn ( / cm 3 ). [Figure 10] FIG. 10 is a graph showing the relationship between the position in the Y-axis direction (Y) and the impurity concentration Cn ( / cm 3 ).

[0007] [Detailed Description] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or corresponding parts in each drawing are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0008] FIG. 1 is a circuit diagram of a semiconductor circuit according to an embodiment.

[0009] The semiconductor circuit 100 is a switching regulator. The semiconductor circuit 100 includes a semiconductor chip 200, a first capacitor C1, an inductor L1, and a second capacitor C2. The first capacitor C1, the inductor L1, and the second capacitor C2 are disposed outside the semiconductor chip 200. A load resistor R1 is connected between output terminals located at both ends of the second capacitor C2. A power supply voltage is supplied to the semiconductor chip 200 from a power supply Vc. One end of the inductor L1 is connected to a third node P3 of the semiconductor device. The second capacitor C2 is connected between the other end of the inductor L1 and a fixed potential (ground potential GND).

[0010] The semiconductor chip 200 supplies a periodically varying current to the inductor L1, and an output voltage generated across the second capacitor C2 is applied to the load resistor R1. The second capacitor C2 has a function of smoothing the output voltage.

[0011] The diode D1, the first transistor Q1, the second transistor Q2, the first driver 101, and the second driver 102 are provided in the same semiconductor chip 200. The first transistor Q1 and the second transistor Q2 are connected in series. The cathode electrode of the diode D1, which includes a pn junction, is electrically connected to the third node P3 via the first capacitor C1. The third node P3 is the connection point between the first transistor Q1 and the second transistor Q2.

[0012] The first transistor Q1 is an N-channel MOS (metal oxide semiconductor) field effect transistor. The first capacitor C1 and the diode D1 configure a bootstrap circuit. The bootstrap circuit has a function of raising the cathode potential of the diode D1, i.e., the first potential V1 of the first node P1, with respect to the potential of the third node P3. It is also possible to insert a resistor in series with the first capacitor C1. The first potential V1 of the first node P1 is the power supply potential of the first driver 101. In other words, the cathode electrode of the diode D1 is connected to the power supply potential of the first driver 101. The output terminal of the first driver 101 is electrically connected to the gate electrode of the first transistor Q1. For example, when a low-level (or high-level) first input signal SIG1 is input to the first driver 101, the first potential V1 is applied to the gate electrode of the first transistor Q1, and a positive gate-source voltage Vgs is applied between the gate electrode and the source electrode.

[0013] The third node P3 is connected to a source electrode of the first transistor Q1 and a drain electrode of the second transistor Q2. The drain electrode of the first transistor Q1 is connected to a transistor power supply potential V IN is connected to

[0014] The second transistor Q2 is also an N-channel MOS field effect transistor. The anode potential of the diode D1, i.e., the second potential V2 of the second node P2, is the power supply potential of the second driver 102. In other words, the anode electrode of the diode D1 is connected to the power supply potential of the second driver 102. The output terminal of the second driver 102 is electrically connected to the gate electrode of the second transistor Q2. For example, when a low-level (or high-level) second input signal SIG2 is input to the second driver 102, the second potential V2 is applied to the gate electrode of the second transistor Q2, and a positive gate-source voltage Vgs is applied between the gate electrode and the source electrode. The source electrode of the second transistor Q2 is connected to a fixed potential (ground potential GND). The first input signal SIG1 and the second input signal SIG2 can be complementary signals.

[0015] The first transistor Q1 and the second transistor Q2 are enhancement type transistors, but can be depletion type transistors. The output voltages of the first driver 101 and the second driver 102 can be shifted from the power supply potential as necessary. Each transistor can be a junction field effect transistor. Each transistor is also a switching element. As another structure applicable to the power supply circuit, the second transistor Q2 can be replaced with a Zener diode.

[0016] The first driver 101 and the second driver 102 are circuits that apply a power supply voltage (or a voltage obtained by shifting the power supply voltage) to the gate electrodes of the transistors in response to an input signal. Each of the first driver 101 and the second driver 102 can be composed of a transistor, an inverter, an operational amplifier, or the like.

[0017] The above-mentioned diode D1 is formed in the semiconductor chip 200. When an SOI (Silicon On Insulator) substrate formed by forming a semiconductor layer on an insulating substrate is used as the substrate of the semiconductor chip 200, the current flowing from the diode D1 to the substrate can be suppressed. On the other hand, when a semiconductor substrate is used instead of the insulating substrate in the SOI substrate, a leakage current flows from the diode D1 toward the depth of the substrate. The semiconductor device according to the embodiment has a structure capable of suppressing the leakage current from the diode D1 to the depth of the substrate.

[0018] FIG. 2 is a diagram showing a vertical cross-sectional configuration of the semiconductor device according to the embodiment.

[0019] This semiconductor device is the above-mentioned semiconductor chip 200, and includes a diode D1. Semiconductors are of p-type and n-type conductivity types. When p-type is the first conductivity type and n-type is the second conductivity type, these conductivity types can be interchanged with each other. In addition, an XYZ three-dimensional orthogonal coordinate system is set. The thickness direction of the semiconductor chip 200 is the Z-axis direction, the direction perpendicular to the Z-axis direction is the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is the Y-axis direction. The positive direction of the Z-axis is the depth direction of the semiconductor chip 200.

[0020] The semiconductor device includes a substrate 1 including a semiconductor substrate 1A and a semiconductor layer 1B. The semiconductor device includes a first semiconductor region 10, a second semiconductor region 20, and a buried layer BLR. The semiconductor substrate 1A is made of a p-type (first conductive type) semiconductor. The semiconductor layer 1B is an epitaxial semiconductor layer made of an n-type (second conductive type) semiconductor and is located on the semiconductor substrate 1A. The first semiconductor region 10 is made of a p-type semiconductor and is formed in the semiconductor layer 1B. The second semiconductor region 20 is made of an n-type semiconductor and is formed in the semiconductor layer 1B. The buried layer BLR is made of an n-type semiconductor and is interposed between the first semiconductor region 10 and the semiconductor substrate 1A.

[0021] The first semiconductor region 10 (anode) and the semiconductor layer 1B form a pn junction. The second semiconductor region 20 (cathode) is formed in the semiconductor layer 1B and is electrically connected to the semiconductor layer 1B. The semiconductor region from the first semiconductor region 10 to the second semiconductor region 20 constitutes a diode D1. In a plan view (when viewed from the Z-axis direction), a first interval (ΔX1) exists between a first end position (x9) on the second semiconductor region 20 side of the buried layer BLR and a second end position (x10) on the first semiconductor region 10 side of the second semiconductor region 20. The first interval (ΔX1) is greater than 0 (0<ΔX1).

[0022] The first semiconductor region 10, the semiconductor layer 1B, and the semiconductor substrate 1A form a pnp-type parasitic transistor Qp. The buried layer BLR prevents leakage current I leak If the buried layer BLR extends to reach the cathode region of the diode D1, i.e., directly below the second semiconductor region 20, the breakdown voltage (applicable reverse voltage) of the diode D1 decreases. In a power device, a breakdown voltage of 500 V or 600 V or more is preferable. Therefore, the buried layer BLR is present directly below the anode region (first semiconductor region 10) of the diode D1, and while it extends toward the second semiconductor region 20, it does not reach a position directly below the second semiconductor region 20.

[0023] In a plan view, the first interval (ΔX1) is smaller (ΔX1<ΔX2) than the second interval (ΔX2) between the third end position (x8) on the second semiconductor region 20 side of the first semiconductor region 10 and the second end position (x10). The buried layer BLR extends from the region directly under the first semiconductor region 10 in the direction toward the second semiconductor region 20 (positive direction of the X-axis) by a distance Δ (=ΔX2-ΔX1).

[0024] The greater the distance Δ, the more the leakage current bypassing the buried layer BLR can be suppressed.The preferred distance Δ is 10% to 30% of the second interval (ΔX2).

[0025] In other words, the suitable first interval (ΔX1) is 70% or more and 90% or less of the second interval (ΔX2) (70%×ΔX2≦ΔX1≦90%×ΔX2). When the first interval (ΔX1) is smaller than the lower limit (when the buried layer BLR approaches the second semiconductor region 20), the breakdown voltage of the diode D1 tends to decrease. When the first interval (ΔX1) is larger than the upper limit (when the horizontal protrusion amount of the buried layer BLR becomes small), the leakage current suppression tends to be insufficient.

[0026] The leakage current suppression capability of the buried layer BLR also depends on the depth position of the buried layer BLR. If the buried layer BLR is too deep, the leakage current tends to diffuse, and if it is too shallow, it affects the breakdown voltage of the diode D1. From this viewpoint, it is preferable that the third distance (ΔZ3) between the buried layer BLR and the first semiconductor region 10 in the longitudinal section (XZ section) is 6 μm or more and 10 μm or less. Regarding the depth (Z), the substrate surface position (contact layer surface position) is set as the reference position (z0=0).

[0027] An insulating film 60 is formed on the surface of the semiconductor layer 1B. The insulating film 60 is an oxide film formed by the LOCOS (Local Oxidation of Silicon) method. In the region directly below the insulating film 60, an n-type channel block region 30 is formed as necessary. In order to electrically isolate the diode D1 from adjacent elements, an upper isolation region 40 is formed directly below the insulating film 60, and a lower isolation region 50 is formed between the upper isolation region 40 and the semiconductor substrate 1A.

[0028] A high-impurity-concentration p-type first contact layer 13 is formed on the first semiconductor region 10 constituting the anode of the diode D1. An anode electrode 11 is electrically connected to the first contact layer 13. A high-impurity-concentration n-type second contact layer 23 is formed on the second semiconductor region 20 constituting the cathode of the diode D1. A cathode electrode 21 is electrically connected to the second contact layer 23.

[0029] The above semiconductor elements are all made of silicon (Si). The thickness and impurity concentration of each semiconductor element are as follows:

[0030] The impurity concentration of the semiconductor substrate 1A is 5×10 13 ( / cm 3 ) or more 5×10 14 ( / cm 3 The thickness of the semiconductor substrate 1A may be 50 μm or more and 800 μm or less.

[0031] The impurity concentration of the semiconductor layer 1B is 1×10 15 ( / cm 3 ) or more 5×10 15 ( / cm 3 The thickness of the semiconductor layer 1B may be set to 14 μm or more and 18 μm or less.

[0032] The buried layer BLR may have a thickness of 7 μm or more and 11 μm or less. The buried layer BLR may have an impurity concentration of 1×10 18 ( / cm 3 ) or more 6×10 18 ( / cm 3 ) or less. The impurity concentration of the buried layer BLR can be set to be higher than the impurity concentration of the semiconductor layer 1B.

[0033] The thickness of the first semiconductor region 10 may be 3 μm or more and 5 μm or less. The impurity concentration of the first semiconductor region 10 may be 1×10 16 ( / cm 3 ) or more 6×10 16 ( / cm 3 ) or less.

[0034] The thickness of the second semiconductor region 20 may be 3 μm or more and 5 μm or less. The impurity concentration of the second semiconductor region 20 may be 7×10 15 ( / cm 3 ) or more 3×10 16 ( / cm 3 The impurity concentration of the second semiconductor region 20 can be set higher than the impurity concentration of the semiconductor layer 1B.

[0035] The thickness of the first contact layer 13 may be 0.5 μm or more and 1.0 μm or less. The impurity concentration of the first contact layer 13 is set to be higher than the impurity concentration of the first semiconductor region 10. The impurity concentration of the first contact layer 13 is set to be 5×10 18 ( / cm 3 ) or more 2×10 19 ( / cm 3 ) or less.

[0036] The thickness of the second contact layer 23 may be 0.2 μm or more and 0.6 μm or less. The impurity concentration of the second contact layer 23 is set to be higher than the impurity concentration of the second semiconductor region 20. The impurity concentration of the second contact layer 23 is set to be 1×10 19 ( / cm 3 ) or more 4×10 19 ( / cm 3 ) or less.

[0037] The thickness of the channel block region 30 may be 3 μm or more and 5 μm or less. The impurity concentration of the channel block region 30 is 7×10 15 ( / cm 3 ) or more 3×10 16 ( / cm 3 ) or less.

[0038] The thickness of the upper isolation region 40 may be 3 μm or more and 5 μm or less. The impurity concentration of the upper isolation region 40 may be 1×10 18 ( / cm 3 ) or more 4×10 18 ( / cm 3 ) or less.

[0039] The thickness of the lower isolation region 50 may be 11 μm or more and 13 μm or less. The impurity concentration of the lower isolation region 50 is 4×10 16 ( / cm 3 ) or more 2×10 17 ( / cm 3 ) or less.

[0040] FIG. 3 is a plan view of the semiconductor device according to the embodiment.

[0041] As shown in the same figure, in a planar view, a first interval (ΔX1) exists between a first end position (x9) on the second semiconductor region 20 side of the buried layer BLR and a second end position (x10) on the first semiconductor region 10 side of the second semiconductor region 20.

[0042] The insulating film 60 has openings in an upper region of the first contact layer 13 and an upper region of the second contact layer 23. The anode electrode 11 is connected to the first contact layer 13. The cathode electrode 21 is connected to the second contact layer 23. The channel block region 30 may be annular in a planar view and may surround the periphery of the first semiconductor region 10 and the second semiconductor region 20 that constitute the diode. The upper isolation region 40 may be annular in a planar view and may surround the periphery of the channel block region 30.

[0043] The dimension in the Y-axis direction of the first semiconductor region 10 is defined by the distance between the Y-direction position (y5) and the Y-direction position (y8). The dimension in the Y-axis direction of the buried layer BLR is defined by the distance between the Y-direction position (y4) and the Y-direction position (y9), and is larger than the dimension in the Y-axis direction of the first semiconductor region 10.

[0044] The dimension in the X-axis direction of the first semiconductor region 10 is defined by the distance between the X-direction position (x5) and the X-direction position (x8). The dimension in the X-axis direction of the buried layer BLR is defined by the distance between the X-direction position (x4) and the X-direction position (x9), and is larger than the dimension in the X-axis direction of the first semiconductor region 10.

[0045] Next, a method for manufacturing the above-mentioned semiconductor device will be described.

[0046] FIG. 4 is a diagram (FIG. 4(a), FIG. 4(b), FIG. 4(c), FIG. 4(d), FIG. 4(e), FIG. 4(f)) explaining a method for manufacturing a semiconductor device according to an embodiment. The manufacturing process of the semiconductor device is carried out sequentially in the order of FIG. 4(a) to FIG. 4(f).

[0047] As shown in FIG. 4(a), a semiconductor substrate 1A is prepared.

[0048] As shown in Fig. 4(b), a buried layer BLR is formed in a surface region of the semiconductor substrate 1A. A p-type impurity doped region 50A is formed in a part of the semiconductor substrate 1A. The impurity doped region 50A is annular in a plan view. These regions can be formed by using an ion implantation method, but may also be formed by using a diffusion method.

[0049] As shown in FIG. 4(c), a semiconductor layer 1B is formed on a semiconductor substrate 1A. The semiconductor layer 1B is an epitaxial layer. Many methods for epitaxial growth of silicon are known. For example, when using a chemical vapor deposition (CVD) method, a source gas containing Si (e.g., SiCl4) is introduced into a chamber together with a carrier gas, and the Si substrate is heated to a high temperature (1000° C. or higher), an epitaxial layer made of Si can be grown on the surface of the Si substrate. The source gas during growth can contain n-type impurities. By forming the semiconductor layer 1B, the impurities in the buried layer BLR diffuse toward the surface of the semiconductor layer 1B, and the impurities in the impurity-doped region 50A also diffuse to form the lower isolation region 50.

[0050] As shown in FIG. 4(d), an insulating film 60 is formed on the semiconductor layer 1B by using the LOCOS method.

[0051] As shown in FIG. 4(e), a p-type impurity is added into the semiconductor layer 1B through the opening in the insulating film 60 to form a first semiconductor region 10. An n-type impurity is added into the semiconductor layer 1B through the opening in the insulating film 60 to form a second semiconductor region 20. These impurity additions can be performed using an ion implantation method. The n-type channel block region 30 and the p-type upper isolation region 40 can also be formed using an ion implantation method. The p-type impurity can be boron (B), and the n-type impurity can be phosphorus (P), arsenic (As), or antimony (Sb).

[0052] 4(f), p-type impurities are further added onto the first semiconductor region 10 through the openings in the insulating film 60 to form a first contact layer 13. N-type impurities are further added onto the second semiconductor region 20 through the openings in the insulating film 60 to form a second contact layer 23. The added impurities are activated by heat treatment.

[0053] The buried layer BLR may have a periodically changing impurity concentration distribution in a horizontal plane (XY plane). The impurity concentration may be constant in the horizontal plane, but when the impurity concentration is high, the electric field strength tends to be high, which may reduce the breakdown voltage.

[0054] FIG. 5 is a plan view of the buried layer.

[0055] The buried layer BLR includes a plurality of buried regions BL arranged in a stripe pattern in a plan view. The buried layer BLR has an impurity concentration that varies along the X-axis direction. The impurity concentration is constant along the Y-axis direction. Gap regions between the plurality of buried regions BL have a relatively lower impurity concentration than the buried regions BL. The impurity concentration of the gap regions can be made equal to the impurity concentration of the semiconductor layer 1B when doping the impurity. The impurity concentration of the gap regions increases during a heat treatment process during manufacturing, and can be made approximately half the impurity concentration of the buried regions BL after the heat treatment process is completed.

[0056] FIG. 6 is a plan view of the buried layer.

[0057] The buried layer BLR includes a plurality of buried regions BL arranged in a matrix in plan view. The buried layer BLR has impurity concentrations that vary along both the X-axis and Y-axis directions. Gap regions between the buried regions BL have impurity concentrations that are relatively lower than the buried regions BL. The impurity concentrations of the gap regions are set in the same manner as described in FIG. 5.

[0058] Figure 7 shows the relationship between depth (Z) and impurity concentration Cn ( / cm 3 7(a) and 7(b) are graphs showing the relationship between the

[0059] FIG. 7(a) shows the distribution of the impurity concentration Cn of the buried layer BLR. Between the depth position (z2) and the depth position (z4) in the Z-axis direction, the impurity concentration Cn is 1×10 18 ( / cm 3 )~6×10 18 ( / cm 3 ) is set to a specific impurity concentration selected from the depth positions (z2) and (z4). In this impurity concentration distribution, the impurity concentration Cn is set to a constant value (maximum value C H ) in the semiconductor layer 1B (see FIG. 2) located above the buried layer BLR. L ) is 1 × 10 15 ( / cm 3 )~5×10 15 ( / cm 3 ) is set to a specific impurity concentration selected from

[0060] FIG. 7(b) shows the distribution of the impurity concentration Cn of the buried layer BLR when the impurity is added by ion implantation, and the impurity concentration Cn changes so as to be upwardly convex between the depth position (z2) and the depth position (z4) in the Z-axis direction.

[0061] Maximum value of impurity concentration Cn of buried layer BLR H The depth position (Zp) at which the impurity concentration Cn of the buried layer BLR is given is set shallower than the interface position (z3) between the semiconductor substrate 1A and the semiconductor layer 1B. The depth direction distance (ΔZ4) between the peak position (Zp) of the impurity concentration and the interface position (z3) is about 1 μm. An exemplary preferred value is 0.8 μm≦ΔZ4≦1.2 μm. H is 1 x 10 18 / cm 3 More than 6×10 18 / cm 3 For example, the maximum value C H is 3 x 1018 ( / cm 3 ) The maximum value of the impurity concentration Cn is C H However, if the lower limit is exceeded, the leakage current blocking effect is reduced, and if the upper limit is exceeded, the breakdown voltage tends to decrease. L ) is 1 × 10 15 ( / cm 3 )~5×10 15 ( / cm 3 ) is set to a specific impurity concentration selected from

[0062] Figure 8 shows the relationship between horizontal position (X) and impurity concentration Cn ( / cm 3 ) is a graph showing the relationship between

[0063] In the figure, the distribution of the impurity concentration Cn in the horizontal direction (X-axis direction) at the depth position (Zp: FIG. 7(b)) is shown. The depth position (Zp) is the position that gives the maximum value of the impurity concentration of the buried layer BLR. This impurity concentration distribution shows that the impurity concentration is a constant value (maximum value C H ) is shown. The outer region in the horizontal direction of the buried layer BLR (the region smaller than the position (x4) or the region larger than the position (x9)) is the semiconductor layer 1B (see FIG. 2). The n-type impurity concentration (minimum value C L ) is 1 × 10 15 ( / cm 3 )~5×10 15 ( / cm 3 ) is set to a specific impurity concentration selected from

[0064] Figure 9 shows the relationship between the position in the X-axis direction (X) and the impurity concentration Cn ( / cm 3 ) is a graph showing the relationship between

[0065] This figure shows the distribution of the impurity concentration Cn in the X-axis direction at the depth position (Zp: FIG. 7(b)). The depth position (Zp) is the position that gives the maximum value of the impurity concentration of the buried layer BLR. In the region between the X-axis position (x4) and the X-axis position (x9), the impurity concentration Cn varies periodically along the X-axis direction.

[0066] The impurity concentration Cn in the buried layer BLR is the maximum value C H 6×10 18 ( / cm 3 The minimum value of the impurity concentration Cn in the buried layer BLR is the minimum value (C M ) is, for example, the maximum value C H is approximately 50% of the H ≦C M ≦60%×C H The lower limit is specified from the viewpoint of maintaining the breakdown voltage, and the upper limit is determined from the viewpoint of preventing leakage current.

[0067] As shown in FIG. 5, the impurity concentration Cn of the buried layer BLR may vary along the X-axis direction, but may be constant along the Y-axis direction. In more detail, the maximum value of the impurity concentration Cn of the buried layer BLR (C H ), the impurity concentration Cn can vary periodically along a first direction (X-axis direction) in a plane perpendicular to the thickness direction of the buried layer BLR.

[0068] Specifically, the region from the X-axis position (x4) to the X-axis position (xA), the region from the X-axis position (xB) to the X-axis position (xC), and the region from the X-axis position (xD) to the X-axis position (x9) have a relatively high concentration (C H On the other hand, the region from the X-axis position (xA) to the X-axis position (xB) and the region from the X-axis position (xC) to the X-axis position (xD) have a relatively low concentration (C M ) is the gap region.

[0069] Figure 10 shows the relationship between the position in the Y-axis direction (Y) and the impurity concentration Cn ( / cm 3 ) is a graph showing the relationship between

[0070] This figure shows the distribution of the impurity concentration Cn in the Y-axis direction at the depth position (Zp: FIG. 7(b)). The depth position (Zp) is the position that gives the maximum value of the impurity concentration of the buried layer BLR. In the region between the Y-axis position (y4) and the Y-axis position (y9), the impurity concentration Cn varies periodically along the Y-axis direction.

[0071] The impurity concentration Cn in the buried layer BLR is the maximum value C H 6×10 18 ( / cm 3 The minimum value of the impurity concentration Cn in the buried layer BLR is the minimum value (C M ) is, for example, the maximum value C H is approximately 50% of the H ≦C M ≦60%×C H The lower limit is specified from the viewpoint of maintaining the breakdown voltage, and the upper limit is determined from the viewpoint of preventing leakage current.

[0072] As shown in FIG. 6, the impurity concentration Cn of the buried layer BLR may vary along the X-axis direction (FIG. 9) and may also vary along the Y-axis direction (FIG. 10). In more detail, the maximum value of the impurity concentration Cn of the buried layer BLR (C H ), the impurity concentration Cn can vary periodically along a first direction (X-axis direction) in the plane perpendicular to the thickness direction of the buried layer BLR, and along a second direction (Y-axis direction) perpendicular to the first direction in the plane.

[0073] Specifically, the region from the Y-axis position (y4) to the Y-axis position (yA), the region from the Y-axis position (yB) to the Y-axis position (yC), and the region from the Y-axis position (YD) to the Y-axis position (y9) have a relatively high concentration (C HOn the other hand, the region from the Y-axis position (yA) to the Y-axis position (yB) and the region from the Y-axis position (yC) to the Y-axis position (yD) have a relatively low density (C M ) is the gap region.

[0074] Various types of circuit configurations of switching regulators using diodes are known. In addition, circuits using transistors, including half-bridge and full-bridge configurations, are also known. Silicon (Si) can be used as the material of the semiconductor elements described above, but compound semiconductors such as SiC or SiGe can also be used. In addition to SiO2, inorganic insulators such as silicon nitride can also be used as the material of the insulating film. The configurations, materials, and numerical ranges of the above elements can be appropriately selected and combined. In addition, when the exemplary ranges of the parameters (impurity concentration, thickness) of the above semiconductor elements are given, the parameters of the semiconductor elements may satisfy the magnitude relationship satisfied by the central value in each exemplary range. This magnitude relationship is preferably satisfied under the condition of being within the corresponding exemplary range, but may be satisfied under the condition outside the exemplary range. The above exemplary ranges show specific examples of suitable ranges in circuit operation, but values ​​outside the exemplary ranges can be adopted as long as the circuit operation is possible within the technical common sense of a person skilled in the art. The connections in the above circuit diagrams mean electrical connections, but the connections between the elements such as electrodes and terminals can also be physical connections. The electrical connection is a direct connection via wiring, but as long as the basic operation of each element can be performed, it is also possible to interpose another circuit element in series or parallel with the target circuit element.

[0075] As described above, according to the above-mentioned semiconductor device and semiconductor circuit, it is possible to suppress leakage current from the diode to a deep portion of the substrate. Various embodiments of the present disclosure can be defined as the following supplementary notes [A1] to [A11].

[0076] [A1] A semiconductor device comprising: a semiconductor substrate 1A of a first conductivity type; a semiconductor layer 1B of a second conductivity type located on the semiconductor substrate 1A; a first semiconductor region 10 of a first conductivity type formed in the semiconductor layer 1B; a second semiconductor region 20 of a second conductivity type formed in the semiconductor layer 1B; and a buried layer BLR of a second conductivity type interposed between the first semiconductor region 10 and the semiconductor substrate 1A, wherein the first semiconductor region 10 and the semiconductor layer 1B form a pn junction, the second semiconductor region 20 and the semiconductor layer 1B are electrically connected, and a first interval (ΔX1) is provided between a first end position (x9) of the buried layer BLR on the second semiconductor region 20 side and a second end position (x10) of the second semiconductor region 20 on the first semiconductor region 10 side in a planar view.

[0077] [A2] A semiconductor device according to A1, wherein, in a planar view, the first distance (ΔX1) is smaller than a second distance (ΔX2) between a third end position (x8) of the first semiconductor region 10 on the second semiconductor region 20 side and the second end position (x10).

[0078] [A3] The semiconductor device according to A2, wherein the first interval (ΔX1) is 70% or more and 90% or less of the second interval (ΔX2).

[0079] [A4] The semiconductor device according to any one of A1 to A3, wherein a third distance (ΔZ3) between the buried layer BLR and the first semiconductor region 10 in a longitudinal section (XZ section) is not less than 6 μm and not more than 10 μm.

[0080] [A5] The maximum value of the impurity concentration of the buried layer BLR (C H ) is 1 × 10 18 / cm 3 More than 6×10 18 / cm 3 The semiconductor device according to any one of A1 to A4, which is:

[0081] [A6] The maximum value of the impurity concentration of the buried layer BLR (C H7B) is shallower than an interface position (Z3) between the semiconductor substrate 1A and the semiconductor layer 1B.

[0082] [A7] The maximum value of the impurity concentration of the buried layer BLR (C H 9 ), the impurity concentration of the buried layer BLR varies periodically ( FIG. 9 ) along a first direction (X-axis direction) in a plane perpendicular to a thickness direction of the buried layer BLR.

[0083] [A8] The maximum value of the impurity concentration of the buried layer BLR (C H 9 and 10, the impurity concentration of the buried layer BLR at a depth position (Zp) that provides a thickness direction of the buried layer BLR varies periodically along a first direction (X-axis direction) in a plane perpendicular to a thickness direction of the buried layer BLR and along a second direction (Y-axis direction) perpendicular to the first direction in the plane.

[0084] [A9] The semiconductor device according to any one of A1 to A8, comprising: a first transistor Q1 and a second transistor Q2 connected in series to the first transistor Q1, a cathode electrode of a diode D1 including the pn junction is connected to a node (third node P3) between the first transistor Q1 and the second transistor Q2 via a first capacitor C1, the cathode electrode of the diode D1 is connected to a power supply potential (V1) of a first driver 101, and an anode electrode of the diode D1 is connected to a power supply potential (V2) of a second driver 102, an output terminal of the first driver 101 is electrically connected to a gate electrode of the first transistor Q1, and an output terminal of the second driver 102 is electrically connected to a gate electrode of the second transistor Q2.

[0085] [A10] The semiconductor device according to A9, wherein the diode D1, the first transistor Q1, the second transistor Q2, the first driver 101, and the second driver 102 are provided within a same semiconductor chip 200.

[0086] [A11] A semiconductor circuit comprising: the semiconductor device described in A10; the first capacitor C1 arranged outside the semiconductor chip 200; an inductor L1 having one end connected to the node (third node P3) of the semiconductor device; and a second capacitor C2 connected between the other end of the inductor L1 and a fixed potential (GND).

[0087] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Elements in different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims. [Explanation of symbols]

[0088] 1A...semiconductor substrate, 1B...semiconductor layer, 10...first semiconductor region, 11...anode electrode, 20...second semiconductor region, 21...cathode electrode, 100...semiconductor circuit, 101...first driver, 102...second driver, 200...semiconductor chip, BLR...buried layer, C2...second capacitor, C H ...maximum value, C1...first capacitor, Cn...impurity concentration, D1...diode, L1...inductor, Q1...first transistor, Q2...second transistor, 13...first contact layer, 23...second contact layer, 30...channel block region, 40...upper isolation region, 50...lower isolation region, 50A...impurity doped region, 60...insulating film, BL...buried region, I leak...leakage current, P1...first node, P2...second node, P3...third node, Q1...first transistor, Qp...parasitic transistor, R1...load resistor, SIG1...first input signal, SIG2...second input signal, V1...first potential, V2...second potential, V IN ...power supply potential for transistor, Vc...power supply, Vgs...gate-source voltage.

Claims

1. a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type located on the semiconductor substrate; a first semiconductor region of a first conductivity type formed in the semiconductor layer; a second semiconductor region of a second conductivity type formed in the semiconductor layer; a buried layer of a second conductivity type interposed between the first semiconductor region and the semiconductor substrate; Equipped with the first semiconductor region and the semiconductor layer form a pn junction; the second semiconductor region and the semiconductor layer are electrically connected; In plan view, a first interval is provided between a first end position of the buried layer on the second semiconductor region side and a second end position of the second semiconductor region on the first semiconductor region side; Semiconductor device.

2. In plan view, the first distance is smaller than a second distance between a third end position of the first semiconductor region on the second semiconductor region side and the second end position; The semiconductor device according to claim 1 .

3. The first interval is: The second interval is 70% or more and 90% or less. The semiconductor device according to claim 2 .

4. In the longitudinal section, a third distance between the buried layer and the first semiconductor region is not less than 6 μm and not more than 10 μm; The semiconductor device according to claim 3 .

5. The maximum impurity concentration of the buried layer is 1×10 １８ / cm ３ Above 6 x 10 １８ / cm ３ Below is the The semiconductor device according to claim 1 .

6. The depth position that gives the maximum value of the impurity concentration of the buried layer is a position shallower than an interface between the semiconductor substrate and the semiconductor layer; The semiconductor device according to claim 1 .

7. At a depth position giving a maximum value of the impurity concentration of the buried layer, the impurity concentration of the buried layer varies periodically along a first direction in a plane perpendicular to a thickness direction of the buried layer. The semiconductor device according to claim 1 .

8. At a depth position giving a maximum value of the impurity concentration of the buried layer, the impurity concentration of the buried layer varies periodically along a first direction in a plane perpendicular to a thickness direction of the buried layer and along a second direction perpendicular to the first direction in the plane. The semiconductor device according to claim 1 .

9. A first transistor; a second transistor connected in series with the first transistor; Equipped with a cathode electrode of the diode including the pn junction is connected to a node between the first transistor and the second transistor via a first capacitor; the cathode electrode of the diode is connected to a power supply potential of a first driver; an anode electrode of the diode is connected to a power supply potential of a second driver; an output terminal of the first driver is connected to a gate electrode of the first transistor; an output terminal of the second driver is connected to a gate electrode of the second transistor; The semiconductor device according to any one of claims 1 to 8.

10. the diode, the first transistor, the second transistor, the first driver, and the second driver are provided within a same semiconductor chip; The semiconductor device according to claim 9.

11. A semiconductor device according to claim 10; the first capacitor disposed outside the semiconductor chip; an inductor having one end connected to the node of the semiconductor device; a second capacitor connected between the other end of the inductor and a fixed potential; A semiconductor circuit comprising:

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