Semiconductor storage device and data erasing method

Abstract

To provide a semiconductor storage device and a detection method which are capable of reducing the loss of valid memory cells and efficiently using the memory cells.SOLUTION: A nonvolatile memory 2 includes a plurality of planes P0 to P3, a sequencer 27, and a source line CELSRC. The sequencer 27 executes erasing sequence of repeatedly performing a plurality of loops including a set of erasing operation of erasing each data of a memory cell included in one erasing target block selected in each of the planes P0 to P3 and erasing verification operation of confirming whether or not data has been erased. Moreover, the sequencer 27, for each erasing target block, detects the presence or absence of current leakage from the source line CELSRC, determines based on results of the detection whether or not the erasing sequence is valid, and cancels the execution of the erasing sequence for the erasing target block determined not to be valid.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device and a data erasing method. [Background technology]

[0002] A NAND flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,312,026 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present embodiment is to provide a semiconductor memory device and a data erasing method that can reduce wear of effective memory cells and use memory cells efficiently. [Means for solving the problem]

[0005] The semiconductor memory device of this embodiment includes a plurality of planes. Each of the plurality of planes includes at least one or more blocks, and the blocks include a plurality of memory cells. The semiconductor memory device includes a control unit that executes an erase sequence that repeats a plurality of loops including a set of an erase operation that erases data of each of the plurality of memory cells included in an erase target block, which is the block selected one by one in each of the plurality of planes, and an erase verify operation that checks whether the data has been erased, and erases the data of each of the plurality of memory cells included in the erase target block. The semiconductor memory device further includes a source line electrically connected to one end of the plurality of memory cells included in all of the plurality of planes. The control unit detects the presence or absence of a current leak from the source line for each of the plurality of erase target blocks, determines the validity of the erase sequence based on the result of the detection, and stops the execution of the erase sequence for the erase target block that is determined to be invalid. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of a memory system using a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of the configuration of a nonvolatile memory according to a first embodiment. [Diagram 3] FIG. 2 is a diagram showing an example of the configuration of a block of a memory cell array having a three-dimensional structure according to the first embodiment. [Figure 4] 1 is a cross-sectional view of a block of a three-dimensional structure NAND memory according to a first embodiment. [Figure 5A] FIG. 2 is a block diagram illustrating an example of a voltage supply path to each line of a memory cell array according to the first embodiment. [Figure 5B] FIG. 2 is a diagram illustrating an example of a configuration of a detection circuit according to the first embodiment. [Figure 6A] FIG. 11 is a diagram for explaining a command sequence and the operation of each plane in the comparative example. [Figure 6B]FIG. 11 is a diagram showing voltage changes in each wiring in a comparative example. [Figure 7] FIG. 11 is a diagram for explaining a command sequence and the operation of each plane in the comparative example. [Figure 8A] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 8B] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 8C] FIG. 4 is a diagram showing an example of voltage changes in each wiring of the detection circuit in the first embodiment. [Figure 8D] FIG. 4 is a diagram showing an example of voltage changes in each signal line in the first embodiment. [Figure 9A] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 9B] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 9C] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 9D] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 9E] FIG. 4 is a diagram showing an example of voltage changes in each wiring in the first embodiment. [Figure 9F] FIG. 4 is a diagram showing an example of voltage changes in each signal line in the first embodiment. [Figure 9G] FIG. 4 is a diagram showing an example of voltage changes in each signal line in the first embodiment. [Figure 10A] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 10B] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 10C] 5A to 5C are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. [Figure 11]FIG. 11 is a block diagram illustrating another example of a voltage supply path to each line of the memory cell array according to the first embodiment. [Figure 12] FIG. 11 is a block diagram illustrating an example of a voltage supply path to each line of a memory cell array according to a second embodiment. [Figure 13A] 13A to 13C are diagrams illustrating an example of pressure boosting operation control of a pump unit during an erase operation and a detection operation according to a second embodiment. [Figure 13B] 13A to 13C are diagrams illustrating an example of pressure boosting operation control of a pump unit during an erase operation and a detection operation according to a second embodiment. [Figure 13C] 13A to 13C are diagrams illustrating an example of pressure boosting operation control of a pump unit during an erase operation and a detection operation according to a second embodiment. [Figure 13D] 13A to 13C are diagrams illustrating an example of pressure boosting operation control of a pump unit during an erase operation and a detection operation according to a second embodiment. [Figure 14A] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 14B] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 14C] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 14D] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 14E] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 14F] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 14G] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 14H] 13A to 13C are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. [Figure 15A]FIG. 4 is a diagram showing an example of a threshold voltage distribution in the first embodiment. [Figure 15B] FIG. 1 is a diagram showing an example of data coding in the first embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. (First embodiment) (1. Composition) (1-1. Memory system configuration) 1 is a block diagram showing a configuration example of a memory system using a semiconductor memory device according to a first embodiment. The memory system includes a memory controller 1 and a non-volatile memory 2 as a semiconductor memory device. The memory system can be connected to a host. The host is, for example, an electronic device such as a personal computer or a mobile terminal.

[0008] The nonvolatile memory 2 is a memory that stores data in a nonvolatile manner, and includes, for example, a NAND memory (NAND flash memory). The nonvolatile memory 2 is, for example, a NAND memory having memory cells capable of storing 3 bits per memory cell, that is, a 3 bit / cell (TLC: Triple Level Cell) NAND memory. The nonvolatile memory 2 may be a NAND memory capable of storing multiple bits such as 1 bit / cell, 2 bits / cell, or 4 bits / cell or more. The nonvolatile memory 2 is usually made up of multiple memory chips.

[0009] The memory controller 1 controls writing of data to the non-volatile memory 2 in response to a write request from the host. The memory controller 1 also controls reading of data from the non-volatile memory 2 in response to a read request from the host. The following signals are transmitted and received between the memory controller 1 and the non-volatile memory 2: chip enable signal / CE, ready / busy signal / RB, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals RE, / RE, write protect signal / WP, data signal DQ<7:0>, and data strobe signals DQS, / DQS. Note that the " / " added to the signal name indicates active low.

[0010] For example, the non-volatile memory 2 and the memory controller 1 are each formed as a semiconductor chip (hereinafter, simply referred to as a "chip").

[0011] The chip enable signal / CE is a signal for selecting and enabling a specific memory chip of the nonvolatile memory 2. The ready / busy signal / RB is a signal for indicating whether the nonvolatile memory 2 is in a ready state (a state in which it is capable of accepting commands from the outside) or a busy state (a state in which it is not capable of accepting commands from the outside). The memory controller 1 can know the state of the nonvolatile memory 2 by receiving the ready / busy signal / RB. The command latch enable signal CLE is a signal for indicating that the signal DQ<7:0> is a command. The command latch enable signal CLE enables a command transmitted as the signal DQ to be latched in a command register in a selected memory chip of the nonvolatile memory 2. The address latch enable signal ALE is a signal for indicating that the signal DQ<7:0> is an address. The address latch enable signal ALE enables an address transmitted as the signal DQ to be latched in an address register in a selected memory chip of the nonvolatile memory 2. The write enable signal / WE is a signal for taking in a received signal into the nonvolatile memory 2, and is asserted by the memory controller 1 every time a command, address, and data are received. The nonvolatile memory 2 is instructed to take in the signals DQ<7:0> while the write enable signal / WE is at the "L (Low)" level.

[0012] The read enable signals RE and / RE are signals for the memory controller 1 to read data from the nonvolatile memory 2. For example, they are used to control the operation timing of the nonvolatile memory 2 when outputting the signal DQ<7:0>. The write protect signal / WP is a signal for instructing the nonvolatile memory 2 to prohibit data writing and erasing. The signal DQ<7:0> is the substance of data transmitted and received between the nonvolatile memory 2 and the memory controller 1, and includes a command, an address, and data. The data strobe signals DQS and / DQS are signals for controlling the timing of input and output of the signal DQ<7:0>.

[0013] The memory controller 1 includes a RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, the processor 12, the host interface 13, the ECC circuit 14, and the memory interface 15 are connected to each other via an internal bus 16.

[0014] The host interface 13 receives requests such as a write request and a read request, user data (write data), etc. from the host. In addition, the host interface 13 transmits user data read from the nonvolatile memory 2, responses from the processor 12, etc. to the host.

[0015] The memory interface 15 controls the process of writing user data and the like to the non-volatile memory 2 and the process of reading user data and the like from the non-volatile memory 2 based on instructions from the processor 12 .

[0016] The RAM 11 temporarily stores user data received from the host before storing it in the nonvolatile memory 2, and temporarily stores data read from the nonvolatile memory 2 before transmitting it to the host. The RAM 11 is, for example, a general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0017] The processor 12 performs overall control of the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the processor 12 receives a request from the host via the host interface 13, the processor 12 performs control according to the request. For example, the processor 12 instructs the memory interface 15 to write user data to the non-volatile memory 2 in accordance with the request from the host. Also, the processor 12 instructs the memory interface 15 to read user data from the non-volatile memory 2 in accordance with the request from the host.

[0018] The processor 12 determines a storage area (memory area) on the nonvolatile memory 2 for user data accumulated in the RAM 11. The user data received from the host is temporarily stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data (page data) in units of pages, which are writing units. The user data temporarily stored in the RAM 11 is generally encoded by the ECC circuit 14 and stored as unit data in the determined memory area of ​​the nonvolatile memory 2. A physical address is assigned to the memory area of ​​the nonvolatile memory 2. The processor 12 manages the memory area to which the unit data is written using the physical address. The processor 12 instructs the memory interface 15 to specify the determined memory area (physical address) and write the user data to the nonvolatile memory 2. The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the processor 12 receives a read request including a logical address from the host, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0019] The ECC circuit 14 encodes the user data stored in the RAM 11 to generate unit data. The ECC circuit 14 also decodes the encoded unit data read from the nonvolatile memory 2. In this embodiment, a configuration in which encoding is performed is shown as an example, but encoding is not essential. The memory controller 1 may store page data in the nonvolatile memory 2 without encoding it.

[0020] 1 shows an example of a configuration in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be built into the memory interface 15. The ECC circuit 14 may also be built into the non-volatile memory 2.

[0021] When a write request is received from the host, the memory system operates as follows. The processor 12 temporarily stores data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs it to the memory interface 15. The memory interface 15 writes the encoded data to the non-volatile memory 2.

[0022] When a read request is received from the host, the memory system operates as follows: The memory interface 15 inputs the encoded data read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the encoded data and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13. (1-2. Non-volatile memory configuration) 2 is a block diagram showing a configuration example of a nonvolatile memory according to the first embodiment. The nonvolatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a memory cell unit MU, a register 26, a sequencer 27, a plane common voltage generating circuit 28A, an input / output pad group 32, a logic control pad group 34, and a power supply input terminal group 35.

[0023] The memory cell unit MU includes a plurality of planes P0 to P3. The planes P0 to P3 are units capable of independently executing read, write, and erase operations. While FIG. 2 shows an example in which four planes are arranged in the nonvolatile memory 2, the number of planes may be three or less, or five or more. The planes P0 to P3 include a memory cell array (memory cell section) 23, a sense amplifier 24, a row decoder 25, a driver set 29, and a plane voltage generating circuit 28B.

[0024] The memory cell array 23 includes a plurality of blocks BLK. Each of the plurality of blocks BLK includes a plurality of memory cell transistors (memory cells). In the memory cell array 23, a plurality of bit lines, a plurality of word lines, a source line, and the like are arranged to control the voltage applied to the memory cell transistors. The specific configuration of the blocks BLK will be described later.

[0025] The input / output pad group 32 includes a plurality of pads (terminals) corresponding to the signals DQ<7:0> and data strobe signals DQS and / DQS in order to transmit and receive various signals including data to and from the memory controller 1.

[0026] The logic control pad group 34 has a plurality of pads (terminals) corresponding to a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, and a write protect signal / WP in order to transmit and receive various signals to and from the memory controller 1.

[0027] The power input terminal group 35 includes a plurality of terminals for inputting power supply voltages VCC, VCCQ, VPP and a ground voltage VSS in order to supply various operating power supplies from the outside to the nonvolatile memory 2. The power supply voltage VCC is a circuit power supply voltage that is generally provided from the outside as an operating power supply, and a voltage of, for example, about 3.3 V is input. The power supply voltage VCCQ is a voltage of, for example, 1.2 V. The power supply voltage VCCQ is used when transmitting and receiving signals between the memory controller 1 and the nonvolatile memory 2.

[0028] The power supply voltage VPP is a power supply voltage higher than the power supply voltage VCC, and for example, a voltage of 12 V is input. When writing data to the memory cell array 23 or erasing data, a high voltage of about 20 V is required. In this case, a desired voltage can be generated faster and with lower power consumption by boosting the power supply voltage VPP of about 12 V rather than boosting the power supply voltage VCC of about 3.3 V. The power supply voltage VPP is a power supply that is additionally and arbitrarily supplied depending on, for example, the usage environment.

[0029] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 transmits and receives signals DQ<7:0> (for example, DQ0 to DQ7) to and from the memory controller 1 via the NAND bus.

[0030] The logic control circuit 21 receives external control signals (e.g., a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, and a write protect signal / WP) via the NAND bus from the memory controller 1. In addition, the logic control circuit 21 transmits a ready / busy signal / RB to the memory controller 1 via the NAND bus.

[0031] The input / output circuit 22 transmits and receives the signal DQ<7:0> and the data strobe signals DQS and / DQS to and from the memory controller 1. The input / output circuit 22 transfers the command and address in the signal DQ<7:0> to the register 26. The input / output circuit 22 also transmits and receives write data and read data to and from the sense amplifiers 24 of each of the planes P0 to P3.

[0032] The register 26 includes a command register, an address register, a status register, etc. The command register temporarily holds a command. The address register temporarily holds an address. The status register temporarily holds data necessary for the operation of the non-volatile memory 2. The register 26 is composed of, for example, an SRAM.

[0033] A sequencer 27 serving as a control unit receives a command from the register 26 and controls the non-volatile memory 2 in accordance with a sequence based on this command.

[0034] The plane common voltage generating circuit 28A receives a power supply voltage from outside the nonvolatile memory 2, and uses this power supply voltage to generate a voltage common to a plurality of planes. The plane common voltage generating circuit 28A generates, for example, a voltage (VERA) required for an erase operation. The plane common voltage generating circuit 28A supplies the generated voltage to the memory cell arrays 23 included in each of the planes P0 to P3.

[0035] The plane voltage generation circuit 28B receives a power supply voltage from outside the nonvolatile memory 2, and generates a plurality of voltages required for write, read, and erase operations using this power supply voltage. The plane voltage generation circuit 28B supplies the generated voltages to the memory cell array 23, the sense amplifier 24, the row decoder 25, the driver set 29, and the like arranged in the same plane P0 to P3 as the plane voltage generation circuit 28B. The plane voltage generation circuit 28B also includes a detection circuit 282. In this embodiment, one detection circuit 282 is provided for each of the planes P0 to P3, and is capable of detecting leakage current in each of the planes P0 to P3.

[0036] The driver set 29 receives various voltages from the plane voltage generating circuit 28B, selects a voltage appropriate for operation, and transfers it to the row decoder 25 and the sense amplifier 24.

[0037] The row decoder 25 receives a row address from the register 26 and decodes the row address. The row decoder 25 selects a word line based on the decoded row address. The row decoder 25 then transfers a number of voltages required for write, read, and erase operations to the selected block.

[0038] The sense amplifier 24 receives a column address from the register 26 and decodes the column address. The sense amplifier 24 has a group of sense amplifier units and a data register. The group of sense amplifier units is connected to each bit line, and selects one of the bit lines based on the decoded column address. When reading data, the group of sense amplifier units detects and amplifies data read from the memory cell transistors to the bit lines. When writing data, the group of sense amplifier units transfers write data to the bit lines.

[0039] When reading data, the data register temporarily holds the data detected by the sense amplifier unit group and transfers it serially to the input / output circuit 22. When writing data, the data register temporarily holds the data serially transferred from the input / output circuit 22 and transfers it to the sense amplifier unit group. The data register is composed of an SRAM or the like. (1-3. Block configuration of memory cell array) Fig. 3 is a diagram showing a configuration example of a block of a memory cell array having a three-dimensional structure according to the first embodiment. Fig. 3 shows one block BLK among a plurality of blocks constituting the memory cell array 23. Fig. 4 is a cross-sectional view of a block of the three-dimensional NAND memory according to the first embodiment. The other blocks of the memory cell array have the same circuit configuration as Fig. 3 and the same cross-sectional structure as Fig. 4.

[0040] As shown in FIG. 3, the block BLK includes, for example, four string units (SU0 to SU3). Each string unit SU includes a plurality of NAND strings NS. Here, each of the NAND strings NS includes eight memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. The memory cell transistors MT include a gate and a charge storage layer, and retain data in a non-volatile manner. For convenience, the number of memory cell transistors MT included in the NAND string NS is set to eight, but may be greater than this number.

[0041] Although the select gate transistors ST1 and ST2 are shown as one transistor in the electric circuit, they may be structurally the same as the memory cell transistors. Also, for example, multiple select gate transistors may be used as the select gate transistors ST1 and ST2. Furthermore, dummy cell transistors may be provided between the memory cell transistor MT and the select gate transistors ST1 and ST2.

[0042] The memory cell transistors MT are arranged so as to be connected in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one end is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other end is connected to the select gate transistor ST2.

[0043] The gates of the select gate transistors ST1 of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3 (hereinafter, referred to as select gate line SGD when there is no need to distinguish between them). On the other hand, the gates of the select gate transistors ST2 are commonly connected to the same select gate line SGS between multiple string units SU in the same block BLK. Also, the gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. That is, while the word lines WL0 to WL7 and the select gate line SGS are commonly connected between multiple string units SU0 to SU4 in the same block BLK, the select gate line SGD is independent for each of the string units SU0 to SU3 even within the same block BLK.

[0044] The gates of the memory cell transistors MT0 to MT7 constituting the NAND string NS are connected to word lines WL0 to WL7, respectively. The gates of the memory cell transistors MTi in the same row in the block BLK are connected to the same word line WLi. In the following description, the NAND string NS may be simply referred to as a "string."

[0045] Each NAND string NS is connected to a corresponding bit line. Therefore, each memory cell transistor MT is connected to a bit line via a select gate transistor ST or other memory cell transistors MT included in the NAND string NS. Data in the memory cell transistors MT in the same block BLK are erased collectively. Meanwhile, data is read and written in units of memory cell groups MG (or pages). In this specification, a memory cell group MG is defined as a plurality of memory cell transistors MT connected to one word line WLi (i is an integer equal to or greater than 0) and belonging to one string unit SU. During read and write operations, one word line WLi and one select gate line SGD are selected according to a physical address, and a memory cell group MG is selected.

[0046] 4, the D1 direction corresponds to the extension direction of the bit lines BL, the D2 direction corresponds to the extension direction of the word lines WL and the select gate lines SGD, SGS, and the D3 direction corresponds to the stacking direction of the word lines WL and the select gate lines SGD, SGS. The D1 direction is parallel to the surface of the semiconductor substrate 100, the D2 direction is parallel to the surface of the semiconductor substrate 100 and perpendicular to the D1 direction, and the D3 direction is perpendicular to the surface of the semiconductor substrate 100 and perpendicular to the D1 and D2 directions.

[0047] 4, a plurality of NAND strings NS are formed on a p-type well region (P-well). That is, a plurality of wiring layers 333 functioning as select gate lines SGS, a plurality of wiring layers 332 functioning as word lines WLi, and a plurality of wiring layers 331 functioning as select gate lines SGD are stacked on the p-type well region.

[0048] A memory hole 334 is formed which penetrates these wiring layers 333, 332, and 331 and reaches the p-type well region. A block insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side surface of the memory hole 334, and further a conductor pillar 338 is embedded in the memory hole 334. The conductor pillar 338 is made of, for example, polysilicon, and functions as a region where a channel is formed during operation of the memory cell transistor MT and the select gate transistors ST1 and ST2 included in the NAND string NS.

[0049] In each NAND string NS, a select gate transistor ST2, a plurality of memory cell transistors MT, and a select gate transistor ST1 are formed on a p-type well region. A wiring layer functioning as a bit line BL is formed above the conductor pillar 338. A contact plug 339 that connects the conductor pillar 338 to the bit line BL is formed above the conductor pillar 338.

[0050] Furthermore, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed in the surface of the p-type well region. A contact plug 340 is formed on the n+ type impurity diffusion layer, and a wiring layer functioning as a source line CELSRC is formed on the contact plug 340. A contact plug 341 is formed on the p+ type impurity diffusion layer, and a wiring layer functioning as a well line CPWELL is formed on the contact plug 341.

[0051] A plurality of the configurations shown in FIG. 4 are arranged in the depth direction (D2 direction) of the paper surface of FIG. 4, and a single string unit SU is formed by a set of a plurality of NAND strings aligned in a row in the depth direction. (1-4. Voltage supply to each wiring in the memory cell array) 5A is a block diagram for explaining a voltage supply path to each wiring of the memory cell array. The driver set 29 includes a plurality of SG drivers 29A that supply voltages to the signal lines SG0 to SG4, respectively, and a plurality of CG drivers 29B that supply voltages to the signal lines CG0 to CG7, respectively. These signal lines SG0 to SG4, CG0 to CG7 are connected to the wiring of each block BLK via the row decoder 25. That is, the signal lines SG0 to SG3 function as global drain side select gate lines, and are connected to the select gate lines SGD0 to SGD3 as local select gate lines in each block BLK via the row decoder 25. The signal lines CG0 to CG7 function as global word lines, and are connected to the word lines WL0 to WL7 as local word lines in each block BLK via the row decoder 25. The signal line SG4 functions as a global source side select gate line, and is connected to the select gate line SGS as a local select gate line in each block BLK via the row decoder 25.

[0052] An SG driver (select gate line driver) 29A and a CG driver (word line driver) 29B supply various voltages generated by the plane voltage generating circuit 28B to the corresponding signal lines SG0 to SG4 and signal lines CG0 to CG7, respectively.

[0053] For example, during a write operation, each CG driver 29B supplies either the voltage VPGM or the voltage VPASS depending on the corresponding signal line CG and word line WL, depending on the target (row address) of the write operation. The CG driver 29B connected to the signal line CG corresponding to the word line WLn that is the target of the write operation supplies the voltage VPGM. The CG drivers 29B connected to the signal lines CGn±1, CGn±2, etc. corresponding to the other word lines WLn±1, WLn±2, etc. supply the voltage VPASS. The voltage VPASS is a voltage that turns on the memory cell transistor MT. The voltage VPGM is a voltage for injecting electrons into the charge storage layer 336, and VPGM>VPASS.

[0054] The driver set 29 also includes a signal line equalizer circuit 291. The signal line equalizer circuit 291 is a circuit that discharges the connected wiring. The signal line equalizer circuit 291 is connected to the signal lines SG0 to SG4 and CG0 to CG7.

[0055] The plane voltage generation circuit 28B generates various voltages and transfers them to the driver set 29. The plane voltage generation circuit 28B includes a plurality of pump units 281A, 281B and a detection circuit 282. FIG. 5A shows a case where the plane voltage generation circuit 28B includes two pump units 281A, 281B, but the number of pump units may be three or more. The pump unit 281A outputs, for example, a voltage Vsel to be transferred to the selected word line WL to the driver set 29. The voltage Vsel is, for example, a voltage VPGM or the like.

[0056] The pump unit 281B outputs, for example, a voltage Vusel to be transferred to the unselected word lines WL to the driver set 29. The voltage Vusel is, for example, a voltage VPASS, a voltage VREAD, a voltage VCGRV, etc. The voltage VREAD is a voltage that turns on the memory cell transistor MT during reading, regardless of the charge stored in the charge storage layer 336 of the memory cell transistor MT (data held by the memory cell transistor MT). The voltage VCGRV is a voltage that is a read reference, and VREAD>VCGRV.

[0057] The detection circuit 282 is a circuit that detects the current flowing through the signal lines CG0 to CG7. The detection circuit 282 is used as a circuit that detects the leakage current between the source line CELSRC and the word line WL of the selected block BLK during an erase operation. The detection circuit 282 is connected to the pump unit 281B.

[0058] 5B is a diagram for explaining an example of the configuration of the detection circuit according to the first embodiment. The detection circuit 282 includes, for example, a switch SWb, a resistor RL, and a leak detection unit LD. The output end of the pump unit 281B is connected to a node NCG2. A first end of the switch SWb is connected to the node NCG2, and a second end of the switch SWb is connected to the node NCG1. One end of the resistor RL is connected to the node NCG2, and the other end of the resistor RL is connected to the node NCG1. The switch SWb is, for example, a two-terminal switch element, and while the switch SWb is in an on state, a signal can be transmitted between the first end and the second end.

[0059] The leak detection unit LD is connected to the nodes NCG1 and NCG2. The leak detection unit LD detects the current flowing through the signal lines CG0 to CG7 based on the voltage Vusel1 of the node NCG1 and the voltage Vusel2 of the node NCG2. The leak detection unit LD can perform either a process of detecting the current flowing into the signal lines CG0 to CG7 or a process of detecting the current flowing out of the signal lines CG0 to CG7 as the leak detection process. Here, since the leak detection unit LD is used to detect the current flowing from the source line CELSRC to the word line WL, the leak detection unit LD performs a process of detecting the current flowing into the signal lines CG0 to CG7.

[0060] For example, during the leak detection process by the leak detection unit LD, the switch SWb is turned off, but otherwise the switch SWb is turned on. When the switch SWb is turned on, the voltage output from the pump unit 281B to the node NCG2 to which the first end is connected is transferred to the node NCG1 to which the second end is connected. This allows the voltage output by the pump unit 281B to be transferred to the driver set 29.

[0061] The leak detection unit LD includes, for example, switches SW1, SW2, SW3, SW4, capacitive elements C1 and C2, an amplifier circuit AMP, and a comparator CMP. First, the connection relationship of these components included in the leak detection unit LD will be described. A first end of the switch SW1 is connected to a node NCG1, and a second end of the switch SW1 is connected to a node N1. The connection between the first end of the switch SW1 and the node NCG1 realizes the connection between the leak detection unit LD and the node NCG1. A first end of the switch SW2 is connected to a node NCG2, and a second end of the switch SW2 is connected to the node N1. The connection between the first end of the switch SW2 and the node NCG2 realizes the connection between the leak detection unit LD and the node NCG2.

[0062] A first electrode of the capacitance element C1 is connected to the node N1, and a second electrode of the capacitance element C1 is connected to the node N2. A first terminal of the switch SW3 is connected to the node N2, and a voltage VBIAS is applied to a second terminal of the switch SW3. The voltage VBIAS is, for example, a substantially constant reference voltage. An input terminal of the amplifier circuit AMP is connected to the node N2, and the voltage VBIAS is applied to a reference voltage terminal of the amplifier circuit AMP. An output terminal of the amplifier circuit AMP is connected to a node N3. A first electrode of the capacitance element C2 is connected to the node N3, and a second electrode of the capacitance element C2 is connected to a node N4.

[0063] A first terminal of the switch SW4 is connected to the node N4, and a second terminal of the switch SW4 is, for example, grounded. In the following description, it is assumed that the second terminal of the switch SW4 is grounded and a voltage of 0V is applied to the second electrode of the switch SW4. A first input terminal of the comparator CMP is connected to the node N4, and a voltage VREF is applied to a second input terminal of the comparator CMP. The voltage VREF is, for example, a substantially constant reference voltage. The voltage VREF is, for example, lower than 0V.

[0064] Next, each component included in the leak detection unit LD will be further described. For example, while the switch SW1 is in an on state and the switch SW2 is in an off state, the switch SW1 transmits the voltage Vusel1 of the node NCG1 to the node N1. On the other hand, for example, while the switch SW1 is in an off state and the switch SW2 is in an on state, the switch SW2 transmits the voltage Vusel2 of the node NCG2 to the node N1. In this way, the switches SW1 and SW2 can selectively transfer one of the voltages Vusel1 and Vusel2 to the node N1. If there is a leak current on the word line WL, while the switch SWb is in an off state and at least one of the switches SW1 and SW2 is in an off state, the leak current flows between the nodes NCG1 and NCG2 through the resistor RL. The switches SW1 and SW2 sequentially transfer the mutually different voltages Vusel1 and Vusel2 to the node N1 in this manner, thereby changing the voltage Vn1 at the node N1 between the voltages Vusel1 and Vusel2. The switches SW1 and SW2 change the voltage Vn1, for example, from the higher of the voltages Vusel1 and Vusel2 to the lower of the voltages Vusel1 and Vusel2.

[0065] While the switch SW3 is in an on state, the switch SW3 transmits the voltage VBIAS applied to the second terminal to the node N2 connected to the first terminal. In this way, the switch SW3 can fix the voltage of the node N2 to the voltage VBIAS. Meanwhile, while the switch SW3 is in an off state, the capacitive element C1 holds the potential difference between the first electrode and the second electrode of the capacitive element C1 when the switch SW3 is turned off. If, for example, the voltage Vn1 changes while the switch SW3 is in an off state, the capacitive element C1 holds the potential difference between the first electrode and the second electrode, so that the voltage Vn2 changes by substantially the same amount as the change in the voltage Vn1. In this way, the capacitive element C1 can transmit the change in the voltage Vn1 to the node N2 as a change in the voltage Vn2.

[0066] The amplifier circuit AMP amplifies the voltage Vn2 at the node N2 connected to the input terminal of the amplifier circuit AMP based on the voltage VBIAS applied to the reference voltage terminal of the amplifier circuit AMP, and outputs the signal resulting from the amplification onto the node N3 connected to the output terminal of the amplifier circuit AMP. In the following description, the amplification factor is assumed to be 10, but the amplification factor is not necessarily limited to this.

[0067] When the voltage Vn2 changes, the amplifier circuit AMP outputs a signal resulting from amplifying the voltage Vn2 based on the voltage VBIAS onto the node N3, so that the voltage Vn3 on the node N3 changes by substantially the same amount as if the amount of change in the voltage Vn2 had been multiplied by 10. In this way, the amplifier circuit AMP amplifies the change in the voltage Vn2 and transmits it to the node N3 as a change in the voltage Vn3.

[0068] While the switch SW4 is in an on state, the switch SW4 transmits 0V applied to the second terminal to the node N4 connected to the first terminal. In this way, the switch SW4 can fix the voltage Vn4 of the node N4 to a voltage of 0V. On the other hand, while the switch SW4 is in an off state, the capacitive element C2 holds the potential difference between the first electrode and the second electrode of the capacitive element C2 when the switch SW4 is turned off. If, for example, the voltage Vn3 changes while the switch SW4 is in an off state, the capacitive element C2 holds the potential difference between the first electrode and the second electrode, so that the voltage Vn4 changes by substantially the same amount as the change in the voltage Vn3. In this way, the capacitive element C2 can transmit the change in the voltage Vn3 to the node N4 as a change in the voltage Vn4.

[0069] The comparator CMP outputs a signal representing the result of comparing the voltage of the node N4 connected to the first input terminal with the voltage VREF applied to the second input terminal. This signal is the signal FLG. The level of the signal FLG differs depending on whether the level of the voltage Vn4 is lower than the voltage VREF or not. A change in the level of the signal FLG may mean that a leakage current has been detected.

[0070] The circuit configuration of the detection circuit 282 is not limited to the one described above. For example, the leakage detection unit LD may have another configuration capable of detecting the leakage current based on the change in the voltage Vn1 described above. The row decoder 25 has a plurality of switch circuit groups 25A corresponding to each block BLK, and a plurality of block decoders 25B provided corresponding to the plurality of switch circuit groups 25A. Each switch circuit group 25A includes a plurality of transistors TR_SG0 to TR_SG3 connecting the signal lines SG0 to SG3 and the select gate lines SGD0 to SGD3, a plurality of transistors TR_CG0 to TR_CG7 connecting the signal lines CG0 to CG7 and the word lines WL0 to WL7, and a transistor TR_SG4 connecting the signal line SG4 and the select gate line SGS. Each of the transistors TR_SG0 to TR_SG4 and the transistors TR_CG0 to TR_CG7 is a high-voltage transistor.

[0071] When each block decoder 25B is specified by a row address, it supplies a block selection signal BLKSEL to the gates of the transistors TR_SG0 to TR_SG4 and the transistors TR_CG0 to TR_CG7. As a result, in the switch circuit group 25A to which the block selection signal BLKSEL is supplied from the block decoder 25B specified by the row address, the transistors TR_SG0 to TR_SG4 and the transistors TR_CG0 to TR_CG7 are turned on and become conductive. Therefore, the voltage supplied from the plane voltage generation circuit 28B to the signal lines SG0 to SG4 and the signal lines CG0 to CG7 is supplied to the select gate lines SGD0 to SGD3, SGS and word lines WL0 to WL7 included in the block BLK to be operated.

[0072] The plane common voltage generating circuit 28A includes a plurality of pump units 280A and 280B. The pump unit 280A generates a voltage to be supplied to the well line CPWELL for all the planes P0 to P3 in the memory unit MU. The well line CPWELL is commonly connected to each block BLK. The pump unit 280B generates a voltage VERA, a voltage VCELSRC, and the like to be supplied to the source line CELSRC for all the planes P0 to P3 in the memory unit MU. The voltage VERA is an erase voltage capable of extracting the charge stored in the charge storage layer 336 during a data erase operation, and is a high voltage of, for example, 20V or more. The voltage VCELSRC is a voltage applied to the source line CELSRC during a data read operation. The source line CELSRC is also commonly connected to each block BLK. (2.Operation) Next, a data erasing operation (hereinafter, referred to as an erasing operation), which is a characteristic operation of this embodiment, will be described. (2-0. Threshold voltage distribution of memory cell transistors) Prior to describing the data erase operation, the threshold voltage distribution of the memory cell transistor will be described. FIG. 15A is a diagram showing an example of the threshold voltage distribution in the first embodiment. FIG. 15A shows an example of the threshold voltage distribution of a 3-bit / cell nonvolatile memory 2. In the nonvolatile memory 2, information is stored based on the amount of charge stored in the charge storage layer of the memory cell. Each memory cell has a threshold voltage according to the amount of charge. A plurality of data values ​​stored in the memory cell are made to correspond to a plurality of regions of the threshold voltage (threshold voltage distribution regions), respectively.

[0073] In Fig. 15A, the eight distributions (mountain shapes) labeled Er, A, B, C, D, E, F, and G indicate eight threshold voltage distribution regions. Thus, each memory cell has a threshold voltage distribution separated by seven boundaries. The horizontal axis of Fig. 15A indicates the threshold voltage, and the vertical axis indicates the distribution of the number of memory cells (cell count).

[0074] In this embodiment, the region where the threshold voltage is below VrA is called region Er (Er level), the region where the threshold voltage is greater than VrA and equal to or less than VrB is called region A, the region where the threshold voltage is greater than VrB and equal to or less than VrC is called region B, and the region where the threshold voltage is greater than VrC and equal to or less than VrD is called region C. Also, in this embodiment, the region where the threshold voltage is greater than VrD and equal to or less than VrE is called region D, the region where the threshold voltage is greater than VrE and equal to or less than VrF is called region E, the region where the threshold voltage is greater than VrF and equal to or less than VrG is called region F, and the region where the threshold voltage is greater than VrG is called region G.

[0075] The threshold voltage distributions corresponding to the regions Er, A, B, C, D, E, F, and G are called distributions Er, A, B, C, D, E, F, and G (1st to 8th distributions), respectively. VrA to VrG are threshold voltages that are boundaries between each region.

[0076] In the non-volatile memory 2, multiple data values ​​are assigned to multiple threshold voltage distribution regions of the memory cell. This assignment is called data coding. This data coding is determined in advance, and when writing (programming) data, charge is injected into the memory cell so that the threshold voltage distribution region corresponds to the data value to be stored according to the data coding. When reading, a read voltage is applied to the memory cell, and the data is determined depending on whether the threshold voltage of the memory cell is lower or higher than the read voltage.

[0077] Fig. 15B is a diagram showing an example of data coding in the first embodiment. The eight threshold voltage distribution regions shown in Fig. 15A are made to correspond to eight data values ​​for three bits, for example, as shown in Fig. 15B. The relationship between the threshold voltage and the data values ​​of the bits corresponding to the Upper, Middle, and Lower pages is as shown below.

[0078] A memory cell whose threshold voltage is within the Er region stores "111".

[0079] A memory cell whose threshold voltage is within region A stores "101".

[0080] A memory cell whose threshold voltage is within region B stores "001".

[0081] A memory cell whose threshold voltage is within region C stores "011".

[0082] Memory cells whose threshold voltage is in region D store "010".

[0083] A memory cell whose threshold voltage is within the E region stores "110".

[0084] A memory cell whose threshold voltage is in the F region stores "100".

[0085] A memory cell whose threshold voltage is within the G region stores "000".

[0086] In this way, the state of 3-bit data of each memory cell can be expressed for each threshold voltage region. When the memory cell is in an unwritten state ("erased" state), the threshold voltage of the memory cell is within the Er region. In addition, in the code shown here, only 1 bit of data changes between any two adjacent states, such as storing data "111" in the Er (erased) state and storing data "101" in the A state. In this way, the coding shown in FIG. 15B is a Gray code in which only 1 bit of data changes between any two adjacent regions.

[0087] In addition, in FIG. 15A, eight levels are distributed discretely, but this is an ideal state immediately after writing data. In reality, adjacent levels may overlap. For example, after writing data, the upper end of distribution Er may overlap the lower end of distribution A due to disturbance or the like. In such a case, the data is corrected using, for example, ECC technology. (2-1. Concept of Erase Operation) The erase operation is an operation for discharging the charge stored in the charge storage layer 336 of each memory transistor MT included in the selected block BLK and setting the threshold voltage of these memory cell transistors MT to the erase level (Er level). The erase operation roughly includes an erase operation (Erase) and an erase verify operation (Evfy).

[0088] The erase operation is an operation to discharge charges from the charge storage layer 336. A high voltage (voltage VERA) is applied to the source line CELSRC, and holes (positive holes) are generated in the memory hole 334 by GIDL (Gate-Induced Drain Leakage) due to the potential difference with the select gate line SGS. The charges stored in the charge storage layer 336 are recombined with the holes, and the threshold voltage of the memory cell transistor MT returns to the Er level.

[0089] The erase verify operation is a read operation performed as a part of the erase operation. After the erase operation, data is read to determine whether the threshold voltage of the memory cell transistor MT has returned to the Er level. That is, the erase verify operation is an operation to check whether the data has been erased. If the threshold voltage of each memory transistor MT included in the selected block BLK has returned to the Er level, the block BLK is determined to be in a pass state (Pass). The block BLK determined to be in a pass state is then prohibited from being erased. On the other hand, if the threshold voltage of each memory cell transistor MT included in the selected block BLK has not returned to the Er level, the block BLK is determined to be in a fail state (Fail). The block BLK determined to be in a fail state is repeatedly subjected to the erase operation and the erase verify operation so that the threshold voltage of each memory transistor MT included in the block BLK returns to the Er level. A set of the erase operation and the erase verify operation is called a loop. An operation of repeatedly performing a plurality of loops is called an erase sequence. A block BLK that is not determined to be in a pass state even after performing an erase operation under a predetermined condition (for example, a predetermined number of times) is prohibited from use as a defective block. Note that, prior to the first erase operation, a preparatory operation such as calculation of a voltage VERA and a preprogram operation may be performed. Note that the preprogram operation is, for example, an operation of writing data to a block BLK to be erased to raise a threshold value in order to prevent memory cells in which data is not written from being over-erased by an erase operation. (2-2. Erase Operation in Comparative Example) Prior to the description of the erase operation in this embodiment, the erase operation in the comparative example will be described. Hereinafter, the erase operation for the nonvolatile memory of the comparative example will be described with reference to Figs. 6A, 6B, and 7. The nonvolatile memory of the comparative example is provided with a memory unit MU having four planes P0 to P3, similar to the nonvolatile memory of the embodiment shown in Fig. 2. Figs. 6A and 7 are diagrams for explaining the command sequence and the operation of each plane in the comparative example in chronological order. Figs. 6A and 7 show the commands transmitted and received by the signals DQ<7:0> (DQ0 to DQ7), the waveform of the ready / busy signal / RB, and the operation of the planes P0 to P3 in chronological order. Fig. 6B is a diagram showing the voltage change of each wiring in the comparative example. Specifically, it shows the voltage change of each wiring in the operation of Fig. 6A.

[0090] First, a case where the erase operation is normally performed will be described with reference to Figures 6A and 6B. As shown in Figure 6A, when the ready-busy signal / RB is in a high state, that is, when the nonvolatile memory 2 is in a ready state, a set of a command 60h instructing block erase as a signal DQ and an address ADD of the target plane and the target block is transmitted from the memory controller 1 to the nonvolatile memory 2. In a nonvolatile memory equipped with a plurality of planes, when an erase instruction is input from the memory controller 1, an erase operation is performed on all the planes. For example, in the case of a nonvolatile memory 2 equipped with four planes, signals are transmitted in the order of command 60h, address ADD (address of the block BLK to be erased in plane 0), command 60h, address ADD (address of the block BLK to be erased in plane 1), command 60h, address ADD (address of the block BLK to be erased in plane 2), command 60h, address ADD (address of the block BLK to be erased in plane 3). Following these signals, when the execution command D0h is sent, the ready / busy signal / RB switches from high to low, and the non-volatile memory 2 switches to a busy state. Then, an erase operation is started for the designated block BLK of each of the planes P0 to P4. The following erase operation is executed based on the instruction of the sequencer 27.

[0091] 6A shows a case where planes P0, P2, and P3 become pass state after three erase operations, and plane P1 becomes pass state after two erase operations. At this time, each signal line has a waveform as shown in FIG. 6B. That is, in the erase operations starting at times T0, T2, and T4, voltage VERA is applied to source line CELSRC, and in the erase verify operations starting at times T1, T3, and T5, voltage VCELSRC is applied to source line CELSRC. Between the erase operations and the erase verify operations, the voltage is lowered to voltage VSS. That is, the source line CELSRC changes in the order of voltage VSS, voltage VERA, voltage VSS, voltage VCELSRC, voltage VSS, ... A signal line CG (shown as CG@P0 in FIG. 6B) that supplies a voltage to the word line WL of the plane P0, a signal line CG (shown as CG@P1 in FIG. 6B) that supplies a voltage to the word line WL of the plane P1, a signal line CG (shown as CG@P2 in FIG. 6B) that supplies a voltage to the word line WL of the plane P2, and a signal line CG (shown as CG@P3 in FIG. 6B) that supplies a voltage to the word line WL of the plane P3 are applied with, for example, a voltage VSS in the erase operation that starts at time T0, T2, and T4. Also, a voltage VCGRV is applied to these signal lines CG in the erase verify operation that starts at time T1, T3, and T5. Note that the voltage applied to each signal line CG in the erase operation may be a voltage other than the voltage VSS. The voltage applied to each signal line CG in the erase operation may be, for example, a voltage VPASS, a voltage VCC (a driving power supply voltage VDD of the circuit), or the like. In any case of the voltage, the waveform is the same as that in FIG. 6B.

[0092] Since the erase operation is performed three times on the planes P0, P2, and P3, the pulse of the voltage VCGRV appears three times at the timing of the erase verify operation. Since the plane P1 passes the erase operation two times, the pulse of the voltage VCGRV appears two times. When the planes P0, P2, and P3 are performing the third erase operation, the plane P1 is in a non-selected state in which no erase operation is performed. In the non-selected state, the signal line CG is in a floating state. Therefore, due to the capacitive coupling between the signal line CG and the source line CELSRC, while the voltage VERA is applied to the source line CELSRC, the voltage of the signal line CG is also boosted as shown by the dotted line in FIG. 6B.

[0093] Returning to FIG. 6A, when the selected blocks BLK in all planes P0 to P3 are determined to be in a pass state, the erase operation is completed, and the ready-busy signal / RB switches from low to high. Then, a command 71h, which is a read status command, is transmitted as a signal DQ from the non-volatile memory 2 to the memory controller 1, followed by a command SR indicating the status. Note that the command 71h and the command SR are only examples, and the status may be transmitted using other commands. In FIG. 6A, a "Pass" command is transmitted as the command SR, indicating that the blocks BLK in all planes P0 to P3 have entered a pass state.

[0094] Next, a case where a leak current occurs in any of the planes (for example, plane P2) and the erase operation is not performed normally will be described with reference to FIG. 7. As described above, when four pairs of a command 60h and an address ADD are transmitted as a signal DQ from the memory controller 1 to the nonvolatile memory 2, followed by a command D0h, an erase operation is started for the designated block BLK of each of the planes P0 to P3. For example, when a defect occurs in the memory cell array 23 of the plane P2 and a leak current occurs from the source line CELSRC to the word line WL, the source line CELSRC cannot be held at the voltage VERA in the erase operation. When the source line CELSRC drops from the voltage VERA, holes for recombining with the charge in the charge storage layer 336 cannot be generated sufficiently. That is, even if the erase operation is repeated, the block BLK cannot be put into a pass state. When the erase operation is performed only for a predetermined condition (for example, a predetermined number of executions), the erase operation ends, and the nonvolatile memory 2 transmits a command 71h and a command SR to the memory controller 1 in that order. Since the source line CELSRC is common to all planes P0 to P3, the block BLK is not judged to be in a pass state in any of the planes P0 to P3 even if the erase operation is repeated. When this state occurs, it is judged to be ESF (Erase Status Fail), and a "Fail" command is sent as a command SR indicating that the block BLK is in a fail state in all of the planes P0 to P3. In this case, the selected block BLK in all of the planes P0 to P3 is prohibited from use as a defective block. In this embodiment, the judgment of ESF is referred to as an ESF judgment.

[0095] In this way, in the comparative example, for example, even though only the block BLK in the plane P2 is defective and the blocks BLK in the planes P0, P1, and P3 are normal, the blocks BLK in all the planes P0 to P3 are classified as defective blocks. In other words, the blocks BLK that are originally usable become unusable, so that the number of usable memory cells decreases, and there is a possibility that the efficiency of memory cell usage decreases. (2-3. Erase Operation in This Embodiment) Next, the erase operation in this embodiment will be described. This embodiment is different from the comparative example described above in that a detection operation of a bad block is performed during the erase operation. In this embodiment, the detection operation (Detect) of a bad block refers to a series of operations from the detection operation to the determination operation. In this embodiment, as the detection operation, the detection circuit 282 is used to detect the leakage current of the erase target block BLK. Specifically, in a state where the voltage VSS is applied to the signal line CG and the voltage VERA is applied to the source line CELSRC, it is detected whether or not a current flows through the signal line CG. The detection of the leakage current is performed for each of the planes P0 to P3. In this embodiment, as the determination operation, the validity of the erase sequence for the erase target block BLK is determined. If the erase sequence is valid, the threshold voltage of each memory transistor MT included in the erase target block BLK is at the Er level. If the erase sequence is not valid, the threshold voltage of each memory transistor MT included in the erase target block BLK is not at the Er level. The determination operation is performed, for example, in the sequencer 27. The block BLK in which the leakage current is detected by the detection operation is determined to be in a fail state (the erase sequence is not valid) in the determination operation of the sequencer 27, and the subsequent erase operation and erase verify operation are not performed.

[0096] The execution timing of the detection operation during the erase operation is roughly divided into three: (a) before the first erase operation, (b) immediately after or during the first erase operation, and (c) after the internal ESF determination. The erase operation of this embodiment will be described below for each execution timing. In the following description of the erase operation in each embodiment, it is assumed that the block BLK of the plane P2 is defective due to a defect or the like, and the planes P0, P1, and P3 are normal. (a) Before the first erase operation An erase operation in the case where a detection operation is performed before the first erase operation is performed will be described with reference to Figures 8A and 8B. Figures 8A and 8B are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. Figure 8A is divided into two parts, upper and lower, but the time indicated by the dotted line A in the upper part and the time indicated by the dotted line A in the lower part indicate the same time. That is, the operation shown in the upper part and the operation shown in the lower part are performed consecutively.

[0097] 8A, when four pairs of command 60h and address ADD are transmitted as signal DQ from memory controller 1 to non-volatile memory 2, followed by command D0h, an erase operation is started for the designated block BLK in each of planes P0 to P3. Then, first, a detection operation is performed for block BLK in plane P0. That is, a voltage VERA is applied to source line CELSRC, a voltage VSS is applied to signal line CG in plane P0, signal lines CG in planes P1 to P3 are set in a floating state, and a leakage current is detected using detection circuit 282 arranged in plane P0.

[0098] FIG. 8C is a diagram showing an example of voltage changes in each wiring of the detection circuit in the first embodiment. FIG. 8C also shows time changes in the voltage of the control signal input to each of several switches SW. Before the start of the leakage current detection operation shown in FIG. 8C, for example, the switch SWb is in an ON state, and the nodes NCG1 and NCG2 are each stable at the voltage VSS. A control signal is input to the switch SW1 at a high (H) level, and the switch SW1 is in an ON state. A control signal is input to the switch SW2 at a low (L) level, and the switch SW2 is in an OFF state. Since the switch SW1 is in an ON state and the switch SW2 is in an OFF state, the switch SW1 in an ON state transmits the voltage Vusel1 to the node N1. As a result, the voltage Vn1 is also stable at the voltage VSS. A control signal is input to the switch SW3 at an H level, and the switch SW3 is in an ON state. The switch SW3 in an ON state transmits the voltage VBIAS to the node N2. As a result, the voltage Vn2 is stable at the voltage VBIAS. The amplifier circuit AMP amplifies the voltage Vn2 with respect to the voltage VBIAS and outputs the resulting signal on the node N3, so the voltage Vn3 is 0V and is shown as the voltage VGND in FIG. 8C. A control signal is input to the switch SW4 at the H level, and the switch SW4 is in the ON state. The switch SW4 in the ON state transmits the voltage VGND to the node N4. As a result, the voltage Vn4 is also stable at the voltage VGND.

[0099] From time T00 to the completion of the leakage current detection operation, a control signal is input to the switch SWb at L level, and the switch SWb is in an off state. At time T00, an operation is started to control the voltage output by the pump unit 281B to the node NCG2 connected to the word line WL to the voltage VERASE (for example, the voltage VSS) during the erase operation. As a result, the voltage Vusel2 is stabilized at the voltage VERASE. The voltage output by the pump unit 281B to the node NCG2 is transmitted to the node NCG1 electrically connected to the node NCG2. As a result, the voltage Vusel1 is stabilized at the voltage VERASEi during the erase operation. Here, a case where a leakage current flows into the word line WL will be described. The leakage current flows, for example, from the node NCG1 to the node NCG2 via the resistor RL. Therefore, a voltage drop occurs in the resistor RL due to the leakage current. In this case, the voltage VERASEi is higher than the voltage VERASE by the amount of the voltage drop. In FIG. 8C, the potential difference between the voltage VERASEi and the voltage VERASE is indicated as ΔVi.

[0100] The levels of the control signals input to the switches SW1, SW2, SW3, and SW4 are maintained. Since the switch SW1 is in the on state, the voltage Vn1 changes according to the voltage Vusel1 and stabilizes at the voltage VERASEi. Although omitted in FIG. 8C, at time T00, the voltage applied to the source line CELSRC is changed from the voltage VSS to the voltage VERA.

[0101] Next, at time T01, the control signal input to the switch SW3 is changed from H level to L level, and the switch SW3 is switched from the on state to the off state. As the switch SW3 turns off, for example, the voltage Vn2 changes and stabilizes at the voltage VBIASi. As the voltage Vn2 changes, the voltage Vn3 changes and stabilizes at the voltage VGNDi. For example, the potential difference between the voltage VGNDi and the voltage VGND is 10 times the voltage difference between the voltage VBIASi and the voltage VBIAS due to amplification by the amplifier circuit AMP. In this way, as the switch SW3 turns off, the voltage Vn2 is released from being fixed at the voltage VBIAS, and the voltages Vn2 and Vn3 are affected by the change in the voltage Vn1 when the voltage Vn1 changes.

[0102] Next, at time T02, the control signal input to switch SW4 is changed from H level to L level, and switch SW4 is turned from on to off. By switch SW4 turning off, voltage Vn4 is released from being fixed to voltage VGND, and if voltage Vn3 changes, it will be affected by the change. Next, at time T03, the control signal input to switch SW1 is changed from H level to L level, and switch SW1 is turned from on to off.

[0103] Next, at time T04, the control signal input to switch SW2 changes from L level to H level, and switch SW2 changes from off state to on state. Since switch SW1 is off state and switch SW2 is on state, switch SW2 in the on state transmits voltage Vusel2 to node N1. As a result, voltage Vn1 is stabilized at voltage VERASE, the same as voltage Vusel2. In this way, voltage Vn1 drops from voltage VERASEi by the voltage difference ΔVi.

[0104] In response to the voltage Vn1 dropping by the voltage difference ΔVi, the voltage Vn2 drops from the voltage VBIASi by the voltage difference ΔVi, because the capacitive element C1 holds the potential difference between the first electrode and the second electrode of the capacitive element C1 when the switch SW3 is turned off.

[0105] In response to the voltage Vn2 dropping by the voltage difference ΔVi, the voltage Vn3 drops from the voltage VGNDi. The change in the voltage Vn3 is 10 times the voltage difference ΔVi, which is the change in the voltage Vn2. This is because the amplifier circuit AMP outputs a signal resulting from amplifying the voltage Vn2 based on the voltage VBIAS onto the node N3.

[0106] In response to the voltage Vn3 dropping by 10 times the voltage difference ΔVi, the voltage Vn4 drops from the voltage VGND by 10 times ΔVi, because the capacitive element C2 holds the potential difference between the first electrode and the second electrode of the capacitive element C2 when the switch SW4 is turned off.

[0107] The comparator CMP outputs a signal FLG that is a result of comparing the voltage Vn4 with the voltage VREF. When the voltage Vn4 changes at time T04 and falls below the voltage VREF as shown in FIG. 8C, the level of the signal FLG output from the comparator CMP changes. This change in the level of the signal FLG means that a leakage current flowing into the word line WL has been detected.

[0108] If no leakage current is detected, the sequencer 27 determines that the block BLK is normal (Pass). On the other hand, if a leakage current is detected, the block BLK is determined to be defective (Fail). In the above description, the current value detected by the detection circuit 282 is output to the sequencer 27, and the sequencer 27 determines whether the block is defective, but the detection circuit 282 may also determine whether the block is defective based on the leakage current. When the detection operation for the block BLK in the plane P0 is completed, the detection operation is sequentially performed on the blocks BLK in the other planes P1 to P3.

[0109] When the detection operation is completed for the blocks BLK of all the planes P0 to P3, the erase operation is performed only for the blocks BLK that are determined to be normal. FIG. 8D is a diagram showing an example of the voltage change of each signal line in the first embodiment. Specifically, it shows the voltage change of each signal line in the erase operation after the detection operation of FIG. 8A is completed. For example, if the block BLK of the plane P2 is determined to be defective in the detection operation, in the erase operation starting at time T0 and T2, the voltage VERA is applied to the source line CELSRC, the voltage VSS is applied to the signal lines CG of the planes P0, P1, and P3, and the signal line CG of the plane P2 is set to a floating state. That is, the block BLK of the plane P2 is deselected, and the erase operation can be selectively performed on the blocks BLK of the other planes P0, P1, and P3. Since the plane P1 is in a pass state after two erase operations, the third erase operation is not performed. That is, in the erase operation starting at time T4, the voltage VERA is applied to the source line CELSRC, the voltage VSS is applied to the signal lines CG of the planes P0 and P3, and the signal lines CG of the planes P1 and P2 are set in a floating state.

[0110] The defective block (plane P2) is not subjected to the erase verify operation. That is, in the erase verify operation starting from time T1 and T3, the voltage VCGRV is applied to the signal lines CG of the planes P0, P1, and P3, and the voltage VSS is applied to the signal line CG of the plane P2. Since the plane P1 is in a pass state after two erase operations, the third erase verify operation is not performed. That is, in the erase verify operation starting from time T5, the voltage VCGRV is applied to the signal lines CG of the planes P0 and P3, and the voltage VSS is applied to the signal lines CG of the planes P1 and P2. When all the blocks BLK of the planes P0, P1, and P3 on which the erase operation has been performed are determined to be in a pass state, the erase operation is terminated. Then, the command 71h is transmitted as the signal DQ from the nonvolatile memory 2 to the memory controller 1, followed by the command SR. In FIG. 8A, the command SR transmitted indicates that the blocks BLK in all of the planes P0, P1, and P3 are in a pass state, and that the block BLK in the plane P2 is in a fail state.

[0111] Thus, according to this embodiment, in an erase operation in which blocks BLK of multiple planes are erased in parallel, a detection operation is performed prior to the first erase operation to detect the presence or absence of a leak current from the source line CELSRC to the signal line CG. This detection operation makes it possible to detect a bad block. Therefore, it is possible to selectively perform an erase operation on blocks other than the bad block. By making the bad block unselected, it is possible to suppress a voltage drop on the source line CELSRC during the erase operation and to maintain the voltage VERA. Therefore, it is possible to put blocks other than the bad block into a pass state. Therefore, it is possible to prevent a decrease in the number of usable memory cells and to use the memory cells efficiently.

[0112] The operation shown in FIG. 8B is different from the operation shown in FIG. 8A described above in that the detection operation performed before the first erase operation is performed in parallel in all the planes P0 to P3. The configuration of the nonvolatile memory 2 performing the operation shown in FIG. 8B is the same as the configuration of the nonvolatile memory 2 performing the operation in FIG. 8A. That is, the detection circuit 282 provided in the plane P0 can detect the leak current from the source line CELSRC to the signal line CG@P0. The detection circuit 282 provided in the plane P1 can detect the leak current from the source line CELSRC to the signal line CG@P1. The detection circuit 282 provided in the plane P2 can detect the leak current from the source line CELSRC to the signal line CG@P2. The detection circuit 282 provided in the plane P3 can detect the leak current from the source line CELSRC to the signal line CG@P3. The detection circuit 282 of each of the planes P0 to P3 is used to detect the leak current of each block BLK in parallel, thereby shortening the time required for the erase operation. (b) Immediately after or during the first erase operation. An erase operation in the case where a detection operation is performed immediately after the first erase operation will be described with reference to Figures 9A and 9B. Figures 9A and 9B are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. Figure 9A is divided into two parts, upper and lower, but the time indicated by the dotted line A in the upper part and the time indicated by the dotted line A in the lower part represent the same time. That is, the operation shown in the upper part and the operation shown in the lower part are performed consecutively.

[0113] As shown in FIG. 9A, when four pairs of a command 60h and an address ADD are transmitted as a signal DQ from the memory controller 1 to the non-volatile memory 2, followed by a command D0h, an erase operation is started for the designated block BLK of each of the planes P0 to P3. FIG. 9F is a diagram showing an example of a voltage change of each signal line in the first embodiment. Specifically, the voltage change of each signal line until the detection operation of FIG. 9A is completed is shown. First, at time T10, the first erase operation is started for the block BLK of the plane P0. When the erase operation is completed at time T11, a detection operation is started in a state in which the source line CELSRC is not lowered to the voltage VSS and the voltage VERA is maintained. The detection operation by the detection circuit 282 is the same as the above-mentioned operation described with reference to FIG. 8A. When the detection operation of the plane 0 is completed at time T12, the detection operations of the blocks BLK of the other planes P1 to P3 are sequentially performed.

[0114] When the detection operation is completed for the blocks BLK in all the planes P0 to P3, the erase verify operation is performed only on the blocks BLK that are determined to be normal. When the blocks BLK in the planes P0, P1, and P3 on which the erase verify operation is performed are all determined to be in a pass state, the erase operation is completed. Then, a command 71h is transmitted as a signal DQ from the non-volatile memory 2 to the memory controller 1, followed by a command SR. In FIG. 9A, a command is transmitted as the command SR indicating that the blocks BLK in all the planes P0, P1, and P3 are in a pass state and that the block BLK in the plane P2 is in a fail state.

[0115] FIG. 9G is a diagram showing an example of voltage changes of each signal line in the first embodiment. Specifically, it shows voltage changes of each signal line from the start of the detection operation of FIG. 8A to the end of the first erase verify operation. As shown in FIG. 9G, when the detection operation is performed before the erase operation, a period Tbst is required to boost the source line CELSRC to the voltage VERA after the detection operation is started at time T20. After the source line CELSRC is boosted to the voltage VERA, leakage current detection is performed in a period Tdet. That is, the time required for the detection operation is period Tbst+period Tdet.

[0116] On the other hand, when the detection operation is performed immediately after the first erase operation, as shown in FIG. 9F, the detection operation is performed while the source line CELSRC holds the voltage VERA after the first erase operation is performed, so that there is no need to boost the source line CELSRC. That is, since the period Tbst is not required, the time required for the detection operation is the period Tdet. Therefore, compared with FIG. 8A, the time required for the detection operation can be shortened, and the time required for the erase operation can also be shortened. Note that the first erase operation may be performed in parallel on all planes P0 to P3 as shown in FIG. 9B. The detection operation may also be performed in parallel on all planes P0 to P3. By performing these operations in parallel on all planes P0 to P3, respectively, the time required for the erase operation can be further shortened.

[0117] Next, an erase operation in which a detection operation is performed while performing a first erase operation will be described with reference to Figures 9C and 9D. Figures 9C and 9D are diagrams for explaining an example of a command sequence and the operation of each plane in the first embodiment. Figure 9C is divided into two parts, upper and lower, but the time indicated by the dotted line A in the upper part and the time indicated by the dotted line A in the lower part represent the same time. That is, the operation shown in the upper part and the operation shown in the lower part are performed consecutively.

[0118] As shown in FIG. 9C, when an erase operation is started for a specified block BLK in each of the planes P0 to P3, a first erase operation is performed for the block BLK in the plane P0. After a predetermined time has elapsed since the erase operation, a detection operation is started while the erase operation is being performed. The detection operation is also performed until the erase operation is completed. The detection operation by the detection circuit 282 is the same as the operation described above with reference to FIG. 8A. After the first erase operation and detection operation of the plane 0 are completed, the first erase operation and detection operation are sequentially performed for the blocks BLK in the other planes P1 to P3.

[0119] In the sense operation, the voltage applied to the source line VCELSRC and the voltage applied to the signal line CG are the same as those applied to them in the erase operation. Moreover, the sense operation does not affect the function of the erase operation. Therefore, the erase operation and the sense operation can be performed in parallel. By performing the sense operation in parallel with the first erase operation, the erase time can be reduced compared to performing the sense operation immediately after the erase operation as shown in FIG. 9A.

[0120] The first erase operation including the detection operation may be performed in parallel in all planes P0 to P3 as shown in FIG. 9D. By performing the erase operation in parallel, the time required for the erase operation can be further shortened. FIG. 9E is a diagram showing an example of the voltage change of each wiring in the first embodiment. Specifically, the voltage change of each wiring in the operation of FIG. 9D is shown. The voltage of the signal line CG in the erase verify operation immediately before the erase operation in which the voltage of the signal line CG first becomes floating is different between the comparative example and the present embodiment. As shown in FIG. 6B, in the comparative example, the voltage of the signal line CG@P1 first becomes floating in the erase operation started at time T4. In the immediately preceding erase verify operation, that is, the erase verify operation started at time T3, the voltage VCGRV is applied to the signal line CG@P1. In contrast, in the present embodiment, the voltage of the signal line CG@P2 first becomes floating in the erase operation started at time T2 as shown in FIG. 9E. In the immediately preceding erase verify operation, that is, the erase verify operation started at time T1, the voltage VSS is applied to the signal line CG@P2. In the comparative example, the signal line CG becomes floating during the erase operation when the erase verify operation determines that the block BLK is in a pass state. In contrast, in this embodiment, the signal line CG becomes floating during the erase operation even if the block is determined to be a bad block in the detection operation. Therefore, as described above, a difference is observed in the voltage of the signal line CG. (c) After internal ESF determination In this specification, the term "ESF judged internally" means that the ESF judgement is performed inside the non-volatile memory 2 without going through the memory controller 1. When the block BLK of at least one of the planes P0 to P3 is a defective block, in the erase operation of the comparative example, the ESF judgement is performed for all the blocks BLK as defective blocks, and the signal DQ is transmitted from the non-volatile memory 2 to the memory controller 1. In this embodiment, the detection operation is performed after the ESF judgement is performed. The erase operation in the case where the detection operation is performed after the ESF judgement is performed internally will be described with reference to FIGS. 10A, 10B, and 10C. FIGS. 10A, 10B, and 10C are diagrams for explaining an example of the command sequence and the operation of each plane in the first embodiment. FIG. 10A is divided into two parts, upper and lower, and the time indicated by the dotted line A in the upper part and the time indicated by the dotted line A in the lower part represent the same time. That is, the operation shown in the upper part and the operation shown in the lower part are performed continuously.

[0121] As shown in the upper part of FIG. 10A, when the erase operation is started, the erase operation and the erase verify operation are repeated a predetermined number of times as in the comparative example, and the ESF judgment is made at the point of time of the dotted line A. Then, as shown in the lower part, the detection operation is sequentially performed on the selected blocks BLK of the planes P0 to P3. When the detection operation is completed for the blocks BLK of all the planes P0 to P3, the erase operation and the erase verify operation are selectively performed only on the blocks BLK that are judged to be normal. The blocks BLK that are judged to be defective in the detection operation are not selected, and neither the erase operation nor the erase verify operation is performed. When all the blocks BLK that are judged to be normal are judged to be in a pass state, the erase operation is completed. Then, the non-volatile memory 2 transmits a command 71h as a signal DQ to the memory controller 1, followed by a command SR. In FIG. 10A, a command indicating that the blocks BLK are in a pass state in all the planes P0, P1, and P3 and the block BLK of the plane P2 has become a fail state is transmitted as the command SR.

[0122] In this way, when the detection operation is performed only after the internal ESF determination, if all blocks BLK are in the pass state, the detection operation is not performed as in the comparative example. Therefore, when the occurrence rate of bad blocks is low, it is possible to shorten the average time of the erase operation compared to the above-mentioned cases (a) and (b) in which the detection operation is always performed for every erase operation.

[0123] The detection operation may be performed in parallel on all planes P0 to P3 as shown in FIG. 10B. By performing the detection operation in parallel, the time required for the erase operation can be shortened. Also, as shown in FIG. 10C, when an ESF is internally determined, the normal block BLK may be selectively erased by selecting the planes P0 to P3 one by one and retrying the erase operation in sequence without performing the detection operation. In the case of the operation shown in FIG. 10C, the detection circuit 282 is not necessary, so that the reduction in the number of usable memory cells can be prevented without increasing the area of ​​the nonvolatile memory 2, and the memory cells can be used efficiently.

[0124] In the above description, the detection circuit 282 is configured to be connected to the pump unit 281B, but the connection position is not limited to this as long as the leakage current that causes the drop in the voltage VERA applied to the source line CELSRC can be detected. Fig. 11 is a block diagram explaining another example of a voltage supply path to each wiring of the memory cell array according to the first embodiment. For example, as shown in Fig. 11, the detection circuit 292 may be connected to a signal line equalizer circuit 291.

[0125] Furthermore, when the nonvolatile memory 2 is configured with one plane P0, the detection operation is not necessary. Therefore, when the nonvolatile memory 2 is configured with one plane P0, for example, the sequencer 27 may be configured to automatically stop the detection operation and execute only the erase operation and the erase verify operation.

[0126] Furthermore, functions that can be performed during a normal erase operation, such as Suspend and Resume, can also be performed in the non-volatile memory 2 of this embodiment. Second embodiment Next, a second embodiment will be described. In the semiconductor memory device of this embodiment, the detection circuit and detection method are different from those of the first embodiment. Therefore, the connection position of the detection circuit is also different from that of the first embodiment. In the detection operation of this embodiment, a faulty block is detected according to the degree of decrease in the voltage VERA applied to the source line CELSRC during the detection operation. The same components are denoted by the same reference numerals and the description will be omitted. Below, the differences from the first embodiment will be described.

[0127] FIG. 12 is a block diagram for explaining an example of a voltage supply path to each wiring of the memory cell array according to the second embodiment. The detection circuit 283 of this embodiment is connected to a pump unit 280B that supplies a voltage to the source line CELSRC. The pump unit 280B drives a charge pump (not shown) according to the period of a predetermined pump clock signal PMPCLK, and continuously performs a boost operation up to the target voltage. When the voltage supplied to the source line CELSRC reaches the target voltage, the pump unit 280B stops the operation of the charge pump and stops the boost operation. The pump unit 280B monitors the voltage of the source line CELSRC, and when the voltage reaches a set lower limit (trigger voltage), it resumes the boost operation according to the period of the pump clock signal PMPCLK. In this way, the pump unit 280B intermittently repeats the boost operation according to the voltage of the source line CELSRC. FIGS. 13A to 13D are diagrams for explaining an example of the boost operation control of the pump unit 280B during the erase operation and the detection operation according to the second embodiment. In FIGS. 13A to 13D, the clock signal CLK is a control clock that controls the driving of the charge pump, and has the same period as that of the pump clock signal PMPCLK.

[0128] As shown in FIG. 13A, for example, during an erase operation, the pump unit 280B sets a target voltage that is higher than the voltage VERA by a predetermined voltage Vth, and oscillates the clock signal CLK to drive the charge pump until the voltage of the source line CELSRC reaches the target voltage. When the voltage of the source line CELSRC reaches the target voltage, the oscillation of the clock signal CLK is stopped, and the charge pump stops operating. The voltage of the source line CELSRC gradually decreases during the erase operation. When the voltage of the source line CELSRC reaches a trigger voltage (here, the voltage VERA), the pump unit 280B oscillates the clock signal CLK to re-drive the charge pump. In this way, the pump unit 280B intermittently drives the charge pump to supply voltage so that the voltage of the source line CELSRC is maintained at the voltage VERA.

[0129] The detection circuit 283 detects a voltage drop of the source line CELSRC from the driving state of the charge pump by monitoring the oscillation operation of the clock signal CLK. Specifically, monitoring the oscillation operation of the clock signal CLK means setting the trigger voltage to the voltage VERA and operating the pump unit 280B in a set detection operation period, similar to the erase operation. The set detection operation period is called, for example, ELD (Erase Leak Detect). As shown in FIG. 13A, in a normal state where the amount of voltage drop of the source line CELSRC is small (a state where the source line CELSRC can be maintained so as not to fall below the trigger voltage), the clock signal CLK alternately repeats oscillation and stopping. That is, in the detection operation period, the number of pulses of the clock signal CLK is smaller than the number of pulses of the pump clock signal PMPCLK, for example, about 50% of the number of pulses of the pump clock signal PMPCLK.

[0130] 13B, if the voltage drop of the source line CELSRC is large and the drop is larger than the boost amount even when the charge pump is driven, the voltage of the source line CELSRC may be boosted to the target voltage once, but it may fall below the trigger voltage and the voltage of the source line CELSRC may not be maintained above the trigger voltage even when the charge pump is driven again. In other words, during the detection operation period, the number of pulses of the clock signal CLK is equal to the number of pulses of the pump clock signal PMPCLK.

[0131] In this way, the number of pulses of the clock signal CLK during the detection operation period is counted, and if the ratio to the number of pulses of the pump clock signal PMPCLK is higher than a set value, it is estimated that the voltage drop amount of the source line CELSRC is large and a leakage current path exists during the erase operation. Therefore, in this embodiment, the detection operation is performed sequentially one by one for the set blocks BLK of the planes P0 to P3. The timing of the detection operation in the erase operation may be, for example, before the first erase operation as shown in FIG. 8A, or immediately after the first erase operation as shown in FIG. 9A. Also, as shown in FIG. 9C, the detection operation may be performed while the first erase operation is being performed. Furthermore, as shown in FIG. 10A, the detection operation may be performed only when the erase operation is performed and an ESF determination is made internally.

[0132] 13A and 13B show an example of the boost pressure operation control of the pump unit 280B when the detection operation is performed immediately after the first erase operation. Also, Figs. 13C and 13D show an example of the case where the detection operation is performed while the first erase operation is being performed. Figs. 13A and 13C show the operation for a normal block BLK, and Figs. 13B and 13D show the operation for a defective block.

[0133] In this way, a defective block can be detected by detecting the driving state of the charge pump in the pump unit 280B that supplies a voltage to the source line CELSRC, and therefore an erase operation can be selectively performed on blocks other than the defective block. This prevents a decrease in the number of usable memory cells, and allows efficient use of memory cells. Third embodiment Next, a third embodiment will be described. The semiconductor memory device of this embodiment differs from the first and second embodiments in the method of detecting a bad block. The same components are given the same reference numerals and the description will be omitted. Below, the points different from the first and second embodiments will be described.

[0134] In the present embodiment, the detection operation is a normal erase operation and an erase verify operation for each of the blocks BLK set in the planes P0 to P3. In the erase verify operation, the ratio of the memory transistors MT included in the selected block BLK whose threshold voltage has returned to the Er level is calculated, and if the ratio is less than a preset criterion, the block BLK is determined to be a defective block. After the determination of whether or not a block is defective is completed for all of the planes P0 to P3, the erase operation and the erase verify operation can be performed in parallel on normal blocks.

[0135] That is, in the detection operation in this embodiment, the result of the first erase verify operation is used to perform the operation of determining the defective block in the sequencer 27 or the like, so there is no need to provide a dedicated detection circuit. Therefore, it is possible to prevent a decrease in the number of usable memory cells without increasing the area of ​​the nonvolatile memory 2, and to use the memory cells efficiently. Note that the result of the second or subsequent erase verify operations may be used for the operation of determining the defective block. Also, the erase operation may be performed in parallel for all planes P0 to P3 as in the comparative example, and the above-mentioned detection operation may be executed only when the ESF is internally determined. (Fourth embodiment) Next, a fourth embodiment will be described. This embodiment differs from the first to third embodiments in that when the memory controller 1 causes the nonvolatile memory 2 to execute an erase operation, the memory controller 1 can specify the timing of the detection operation to be performed. The erase operation in this embodiment will be described below with reference to Figures 14A to 14H.

[0136] 14A to 14H are diagrams for explaining an example of a command sequence and the operation of each plane in the fourth embodiment. In the erase operation in this embodiment, a command specifying the timing of the detection operation is added before the command 60h transmitted as a signal DQ from the memory controller 1 to the non-volatile memory 2. A command that is prefixed in advance is used as the command specifying the timing of the detection operation. In FIGS. 14A to 14F, command XX, command YY, command YY', command ZZ, and command ZZ' are used as examples of the prefixed commands.

[0137] When command XX is added before command 60h, a detection operation is performed before the first erase operation as shown in FIG 14A. When command YY is added before command 60h, a detection operation is performed following the first erase operation as shown in FIG 14B. When command YY' is added before command 60h, a detection operation is performed during the first erase operation as shown in FIG 14C. When command ZZ is added before command 60h, a detection operation is performed after an internal ESF determination as shown in FIG 14D.

[0138] In addition, when a bad block is detected after the ESF judgment and an erase operation is performed again on only normal blocks, the detection operation may be performed without delay on the nonvolatile memory 2 side after the ESF judgment, as shown in FIG. 14D, or, as shown in FIG. 14E, a command 71h and a command SR may be sent in that order from the nonvolatile memory 2 to the memory controller 1, and a command ZZ may be given again from the memory controller 1 side to instruct re-erasure.

[0139] Also, when command ZZ' is added before command 60h, as shown in FIG. 14F, after an internal ESF determination is made, no detection operation is performed, and planes P0 to P3 are selected one by one and the erase operation is sequentially retried to selectively erase normal blocks BLK.

[0140] In addition, the timing of the detection operation can be specified by adding the prefixed command before the command 60h as described above, or by replacing the execution command D0h with the prefixed command and transmitting it. For example, as shown in FIG. 14G, by setting the execution command to command ZZ", after the internal ESF determination, the detection operation is not performed, and the planes P0 to P3 are selected one by one and the erase operation is sequentially retried to selectively erase the normal block BLK. That is, the erase operation shown in FIG. 14G is the same as the erase operation shown in FIG. 14F. In this way, when instructing the timing of the detection operation or the re-erase operation after the ESF determination, a command sequence in which command ZZ' is added before command 60h may be transmitted, or a command sequence in which command ZZ" is replaced as the execution command may be transmitted.

[0141] Furthermore, the timing of the detection operation may be set in advance by a parameter setting change command (Set Feature command) prior to the erase operation. When the timing of the detection operation is set using the Set Feature command, for example, a command sequence as shown in FIG. 14H can be used. That is, the setting can be switched as described above by sending the Set Feature command, which is a command D5h, a command LUN, an address ADD, followed by data B0 to B3, and finally sending an execution command D0h. Note that any bit of the data B0 to B3 is used to switch the setting of the detection execution timing. FIG. 14H shows a case where the timing of the detection operation is set before the first erase operation by the Set Feature command.

[0142] In this way, the timing of the detection operation from the memory controller 1 to the nonvolatile memory 2 can be switched by adding a prefix command to the beginning, changing the execution command, or using the Set Feature command.

[0143] The above-described embodiment of the present invention is shown as an example, and is not intended to limit the scope of the invention. This novel embodiment can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0144] 1...memory controller, 2...non-volatile memory, 23...memory cell array, 24...sense amplifier, 25...row decoder, 26...register, 27...sequencer, 28A...plane common voltage generation circuit, 28B...plane voltage generation circuit, 29...driver set, 281A, 281B...pump unit, 282, 283, 292...detection circuit, 291...signal equalization circuit, 336...charge storage layer, P0, P1, P2, P3...plane, BLK...block,

Claims

1. In a semiconductor memory device having a plurality of planes, Each of the plurality of planes comprises at least one block; The block includes a plurality of memory cells; The semiconductor memory device includes: a control unit that executes an erase sequence that repeats a plurality of loops including a set of an erase operation that erases data of each of the plurality of memory cells included in an erase target block, the block being the block selected one by one in each of the plurality of planes, and an erase verify operation that checks whether the data has been erased, and erases the data of each of the plurality of memory cells included in the erase target block; a source line electrically connected to one end of each of the plurality of memory cells included in each of the plurality of planes; It further comprises: The control unit detects whether or not there is a current leakage from the source line for each of the multiple erase target blocks, determines the validity of the erase sequence based on the results of the detection, and stops execution of the erase sequence for the erase target blocks that are determined to be invalid.

2. a first voltage generating circuit that generates a voltage to be supplied to the source line; 2. The semiconductor memory device according to claim 1, wherein said first voltage generating circuit supplies an erase voltage to said source line during said erase operation.

3. a plurality of word lines connected to the gates of the plurality of memory cells; a plurality of second voltage generating circuits each generating a voltage to be supplied to the plurality of word lines and corresponding to each of the plurality of planes; Further comprising:

3. The semiconductor memory device according to claim 2, wherein during the erase operation, the word lines connected to the memory cells included in the block to be erased in one of the planes are supplied with a ground voltage from the second voltage generating circuit corresponding to the one of the planes.

4. Each of the plurality of planes further includes a first detection circuit that performs a first detection operation to detect currents of the plurality of word lines to which a voltage is supplied from a corresponding one of the second voltage generating circuits; each of the first detection circuits performs the first detection operation in a state in which the erase voltage is supplied from the first voltage generation circuit to the source line and the ground voltage is supplied from the second voltage generation circuit to the word lines connected to the memory cells included in the block to be erased; 4. The semiconductor memory device according to claim 3, wherein said control section determines that said erase sequence is not valid for said erase target block when said current is detected in said first detection operation.

5. a second detection circuit configured to perform a second detection operation of detecting a clock number of a charge pump that generates a voltage of the source line in the first voltage generation circuit; the second detection circuit performs the second detection operation in a state in which the erase voltage is supplied from the first voltage generation circuit to the source line and the ground voltage is supplied from one of the second voltage generation circuits to the word lines connected to the memory cells included in the block to be erased; 4 . The semiconductor memory device according to claim 3 , wherein said control unit determines that said erase sequence is not valid for said erase target block when said clock count is higher than a set threshold value in said second detection operation.

6. 2. The semiconductor memory device according to claim 1, wherein the control unit sequentially executes the erase operation and the erase verify operation for each of the plurality of erase target blocks, and determines that the erase sequence is not valid for a block to be erased in which the degree of erasure of the data is equal to or less than a set value in the erase verify operation.

7. 7. The semiconductor memory device according to claim 4, wherein the determination in the control unit is performed after a first erase operation in the erase sequence is performed, and after the determination operation is completed, the erase sequence is executed from the erase verify operation.

8. 7. The semiconductor memory device according to claim 4, wherein the determination in the control unit is performed before a first erase operation in the erase sequence is performed, and after the determination is completed, the erase sequence is executed from the erase operation.

9. A data erasing method for a semiconductor memory device having a plurality of planes, comprising the steps of: Each of the plurality of planes comprises at least one block; The block includes a plurality of memory cells; a source line electrically connected to one end of a plurality of the memory cells included in all of the plurality of planes; detecting the presence or absence of current leakage from the source line for each of the blocks to be erased, the blocks being the blocks selected one by one in each of the plurality of planes; determining, based on a result of the detection, the validity of an erase sequence that repeatedly performs a plurality of loops including a set of an erase operation for erasing data from each of the plurality of memory cells included in each of the blocks and an erase verify operation for verifying whether or not the data has been erased; canceling the execution of the erase sequence for the block to be erased that is determined to be invalid; A method for erasing data, including

10. Detecting the presence or absence of current leakage from the source line includes: measuring, for each of the selected blocks included in each of the plurality of planes, the number of operation clocks of a charge pump that supplies a voltage to the source line between a first erase operation and a first erase verify of the erase sequence; determining that the erase sequence of the block for which the number of operation clocks has exceeded a set threshold is invalid; The data erasure method according to claim 9 , further comprising:

11. In a semiconductor memory device having a first plane and a second plane, the first plane includes a first block having a first memory cell; the second plane includes a second block having second memory cells; a source line electrically connected to one end of each of the first and second memory cells; a second voltage generating circuit that supplies a voltage to the source line; a second detection circuit for performing a second detection operation in the second voltage generating circuit to detect a clock number of a charge pump that generates a voltage of the source line; a control unit that executes an erase sequence that repeats a plurality of loops including a set of an erase operation that erases data in the first memory cell and the second memory cell, and an erase verify operation that checks whether the data has been erased; the second detection circuit performs the second detection operation during a first erase operation and a first erase verify operation, in a state in which the erase voltage is supplied from the first voltage generation circuit to the source line and a ground voltage is supplied to a plurality of word lines connected to either the first memory cell or the second memory cell; A semiconductor memory device, wherein when the number of clocks detected in the second detection operation in the first plane is higher than a threshold value and the number of clocks detected in the second detection operation in the second plane is lower than a threshold value, the control unit executes the erase sequence on the first plane and stops execution of the erase sequence on the second plane.

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