Integrated circuit and data storage method

Abstract

To improve management of secure access to multiple memory dies stacked in a common package.SOLUTION: An integrated circuit includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary chip select signal via a primary chip select line. The secondary memory die is coupled to the bus, excluding the primary chip select line, and coupled to a secondary chip select line provided by the primary memory die. The primary memory die is configured to: receive a command while the primary chip select signal is active; in response to identifying that the command is destined for the primary memory die, execute the command within the primary memory die; and, in response to identifying that the command is destined for the secondary memory die, cause the secondary memory die to execute the command by transferring the primary chip select signal on the secondary chip select line.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to secure data storage, and more particularly to a secure storage method and system for use in multi-die packages. [Background technology]

[0002] Various systems store data in storage devices that include multiple memory dies stacked in a common package.

[0003] The use of multiple memory dies stacked in a common package is a known technique. For example, U.S. Patent 9,245,590 describes stacking and packaging any number of Serial Peripheral Interface ("SPI") flash memory dies to achieve any one or combination of various features, such as low bit cost, high density storage, code shadowing to RAM, and fast random access for "execute in place" applications, while retaining the benefits of the SPI interface. When the device is manufactured, each stacked die is assigned a unique identification or "die ID" relative to the other stacked dies in the package. During normal operation, the unique die ID is used by a die select command to enable any one of the stacked dies to respond to subsequent commands on the SPI interface and to prevent other stacked dies in the package from responding to subsequent commands, except for some "universal" commands, including the die select command, to support parallel operation of the stacked dies.

[0004] As another example, U.S. Patent No. 11,194,726 describes a method, system, and apparatus for stacking memory dies and combining access operations. The apparatus may include multiple memory dies. One die may be configured as a master device and the other die may be configured as a slave device. The master device may communicate with a host device. The slave device may be coupled to the master device. The apparatus may include a first die (e.g., a master device) and a second die (e.g., a slave device). The first die may be coupled to the host device and configured to output a data set in response to a read command. The first die may provide a first subset of data and obtain a second subset of data from the second die. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENT EMBODIMENTS Embodiments of the present invention provide improvements for managing secure access to multiple memory dies stacked in a common package. [Means for solving the problem]

[0006] The embodiments described herein provide an integrated circuit (IC) including a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary CS signal via a primary Chip Select (CS) line connecting to the primary memory die. The secondary memory die is coupled to the bus not including the primary CS line and coupled to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command via the bus when the primary CS signal is active; in response to identifying that the command is addressed to the primary memory die, execute the command in the primary memory die; and in response to identifying that the command is addressed to the secondary memory die, cause the secondary memory die to execute the command by transmitting the primary CS signal as a secondary CS signal on the secondary CS line.

[0007] In some embodiments, the primary memory die includes a local memory selectable by a local enable signal carried on the local enable line, and the primary memory die is configured to execute a command by (i) transmitting a primary CS signal on the local enable line as a local enable signal; and (ii) deactivating a secondary CS signal provided to the secondary memory die. In other embodiments, the IC includes another secondary die, the other secondary die coupled to a bus not including the primary CS line and coupled to another secondary CS line carrying another secondary CS signal provided by the primary memory die, and the primary die is configured to cause the other secondary die to execute a command by (i) transmitting the primary CS signal on the other secondary CS line as another secondary CS signal; (ii) deactivating the secondary CS signal provided to the secondary die; and (iii) deactivating a local enable signal of the local memory provided to the primary die. In other embodiments, the primary memory die and the secondary memory die have corresponding first and second different memory types, each memory type selected from a list including at least (i) a NAND flash memory type; or (ii) a NOR flash memory type.

[0008] In one embodiment, the primary memory die and the secondary memory die support corresponding first and second distinct access protocols, and the primary memory die is configured to present the second access protocol to a host coupled to the bus to the secondary memory die. In another embodiment, the primary memory die is configured, in response to receiving a die selection command that specifies a memory die selected between the primary memory die and the secondary memory die, to cause the selected memory die to execute one or more commands received after the die selection command. In yet another embodiment, the primary memory die and the secondary memory die are mapped to different corresponding address sub-ranges of a common address space, and the primary memory die is configured to identify an address parameter in the received command and execute the received command through either the primary memory die or the secondary memory die depending on which address range the address parameter belongs to.

[0009] In some embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the second CS signal to block access to the secondary memory die for all received commands. In other embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the second CS signal to allow access to the secondary memory die for a partial subset of the commands supported by the secondary memory die. In yet another embodiment, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the second CS signal to allow full access to the secondary memory die for all commands supported by the secondary memory die while selectively executing commands that modify the access mode.

[0010] In one embodiment, the primary memory die is configured to locally store boot code for hosts coupled to the bus and manage secure access to the stored boot code. In another embodiment, the primary memory die is arranged to act as a Root of Trust (RoT) for an underlying system including the IC to secure store operations to the secondary memory die.

[0011] According to the embodiments described herein, there is further provided a method of data storage, in an integrated circuit (IC), the integrated circuit including a primary memory die coupled to a bus providing a primary chip select (CS) signal via a primary CS line connecting to the primary memory die, and a secondary memory die coupled to the bus not including the primary CS line and coupled to a secondary CS line carrying a secondary CS signal provided by the primary memory die, the primary memory die receiving a command via the bus when the primary CS signal is active, in response to identifying that the command is addressed to the primary memory die, executing the command in the primary memory die, and in response to identifying that the command is addressed to the secondary memory die, causing the secondary memory die to execute the command by transmitting the primary CS signal as a secondary CS signal on the secondary CS line. Effect of the Invention

[0012] Embodiments of the present invention can improve management of secure access to multiple memory dies stacked in a common package. [Brief description of the drawings]

[0013] [Figure 1] 1 illustrates a block diagram of a computer system including multiple memory dies stacked within a common package according to embodiments described herein. [Diagram 2]2 illustrates a flow diagram of a method for executing commands in a multi-die memory device according to embodiments described herein. [Diagram 3] 4 illustrates a timing diagram of signals generated during execution of a read command in a multi-die memory device according to embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Embodiments herein provide methods and systems for improved management of secure access to multiple memory dies stacked in a common package. In the disclosed embodiments, one memory die controls access to the other memory dies by controlling its corresponding chip select (CS) input. The disclosed embodiments can be applied to different types of memory dies having different corresponding command sets and / or supporting different access protocols.

[0015] In various systems, a host is coupled to a storage device that includes multiple memory dies via a bus, which typically includes one or more Input / Output (IO) lines that carry opcodes, addresses, and data, and a CS signal that is active during a command.

[0016] Each memory die has a CS input that, when active, selects which memory die to use to execute a command. A memory die can complete execution of a supported command if its CS input is active throughout the command, and typically abandons execution of a command if its CS input becomes inactive before execution is complete. A memory die typically ignores unsupported commands, even if its CS input is active throughout the command.

[0017] Various structures can be used to access the individual memory dies in a package. For example, the entire bus signal, including the bus CS signal, can be coupled in parallel to all memory dies. This type of technology is offered by Winbond Electronics Corp under the name SpiStack® and is implemented in their W25M product series. When sending a command over the bus, all memory dies receive the command together first, and each memory die independently decides whether to execute the command or to abandon the command. This parallel bus approach is not suitable for mixing different types of memory dies in a package, since the memory dies usually need to be of the same memory type and share a common rule for deciding to execute or abandon a command.

[0018] In another approach, the host bus can be coupled to an intermediary controller that terminates the host bus and generates separate bus signals, including corresponding CS signals, to the different memory dies. The host can only communicate with each memory die indirectly through the controller. This approach is typically highly complex and expensive, as the controller handles multiple full buses per memory die.

[0019] In the disclosed embodiment, the bus is coupled in parallel to the multiple memory dies, except for a CS signal that is connected to only one of the memory dies (referred to herein as the “primary memory die”). The primary memory die controls access to the other memory dies (also referred to herein as the “secondary die”) by providing a separate CS signal to each secondary die.

[0020] Consider an integrated circuit (IC) that includes a primary memory die and one or more secondary memory dies. The primary memory die is coupled to a bus that provides a primary chip select (CS) signal via a primary CS line that connects only to the primary memory die. The secondary memory die is coupled to the bus that does not include a primary CS line and is coupled to a corresponding secondary CS line that carries a corresponding secondary CS signal provided by the primary memory die. When the primary CS signal is active, the primary memory die receives a command via the bus and, in response to identifying the command as being addressed to the primary memory die, executes the command within the primary memory die. Otherwise, in response to identifying the command as being addressed to the secondary memory die, the primary memory die causes a given secondary memory die to execute the command by transmitting the primary CS signal as a secondary CS signal on the secondary CS line of the given secondary memory die.

[0021] In the following description, for clarity, some of the described embodiments refer to a package that includes a primary memory die and a single secondary die, however, the disclosed techniques are equally applicable to packages that include multiple secondary memory dies.

[0022] In some embodiments, the primary memory die includes a local memory selectable by a local “enable signal” transmitted on a local “enable line,” and the primary memory die executes a command by (i) transmitting a primary CS signal on the local enable line as a local enable signal; and (ii) deactivating a secondary CS signal provided to the secondary memory die.

[0023] In other embodiments, the IC includes another secondary die coupled to a bus that does not include a primary CS line and coupled to another secondary CS line carrying another secondary CS signal provided by the primary memory die. In these embodiments, the primary die causes the other secondary die to execute a command via the operations of (i) transmitting the primary CS signal as another secondary CS signal on another secondary CS line, (ii) deactivating the secondary CS signal provided to the secondary die, and (iii) deactivating a local enable signal of the local memory provided to the primary die.

[0024] In the disclosed structures, at least a portion of the primary memory die and the secondary memory die may be of different corresponding memory types, each memory type selected from a list including at least: (i) a NAND flash memory type; and (ii) a NOR flash memory type.

[0025] In one embodiment, the primary memory die and the secondary memory die support corresponding first and second distinct access protocols, and the primary memory die presents the second access protocol to the secondary memory die to a host coupled to the bus.

[0026] The primary memory die may select a target memory die for executing the received command (or one or more subsequent commands) using any suitable method (e.g., based on a dedicated die selection command or based on address information included in the command).

[0027] In some embodiments, the primary die can operate in one of three access modes: a “Standalone” mode, a “Restricted-Access” mode, and a “Full-Access” mode. In the Standalone mode, the primary memory die controls the second CS signal to block access to the secondary memory die for all received commands. In the Restricted-Access mode, the primary memory die controls the second CS signal to allow access to the secondary memory die for a partial subset of corresponding commands supported by the secondary memory die. In the Full-Access mode, the primary memory die controls the second CS signal to allow full access to the secondary memory die for all commands supported by the secondary memory die while selectively executing commands (by the primary memory die) to modify the access mode.

[0028] The disclosed structures can be used, for example, for secure boot. In such an exemplary embodiment, the primary memory die locally stores boot code for hosts coupled to the bus and manages secure access to the stored boot code, such as when storing, updating, uploading, etc.

[0029] In one embodiment, the primary memory die acts as a root of trust (RoT) for the underlying system including the IC to secure storage operations to the secondary memory die. For example, the primary memory die can provide various cryptographic services, such as write protection, encryption, and data authentication, to the secondary memory die.

[0030] In the disclosed technology, a primary memory die controls access to a secondary memory die by controlling the corresponding CS input. The disclosed structure and related embodiments provide reduced complexity, reduced power consumption, and faster access to the secondary memory die. They also support memory dies of various storage technologies, such as mixing Flash NOR and Flash NAND dies in the same package. Because the primary die manages the selection of each command die, the memory dies do not need to follow common rules and / or otherwise cooperate with each other to select a target die, resulting in simplified and flexible implementation.

[0031] 1, a computer system 20 includes a host 24 coupled to an integrated circuit (IC) 28, which in this embodiment implements a storage device, via a bus 32 (also referred to as a link or interface). The bus 32 includes a number (e.g., 'n') of input / output (IO) lines, a clock line designated "CLK", and a chip select (CS) line designated "CS-0". The bus 32 may include, for example, a Serial Peripheral Interface (SPI). Alternatively, any other suitable type of bus may be used, such as, for example, an extended SPI, an extended SPI (xSPI), or an Inter-Integrated Circuit (I2C) bus.

[0032] In computer system 20, host 24 typically sends commands via bus 32 and storage device 28. Communications may include sending opcodes, sending addresses, sending data, and / or receiving data.

[0033] The computer system 20 may be used in a variety of applications, such as Internet of Things (IoT) devices, automotive applications, PC / server Basic Input-Output Systems (BIOS), and industrial controllers.

[0034] Storage device 28 includes a memory die 40, designated “die-0”, which includes local memory 42 and CS logic 46. Memory die 40 is referred to herein as a “primary memory die”, or simply “primary die”. Storage device 28 further includes one or more memory die 50, each of which includes memory 54. Memory die 50 is designated “die-m”, where 'm' represents an integer greater than 0. Memory die 50 is referred to herein as a “secondary memory die”, or simply “secondary die”.

[0035] Both the primary die and each secondary die have a CS input that, when active, selects the corresponding memory die. Note that selecting a memory die means gaining access to the internal memory of the memory die. In FIG. 1, memory device 28 includes two secondary dies, designated Die-1 and Die-2, although in alternative embodiments, memory device 28 may include a single secondary die or more than one secondary die.

[0036] In the structure of FIG. 1, the CLK and IO lines of bus 32 are connected in parallel between host 24 and each of the primary and secondary dies. In comparison, the CS-0 line of bus 32 (also referred to herein as the “primary CS line”) is connected between the host and the CS input of the primary die, but not to the CS input of the secondary die. The memory select lines (also referred to herein as the “enable lines”) are connected between the CS logic and the local memories 42. The CS lines, designated “CS-1” and “CS-2” (also referred to herein as the “secondary CS lines”), are connected between the CS logic and the CS input of the corresponding secondary die. The above structure allows the CS logic 46 to control access to its local memory (42) as well as the secondary die (50) and its memory (54).

[0037] In the following description, the CS signal transmitted on the primary CS line is also referred to herein as the “primary CS signal,” the CS signal transmitted on the secondary CS line is also referred to herein as the “secondary CS signal,” and the memory select signal transmitted on the enable line is also referred to herein as the “enable signal.” In the following description, the CS logic controls the enable signal for accessing the local memory 42 of the primary die and controls the secondary CS signal for accessing the secondary die.

[0038] The local memory 42 of the primary die 40 and the memory 54 of the secondary die 50 may include any suitable type of memory. In one embodiment, the local memory 42 of die-0 includes a NOR flash device and the memory 54 of die-1 and die-2 include a NAND flash device. However, in other embodiments, any other suitable combination of memory types may be used. For example, the local memory 42 of the primary die and the memories 54 of all the secondary dies may be the same memory type. As another example, the memories 54 of two (or more) of the secondary dies may be different corresponding memory types. In the description of the present invention, the primary memory types used are NOR and NAND dies, but this is not required and other suitable memory types (volatile or non-volatile) may be used.

[0039] When the host 24 sends a command over the bus, the primary die controls the enable and secondary signals while the primary CS signal (transmitted on the CS-0 line) is active so that the command is initially received by the primary die and all secondary die. As the command progresses (e.g., after receiving the opcode parameters), the CS logic determines the target die to which the command is sent and controls the enable and secondary CS signals so that the command is executed by the target die and discarded by all other memory die.

[0040] A method for determining the target die will be described in detail below.

[0041] Executing commands in a multi-die storage device - Patents.com

[0042] With reference to Figure 2, the method is described as being performed by the primary die (die-0) of memory device 28 of Figure 1. For example, the method of Figure 2 may be applied when all memory dies of a memory device all support the same command set and command format.

[0043] The method begins with a receive command step 100, where die-0 receives a command from host 24 over bus 32. The command is transmitted on the bus IO lines using the bus CLK signal, and it is assumed that the primary CS signal transmitted on the primary CS line (CS-0) is active during the command.

[0044] In response to the primary CS signal, the CS logic 46 of die-0 first selects the local memory 42 and all the secondary dies 50 (die-1 and die-2 in this embodiment). To this end, the CS logic transmits the primary CS signal as a valid signal on the internal enable line and transmits the primary CS signal as a secondary CS signal on the secondary CS lines of the secondary dies. Thus, the local memory 42 of die-0 and the memory 54 of the secondary dies receive at least the opcode parameters of the command. Thus, each of the primary and secondary dies is ready to execute the command if selected as the target die.

[0045] In die selection step 104, the CS logic of die-0 determines the target die to which the command is sent. Die-0 may determine the target die based on information conveyed in the opcode parameter and / or address parameter (if available) in the current or previous command, for example.

[0046] If die-0 is selected as the target die in step 104, the method proceeds to a primary die execution step 108. Further, if die-1 or die-2 is selected as the target die, the method proceeds to a secondary die execution step 112.

[0047] In step 108, die-0 executes the command via its CS logic by (i) sending the (active) primary CS signal as a valid signal on the local enable line of local memory 42; and (ii) deactivating the secondary CS signals of all secondary dies (in this embodiment, die-1 and die-2). Because the selection of the selected secondary die is deselected, the secondary dies abandon the execution of the command.

[0048] In step 112, die-0 causes the target die (in this embodiment, die-1 or die-2) to execute the command via the CS logic by (i) sending the primary CS signal as a secondary CS signal on the secondary CS line of the target die; (ii) deactivating the secondary CS signals of the other secondary dies; and (iii) deactivating the local enable signal of die-0.

[0049] Deactivation of the enable signal or secondary CS signal may be accomplished in any suitable manner, such as using a logical OR gate when the signal is active low, or a logical AND gate when the signal is active high, etc. After steps 108 and 112, the method loops back to step 100 to receive a subsequent command.

[0050] 2 is shown as an example, and other suitable methods may be used. For example, if the command includes only an opcode command (e.g., a configuration command), the primary die can control the enable signal and the secondary CS signal to cause multiple memory dies to execute the command in parallel with each other.

[0051] Referring to FIG. 3, the timing diagram describes a system (eg, system 20) in which a host 24 executes a read command, for example, using the method of FIG.

[0052] In one embodiment, bus 32 includes an SPI having an IO0 line for sending commands to memory device 28 and an IO1 line for receiving data from the memory device. As shown, the command has an 8-bit opcode parameter 150 transmitted starting with the Most Significant bit (MSb) and ending with the Least Significant bit (LSb). The opcode parameter is followed by a 32-bit address parameter 154 transmitted starting with the Most Significant address bit (A31) and ending with the Least Significant address bit (A0). In response to a read command, the memory device transmits byte-0 ... byte-m of the data read from the target die back to the host over the IO1 line.

[0053] The primary CS signal 158, transmitted from the host over the primary CS line (CS-0) of the bus, becomes active during the command. In the embodiment of Figure 3, the primary CS signal becomes active (e.g., goes from high to low in this embodiment) just before the start of the MSb of the opcode and remains active until the memory device has completed transmitting the mth data byte over the IO1 line.

[0054] 3, assume that die-0 determines the target die at time instance 162 based on some upper address bits of the address parameter. The timing diagram shows the enable and secondary CS signals when (i) the target die is primary die-0 (170) and (ii) the target die is secondary die-2 (174).

[0055] When the primary CS 158 signal goes active, the CS logic first sends the primary CS signal as a valid signal on the enable line of die-0, and then sends it as a secondary signal on the secondary CS lines of both die-1 and die-2, allowing all memory dies to receive at least a portion of the opcode and address parameters.

[0056] If die-0 is the target die, the CS logic continues to transmit the primary CS signal as an enable signal on the enable line. Also, die-1 and die-2 abandon the command by deactivating the secondary CS signal of the secondary die by the CS logic. If die-2 (for example) is the target die, die-2 executes the command by transmitting the primary CS signal as a secondary signal on the secondary CS line of die-2. Also, the CS logic causes die-1 and die-0 to abandon the command by deactivating the secondary CS signal of die-1 and the enable signal of die-0, respectively.

[0057] The timing diagram shown in FIG. 3 and described above is cited as an example. Alternate embodiments may use other suitable timing diagrams. For example, in some embodiments, the bus width operating mode may be quad or octal, and additional IO lines may be added accordingly, sending multiple bits of the command per clock cycle. Although FIG. 3 shows a 32-bit address parameter, other address lengths may be used, such as a 24-bit address. As another example, although the timing diagram in FIG. 3 illustrates a low active CS signal, alternate embodiments may use a high active CS signal.

[0058] After receiving a command from memory device 28, the primary die determines (e.g., using CS logic 46) which memory die in the memory device will execute the command. The memory die selected to execute a given command is referred to herein as the “target die” for the given command. The target die may be the primary die or one of the secondary die. In general, a command sequence may include commands sent to the same memory die or to two or more different memory dies. In the disclosed embodiment, the primary die 40 (die-0) handles the selection of a single target die for each command.

[0059] The primary die may determine the target die for a given command in a variety of ways, as described below. In one embodiment, each memory die is pre-assigned a corresponding die identifier, and the primary die selects the target die in response to a dedicated die selection command that specifies the identifier of the target die. The dedicated command may specify the die identifier, for example, in the opcode parameter or in a separate parameter following the opcode parameter. The die selection command is processed by the primary die but is ignored by the secondary die because it is not part of the command set supported by the secondary die.

[0060] In one embodiment, in response to the die selection command, the primary die controls the enable signal and the secondary CS signal so that subsequent commands are executed by the target die (and typically not by any other die). The primary die continues to monitor subsequent received commands, even if the target die is a secondary die, and reselects the target die accordingly upon receiving another die selection command.

[0061] Some commands, such as read, program, and erase commands, include an address parameter. For such commands, the primary die can determine the target die based on the address parameter. In this method, the primary die and the secondary die are mapped to a common address space that is divided into multiple address sub-ranges. Here, each memory die is mapped to a corresponding address sub-range of the address space. In some embodiments, after receiving a command with an address parameter, the primary die determines the target die based on at least a portion of the address parameter (e.g., the Most Significant (MS) byte of the address) by identifying the address sub-range to which the address parameter belongs. The address-based target die selection described above can be applied to, but is not limited to, storage devices in which all memory dies share a common command set and command format.

[0062] As discussed above in FIG. 1, a storage device may include memory dies of various memory types that follow different command sets, different command formats, and / or different access protocols, such as when mixing NOR and NAND flash memory devices in the same storage device. In such an embodiment, a host accessing a target die must use a command from the command set supported by the corresponding target die. Alternatively or additionally, a primary die may present to the host an access protocol that is used by a secondary die having a different memory type than the primary die. This allows the host to communicate with all memory dies using a common access protocol.

[0063] For example, consider a read operation in a memory device 28 in which the primary die is a NOR flash device and the secondary die is a NAND flash device. A read (or write) command for a NOR flash device typically carries a full address parameter for direct access (e.g., a 24-bit or 32-bit memory address). In contrast, a read operation applied to a NAND flash device is typically indirect and includes a "page load" command followed by one or more "page read" commands. In the target NAND device, a page load command loads a page from memory into a local read buffer (not shown) of the target NAND device. A page may contain several thousand bytes of data (e.g., 4 thousand bytes or other suitable size). A page read command reads data from the read buffer that was loaded by a previous page load command. A page load command typically carries only the most significant 16 bits of the address parameter (e.g., A31...A16), and a page read command typically carries only the least significant 16 bits of the address parameter (e.g., A15...A0). In this embodiment, the primary die selects a given target die if the portion of the address transmitted in the page load command is within the sub-range assigned to the given target die.

[0064] The page load command is normally executed by all the secondary NAND dies. After determining the NAND target die, the primary die controls the enable signal and the secondary CS signal so that the subsequent page read command is executed only by the target NAND die and is discarded by the primary die and other secondary dies. The primary die also monitors subsequent commands received via the bus, and after detecting the subsequent page load command, reselects the target die based on the address parameters transmitted in the above-mentioned subsequent page load command.

[0065] Various address mappings can be used when the corresponding storage sizes of two or more memory dies are different. For example, consider a storage device that includes a 128 megabit primary NOR die and one or more 1 gigabit secondary NAND dies. This structure is suitable, for example, for storing a relatively small boot code in the NOR device and using the secondary NAND dies to expand the overall storage space.

[0066] In one such embodiment, the primary die may be mapped to an address sub-range beyond that assigned to the secondary NAND die, for example, for a single 1 Gigabit secondary NAND die, the NAND die may be mapped to address sub-range 0000_0000h-07FF_FFFFh, and the 128 Mbit primary NAND die may be mapped to address range 0800_0000h-08FF_FFFFh.

[0067] In another embodiment, the address sub-ranges assigned to the primary NOR die and the secondary NAND die overlap (for example, a 128 Mbit primary NOR die is mapped to an address sub-range specified by 0000_0000h-00FF_FFFFh, and a single 1 Gbit secondary NAND die is mapped to an address sub-range specified by 0100_0000h-07FF_FFFFh), in which case the lower 128 Mbit addresses of the secondary die are inaccessible.

[0068] In some embodiments, the primary die NOR presents the access protocol of the secondary die NAND to the host. To this end, the primary die NOR implements the page load and page read commands of the NAND die, allowing the host of the controller with NAND flash to access the primary die NOR and the secondary die NAND using the same command set and format (at least for read operations). In these embodiments, the local memory of the primary die NOR appears to the host as a NAND device, so that software executed by the host can access the memory in the storage device as it would access a monolithic (single die) NAND flash memory device. In some embodiments, before accessing either the primary die or the secondary NAND die in NAND format, the host must load an appropriate driver designed to access NAND memory, for example, from the storage device.

[0069] Some commands may be too short to allow the primary die enough time to determine the target die based on the address parameters. For example, a block erase command for a NAND device issued in xSPI Octal Dual Transfer Rate (DTR) bus mode (also referred to as "8d-8d-8d" mode, meaning that the command, address, and data are transmitted as an 8-bit wide DTR) requires one clock cycle for the opcode, followed by an additional clock cycle for the address. In this case, the secondary die may undesirably execute an erase command (in response to the opcode and address parameters) before the primary die has determined the target die based on the address parameters. In some embodiments, to avoid such erroneous command execution, the primary die limits the use of the address-based target selection method to selected commands (e.g., only read operations) and blocks commands that may cause erroneous execution (such as erase and programming operations).

[0070] Note that unlike the erase and program commands, for a read command, the die continues to process the command after receiving its address, prepares its response, and starts sending the response to the host, allowing enough time for any dice other than the target die to complete the command.

[0071] In some embodiments, commands that modify the contents stored in the memory device (such as programming and erase commands) are preceded by a Write-Enable command. The primary die monitors the commands received over the bus, and upon detection of a Write-Enable command (or other condition) when the target die is one of the secondary dies, the primary die blocks further access to the secondary die, for example, until the next system reset, or depending on a predefined condition implemented within the primary die. Thus, the primary die blocks any command sequence that starts with a Write-Enable command followed by a programming or erase command. This means that the secondary die is inherently write-protected. Thus, the primary die manages the write-protection of the secondary die, even if the secondary die itself does not support an inherent write-protection mechanism.

[0072] In some embodiments, the primary die supports security features that are used to provide write protection (and other security features) to the secondary die even if the secondary die does not support its own security features. For example, the primary die can execute security commands protected by, for example, a signature, password, and / or other user authentication mechanism to gain access to the secondary die.

[0073] In some embodiments, the primary die supports an access mode selected from a number of predefined modes. In an exemplary embodiment, the primary die supports three access modes, including: (i) a “standalone mode,” (ii) a “limited access” mode, and (iii) a “full access” mode. In one embodiment, the primary die 40 switches between access modes under the control of the host 24.

[0074] In standalone mode, the primary die only allows access to local memory and blocks access to the secondary die. This mode is useful, for example, in systems where the host boots from the primary die (e.g., a NOR flash device). In standalone mode, the primary die selects itself as the target die for all incoming commands. Thus, the target die does not need to be determined on the fly.

[0075] After the boot process is complete, the primary die may be switched to a restricted access mode in which the primary die (e.g., NOR) allows access (e.g., read access) to the secondary die (e.g., NAND) for some commands that include an address parameter. In the restricted access mode, the primary die can present the access protocol of the secondary die to the host, as described above.

[0076] In full access mode, the primary die allows access to the secondary die for all supported commands. This mode can be used to program, erase, and / or configure the secondary die. In full access mode, the primary die monitors received commands and responds only to store commands that modify the access mode to limited access mode or standalone mode.

[0077] In some embodiments, the standalone mode serves as the default access mode after a reset. In such an embodiment, in response to a reset event, the primary die automatically begins operating in the standalone mode, allowing the host to boot from the primary die (e.g., NOR). At a later appropriate time, e.g., after booting is complete, the host loads firmware (FW) code from the storage device, including a driver for accessing the NAND die, and switches to the limited access or full access mode. In other embodiments, the limited access or full access mode may serve as the default mode after a reset. In this case, after a reset, the primary die begins operating in the limited access or full access mode. For example, this embodiment is useful if the host boots from the secondary die rather than from the primary die.

[0078] In an exemplary embodiment, the primary die includes a security device stacked in the same package as one or more secondary dies. In such an embodiment, the primary die acts as a root of trust (RoT) for the system. The storage device can rely on the security features of the primary die to store, protect, and update the boot code stored in the primary die.

[0079] The above embodiments are provided by way of example, and other suitable embodiments may be used. For example, while some embodiments above refer to memory devices including a NOR primary die and one or more NAND secondary dies, this structure is not required, and other embodiments may use other suitable combinations of NOR, NAND, and / or other memory types.

[0080] The configuration of computer system 20 (including host 24, storage device 28 and its components such as primary die 40, local memory 42, CS logic 46, and secondary die 50 and its memory 54) is an example configuration shown solely for conceptual clarity. In alternative embodiments, any other suitable computer, host, and memory die configurations may be used.

[0081] The different sub-units of memory device 28 may be implemented using suitable hardware, such as one or more Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs), or using software, or using a combination of hardware and software elements.

[0082] Storage device 28 may include one or more general-purpose processors programmed with software to perform the functions described herein. The software may be in electronic form, for example downloaded to the processor via a network or host, or alternatively or additionally may be provided and / or stored on non-transitory tangible media such as (e.g., magnetic, optical, or electronic memory). [Industrial Applicability]

[0083] The method and system for secure storage in a multi-die package of the present invention can be applied to memory devices. [Explanation of symbols]

[0084] 20: Computer Systems 24: Host 28: Integrated circuits / memory devices 32: Bus 40: Primary memory die 42: Local memory 46:CS logic 50: Secondary memory die 54: Memory 100, 104, 108, 112: Step 150: Opcode parameters 154: Address parameters 158: Primary CS signal 162: Time instance A0: lowest address bit A31: Highest address bit LSb: least significant bit MSb: Most significant bit

Claims

1. a primary memory die coupled to a bus providing a primary chip select signal via a primary chip select line connecting to the primary memory die; a secondary memory die coupled to the bus that does not include the primary chip select lines and coupled to secondary chip select lines that carry secondary chip select signals provided by the primary memory die; Including, The primary memory die includes: receiving a command over the bus when the primary chip select signal is active; responsive to identifying the command as being directed to the primary memory die, executing the command within the primary memory die; in response to identifying the command as being directed to the secondary memory die, transmitting the primary chip select signal as the secondary chip select signal on the secondary chip select line, thereby causing the secondary memory die to execute the command. The following are arranged in such a way that Integrated circuits.

2. the primary memory die includes a local memory selectable by a local enable signal carried on a local enable line, the primary memory die being configured to: (i) transmit the primary chip select signal on the local enable line as the local enable signal; and (ii) execute the command via an operation of deactivating the secondary chip select signal provided to the secondary memory die.

10. The integrated circuit of claim 1.

3. the integrated circuit includes another secondary die coupled to the bus not including the primary chip select line and coupled to another secondary chip select line carrying another secondary chip select signal provided by the primary memory die, the primary die being configured to: (i) transmit the primary chip select signal as the other secondary chip select signal on the other secondary chip select line; (ii) deactivate the secondary chip select signal provided to the secondary die; and (iii) cause the other secondary die to execute the command via the operations of deactivating the local enable signal of the local memory provided to the primary die.

3. The integrated circuit of claim 2.

4. The primary memory die and the secondary memory die have corresponding first and second different memory types, each memory type selected from a list including at least: i. a NAND flash memory type; and ii. a NOR flash memory type.

10. The integrated circuit of claim 1.

5. the primary memory die and the secondary memory die support corresponding first and second distinct access protocols, and the primary memory die is configured to present the second access protocol to the secondary memory die to a host coupled to the bus.

10. The integrated circuit of claim 1.

6. the primary memory die is configured to, in response to receiving a die selection command specifying a memory die selected between the primary memory die and the secondary memory die, cause the selected memory die to execute one or more commands received after the die selection command.

10. The integrated circuit of claim 1.

7. the primary memory die and the secondary memory die are mapped to different corresponding address sub-ranges of a common address space, and the primary memory die is configured to identify an address parameter in the received command and execute the received command through the primary memory die or the secondary memory die depending on which address range the address parameter belongs to.

10. The integrated circuit of claim 1.

8. the primary memory die is configured to operate according to an access mode in which the primary memory die controls a second chip select signal to block all received commands from accessing the secondary memory die; 10. The integrated circuit of claim 1.

9. the primary memory die is configured to operate according to an access mode in which the primary memory die controls second chip select signals to permit access to the secondary memory die for a partial subset of the commands supported by the secondary memory die.

10. The integrated circuit of claim 1.

10. the primary memory die is configured to control second chip select signals to selectively execute commands that modify the access mode while simultaneously operating according to an access mode that allows full access to the secondary memory die for all commands supported by the secondary memory die; 10. The integrated circuit of claim 1.

11. the primary memory die locally stores boot code for a host coupled to the bus and manages secure access to the stored boot code; 10. The integrated circuit of claim 1.

12. the primary memory die is arranged to act as a root of trust for an underlying system including the integrated circuit to secure store operations to the secondary memory die; 10. The integrated circuit of claim 1.

13. an integrated circuit including: a primary memory die coupled to a bus providing a primary chip select signal via a primary chip select line connecting to the primary memory die; and a secondary memory die coupled to the bus not including the primary chip select line and coupled to a secondary chip select line carrying a secondary chip select signal provided by the primary memory die; when the primary chip select signal is active, the primary memory die receives commands over the bus; responsive to identifying the command as being directed to the primary memory die, executing the command within the primary memory die; in response to identifying the command as being directed to the secondary memory die, transmitting the primary chip select signal as the secondary chip select signal on the secondary chip select line, thereby causing the secondary memory die to execute the command. Data storage method.

14. the primary memory die includes a local memory selectable by a local enable signal carried on a local enable line, and executing the command in the primary memory die includes: i. transmitting the primary chip select signal as the local enable signal on the local enable line; and ii. executing the command via deactivating the secondary chip select signal provided to the secondary memory die.

14. The method of storing data according to claim 13.

15. The integrated circuit includes another secondary die coupled to the bus not including the primary chip select line and coupled to another secondary chip select line carrying another secondary chip select signal provided by the primary memory die, the method including: i. transmitting the primary chip select signal on the other secondary chip select line as the other secondary chip select signal; ii. deactivating the secondary chip select signal provided to the secondary die; and iii. causing the other secondary die to execute the command via the operation of deactivating the local enable signal of the local memory provided to the primary die.

15. The method of storing data according to claim 14.

16. The primary memory die and the secondary memory die have corresponding first and second different memory types, each memory type selected from a list including at least: i. a NAND flash memory type; and ii. a NOR flash memory type.

14. The method of storing data according to claim 13.

17. the primary memory die and the secondary memory die support corresponding first and second distinct access protocols, the method including presenting, via the primary die, a second access protocol to the secondary memory die to a host coupled to the bus; 14. The method of storing data according to claim 13.

18. in response to receiving a die selection command specifying a selected memory die between the primary memory die and the secondary memory die, causing the selected memory die to execute one or more commands received following the die selection command.

14. The method of storing data according to claim 13.

19. the primary memory die and the secondary memory die are mapped to different corresponding address sub-ranges of a common address space, the method including identifying an address parameter in the received command and executing the received command through the primary memory die or the secondary memory die depending on which address range the address parameter belongs to.

14. The method of storing data according to claim 13.

20. and operating responsive to an access mode, wherein in the access mode, the primary memory die controls a second chip select signal to block access to the secondary memory die for all received commands.

14. The method of storing data according to claim 13.

21. and further comprising operating responsive to an access mode, wherein in the access mode, the primary memory die controls a second chip select signal to allow access to the secondary memory die for a partial subset of the commands supported by the secondary memory die.

14. The method of storing data according to claim 13.

22. and further comprising operating in response to an access mode, wherein in the access mode, the primary memory die controls a second chip select signal to allow full access to the secondary memory die for all commands supported by the secondary memory die, while selectively executing commands that modify the access mode.

14. The method of storing data according to claim 13.

23. locally storing boot code for a host coupled to the bus and managing secure access to the stored boot code.

14. The method of storing data according to claim 13.

24. and acting as a root of trust for an underlying system including the integrated circuit to secure store operations to the secondary memory die.

14. The method of storing data according to claim 13.

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