Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the warpage of a substrate.SOLUTION: A semiconductor device according to an embodiment comprises a substrate including a first and a second principal surface and first to third non-volatile semiconductor memories mounted on the first principal surface. The substrate comprises a first wiring layer provided on the first principal surface, a second wiring layer provided on the second principal surface as a mesh-like wiring layer, a plurality of wiring layers formed as an inner layer, and a plurality of insulation layers provided between the wiring layers. Third and fourth wiring layers of the inner layer are plane layers. The third wiring layer is formed closer to the first principal surface side than a central line of a layer structure of the substrate. The fourth wiring layer is formed closer to the second principal surface side than the central line of the layer structure of the substrate. In the fourth wiring layer, a first slit is formed in a part of a portion facing the gap between the first and second non-volatile semiconductor memories, and a second slit is formed in a part of a portion facing the gap between the second and third non-volatile semiconductor memories.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, a semiconductor device has been used in which a nonvolatile semiconductor memory element such as a NAND flash memory is mounted on a substrate on which a connector is formed. In addition to the nonvolatile semiconductor memory element, the semiconductor device also has a volatile semiconductor memory element and a controller that controls the nonvolatile semiconductor memory element and the volatile semiconductor memory element.

[0003] In such semiconductor devices, the shape and size of the substrate may be restricted according to the environment and standards in which the semiconductor device is used, and for example, a substrate having a rectangular shape in a plan view may be used. In addition, due to the recent demand for miniaturization of semiconductor devices, the substrate tends to be thinner. When using such a thin rectangular substrate, it is required to suppress warping of the substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2010-79445 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing warpage of a substrate. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a substrate, first to third nonvolatile semiconductor memories, a first adhesive portion, and a second adhesive portion. The substrate has a first main surface and a second main surface facing the opposite side to the first main surface. The first to third nonvolatile semiconductor memories are mounted on the first main surface of the substrate. The first adhesive portion fills a gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory while exposing the surfaces of the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory. The second adhesive portion fills a gap between the second nonvolatile semiconductor memory and the third nonvolatile semiconductor memory while exposing the surfaces of the second nonvolatile semiconductor memory and the third nonvolatile semiconductor memory. The substrate includes a first wiring layer provided on the first main surface, a second wiring layer as a mesh wiring layer provided on the second main surface, a plurality of wiring layers formed as inner layers, and a plurality of insulating layers provided between the wiring layers. Among the multiple wiring layers formed as the inner layers, the third and fourth wiring layers are plane layers. The third wiring layer is formed on the first main surface side of the center line of the layer structure of the substrate, and faces the first wiring layer across an insulating layer. The fourth wiring layer is formed on the second main surface side of the center line of the layer structure of the substrate. The fourth wiring layer faces the second wiring layer across an insulating layer. In the fourth wiring layer, a first slit is formed in a part of a portion facing the gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory, and a second slit is formed in a part of a portion facing the gap between the second nonvolatile semiconductor memory and the third nonvolatile semiconductor memory. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view showing a schematic configuration of the semiconductor device. [Diagram 3] FIG. 3 is a side view of the semiconductor device. [Figure 4]FIG. 4 is a diagram showing the layer structure of the substrate. [Diagram 5] FIG. 5 is a diagram showing the wiring density of each layer of the substrate. [Figure 6] FIG. 6 is a diagram showing a wiring pattern formed on the back surface layer (eighth layer) of the substrate. [Figure 7] FIG. 7 is a diagram showing the wiring density of each layer of a substrate as a comparative example. [Figure 8] FIG. 8 is a diagram for explaining the line width and spacing of the wiring pattern formed on the back surface layer (eighth layer) of the substrate. [Figure 9] FIG. 9 is a diagram showing an adhesive portion filled in the gap of a NAND memory. [Figure 10] FIG. 10 is a diagram showing a slit formed in the seventh layer of the substrate. [Figure 11] FIG. 11 is a diagram showing a layer configuration of a substrate included in the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is an external perspective view of a holding member used in the semiconductor device transport method according to the third embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a state in which the holding member shown in FIG. 12 is stored in a box. [Figure 14] FIG. 14 is a front view of a holding member according to a modified example of the third embodiment. [Figure 15] FIG. 15 is a diagram showing a state in which the movable portion of the holding member shown in FIG. 14 is opened. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0009] (First embodiment) 1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment. The semiconductor device 100 is connected to a host device (hereinafter abbreviated as host) 1 such as a personal computer or a CPU core via a memory connection interface such as a SATA interface (ATA I / F) 2, and functions as an external memory for the host 1. Examples of the host 1 include the CPU of a personal computer, and the CPU of an imaging device such as a still camera or a video camera. The semiconductor device 100 can also transmit and receive data to and from a debugging device 200 via a communication interface 3 such as an RS232C interface (RS232C I / F).

[0010] The semiconductor device 100 includes a NAND flash memory (hereinafter, abbreviated as NAND memory) 10 as a non-volatile semiconductor memory element, a drive control circuit 4 as a controller, a DRAM 20 as a volatile semiconductor memory element capable of faster storage operation than the NAND memory 10, a power supply circuit 5, an LED 6 for displaying a status, and a temperature sensor 7 for detecting the temperature inside the drive. The temperature sensor 7 measures the temperature of the NAND memory 10 directly or indirectly, for example. When the measurement result by the temperature sensor 7 reaches or exceeds a certain temperature, the drive control circuit 4 restricts writing of information to the NAND memory 10, thereby suppressing a further increase in temperature.

[0011] The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from a power supply circuit on the host 1 side, and supplies these internal DC power supply voltages to each circuit in the semiconductor device 100. In addition, the power supply circuit 5 detects the rising edge of the external power supply, generates a power-on reset signal, and supplies it to the drive control circuit 4.

[0012] FIG. 2 is a plan view showing a schematic configuration of the semiconductor device 100. FIG. 3 is a side view of the semiconductor device 100. The power supply circuit 5, the DRAM 20, the drive control circuit 4, and the NAND memory 10 are mounted on a substrate 8 on which a wiring pattern is formed. The substrate 8 has a substantially rectangular shape in a plan view. On one short side of the substantially rectangular substrate 8, a connector 9 is provided which is connected to the host 1 and functions as the SATA interface 2 and the communication interface 3 described above. The connector 9 functions as a power input unit which supplies the power input from the host 1 to the power supply circuit 5. The connector 9 is, for example, an LIF connector. Note that a slit 9a is formed in the connector 9 at a position offset from the center position along the short side direction of the substrate 8, and is adapted to fit into a protrusion (not shown) or the like provided on the host 1 side. This makes it possible to prevent the semiconductor device 100 from being attached upside down.

[0013] The substrate 8 has a multi-layer structure formed by stacking synthetic resins, for example, an eight-layer structure. The number of layers of the substrate 8 is not limited to eight. FIG. 4 is a diagram showing the layer structure of the substrate 8. In the substrate 8, wiring patterns are formed as wiring layers 8b in various shapes on the surface or inner layer of each layer (insulating film 8a) made of synthetic resin. The wiring patterns are formed of, for example, copper. The power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 mounted on the substrate 8 are electrically connected to each other via the wiring patterns formed on the substrate 8. In addition, the surface (first layer side) and back surface (eighth layer side) of the substrate are covered with solder resist 8c as a protective film.

[0014] 5 is a diagram showing the wiring density of each layer of the substrate 8. Here, the first to fourth layers formed on the front layer side of the center line 30 (see also FIG. 4) of the layer structure of the substrate 8 are referred to as upper layers, and the fifth to eighth layers formed on the back layer side of the center line 30 are referred to as lower layers.

[0015] The wiring layers 8b formed on each layer of the substrate 8 function as signal layers for transmitting and receiving signals and plane layers serving as ground and power lines, as shown in Fig. 5. The wiring density of the wiring patterns formed on each layer, i.e., the ratio of the wiring layers to the surface area of ​​the substrate 8, is configured as shown in Fig. 5.

[0016] In this embodiment, the eighth layer, which functions as the ground, is a mesh wiring layer rather than a plain layer, thereby suppressing the wiring density to 30-60%. Here, the wiring density in the entire upper layer of the substrate 8 is about 60%. Therefore, by forming a wiring pattern with a wiring density of about 30% in the eighth layer, the wiring density in the entire lower layer can be about 60%, and the wiring density in the entire upper layer and the wiring density in the entire lower layer can be made substantially equal. Note that the wiring density of the eighth layer may be adjusted within a range of about 30-60% so that it is substantially equal to the wiring density in the entire upper layer.

[0017] Fig. 6 is a diagram showing a wiring pattern formed on the back surface layer (eighth layer) of substrate 8. As shown in Fig. 6, a wiring pattern is formed in a mesh shape on the back surface layer (eighth layer) of substrate 8. By making the eighth layer of substrate 8 into a mesh-shaped wiring layer in this way, the wiring density is kept lower than if it were formed as a plain layer.

[0018] The wiring layer formed on the back surface layer is also required to function as a shielding layer to reduce the influence of noise leaking from the semiconductor device 100 on other devices. Fig. 8 is a diagram for explaining the line width and spacing of the wiring pattern formed on the back surface layer (eighth layer) of the substrate. As shown in Fig. 8, a mesh wiring having a line width L of 0.3 mm and a line spacing S of 0.9 mm is formed on the eighth layer of the substrate 8. In the mesh wiring formed in this manner, the opening width W is 0.9 x √2 = 1.27 mm.

[0019] For example, the shielding effect against high frequency noise such as the 3GHz SATA fundamental wave is as follows. First, calculate the half wavelength (λ / 2) of the second harmonic of the SATA fundamental wave from C=f×λ×√ε. Here, C is the speed of light, which is 3.0×10 8m / s. f is the frequency of the second harmonic, 6.0×10 9 Hz. ε is the relative dielectric constant, which is 4.6.

[0020] According to the above conditions, λ is 23.3 mm, and 1 / 2 wavelength (λ / 2) is 11.7 mm. In other words, 1 / 2 wavelength (λ / 2) is about 10 times the aperture width W (1.27 mm). In addition, since λ / 20=1.2 mm is almost equal to the aperture width W, the shielding effect is about -20 dB.

[0021] FIG. 9 is a diagram showing adhesive parts filled in the gaps of the NAND memories 10. As shown in FIG. 9, the gaps between the NAND memories 10 and the substrate 8 are filled with adhesive parts 31 made of a synthetic resin material, and the NAND memories 10 and the substrate 8 are bonded together. A part of the adhesive part 31 protrudes from the gap between the NAND memories 10 and the substrate 8. The protruding part fills the gaps between the NAND memories 10 arranged along the longitudinal direction of the substrate 8. Therefore, the adhesive part 31 bonds the NAND memories 10 together at their side surfaces. The adhesive part 31 protrudes to an extent that does not exceed the height of the NAND memories 10, and the surface of the NAND memories 10 is exposed. In FIG. 9, the adhesive part 31 is filled up to about the middle part of the height of the NAND memories 10, but it may be lower than this, as long as the adhesive part 31 is in contact with the adjacent NAND memories 10. Of course, the adhesive part 31 may be filled between the NAND memories 10 so that the height is higher than that shown in FIG. 9.

[0022] FIG. 10 is a diagram showing slits formed in the seventh layer of the substrate 8. FIG. 10 shows the substrate 8 as viewed from the back layer side, with the eighth layer omitted. The NAND memory 10 mounted on the front layer side is shown by a dashed line. A plane layer is formed as a wiring layer in the seventh layer of the substrate 8. As shown in FIG. 10, a wiring pattern is formed as a plane layer in the seventh layer of the substrate 8 over almost the entire area of ​​the seventh layer, and a slit 32 (a portion where no wiring layer is formed) is provided in a part of the wiring pattern. The slit 32 is provided in a portion of the wiring pattern formed over almost the entire area of ​​the seventh layer that faces the gap of the NAND memory 10.

[0023] FIG. 7 is a diagram showing the wiring density of each layer of a substrate as a comparative example. As shown in the comparative example of FIG. 7, in the conventional substrate, the wiring density is about 90% by making the 8th layer a plain layer. Therefore, the wiring density of the lower layer is about 75%, and the difference with the wiring density of the upper layer (about 60%) is large. Due to the difference in wiring density, the ratio of the insulating film 8a (synthetic resin) and the wiring portion (copper) in the entire upper layer of the substrate 8 is different from the ratio of the synthetic resin and copper in the entire lower layer of the substrate 8. As a result, the thermal expansion coefficients of the upper and lower layers of the substrate 8 are also different. Due to this difference in thermal expansion coefficient, warping that forms a convex shape (upward convex shape in FIG. 3) on the surface layer side along the longitudinal direction of the substrate 8 is likely to occur with the temperature change of the substrate 8. Such temperature change is likely to occur during the manufacturing process of the semiconductor device 100. In addition, due to the recent demand for miniaturization of semiconductor devices, the substrate 8 also tends to become thinner, making such warping more likely to occur.

[0024] On the other hand, in this embodiment, the wiring density of the eighth layer is adjusted in the range of about 30 to 60%, and the wiring density of the entire upper layer is made substantially equal to the wiring density of the entire lower layer, so that the thermal expansion coefficients are also substantially equal. This makes it possible to suppress the occurrence of warping in the substrate 8. Also, since the wiring density is adjusted in the eighth layer, which is the furthest from the center line 30 (see also FIG. 4), it is possible to generate a larger moment for suppressing warping.

[0025] Furthermore, since the wiring density is adjusted on the eighth layer of the substrate 8, the wiring design is easier and costs can be reduced compared to adjusting the wiring density on a layer with restrictions on wiring layout, such as a signal layer.

[0026] Furthermore, because the adhesive portion 31 fills the gaps between adjacent NAND memories 10, a force attracting the NAND memories 10 to each other is generated by the bonding force of the adhesive portion 31 as indicated by the arrow X. This force attracting the NAND memories 10 to each other counters the force that warps the substrate 8 to form a convex shape, and therefore the occurrence of warping of the substrate 8 can be suppressed.

[0027] Furthermore, among the wiring patterns formed over substantially the entire area of ​​the seventh layer of the substrate 8, the wiring patterns are provided in the portions facing the gaps between the NAND memories 10, and therefore the bonding strength of the wiring patterns is weakened at the slits 32. As a result, the force that resists the force (see also the arrow X in FIG. 9 ) generated by the adhesive portion 31 filling the gaps between the NAND memories 10 is weakened, and the occurrence of warping of the substrate 8 can be suppressed even more effectively.

[0028] In this embodiment, the eighth wiring layer is a mesh wiring layer in order to adjust the wiring density of the entire lower layer of the substrate 8, but this is not limited thereto, and for example, the wiring layer may be formed in lines. Also, the wiring density of the layers other than the eighth layer among the lower layers, i.e., the wiring layers from the fifth layer to the seventh layer, may be adjusted to adjust the wiring density of the entire lower layer. Of course, the wiring density of all layers from the fifth layer to the eighth layer may be adjusted to adjust the wiring density of the entire lower layer.

[0029] Furthermore, the layer in which the slits 32 are formed is not limited to the seventh layer. Slits may be formed in the lower layers other than the seventh layer, that is, in the fifth to sixth and eighth layers.

[0030] (Second embodiment) 11 is a diagram showing a layer structure of a substrate provided in a semiconductor device according to a second embodiment. In this embodiment, an outermost layer is provided as a ninth layer outside the eighth layer of substrate 8. The outermost layer is entirely covered with copper foil to form a shielding layer. By covering the entire outermost layer with copper foil in this manner, it is possible to more reliably prevent noise leakage from the semiconductor device. Note that the entire layers inside the ninth layer may be covered with copper foil to form a shielding layer.

[0031] (Third embodiment) Fig. 12 is an external perspective view of a holding member used in a semiconductor device transport method according to a third embodiment. Fig. 13 is a cross-sectional view showing a state in which the holding member shown in Fig. 12 is stored in a box. In this embodiment, the semiconductor device 100 is packed in a holding member 50 and transported. The holding member 50 suppresses warping of the substrate 8 due to changes over time.

[0032] The holding member 50 includes a clamping portion 51 and a connecting portion 52. Two clamping portions 51 are provided for one holding member 50. The clamping portions 51 clamp and hold the portion of the substrate 8 along the longitudinal direction. In order to hold the substrate 8 from both sides, two clamping portions 51 are provided for one holding member 50. The clamping portions 51 are formed in a U-shaped cross section, and clamp the portion of the substrate 8 along the longitudinal direction in the gap between them. The clamping portions 51 suppress the warping of the substrate 8 against the force that causes the substrate 8 to warp along the longitudinal direction with time. Therefore, the clamping portions 51 are formed with a strength that can resist the force that tries to warp the substrate 8.

[0033] Furthermore, in order to suppress warping of the substrate 8, it is preferable that the clamping portion 51 is in close contact with the substrate 8 while holding the substrate 8. The gap formed in the clamping portion 51 may be formed, for example, slightly narrower than the thickness of the substrate 8, and the substrate 8 may be inserted into the clamping portion 51 while pushing and widening the gap. Alternatively, the clamping portion 51 may be formed to have a width substantially equal to or slightly wider than the substrate 8, and the substrate 8 may be easily inserted into the gap.

[0034] The connecting portion 52 connects the two clamping portions 51 together, thereby integrating the holding member 50. As shown in Fig. 13, when a plurality of semiconductor devices 100 are stored in a box, the connecting portion 52 maintains the distance between the semiconductor devices 100 and also functions as a cushioning material that absorbs shocks applied to the semiconductor devices 100 during transportation.

[0035] Each of the clamping portions 51 is formed with a spacing portion 53. The spacing portion 53 is formed to extend to the opposite side of the clamping portion 51 from the side where the connecting portion 52 is provided. As shown in Fig. 13, the spacing portion 53 maintains the spacing between the semiconductor devices 100 when a plurality of semiconductor devices 100 are stored in a box, and functions as a cushioning material that absorbs impacts applied to the semiconductor devices 100 during transportation.

[0036] In the present embodiment, the clamping portion 51 is described as clamping the substrate 8, but electronic components such as resistors and capacitors (not shown), the NAND memory 10, etc. are mounted on the substrate 8. Therefore, when electronic components, etc. are mounted on the periphery of the substrate 8, the clamping portion 51 should be formed with a width that can clamp the substrate 8 and the electronic components, etc. together.

[0037] 14 is a front view of holding member 50 according to a modified example of the third embodiment. In this modified example, clamping section 51 is configured to have fixed section 51a and movable section 51b. Fixed section 51a and movable section 51b are rotatably connected at a portion corresponding to the bottom of a gap formed in clamping section 51, and movable section 51b can be opened and closed.

[0038] Each of the movable parts 51b is formed with a closing part 55. As shown in Fig. 14, when the movable parts 51b are closed, the closing parts 55 are caught by each other to keep the movable parts 51b in the closed state. In addition, by keeping the movable parts 51b in the closed state, the width of the gap formed in the clamping part 51 is kept constant.

[0039] Fig. 15 is a diagram showing a state in which the movable part 51b of the holding member 50 shown in Fig. 14 is opened. As shown in Fig. 15, by opening the movable part 51b, the gap of the clamping part 51 can be widened. With the gap of the clamping part 51 widened, by placing the semiconductor device 100 on the fixed part 51a and closing the movable part 51b, the semiconductor device 100 can be held by the holding member 50 more easily than in the case in which the semiconductor device 100 is inserted into the clamping part 51 while pushing the gap wide. [Explanation of symbols]

[0040] 1 host, 2 SATA interface (ATA / IF), 3 communication interface, 4 drive control circuit (controller), 5 power supply circuit, 7 temperature sensor, 8 substrate, 8a insulating film, 8b wiring layer, 9 connector, 9a slit, 10 NAND memory (NAND type flash memory, non-volatile semiconductor memory element), 20 DRAM (volatile semiconductor memory element), 30 center line, 31 adhesive portion, 32 slit, 50 holding member, 51 clamping portion, 52 connecting portion, 53 spacing holding portion, 55 closing portion, 100 semiconductor device, 200 debugging equipment.

Claims

1. a substrate having a first main surface and a second main surface facing in a direction opposite to the first main surface; first to third nonvolatile semiconductor memories mounted on the first main surface of the substrate; a first adhesive portion that fills a gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory while exposing surfaces of the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory; a second adhesive portion that fills a gap between the second nonvolatile semiconductor memory and the third nonvolatile semiconductor memory while exposing surfaces of the second nonvolatile semiconductor memory and the third nonvolatile semiconductor memory; the substrate includes a first wiring layer provided on the first main surface, a second wiring layer as a mesh wiring layer provided on the second main surface, a plurality of wiring layers formed as inner layers, and a plurality of insulating layers respectively provided between the wiring layers; Among the plurality of wiring layers formed as the inner layers, a third and a fourth wiring layer are plane layers, the third wiring layer is formed on the first main surface side of a center line of a layer structure of the substrate and faces the first wiring layer across an insulating layer; the fourth wiring layer is formed on the second main surface side with respect to a center line of a layer structure of the substrate, the fourth wiring layer faces the second wiring layer across an insulating layer; A semiconductor device in which a first slit is formed in a portion of the fourth wiring layer facing the gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory, and a second slit is formed in a portion of the fourth wiring layer facing the gap between the second nonvolatile semiconductor memory and the third nonvolatile semiconductor memory.

2. a fifth wiring layer facing the third wiring layer across an insulating layer and the first wiring layer among the plurality of wiring layers formed as the inner layers are signal layers for transmitting and receiving signals; 2. The semiconductor device according to claim 1, wherein a surface of the first wiring layer is covered with a solder resist.

3. 3. The semiconductor device according to claim 2, wherein a sixth wiring layer, among the plurality of wiring layers formed as the inner layers, which faces the fifth wiring layer across an insulating layer, is a signal layer for transmitting and receiving signals, and at least one of the third and fourth wiring layers is a wiring layer having a ground.

4. The substrate has a substantially rectangular shape in a plan view, a connector provided on a side along a short side direction of the substrate for connecting to an external device; and a controller electrically connected to the connector, controlling the first to third nonvolatile semiconductor memories, and mounted on the first main surface of the substrate, the first to third nonvolatile semiconductor memories are provided on an opposite side of the connector from a position of the controller in a plan view, the second nonvolatile semiconductor memory is provided on an opposite side to the controller as viewed in a plan view with respect to a position of the first nonvolatile semiconductor memory; 4. The semiconductor device according to claim 1, wherein the third nonvolatile semiconductor memory is provided on an opposite side to the first nonvolatile semiconductor memory with respect to a position of the second nonvolatile semiconductor memory in a plan view.

5. a volatile semiconductor memory mounted on the first main surface of the substrate; The controller controls the volatile semiconductor memory; The semiconductor device according to claim 4 , wherein the volatile semiconductor memory is provided on the same side as the connector when viewed from the position of the controller.

6. The substrate has a substantially rectangular shape in a plan view, the first slit extends from a first side along a longitudinal direction of the substrate along a lateral direction of the substrate, the second slit extends along the short side direction from a second side that is a side along a longitudinal direction of the substrate and is different from the first side, The semiconductor device according to claim 1 , wherein the first slit does not reach the second side, and the second slit does not reach the first side.

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