Quantum computation apparatus, quantum computation method, and program

Abstract

To cause a symmetry verification method in quantum computation to be applied during execution of a quantum circuit.SOLUTION: A quantum computation apparatus is provided with: a quantum computation unit for using an auxiliary quantum bit as a control quantum bit and executing a quantum circuit including a control gate which uses a symmetry operator as a target a plurality of times to obtain a measurement result of a physical quantity and a measurement result of the auxiliary quantum bit; and an expected value calculation unit for using the measurement result of the physical quantity and the measurement result of the auxiliary quantum bit to calculate an expected value of the physical quantity in which an error is reduced.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to techniques for quantum error suppression. [Background technology]

[0002] One of the quantum error suppression methods is a method called the symmetry expansion method (Non-Patent Documents 1, 2). The symmetry expansion method is a method that suppresses errors by using symmetry when the quantum system being considered has symmetry.

[0003] In this method, a projection operator onto an ideal quantum state free of computational errors is constructed using symmetry operators derived from the symmetry of the quantum system, and the expectation values ​​of physical quantities corresponding to the error-free quantum state are virtually constructed by post-processing the computation results.

[0004] Here, "virtual" does not mean that the quantum state itself with reduced errors is actually obtained, but that only the expected value of the physical quantity corresponding to the quantum state with reduced errors is obtained. Also, the quantum state obtained by applying the projection operator constructed from symmetry to the quantum state with a calculation error corresponds to the quantum state in which the error is detected. In the quantum error detection method, the detected error is discarded and the calculation is performed, so the quantum state in which the error is detected is the quantum state in which the error is reduced. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] McClean, Jarrod R., Zhang Jiang, Nicholas C. Rubin, Ryan Babbush, and Hartmut Neven. "Decoding quantum errors with subspace expansions." Nature communications 11, no. 1 (2020): 1-9. [Non-Patent Document 2] Cai, Zhenyu. "Quantum error mitigation using symmetry expansion." Quantum 5 (2021): 548. Summary of the Invention [Problem to be solved by the invention]

[0006] In conventional technology, the application of symmetry expansion methods (also called symmetry verification methods) was limited to error suppression of quantum states immediately before measurements (Non-Patent Documents 1 and 2), or to the quantum state preparation stage before starting calculations in continuous quantum computing.

[0007] The present invention has been made in consideration of the above points, and has an object to make it possible to apply a symmetry checking method during the execution of a quantum circuit in quantum computing. [Means for solving the problem]

[0008] According to the disclosed technology, a quantum computing unit that uses an auxiliary quantum bit as a control quantum bit and acquires a measurement result of a physical quantity and a measurement result of the auxiliary quantum bit by executing a quantum circuit including a control gate using a symmetry operator as a target multiple times; an expectation value calculation unit that calculates an expectation value of the physical quantity with reduced error, using a measurement result of the physical quantity and a measurement result of the ancillary quantum bit; A quantum computing device is provided comprising: Effect of the Invention

[0009] The disclosed technology makes it possible to apply symmetry checking methods during the execution of quantum circuits in quantum computing. [Brief description of the drawings]

[0010] [Figure 1] FIG. 3 is a diagram illustrating an example of the configuration of a quantum computing device 300. [Diagram 2]FIG. 2 is a diagram illustrating an example of a functional configuration of a quantum computing device 300 (control device 100). [Diagram 3] FIG. 1 is a diagram illustrating an example of a quantum circuit that is affected by noise. [Figure 4] FIG. 1 illustrates a quantum circuit used to determine the expectation of a state with reduced error. [Diagram 5] 4 is a flowchart showing the operation of the quantum computing device 300. [Figure 6] FIG. 1 is a diagram showing a Hadamard test circuit. [Figure 7] FIG. 2 illustrates an example of a hardware configuration of the apparatus. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention (the present embodiment) will be described with reference to the drawings. The embodiment described below is merely an example, and the embodiment to which the present invention is applied is not limited to the following embodiment.

[0012] (Outline of the embodiment) In this embodiment, the problems of the conventional technology are solved, and the symmetry verification method can be applied even while the quantum circuit is running. Since this method can obtain the same expected value of the physical quantity as when quantum error detection is performed while the quantum circuit is running, in this embodiment, this method is called a virtual quantum error detection method (VQED).

[0013] Furthermore, in the conventional quantum error detection method, the number of measurements for error detection must be the same as the number of stabilizer generators, whereas the number of gate operations required to implement the virtual quantum error detection method does not depend on the number of stabilizer generators, so the cost of error reduction in the virtual quantum error detection method can be lower than that in the conventional quantum error detection method.

[0014] The configuration and operation of a device for implementing the virtual quantum error detection method will now be described in detail.

[0015] (Example of overall device configuration) 1 shows an example of the configuration of a quantum computing device 300 according to this embodiment. The "quantum computing device" may also be called a "quantum computer" or a "quantum computing system."

[0016] 1, the quantum computing device 300 includes a control device 100 and a quantum processor 200. The control device 100 performs quantum computing by transmitting control signals and the like to the quantum processor 200 and acquiring calculation results (measurement results) from the quantum processor 200. The control device 100 can be realized by, for example, a classical computer. Hereinafter, "computer" means "classical computer".

[0017] The quantum processor 200 has a physical quantum system. In this embodiment, for example, a two-level quantum bit or a bosonic quantum bit capable of performing continuous quantum computation can be used as the quantum system. For example, a superconducting circuit, an ion trap, a quantum dot, a microwave photon, etc. can be used as a physical system for realizing the quantum system.

[0018] (Example of functional configuration of quantum computing device 300) The "control device 100 and quantum processor 200" included in the quantum computing device 300 cooperate with each other to realize the function for quantum computing by the quantum computing device 300.

[0019] An example of the functional configuration of the quantum computing device 300 of this embodiment is shown in Fig. 2. As shown in Fig. 2, the quantum computing device 300 has a quantum state preparation unit 310, a quantum computing unit 320, and an expectation value calculation unit 330. The operation of each unit will be described later. Since the control for quantum computing is mainly performed by the control device 100, the functional configuration shown in Fig. 2 may be regarded as the functional configuration of the control device 100.

[0020] It should be noted that the "quantum state preparation unit 310, quantum calculation unit 320, and expectation value calculation unit 330" in the quantum computing device 300 do not need to be provided in one device. For example, the "quantum state preparation unit 310, quantum calculation unit 320" may exist in one device, and the expectation value calculation unit 330 may exist in one or more devices located in another location.

[0021] Furthermore, the quantum bits in this embodiment are not limited to those using an actual physical system. For example, the quantum bits may be on a simulator realized by software. In this case, the quantum processor 200 functions as a simulator of the quantum bits. This simulator may be provided inside the control device 100.

[0022] (Operation of quantum computing device 300) In explaining the operation of the quantum computing device 300, first, problem setting will be explained. Here, G={G1, . . . , G n-k} is generated as a set of stabilizers S={S1,S2,...,S 2^n-k We use a stabilizer code C(S) for [n,k,l] defined by {n,k,l}. The elements of the stabilizer group S may be called symmetry operators.

[0023] As a basic operation, first, the quantum state preparation unit 310 prepares an initial state ρ0 in the code space of the stabilizer code C(S). Next, the quantum computing unit 320 creates L logical quantum gates U l (·)=U l ·U l † (l=1, 2, . . . , L) in order, and finally, a projection measurement of the physical quantity (observable) O in the code space is performed, and the expectation calculation unit 330 calculates the expectation. l is a unitary operator representing the l-th gate.

[0024] However, these logical quantum gates are subject to noise. Let E be the noise process that represents the noise of the lth gate. l In reality, E l 〇Ul In the text of the specification, which is not an image, the symbol "o" is intended to represent a small circle. Figure 3 shows an image (b) of a logical quantum gate (a) being affected by noise.

[0025] In this embodiment, we assume that the noise that enters the logical quantum gate is Markovian, that there is no correlation of errors between gates, and that the auxiliary operations for error suppression described below can be performed without errors.

[0026] In this embodiment, the noise E i In order to virtually suppress the errors caused by the quantum error detection method, the quantum circuit shown in Fig. 4 is used. In the quantum circuit shown in Fig. 4, in the quantum circuit with noise as shown in Fig. 3(b), there is a gate E l 〇U l After the action of |0>+|1>, the control qubit is an ancillary qubit that is a single physical qubit initialized to |+>=(1 / √2)(|0>+|1>). i and control S j and then perform a Pauli X measurement on the ancillary qubit.

[0027] That is, the quantum circuit shown in Figure 4 uses an auxiliary qubit as the control qubit and a symmetry operator (e.g., S i , S j ) as a target.

[0028] The ancillary quantum bit is initialized by quantum state preparation unit 310, and the Pauli X measurement is performed by quantum computing unit 320. The ancillary quantum bit may also be called an ancilla quantum bit.

[0029] Control S i_l The gate acts when the ancillary qubit is 0, as shown by the open circle in Figure 4, and the control S j_lThe gate works when the ancillary qubit is 1, as shown by the black circle in Figure 4. The pre-measurement state of this quantum circuit (including the ancillary qubit) is as follows:

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[0034] A flowchart of the operation procedure of the quantum computing device 300 based on the above processing is shown in FIG. 5. By the procedure in FIG. 5, it is possible to obtain the expected value of a physical quantity in a quantum state in which errors are reduced (the same quantum state as when the quantum error detection method is used). The operation of the quantum computing device 300 will be explained along the procedure in FIG. 5. FIG. 5 mainly shows the operation of the quantum computing unit 320 and the expected value calculation unit 330.

[0035] The quantum computing device 300 repeats S102 to S104 for s=1, . . . , N.

[0036] That is, the quantum computing unit 320 sets s=1 in S101. In S102, the quantum computing unit 320 sets i1, . . . , i L ,j1,···,j L ∈{1, ,2 n-k} is randomly selected, and in S103, the selected i1, . . . , i L ,j1,···,j L The quantum circuit shown in Figure 4 is executed using the above. Execution of the quantum circuit includes gate operations, measurement of the ancillary quantum bit X, and measurement of the physical quantity O.

[0037] In S104, the quantum computing unit 320 calculates a product a of the measurement results of the X measurements of the L ancillary quantum bits. s , and a s and the product b of the measurement result of physical quantity O s This is recorded in a storage unit such as a memory. S102 to S104 are repeated until s = N. After the repetition is completed, the process proceeds to S107.

[0038] In S107, the expected value calculation unit 330 reads data from the storage unit and calculates a=(1 / N)Σ s a s , and b=(1 / N)Σ s bs Here, Σ means the sum of N times. In S108, the expected value calculation section 330 calculates and outputs b / a.

[0039] The above a corresponds to p0 shown in "Equation 4," and the above b corresponds to "Equation 2" (the expected value of the physical quantity before normalization).

[0040] The number of times (N) the process is performed to detect virtual errors may be adjusted according to the amount of calculation errors that occur.

[0041] (Detailed example) The virtual quantum error detection method in this embodiment will be described in more detail. In the following, in order to facilitate understanding of the virtual quantum error detection method, first, the quantum error detection method and quantum error correction method using stabilizer codes and the symmetry expansion method will be described as related techniques, and then the virtual quantum error detection method will be described.

[0042] <Quantum error detection and correction using stabilizer codes> Here we provide an overview of stabilizer codes and quantum error detection (QED) and quantum error correction (QEC) that use stabilizer codes. QED and QEC work by consuming multiple quantum systems to encode quantum information into an extended Hilbert space, where redundancy allows errors to be detected / corrected during the computation.

[0043] Here we explain the stabilizer formalism, which is the most standard way to construct quantum error-correcting codes. Consider the Pauli group of n qubits shown below.

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[0049] To detect physical errors during quantum computation, we use a Hadamard test circuit, as shown in Figure 6, to test the generators G1, ,G n-k This measurement is called the syndrome measurement. If the measurement result is -1, G i If exists, it can be determined that there is an error in the calculation. Conversely, if all G i If the measurement result of is +1, then there is a sufficiently high probability that there was no error. By continuing the calculation only when the measurement results of all generators are +1, we can obtain the noisy state ρ = E(ρ id ) can be projected into the code space.

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[0052] By applying appropriate feedback operations depending on the measurement results, we can not only detect errors but also correct them. This allows us to suppress the effects of noise without the need for additional quantum circuit implementations. i The measurement result is s i and in the absence of measurement errors, the recovery operator R s The error can be corrected by applying R s is set to s=(s1,...,s n-k ) The recovered Pauli operators at least map quantum states to logical states, so R s s i =+1 then G i and s i =-1 then G i is in an anti-exchange relationship with

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[0056] <Symmetry expansion method> Next, we provide an overview of the symmetry expansion method. The symmetry expansion method (SE) is a method for mitigating errors by virtually projecting a noisy quantum state into a symmetric subspace without syndrome measurements.

[0057] Noise-free state ρ id The expectation value of the physical quantity O for the noisy state ρ = E(ρ id ) from measurements. We assume that the physical quantity O commutes with the projection operator P. Then, we can mitigate the error by virtually projecting the noisy state into the code space as follows:

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[0059] For S1:s=1,...,N, repeat the following operations (a) to (b).

[0060] (a)S i Sample ∈S uniformly.

[0061] (b)S i and OS i Measure the noisy state ρ for s and b s Record as.

[0062] S2: a = (1 / N)Σ s a s , and b=(1 / N)Σ s b s Calculate.

[0063] S3: Output b / a.

[0064] The number of measurements required to estimate equation (6) with a fixed accuracy ε is N=O(ε -2 tr[ρP] -2 ) in the noisy state ρ. det We can obtain the error-relaxed expectation value of the physical quantity O, which corresponds to the virtual projection onto

[0065] <Hypothetical quantum error detection method> Next, the virtual quantum error detection method will be described. As described above, in the conventional technology, the symmetry expansion method was applicable only to the state immediately before the measurement and the state preparation of the rotationally symmetric Bosonic code, but the virtual quantum error detection method in this embodiment makes it possible to calculate an error-relaxed expected value corresponding to a state post-selected after a syndrome measurement during the execution of the quantum circuit.

[0066] Here, we will explain the virtual quantum error detection in more detail. Although there are some overlapping parts with the above explanation, here we will show the mathematical expressions etc. in more detail.

[0067] Preparation of the logical initial state ρ0, followed by L logical unitary gates U l (·)=U l ·U † l Consider a logical quantum circuit consisting of (l=1, , L) and the measurement of a physical quantity O. This logical quantum circuit creates a state ρ id =U L Consider estimating the expectation value of a physical quantity O for 〇···〇U1(ρ0).

[0068] As mentioned before, these logical quantum gates are subject to Markovian noise, so the actual gates are U´ l =E l 〇U l For simplicity, we ignore state preparation and measurement (SPAM) errors, but their effects can be easily accounted for. If we can perform quantum error detection after each gate, we obtain

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[0071] As mentioned above, gate E has a calculation error. l 〇U l After applying the function, the control qubit is initialized to |+>=(1 / √2)(|0>+|1>) as the control qubit. i and control S j Then, a Pauli X measurement is performed on the ancillary qubit. This allows us to obtain the expectation value of the physical quantity O corresponding to the quantum state with reduced errors. i_l The gate acts when the ancillary qubit is 0 and the control S j_l The gate works when the ancillary qubit is 1. The state of this quantum circuit just before the measurement, ρ bf As mentioned above, p and q are bit strings of length L, as follows:

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[0078] For S1:s=1,...,N, repeat the following operations (a) to (c).

[0079] (a)il ,j l ∈{1, ,2 n-k}(1≦l≦L) are uniformly sampled.

[0080] (b) Execute the quantum circuit shown in Figure 4.

[0081] (c) The product of the X measurements is a s Record it as a s and the measurement result of physical quantity O are multiplied by b s Record as.

[0082] S2: a = (1 / N)Σ s a s , and b=(1 / N)Σ s b s Calculate.

[0083] S3: Output b / a.

[0084] As above, N=O(ε -2 tr[ρ´det] -2 ) allows us to perform a hypothetical quantum error checking method on the quantum circuit generated during the computation with some fixed precision ε. The above method can be applied not only to QEC / QED codes but also to stabilizer-based QEM methods for spin and electron number conservation.

[0085] The virtual quantum error verification method in this embodiment makes it possible to measure the expected value of a physical quantity without performing syndrome measurement of the stabilizer generator, which requires highly accurate single-shot measurement of the ancillary quantum bit.

[0086] In addition, while conventional quantum error detection methods require measurement of the stabilizer generator of nk using the Hadamard test circuit shown in Figure 6, the virtual quantum error verification method of this embodiment only requires two control operations, regardless of the number of stabilizer generators.

[0087] <Hypothetical implementation of quantum error correction> A method for the quantum computing device 300 to virtually perform quantum error correction without syndrome measurement or feedback operation will be described. The main idea is that the error-corrected state shown in equation (4) can also be expressed as follows:

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[0092] (Example of hardware configuration of control device 100) Any of the devices described in this embodiment (the control device 100 and the quantum computing device 300) can be realized by causing a computer to execute a program. This computer may be a physical computer or a virtual machine on the cloud.

[0093] That is, the device can be realized by executing a program corresponding to the processing performed by the device, using hardware resources such as a CPU and memory built into a computer. The program can be recorded on a computer-readable recording medium (such as a portable memory) and stored or distributed. The program can also be provided via a network such as the Internet or email.

[0094] Fig. 7 is a diagram showing an example of the hardware configuration of the computer. The computer in Fig. 7 includes a drive device 1000, an auxiliary storage device 1002, a memory device 1003, a CPU 1004, an interface device 1005, a display device 1006, an input device 1007, an output device 1008, and the like, all of which are connected to one another via a bus BS. The computer may further include a GPU.

[0095] The program for realizing the processing on the computer is provided by a recording medium 1001 such as a CD-ROM or a memory card. When the recording medium 1001 storing the program is set in the drive device 1000, the program is installed from the recording medium 1001 to the auxiliary storage device 1002 via the drive device 1000. However, the program does not necessarily have to be installed from the recording medium 1001, but may be downloaded from another computer via a network. The auxiliary storage device 1002 stores the installed program as well as necessary files, data, etc.

[0096] The memory device 1003 reads out and stores the program from the auxiliary storage device 1002 when an instruction to start the program is received. The CPU 1004 realizes functions related to the device in accordance with the program stored in the memory device 1003. The interface device 1005 is used as an interface for connecting to a network, the quantum processor 200, etc. The display device 1006 displays a GUI (Graphical User Interface) based on a program, etc. The input device 1007 is composed of a keyboard and mouse, buttons, a touch panel, etc., and is used to input various operation instructions. The output device 1008 outputs the calculation results.

[0097] (Effects of the embodiment) As described above, the technique described in this embodiment allows the application of a symmetry verification method during the execution of a quantum circuit in quantum computing. In addition, since the number of gate operations does not depend on the number of stabilizer generators, the cost for error reduction can be reduced compared to conventional quantum error detection methods.

[0098] The following supplementary notes are further disclosed regarding the above embodiment.

[0099] <Additional Notes> (Additional note 1) a quantum computing unit that uses an auxiliary quantum bit as a control quantum bit and acquires a measurement result of a physical quantity and a measurement result of the auxiliary quantum bit by executing a quantum circuit including a control gate using a symmetry operator as a target multiple times; an expectation value calculation unit that calculates an expectation value of the physical quantity with reduced error, using a measurement result of the physical quantity and a measurement result of the ancillary quantum bit; A quantum computing device comprising: (Additional note 2) The quantum circuit includes a first control gate having a first symmetry operator that operates when the ancillary qubit is 0, and a second control gate having a second symmetry operator that operates when the ancillary qubit is 1. Item 1. The quantum computing device according to item 1. (Additional note 3) The quantum circuit includes a plurality of logical quantum gates, and the first control gate and the second control gate are provided between a certain logical quantum gate and another logical quantum gate. 3. The quantum computing device according to claim 2. (Additional note 4) The expected value calculation unit calculates an average value a of a first product which is a product of measurement results of a plurality of the ancillary quantum bits, and an average value b of a second product which is a product of the first product and a measurement result of the physical quantity, and calculates b / a as an expected value of the physical quantity. 4. The quantum computing device according to claim 1, (Additional note 5) A quantum computing step of acquiring a measurement result of a physical quantity and a measurement result of the auxiliary quantum bit by executing a quantum circuit including a control gate using the auxiliary quantum bit as a control quantum bit and using a symmetry operator as a target a plurality of times; an expectation value calculation step of calculating an expectation value of the physical quantity with reduced error by using the measurement result of the physical quantity and the measurement result of the ancillary quantum bit; A quantum computing method comprising: (Additional note 6) A non-transitory storage medium storing a program for causing a computer to function as each unit in the quantum computing device according to any one of claims 1 to 4.

[0100] Although the present embodiment has been described above, the present invention is not limited to such a specific embodiment, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0101] 100 Control device 200 Quantum Processors 300 Quantum computing device 310 Quantum State Preparation Department 320 Quantum Computation Department 330 Expected Value Calculation Unit 1000 Drive Device 1001 Recording media 1002 Auxiliary storage device 1003 Memory device 1004 CPU 1005 Interface device 1006 Display device 1007 Input Device 1008 Output device

Claims

1. a quantum computing unit that uses an auxiliary quantum bit as a control quantum bit and acquires a measurement result of a physical quantity and a measurement result of the auxiliary quantum bit by executing a quantum circuit including a control gate using a symmetry operator as a target multiple times; an expectation value calculation unit that calculates an expectation value of the physical quantity with reduced error, using a measurement result of the physical quantity and a measurement result of the ancillary quantum bit; A quantum computing device comprising:

2. The quantum circuit includes a first control gate having a first symmetry operator that operates when the ancillary qubit is 0, and a second control gate having a second symmetry operator that operates when the ancillary qubit is 1. The quantum computing device of claim 1 .

3. The quantum circuit includes a plurality of logical quantum gates, and the first control gate and the second control gate are provided between a certain logical quantum gate and another logical quantum gate. The quantum computing device of claim 2 .

4. The expected value calculation unit calculates an average value a of a first product which is a product of measurement results of a plurality of the ancillary quantum bits, and an average value b of a second product which is a product of the first product and a measurement result of the physical quantity, and calculates b / a as an expected value of the physical quantity. The quantum computing device of claim 1 .

5. A quantum computing step of acquiring a measurement result of a physical quantity and a measurement result of the auxiliary quantum bit by executing a quantum circuit including a control gate using the auxiliary quantum bit as a control quantum bit and using a symmetry operator as a target a plurality of times; an expectation value calculation step of calculating an expectation value of the physical quantity with reduced error by using the measurement result of the physical quantity and the measurement result of the ancillary quantum bit; A quantum computing method comprising:

6. A program for causing a computer to function as each unit in the quantum computing device according to any one of claims 1 to 4.

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