Printed wiring board

Abstract

To provide a printed wiring board whose seed layer is hardly ruptured by thermal shock.SOLUTION: A printed wiring board has: a first resin insulation layer; a first conductor layer formed on the first resin insulation layer; a second resin insulation layer which has a first surface and a second surface opposite to the first surface, is formed on the first resin insulation layer and the first conductor layer such that the second surface faces the first conductor layer, and has a via conductor opening reaching the first conductor layer; a second conductor layer formed on the second resin insulation layer; and a via conductor which is formed inside the opening so as to connect the first conductor layer to the second conductor layer. The second conductor layer is made up of: a seed layer on the second resin insulation layer; and an electrolytic plating film on the seed layer. The seed layer is made up of a plurality of copper particles each of which is a single crystal. The copper particles are horizontally arranged.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a printed wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board having a resin substrate, a resin insulating layer formed on the resin substrate, and a conductor circuit. The conductor circuit is formed on the resin insulating layer via an alloy layer containing a specific metal. For example, the specific metal is shown in paragraph

[0008] of Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-124602 A Summary of the Invention

[0004] [Problem of Patent Document 1] In the printed wiring board having the alloy layer of Patent Document 1, it is believed that the seed layer breaks due to thermal shock. [Means for solving the problem]

[0005] The printed wiring board of the present invention comprises a first resin insulating layer, a first conductor layer formed on the first resin insulating layer, a second resin insulating layer having a first surface and a second surface opposite to the first surface, the second surface being formed on the first resin insulating layer and the first conductor layer such that the second surface faces the first conductor layer, the second resin insulating layer having an opening for a via conductor leading to the first conductor layer, a second conductor layer formed on the second resin insulating layer, and a via conductor formed in the opening and connecting the first conductor layer and the second conductor layer. The second conductor layer is composed of a seed layer on the second resin insulating layer and an electrolytic plating film on the seed layer, the seed layer is formed of a plurality of copper particles made of single crystals, and each of the copper particles is arranged horizontally.

[0006] In the printed wiring board according to the embodiment of the present invention, the seed layer is formed of a plurality of copper particles made of single crystals. Each of the copper particles is arranged horizontally. Therefore, the thermal expansion coefficients of the particles forming the seed layer are almost equal. Therefore, the seed layer is not easily broken by thermal shock. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view illustrating a printed wiring board according to an embodiment. [Figure 2A] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 2B] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 2C] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 2D] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 3A] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 3B] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 3C] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 3D] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 3E] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 4A] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 4B] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 4C] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 4D] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 5A] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 5B] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 5C] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 5D] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] <Printed Wiring Board of the Embodiment> Fig. 1 is a cross-sectional view of a printed wiring board 100 according to an embodiment. As shown in Fig. 1, the printed wiring board 100 has a substrate 1 and build-up layers 80U, 80L formed on the front and back sides of the substrate 1. A first conductor layer consisting of a lower layer conductor circuit 9 and a conductor layer 10 is formed on the substrate 1.

[0009] The build-up layers 80U and 80L are formed of the resin insulating layers 12U and 12L, the seed layer 14, the second conductor layer consisting of the electrolytic copper plating film (electrolytic plating film) 15 on the seed layer 14, and the via conductors 15A that penetrate the resin insulating layers 12U and 12L and connect the adjacent conductor layers. The resin insulating layers 12U and 12L are second resin insulating layers. The resin insulating layers 12U and 12L have a first surface 12a and a second surface 12b opposite to the first surface 12a. The second surface 12b faces the lower layer conductor circuit 9 and the conductor layer 10. The resin insulating layers 12U and 12L are formed on the substrate 1, the lower layer conductor circuit 9, and the conductor layer 10. The resin insulating layers 12U and 12L have via conductor openings 13 that reach the lower layer conductor circuit 9 and the conductor layer 10. The via conductors 15A are formed in the via conductor openings 13. The resin insulating layers 12U and 12L contain glass particles, carbon, oxygen, and silicon.

[0010] The seed layer 14 is formed on the resin insulating layers 12U and 12L. As shown in the enlarged view in FIG. 1, the seed layer 14 is formed of a plurality of copper particles made of single crystals, and each of the copper particles is arranged horizontally. No copper particles are formed on one copper particle. The copper particles are not stacked vertically. Therefore, the thermal expansion coefficients of the particles forming the seed layer 14 are approximately equal. Therefore, the seed layer is not easily broken by thermal shock.

[0011] The (1,1,1) planes of the copper particles and the first surfaces 12a of the resin insulating layers 12U and 12L are approximately parallel. The thickness of the seed layer 14 and the thickness of the copper particles are approximately equal. All of the copper particles forming the seed layer 14 are in contact with the resin insulating layers 12U and 12L.

[0012] The diameter of the copper particles is 50 nm or more and 200 nm or less. The thickness of the copper particles is 30 nm or more and 800 nm or less. The surface roughness of the copper particles on the resin insulating layer (12U, 12L) side is 20 nm or more and 100 nm or less. The surface roughness of the copper particles on the electrolytic copper plating film (15) side is 20 nm or more and 100 nm or less.

[0013] The copper particles contain carbon, oxygen, and silicon as impurities. Therefore, the adhesive strength with the resin insulating layers 12U, 12L, which also contain carbon, oxygen, and silicon, is strong. The adhesive strength between the seed layer 14 and the resin insulating layers 12U, 12L is high. The adhesive strength between the seed layer 14 and the resin insulating layers 12U, 12L is high. The amount of impurities in the seed layer 14 gradually decreases from the resin insulating layer 12U, 12L side toward the electrolytic copper plating film 15 side. The amount of copper in the seed layer 14 gradually increases from the resin insulating layer 12U, 12L side toward the electrolytic copper plating film 15 side.

[0014] In FIG. 1, the multi-layering process described later is omitted, and the illustration shows a mode in which build-up layers 80U, 80L consisting of resin insulating layers 12U, 12L, a second conductor layer, and via conductors 15A are formed on a substrate 1 having an upper layer conductor circuit 19 formed in FIG. 5C described later. In reality, in the build-up layers 80U, 80L, the second resin insulating layer from the outermost layer (first resin insulating layer) is laminated on the inner layer side of the outermost resin insulating layer (second resin insulating layer) by the multi-layering process described above. A conductor layer (first conductor layer) is formed on the second resin insulating layer from the outermost layer. The outermost resin insulating layer is formed on the second resin insulating layer from the outermost layer and the first conductor layer. The second surface of the outermost resin insulating layer faces the first conductor layer. A conductor layer (second conductor layer) formed on the outermost resin insulation layer and a conductor layer (first conductor layer) formed on the second-to-outermost resin insulation layer are connected by a via conductor formed in an opening for the via conductor leading to the first conductor layer.

[0015] The printed wiring board 100 has solder resist pattern layers 18U, 18L on the build-up layers 80A, 80B. The solder resist pattern layers 18U, 18L have openings 21U, 21L. The second conductor layer exposed by the openings 21U, 21L functions as a pad for mounting an electronic component. Solder bumps 23 for mounting the electronic component are formed on the pads.

[0016] <Method of manufacturing a printed wiring board according to an embodiment> 2A to 5D show a method for manufacturing printed wiring board 100 according to an embodiment.

[0017] As shown in FIG. 2A, a copper-clad laminate having copper foil 2 attached to both sides of a substrate 1 is used as a starting material. As shown in FIG. 2B, the copper-clad laminate is drilled to form through holes for through holes. Then, electroless plating is applied to form an electroless plating film on the entire surface of the substrate 1. Furthermore, electrolytic copper plating is applied to form an electrolytic copper plating film. As shown in FIG. 2C, a conductor layer 3 including through holes 3a is formed on the entire surface of the substrate 1.

[0018] The substrate 1 on which the conductor layer 3 is formed is washed with water and dried. Thereafter, the substrate 1 is subjected to an oxidation-reduction treatment using an oxidation bath (blackening bath) made of a predetermined aqueous solution and a reduction bath, and as shown in FIG. 2D, a roughened surface 4 is formed on the entire surface of the conductor layer 3 including the through-holes 3a.

[0019] 3A, a metal particle paste 5 containing copper particles is filled into the through-holes 3a by screen printing, and is then dried and hardened. Then, the roughened surface 4 formed on the surface of the conductor layer 3 and the metal particle paste 5 protruding from the through-holes 3a are removed by polishing, and the surface of the substrate 1 is planarized.

[0020] As shown in FIG. 3B, electroless plating is applied to the planarized surface of the substrate 1, thereby forming an electroless copper plating film 6.

[0021] Thereafter, electrolytic copper plating is performed under predetermined conditions to form an electrolytic copper plating film 7, and in the step of FIG. 3D described below, the portion that will become the lower layer conductor circuit 9 is thickened, and the portion that will become the conductor layer 10 that covers the metal particle paste 5 filled in the through hole 3a is formed.

[0022] As shown in FIG. 3C, a photosensitive dry film is attached to both sides of the substrate 1 on which the portions that will become the lower layer conductor circuit 9 and the conductor layer 10 are formed, a mask is placed on the film, the film is exposed to light, and then a development process is performed to form an etching resist 8.

[0023] 3D, the plating film in the portion where the etching resist 8 is not formed is dissolved and removed by etching. Thereafter, the etching resist 8 is peeled off and removed, thereby forming an independent lower layer conductor circuit 9 and conductor layer 10.

[0024] As shown in FIG. 3E, a roughened layer 11 is formed on the surfaces of the lower layer conductor circuit 9 and the conductor layer 10, and further, a Sn layer (not shown) is formed on the surface of this roughened layer 11.

[0025] As shown in FIG. 4A, an epoxy resin composition is applied to both sides of the substrate 1 to form resin layers 120U and 120L which will become the resin insulating layers 12U and 12L.

[0026] 4B, after the formation of the resin layers 120U, 120L, exposure to ultraviolet light and development processing are appropriately performed to form via conductor openings 13. Furthermore, thermal curing is performed to form the resin insulating layers 12U, 12L.

[0027] As shown in FIG. 4C, a seed layer 14 is formed on resin insulating layer 12, via-conductor openings 13, lower-layer conductor circuits 9, and conductor layer 10 by a predetermined sputtering method.

[0028] As shown in FIG. 4D, a photosensitive dry film is attached to both sides of the substrate 1 on which the seed layer 14 is formed, and a photomask film is placed thereon and exposed to light, followed by development processing to form a pattern of the plating resist 16.

[0029] As shown in Fig. 5A, electroplating is performed under predetermined conditions to form an electrolytic copper plating film 15. The lower conductor circuit 9 portion is thickened and the via hole portion is filled with plating (see Fig. 5B described later) by this electrolytic copper plating film 15. The electrolytic copper plating film 15 in the via hole portion forms a via conductor 15A.

[0030] 5B, after the plating resist 16 is peeled off and removed, the seed layer 14 existing under the plating resist 16 is removed by etching. An upper layer conductor circuit 19 is formed, which is made of the seed layer 14 and the electrolytic copper plating film 15 including the via conductors 15A.

[0031] As shown in Fig. 5C, a predetermined sputtering is performed on the substrate 1 on which the upper layer conductor circuit 19 is formed, and an alloy layer 20 made of Ni-Sn is formed on the surface of the upper layer conductor circuit 19. Thereafter, the steps of Fig. 4A to Fig. 5C are repeated to form a multi-layer structure.

[0032] A suitable solder resist composition is applied to both sides of the substrate 1 and dried. Then, a photomask on which a pattern of solder resist openings is drawn is attached to the solder resist layer, exposed to ultraviolet light, and developed to form openings. The solder resist layer is then cured by heating under predetermined conditions to form solder resist pattern layers 18U and 18L having openings 21U and 21L, as shown in FIG. 5D.

[0033] The substrate 1 on which the solder resist pattern layers 18U, 18L are formed is immersed in a predetermined electroless plating solution to form a gold plating layer 22 on the nickel plating layer. Then, solder paste is printed in the openings 21U, 21L of the solder resist pattern layers 18U, 18L and reflowed to form solder bumps 23. The printed wiring board 100 of the embodiment is obtained (see FIG. 1). [Explanation of symbols]

[0034] 1: Substrate 2: Copper foil 3: Conductive layer 3a :Through hole 4: Roughened surface 5: Metal particle paste 6: Electrolytic copper plating film 7: Electroplated copper film 8: Etching resist 9: Lower conductor circuit 10: Conductive layer 11: Roughening layer 12: Resin insulation layer 12a: 1st page 12b: 2nd side 12L: Resin insulation layer 12U: Resin insulation layer 13: Opening for via conductor 14: Seed layer 15: Electrolytic copper plating film 15A: Via conductor 16: Plating resist 18L: Solder resist pattern layer 18U: Solder resist pattern layer 19: Upper layer conductor circuit 20: Alloy layer 21L: Opening 21U:Aperture 22: Gold plating layer 23: Solder bump 80L: Build-up layer 80U: Build-up layer 100: Printed wiring board 120L: Resin layer 120U: Resin layer

Claims

1. A first resin insulation layer; a first conductor layer formed on the first resin insulating layer; a second resin insulating layer having a first surface and a second surface opposite to the first surface, the second surface being formed on the first resin insulating layer and the first conductor layer such that the second surface faces the first conductor layer, the second resin insulating layer having an opening for a via conductor reaching the first conductor layer; a second conductor layer formed on the second resin insulating layer; a via conductor formed in the opening and connecting the first conductor layer and the second conductor layer, the second conductor layer includes a seed layer on the second resin insulating layer and an electrolytic plating film on the seed layer, The seed layer is formed of a plurality of single crystal copper particles, each of which is aligned horizontally.

2. 2. The printed wiring board according to claim 1, wherein a (1,1,1) face of the copper particle and the first face of the second resin insulating layer are substantially parallel to each other.

3. 2. The printed wiring board according to claim 1, wherein the thickness of said seed layer and the thickness of said copper particles are substantially equal.

4. 2. The printed wiring board according to claim 1, wherein the copper particles contain carbon, oxygen and silicon as impurities.

5. 5. The printed wiring board according to claim 4, wherein the amount of the impurities in the seed layer gradually decreases from the second resin insulating layer side toward the electrolytic plating film side.

6. 2. The printed wiring board according to claim 1, wherein the amount of copper in the seed layer gradually increases from the second resin insulating layer side toward the electrolytic plating film side.

7. 5. The printed wiring board according to claim 4, wherein the second resin insulating layer contains carbon, oxygen and silicon.

8. 2. The printed wiring board according to claim 1, wherein the seed layer is formed by sputtering.

9. 2. The printed wiring board according to claim 1, wherein the copper particles have a particle size of 50 nm or more and 200 nm or less.

10. 2. The printed wiring board according to claim 1, wherein the copper particles have a thickness of 30 nm or more and 800 nm or less.

11. 2. The printed wiring board according to claim 1, wherein the copper particles have a surface roughness of 20 nm or more and 100 nm or less on the second resin insulating layer side and a surface roughness of 20 nm or more and 100 nm or less on the electrolytic plating film side.

12. 2. The printed wiring board according to claim 1, wherein all of the copper particles forming the seed layer are in contact with the second resin insulating layer.

13. 2. The printed wiring board of claim 1, wherein said copper particles are not stacked vertically.

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