Semiconductor device and manufacturing method thereof

Abstract

To provide a compact semiconductor device with less degradation of characteristics.SOLUTION: A semiconductor device 100 includes a substrate 10, a first source electrode 12a extending in a first direction, a first drain electrode 16a extending in the first direction, a first gate electrode 14a extending in the first direction and being provided between the first source electrode and the first drain electrode along a second direction crossing the first direction. The semiconductor device 100 includes a second unit FET 60b provided on the substrate in a Y direction relative to a first unit FET 60a, and a first source line 22a provided on the first source electrode while extending in the Y direction, and coming into contact with the first source electrode. The maximum width in the Y direction of an area where the first source line comes into contact with the first source electrode is more than half the maximum width in the Y direction of an area where the first source line overlaps the first source electrode when viewed from the thickness direction of the substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a field effect transistor (FET) having finger-shaped source, gate and drain electrodes, it is known to arrange a plurality of unit FETs each having a source, gate and drain electrode in the extension direction of the electrodes (e.g., Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-299351 A [Patent Document 2] U.S. Patent No. 9,786,660 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Documents 1 and 2, the width of the gate electrode in the unit FET can be shortened by arranging a plurality of unit FETs in the extension direction of the electrode. This makes it possible to suppress the gate resistance. However, the gate wiring that electrically connects the gate pad and the gate electrode that is distant from the gate pad is provided above the unit FET. This increases the parasitic capacitance between the gate wiring and the drain electrode, degrading characteristics such as gain. On the other hand, if the gate wiring is arranged so as not to overlap the unit FET, the semiconductor device becomes larger.

[0005] The present disclosure has been made in consideration of the above problems, and aims to suppress deterioration of characteristics and reduce size. [Means for solving the problem]

[0006] One embodiment of the present disclosure relates to a first unit FET including a substrate, a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction, the first unit FET being provided on the substrate, a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction, the second unit FET being provided on the substrate in the first direction relative to the first unit FET, and a second unit FET extending in the first direction and provided on the first source electrode, the first unit FET being provided on the substrate in the first direction relative to the first unit FET, a first source wiring in electrical contact with a first source electrode, a gate bus bar arranged to sandwich the first gate electrode between the first gate electrode and the second gate electrode in the first direction and electrically connected to the first gate electrode, and a gate wiring arranged above the first source electrode in a non-contact state with the first source electrode, sandwiching the first source wiring between the first drain electrode and the first drain electrode in the second direction, extending in the first direction, and electrically connecting the gate bus bar and the second gate electrode, wherein a maximum width in the first direction of a region where the first source wiring is in contact with the first source electrode is equal to or greater than half the maximum width in the first direction of a region where the first source wiring overlaps the first source electrode as viewed from a thickness direction of the substrate.

[0007] One embodiment of the present disclosure includes a method for manufacturing a semiconductor device comprising the steps of: forming, on a substrate, a first unit FET including a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction; and a second unit FET including a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction, the second unit FET being positioned in the first direction relative to the first unit FET; and forming a gate wiring that is provided above the first source electrode in non-contact with the first source electrode, sandwiches the first source wiring between the first drain electrode and the first drain electrode in the second direction, and electrically connects the first source electrode to the first gate electrode. Effect of the Invention

[0008] According to the present disclosure, deterioration of characteristics can be suppressed and size can be reduced. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line CC in FIG. [Diagram 5] FIG. 5 is a cross-sectional view taken along line DD in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line E-E in FIG. [Figure 7A] FIG. 7A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7B] FIG. 7B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8A] FIG. 8A is a cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8B] FIG. 8B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9A] FIG. 9A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9B] FIG. 9B is a cross-sectional view showing the method for manufacturing the semiconductor device in accordance with the first embodiment. [Figure 10A] FIG. 10A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10B] FIG. 10B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11A] FIG. 11A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11B] FIG. 11B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12A] FIG. 12A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12B] FIG. 12B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13A] FIG. 13A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13B] FIG. 13B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14A] FIG. 14A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14B] FIG. 14B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15]FIG. 15 is a cross-sectional view of the semiconductor device in the first comparative example. [Figure 16] FIG. 16 is a cross-sectional view of a semiconductor device in Comparative Example 2. As shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 18] FIG. 18 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 19] FIG. 19 is a plan view of a semiconductor device according to Modification 2 of the first embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along line AA in FIG. [Figure 21] FIG. 21 is a cross-sectional view taken along line BB in FIG. [Figure 22] FIG. 22 is a plan view of a semiconductor device according to a third modification of the first embodiment. [Figure 23] FIG. 23 is a cross-sectional view taken along line AA in FIG. [Figure 24] FIG. 24 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Diagram 25] FIG. 25 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 26] FIG. 26 is a cross-sectional view of a semiconductor device according to a fifth modification of the first embodiment. [Figure 27] FIG. 27 is a plan view of a semiconductor device according to a sixth modification of the first embodiment. [Figure 28] FIG. 28 is a cross-sectional view taken along line AA in FIG. [Figure 29] FIG. 29 is a plan view of a semiconductor device in the second embodiment. [Diagram 30] FIG. 30 is a cross-sectional view taken along line AA of FIG. [Diagram 31] FIG. 31 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. [Diagram 32] FIG. 32 is a cross-sectional view showing a method for manufacturing the semiconductor device of the second embodiment. [Diagram 33] FIG. 33 is a cross-sectional view showing a method for manufacturing the semiconductor device of the second embodiment. [Diagram 34] FIG. 34 is a cross-sectional view showing a method for manufacturing the semiconductor device of the second embodiment. [Diagram 35] FIG. 35 is a cross-sectional view showing a method for manufacturing the semiconductor device of the second embodiment. [Diagram 36] FIG. 36 is a plan view of a semiconductor device according to a first modification of the second embodiment. [Figure 37] FIG. 37 is a cross-sectional view taken along line AA in FIG. [Figure 38] FIG. 38 is a cross-sectional view taken along line BB of FIG. [Figure 39] FIG. 39 is a plan view of a semiconductor device in the third embodiment. [Diagram 40] FIG. 40 is a cross-sectional view taken along line AA in FIG. [Diagram 41] FIG. 41 is a plan view of a semiconductor device according to a first modification of the third embodiment. [Diagram 42] FIG. 42 is a plan view of a semiconductor device according to Modification 2 of the third embodiment. [Diagram 43] FIG. 43 is a plan view of a semiconductor device according to a third modification of the third embodiment. [Diagram 44] FIG. 44 is a plan view of a semiconductor device in accordance with a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure provides a first unit FET including a substrate, a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction, the first unit FET being provided on the substrate, a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction, the second unit FET including a second unit FET provided on the substrate in the first direction relative to the first unit FET, and a second unit FET extending in the first direction and provided on the first source electrode, the first unit FET being provided on the substrate, The semiconductor device includes a first source wiring electrically contacting a source electrode, a gate bus bar provided so as to sandwich the first gate electrode between the second gate electrode in the first direction and electrically connected to the first gate electrode, and a gate wiring provided above the first source electrode in a non-contact manner with the first source electrode, sandwiching the first source wiring between the first drain electrode in the second direction, extending in the first direction, and electrically connecting the gate bus bar and the second gate electrode, wherein the maximum width in the first direction of a region where the first source wiring is in contact with the first source electrode is at least 1 / 2 times the maximum width in the first direction of a region where the first source wiring overlaps the first source electrode as viewed from the thickness direction of the substrate. This makes it possible to suppress gate-drain capacitance and suppress deterioration of characteristics. In addition, it is possible to miniaturize the semiconductor device. (2) In the above (1), a height of an upper surface of the gate wiring from an upper surface of the substrate may be smaller than a height of an upper surface of the first source wiring from an upper surface of the substrate, thereby making it possible to further suppress gate-drain capacitance. (3) In the above (1) or (2), a first drain wiring may be provided on the first drain electrode, extending in the first direction, and electrically contacting the first drain electrode, and the thickness of the first source wiring may be equal to or less than the thickness of the first drain wiring, thereby reducing the number of manufacturing steps. (4) In any one of the above (1) to (3), a second source wiring may be provided on the second source electrode, extending in the first direction, and electrically contacting the second source electrode, and a thickness of the first source wiring may be equal to a thickness of the second source wiring, thereby reducing the number of manufacturing steps. (5) In any one of the above (1) to (4), an inorganic insulating film may be provided on the first source electrode, and an organic insulating film or a gap may be provided between the inorganic insulating film and the gate wiring, thereby making it possible to reduce gate-source capacitance and suppress deterioration of characteristics. (6) In the above (5), a first location of a part of a region in the first direction where the gate wiring overlaps with the first source electrode as viewed from the thickness direction of the substrate may contact the inorganic insulating film without sandwiching the organic insulating film or the gap, and a second location of the region sandwiching the first location in the first direction may sandwich the organic insulating film or the gap between the inorganic insulating film and a second location of the region sandwiching the organic insulating film or the gap. This makes it possible to stabilize the shape of the gate wiring. (7) In any one of (1) to (6) above, a second source wiring extending in the first direction, provided on the second source electrode, and electrically contacting the second source electrode, and a first connection wiring extending in the second direction, sandwiched between the first source electrode and the second source electrode in the first direction, and electrically connecting the gate wiring and the second gate electrode, may be provided, and the first source wiring may be connected to the second source wiring by crossing the first connection wiring without contacting it. This can further reduce gate-drain capacitance. (8) In any one of (1) to (7) above, a third unit FET provided on the substrate, the third unit FET including: the first source electrode; a third drain electrode extending in the first direction and sandwiching the first source electrode with the first drain electrode in the second direction; and a third gate electrode extending in the first direction and provided between the first source electrode and the third drain electrode in the second direction, the second source electrode; a fourth drain electrode extending in the first direction and sandwiching the second source electrode with the second drain electrode in the second direction; a fourth gate electrode provided between the third unit FET and the first drain electrode, a fourth unit FET provided on the substrate in the first direction with respect to the third unit FET, and a third source wiring extending in the first direction and provided on the first source electrode, sandwiching the gate wiring between the third unit FET and the first source wiring in the second direction and electrically contacting the first source electrode, wherein a maximum width in the first direction of a region where the third source wiring is in contact with the first source electrode may be equal to or greater than half a maximum width in the first direction of a region where the third source wiring overlaps with the first source electrode as viewed in a thickness direction of the substrate. This enables miniaturization of the semiconductor device. (9) In the above (8), a first connection wiring may be provided between the first source electrode and the second source electrode in the first direction and electrically connecting the second gate electrode and the fourth gate electrode, and an end of the gate wiring may be connected to a center part of the first connection wiring in the second direction, thereby supplying a gate potential to the second gate electrode and the fourth gate electrode. (10) In the above (8) or (9), a guard metal layer may be provided above the gate wiring in a non-contact manner, connecting the first source wiring and the third source wiring, thereby making it possible to further reduce gate-drain capacitance. (11) In any one of (1) to (10) above, the semiconductor device may further include a fifth unit FET provided on the substrate, the fifth unit FET including a third source electrode extending in the first direction and sandwiching the first drain electrode between the first source electrode and the first drain electrode in the second direction, the first drain electrode, and a fifth gate electrode extending in the first direction and provided between the third source electrode and the first drain electrode in the second direction, a fourth source wiring extending in the first direction and provided on the third source electrode and electrically contacting the third source electrode, and a second connection wiring provided between the first drain electrode and the gate bus bar in the first direction and electrically connecting the first source wiring and the fourth source wiring. This can further suppress gate-drain capacitance. (12) One embodiment of the present disclosure relates to a method for manufacturing a semiconductor device comprising the steps of: forming, on a substrate, a first unit FET including a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction; and a second unit FET including a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction, the second unit FET being positioned in the first direction relative to the first unit FET; and forming, on a substrate, a first unit FET including a first source electrode extending in the first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in the second direction intersecting the first direction. The method for manufacturing a semiconductor device includes a step of simultaneously forming a first source wiring provided on a source electrode and electrically contacting the first source electrode, a second source wiring extending in the first direction and provided on the second source electrode and electrically contacting the second source electrode, and a first drain wiring extending in the first direction and provided on the first drain electrode and electrically contacting the first drain electrode, and a step of forming a gate wiring provided above the first source electrode in a non-contact with the first source electrode, sandwiching the first source wiring between the first drain electrode in the second direction, extending in the first direction, and electrically connecting a gate bus bar and the second gate electrode. This makes it possible to suppress deterioration of characteristics. Also, it is possible to reduce the size of the semiconductor device. Furthermore, it is possible to reduce the manufacturing process.

[0011] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] A semiconductor device used in an amplifier for amplifying high-frequency signals of, for example, 0.5 GHz to 10 GHz in a mobile communication base station will be described as an example. Fig. 1 is a plan view of the semiconductor device in Example 1. Figs. 2 to 6 are AA, BB, CC, DD and EE cross-sectional views in Fig. 1, respectively. The thickness direction of the substrate 10 is the Z direction, the extension direction of each finger-shaped electrode is the Y direction (first direction), and the arrangement direction of each electrode is the X direction (second direction intersecting the first direction).

[0013] In each figure, the source electrode 12, the gate electrode 14, the drain electrode 16, the source wiring 22, the drain wiring 26, and the unit FET 60 indicate general elements, and the source electrodes 12a, 12b, the gate electrodes 14a to 14d, the drain electrodes 16a, 16b, the source wirings 22a to 22c, the drain wirings 26a, 26b, and the unit FETs 60a to 60d indicate specific elements included in the general elements. In the following, the unit FETs 60a to 60d will be mainly described using the source electrodes 12a, 12b, the gate electrodes 14a to 14d, the drain electrodes 16a, 16b, the source wirings 22a to 22c, and the drain wirings 26a and 26b.

[0014] 1 to 6, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The semiconductor layer 10b includes, for example, a channel layer 10c and a barrier layer 10d. In an XY plane parallel to the X and Y directions, a region of the semiconductor layer 10b that has been inactivated by ion implantation or the like is an inactive region 13, and a region that has not been inactivated is an active region 11a and 11b.

[0015] The active regions 11a and 11b are arranged in the Y direction and extend in the X direction. The active region 11a is provided with a FET group 62a including a plurality of unit FETs 60 arranged in the X direction. The active region 11b is provided with a FET group 62b including a plurality of unit FETs 60 arranged in the X direction.

[0016] In the FET group 62a, the source electrode 12a (first source electrode), the gate electrode 14a (first gate electrode), 14c (third gate electrode), and the drain electrodes 16a (first drain electrode) and 16b (third drain electrode) each extend in the Y direction. In the X direction, the gate electrodes 14a and 14c sandwich the source electrode 12a. In the X direction, the gate electrode 14a is provided between the source electrode 12a and the drain electrode 16a, and the gate electrode 14c is provided between the source electrode 12a and the drain electrode 16b. The unit FET 60a (first unit FET) includes the source electrode 12a, the gate electrode 14a, and the drain electrode 16a. The unit FET 60c (third unit FET) includes the source electrode 12a, the gate electrode 14c, and the drain electrode 16b. The source wiring 22a (first source wiring) and 22c (third source wiring) are provided on the source electrode 12a and are in electrical contact with the source electrode 12a. The source lines 22a and 22c extend in the Y direction and are arranged in the X direction.

[0017] In the FET group 62b, the source electrode 12b (second source electrode), the gate electrode 14b (second gate electrode), 14d (fourth gate electrode), and the drain electrodes 16a (second drain electrode) and 16b (fourth drain electrode) each extend in the Y direction. In the X direction, the gate electrodes 14b and 14d sandwich the source electrode 12b. In the X direction, the gate electrode 14b is provided between the source electrode 12b and the drain electrode 16a, and the gate electrode 14d is provided between the source electrode 12b and the drain electrode 16b. The unit FET 60b (second unit FET) includes the source electrode 12b, the gate electrode 14b, and the drain electrode 16a. The unit FET 60d (fourth unit FET) includes the source electrode 12b, the gate electrode 14d, and the drain electrode 16b. The source wiring 22b (second source wiring) is provided on the source electrode 12b and is in electrical contact with the source electrode 12b. The source wiring 22b extends in the Y direction.

[0018] The drain electrode 16a of the FET group 62a and the drain electrode 16a of the FET group 62b are provided integrally and continuously, and the drain electrode 16b of the FET group 62a and the drain electrode 16b of the FET group 62b are provided integrally and continuously. The drain wirings 26a (first drain wiring) and 26b (second drain wiring) are provided on the drain electrodes 16a and 16b, respectively, and are in electrical contact with the drain electrodes 16a and 16b, respectively. The drain wirings 26a and 26b extend in the Y direction. The drain bus bar 36 is provided so as to sandwich the FET group 62b between the FET group 62a and the drain bus bar 36 in the Y direction. The negative ends in the Y direction of the drain electrodes 16a and 16b are connected to the drain bus bar 36.

[0019] The gate bus bar 34 is provided so as to sandwich the FET group 62a between the FET group 62b in the Y direction. The gate bus bar 34 includes a gate metal layer 34a and a pad metal layer 34b provided on the gate metal layer 34a. A connection wiring 29a is provided between the gate bus bar 34 and the FET group 62a in the Y direction. The connection wiring 29a extends in the X direction and connects the + end of the gate electrode 14a in the X direction to the + end of the gate electrode 14c in the X direction. The gate bus bar 34 and the gate electrodes 14a and 14c are electrically connected and short-circuited via the connection wiring 29a.

[0020] A connection wiring 29b is provided between the FET groups 62a and 62b in the Y direction. The connection wiring 29b (first connection wiring) extends in the X direction and connects the + end in the X direction of the gate electrode 14b and the + end in the X direction of the gate electrode 14d. The gate wiring 28 is provided above the source electrode 12a in a non-electrical contact with the source electrode 12a and extends in the Y direction. The connection wirings 29a and 29b are electrically connected by the gate wiring 28. The gate bus bar 34 and the gate electrodes 14b and 14d are electrically connected and short-circuited via the connection wiring 29a, the gate wiring 28, and the connection wiring 29b.

[0021] An insulating film 35a is provided on the substrate 10 so as to cover the source electrodes 12a, 12b, the gate electrodes 14a to 14d, the drain electrodes 16a, 16b, and the connection wirings 29a and 29b. The insulating film 35a has an opening 25 that exposes the upper surfaces of the source electrodes 12a, 12b, the drain electrodes 16a, 16b, and the connection wirings 29a and 29b. The source wirings 22a and 22c provided on the source electrode 12a are electrically in contact with the source electrode 12a through the opening 25. The source wiring 22b and the drain wirings 26a and 26b provided on the source electrode 12b and the drain electrodes 16a and 16b are electrically in contact with the source electrode 12b and the drain electrodes 16a and 16b through the opening 25, respectively. The gate wiring 28 is electrically in contact with the connection wirings 29a and 29b through the opening 25.

[0022] An insulating film 35b is provided on the source wirings 22a to 22c, the drain wirings 26a and 26b, and the gate wiring 28. The insulating film 35b is provided above the source electrode 12a so as to surround the upper surface, lower surface, and side surfaces of the gate wiring 28. The insulating film 35a, a space 31, and the insulating film 35b are provided between the gate wiring 28 and the source electrode 12a above the source electrode 12a. The space 31 is, for example, a gap (gas such as air).

[0023] The via hole 30 penetrates the substrate 10 and connects to the source electrodes 12a and 12b. A metal layer 32 is provided on the lower surface of the substrate 10. A metal layer 32a is provided on the inner surface of the via hole 30. As a result, the metal layer 32 is electrically connected to the source electrodes 12a and 12b through the via hole 30, and is short-circuited.

[0024] A source potential (e.g., a reference potential such as a ground potential) is supplied from the metal layer 32 to the source electrodes 12a and 12b via the metal layer 32a of the via hole 30. A gate potential (e.g., a high-frequency signal and a gate bias voltage) is supplied from the gate bus bar 34 to the gate electrodes 14a and 14c via the connection wiring 29a. The gate potential is also supplied from the gate bus bar 34 to the gate electrodes 14b and 14d via the connection wiring 29a, the gate wiring 28 and the connection wiring 29b. A drain bias voltage is supplied from the drain bus bar 36 to the drain electrodes 16a and 16b. The high-frequency signals amplified in each of the unit FETs 60a to 60d are output from the drain electrodes 16a and 16b to the drain bus bar 36.

[0025] In the unit FETs 60a and 60c, the high frequency signal is input from the + ends in the Y direction of the gate electrodes 14a and 14c. In the unit FETs 60b and 60d, the high frequency signal is input from the + ends in the Y direction of the gate electrodes 14b and 14d. When the high frequency signal is input to the gate electrodes 14a and 14c from both the + ends and - ends in the Y direction of the gate electrodes 14a and 14c, the high frequency characteristics of the unit FETs 60a and 60c are deteriorated due to a phase difference or the like. In the first embodiment, the - ends in the Y direction of the gate electrodes 14a and 14c are not connected to the + ends in the Y direction of the gate electrodes 14b and 14d, so that deterioration of the high frequency characteristics of the unit FETs 60a and 60c can be suppressed.

[0026] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and / or an InGaN layer. When the unit FETs 60a to 60d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the channel layer 10c is a GaN layer, and the barrier layer 10d is an AlGaN layer. When the semiconductor device 100 is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and / or an InGaAs layer. The semiconductor device 100 may be a silicon semiconductor device such as an LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0027] The source electrodes 12a, 12b and the drain electrodes 16a and 16b are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d, the connection wirings 29a, 29b and the gate metal layer 34a are metal films, for example, nickel films and gold films from the substrate 10 side. The source wirings 22a to 22c, the drain wirings 26a, 26b and the pad metal layer 34b are gold layers, copper layers or aluminum layers, for example. The gate wiring 28 and the metal layer 32 are gold layers, copper layers or aluminum layers, for example. The insulating films 35a and 35b are inorganic insulating films, for example, silicon nitride films.

[0028] The length of the source electrodes 12a and 12b in the X direction is, for example, 10 μm to 100 μm. The length of the drain electrodes 16a and 16b in the X direction is, for example, 1 μm to 50 μm. The length of the source wirings 22a and 22c in the X direction is, for example, 1 μm to 50 μm. The length of the source wiring 22b in the X direction is, for example, 5 μm to 100 μm. The length of the gate wiring 28 in the X direction is, for example, 1 μm to 50 μm. The distance in the X direction between the source electrode 12a and the drain electrode 16 is, for example, 1 μm to 20 μm. The thickness of the source wirings 22a to 22c and the drain wirings 26a and 26b is, for example, 1 μm to 10 μm. The thickness of the gate wiring 28 is, for example, 0.5 μm to 5 μm.

[0029] [Production method of Example 1] 7A to 14B are cross-sectional views showing a method for manufacturing a semiconductor device according to Example 1. Figures 7A to 14A correspond to a part of the AA cross section in Figure 1, and Figures 7B to 14B correspond to a part of the EE cross section in Figure 1.

[0030] As shown in Figures 7A and 7B, source electrodes 12a to 12c, gate electrodes 14a to 14d, drain electrodes 16a, 16b, and connection wirings 29a and 29b are formed on a substrate 10. An insulating film 35a is formed on the substrate 10 so as to cover the source electrodes 12a to 12c, gate electrodes 14a to 14d, drain electrodes 16a, 16b, and connection wirings 29a and 29b. An opening 25 is formed in the insulating film 35a. A mask layer 50 is formed on the insulating film 35a. The mask layer 50 has an opening 51 that exposes the opening 25. The mask layer 50 is, for example, a photoresist.

[0031] 8A and 8B, a seed layer 40 is formed so as to cover the inside of the opening 51 and the mask layer 50. The seed layer 40 is formed on the entire surface of the substrate 10 by, for example, a sputtering method. The seed layer 40 has, for example, an adhesion layer and a low resistance layer on the adhesion layer. The low resistance layer is, for example, a metal layer made of the same material as the plating layers 41 and 42 described later.

[0032] 9A and 9B, a mask layer 52 is formed on the seed layer 40. The mask layer 52 has an opening 53 that exposes the seed layer 40 on the mask layer 50 on the source electrode 12a. The opening 53 is provided to connect the openings 25 on the connection wirings 29a and 29b. The mask layer 52 is, for example, a photoresist.

[0033] 10A and 10B, a plating layer 41 is formed in the opening 53. The plating layer 41 is formed by, for example, an electrolytic plating method in which a current is supplied via the seed layer 40.

[0034] 11A and 11B, the mask layer 52 is peeled off. A mask layer 54 is formed on the seed layer 40 and the plating layer 41. The mask layer 54 has an opening 55 through which the seed layer 40 is exposed above the opening 25. The mask layer 54 is, for example, a photoresist.

[0035] 12A and 12B, a plating layer 42 is formed in the opening 55. The plating layer 42 is formed by, for example, an electrolytic plating method in which a current is supplied via the seed layer 40.

[0036] The plating layer 42 may be formed before the plating layer 41 is formed. If the plating layer 42 is formed before the plating layer 41, the mask layer 50 will be provided so as to cover the plating layer 42. If the plating layer 42 is thicker than the plating layer 41, it is difficult to provide the mask layer 50 so as to cover the thick plating layer 42. Therefore, if the plating layer 41 is thinner than the plating layer 42, the plating layer 41 may be formed before the plating layer 42.

[0037] As shown in Figures 13A and 13B, the mask layer 54 is peeled off. The seed layer 40 is removed using the plating layers 41 and 42 as a mask. As a result, the gate wiring 28 is formed from the seed layer 40 and the plating layer 41. The source wirings 22a to 22c and the drain wirings 26a and 26b are formed from the seed layer 40 and the plating layer 42. Hereinafter, illustration of the seed layer 40 is omitted.

[0038] 14A and 14B, the mask layer 50 is peeled off. An insulating film 35b is formed so as to cover the source wirings 22a to 22c, the drain wirings 26a and 26b, and the gate wiring 28. As a result, a space 31 is formed between the gate wiring 28 and the source electrode 12a. In this manner, the semiconductor device of Example 1 is manufactured.

[0039] Comparative Example 1 Fig. 15 is a plan view of the semiconductor device in Comparative Example 1. As shown in Fig. 15, in the semiconductor device 120 of Comparative Example 1, unit FETs 60a and 60b are arranged in the Y direction. The gate electrode 14a of the unit FET 60a is directly connected to the gate bus bar 34. The gate electrode 14b of the unit FET 60b is connected to the gate bus bar 34 via a connection wiring 29b and a gate wiring 28. The gate wiring 28 is provided so as to sandwich the source electrode 12a between itself and the drain electrode 16a, and the connection wiring 29b is provided between the unit FETs 60a and 60b.

[0040] When the width of the gate electrode of the unit FET in the Y direction increases, the gate resistance of the unit FET increases. When the gate resistance increases, the frequency at which the maximum stable gain switches to the maximum available power gain decreases, and the gain at high frequencies decreases. In the first comparative example, the gate width of the unit FETs 60a and 60b in the Y direction is shortened. The gate electrode 14b and the gate bus bar 34 are electrically connected via the connection wiring 29b and the gate wiring 28. This makes it possible to suppress the gate resistance. Therefore, it is possible to improve the gain at high frequencies. Furthermore, when the gate-drain capacitance increases, the reverse power gain S12 increases. In the first comparative example, the source wiring 22a is provided between the gate wiring 28 and the drain wiring 26a. This causes the source wiring 22a to shield the electric field lines 64 between the gate wiring 28 and the drain wiring 26a. Therefore, the gate-drain capacitance is suppressed, so that the reverse power gain S12 is reduced, and the gain characteristics of the FET can be improved.

[0041] However, the provision of the gate wiring 28 increases the chip size.

[0042] Comparative Example 2 FIG. 16 is a cross-sectional view of a semiconductor device in Comparative Example 2. As shown in FIG. 16, in a semiconductor device 122 in Comparative Example 2, a source wiring 22a and drain wirings 26a and 26b are provided on a source electrode 12a and drain electrodes 16a and 16b, respectively. An insulating film 38a is provided so as to cover the source wiring 22a and the drain wirings 26a and 26b. Guard metal layers 23a, 23b and a gate wiring 28 are provided on the insulating film 38a. The guard metal layers 23a and 23b sandwich the gate wiring 28. The guard metal layers 23a, 23b and the gate wiring 28 are provided so as to overlap the source wiring 22a when viewed from the Z direction. An insulating film 38b is provided so as to cover the guard metal layers 23a, 23b and the gate wiring 28. The other configurations are the same as those in Example 1.

[0043] In Comparative Example 2, the gate wiring 28 is provided so as to overlap the source wiring 22a, so that the chip size can be made smaller than that of Comparative Example 1. Guard metal layers 23a and 23b to which a source potential is supplied are provided so as to sandwich the gate wiring 28. As a result, the guard metal layers 23a and 23b shield the electric field lines 64 between the gate wiring 28 and the drain wirings 26a and 26b. This suppresses the gate-drain capacitance, reduces the reverse power gain S12, and improves the gain characteristics of the FET.

[0044] However, in order to provide the gate wiring 28 and the drain wirings 26a and 26b on the insulating film 38a, the insulating film 38a is formed of an organic insulating film, and the insulating film 38a is flattened. In this way, the number of manufacturing steps is increased because a multi-layer wiring process is performed. In addition, since the insulating films 38a and 38b, which are organic insulating films, become thick, stress increases and the warping of the wafer increases. This reduces the freedom of process selection in the manufacturing process.

[0045] (Description of Example 1) According to the first embodiment, the gate wiring 28 sandwiches the source wiring 22a between the drain electrode 16a in the X direction, and the source wiring 22c between the drain electrode 16b in the X direction. The gate wiring 28 electrically connects the gate bus bar 34 to the gate electrode 14b, and electrically connects the gate bus bar 34 to the gate electrode 14d. In this way, the source wirings 22a and 22c shield the electric field lines 64 (see FIG. 2) between the gate wiring 28 and the drain electrodes 16a and 16b. This makes it possible to suppress the gate-drain capacitance and suppress deterioration of characteristics without using multilayer wiring as in the second comparative example. In this way, the manufacturing process can be simplified because multilayer wiring is not used. Also, warping of the wafer can be suppressed. Also, the gate wiring 28 is provided above the source electrode 12a. This makes it possible to reduce the size of the semiconductor device compared to the first comparative example.

[0046] The gate electrodes 14c and 14d, the drain electrode 16b, and the source wiring 22c may not be provided. By providing the gate electrodes 14c and 14d, the drain electrode 16b, and the source wiring 22c, the semiconductor device 100 can be made smaller.

[0047] A negative end (first end) of gate wiring 28 in the Y direction is connected to a central portion of connection wiring 29b in the X direction. This allows a gate potential to be supplied to gate electrodes 14b and 14d via gate wiring 28 and connection wiring 29b. In the first embodiment, a positive end (second end) of gate wiring 28 in the Y direction is connected to a central portion of connection wiring 29a in the X direction. Gate electrodes 14a and 14b may be directly connected to gate bus bar 34, and a positive end (second end) of gate wiring 28 in the Y direction may be directly connected to gate bus bar 34.

[0048] The source wirings 22a and 22c are wirings for reducing the current density flowing in the Y direction of the source electrode 12a. Therefore, the source wirings 22a and 22c each contact the source electrode 12a through one opening 25. If the area of ​​contact between the source wiring 22a and the source electrode 12a is small, the effect of suppressing the current density flowing in the Y direction of the source electrode 12a is reduced. From this viewpoint, as shown in FIG. 6, the maximum width in the Y direction of the region where each of the source wirings 22a and 22c overlaps with the source electrode 12a as viewed from the Z direction is set to D1, and the maximum width in the Y direction of the region where each of the source wirings 22a and 22c contacts with the source electrode 12a is set to D2. In this case, the maximum width D2 is 1 / 2 or more times, 3 / 4 or more times, or 4 / 5 or more times the maximum width D1. D2 is 1 or less times D1. The contact area of ​​each of the source wirings 22a and 22c with the source electrode 12a is 1 / 4 or more, 1 / 2 or more, or 3 / 4 or more times the area of ​​the region where each of the source wirings 22a and 22c overlaps when viewed from the Z direction.

[0049] 2 and 4, with respect to the top surface of the substrate 10, the height of the top surfaces of the source wirings 22a and 22c is H1, the height of the top surface of the source wiring 22b is H2, and the height of the top surfaces of the drain wirings 26a and 26b is H3. With respect to the top surface of the substrate 10, the height of the top surface of the gate wiring 28 is H4. The thickness of the source wirings 22a and 22c is T1, the thickness of the source wiring 22b is T2, and the thickness of the drain wirings 26a and 26b is T3.

[0050] At this time, the height H4 is smaller than the height H1. As a result, the electric field lines between the gate wiring 28 and the drain electrode 16a and the drain wiring 26a are shielded by the source wiring 22a, and the electric field lines between the gate wiring 28 and the drain electrode 16b and the drain wiring 26b are shielded by the source wiring 22c. This makes it possible to further suppress the gate-drain capacitance. The height H4 is, for example, 0.9 times or less, or 0.8 times or less, of the height H1. From the viewpoint of reducing the resistance of the gate wiring 28, the height H4 is, for example, 0.2 times or more of the height H1. Note that even if the height H4 is higher than the height H1, it has the effect of suppressing the gate-drain capacitance.

[0051] The source wiring 22b is a wiring for reducing the current density flowing in the Y direction of the source electrode 12b. The drain wirings 26a and 26b are wiring for reducing the current density flowing in the Y direction of the drain electrodes 16a and 16b, respectively. As shown in FIG. 12A and FIG. 13A, the source wirings 22a to 22c and the drain wirings 26a and 26b are formed simultaneously. This allows the number of manufacturing steps to be reduced compared to the case where the guard metal layers 23a and 23b are formed separately from the source wiring and the drain wiring as in Comparative Example 2. When manufactured in this manner, the thicknesses T2 and T3 are equal to the thickness T1. The height H2 is equal to the height H1, and the height H3 is equal to the height H1. Note that the thicknesses T2 and T3 are equal to (approximately equal to) the thickness T1, allowing for manufacturing errors, and for example, |T2-T1| / T1 and |T3-T1| / T1 may be 0.1 times or less.

[0052] In FIG. 5, an insulating film 35a (inorganic insulating film) is provided on the source electrode 12a. The gate wiring 28 does not need to be in contact with the source electrode 12a, and may be in contact with the insulating film 35a on the source electrode 12a, for example. However, if the gate wiring 28 is in contact with the insulating film 35a, the gate-source capacitance between the gate wiring 28 and the source electrode 12a increases. Therefore, a space 31, which is an air gap, is provided between the insulating film 35a and the gate wiring 28. This makes it possible to reduce the gate-source capacitance and suppress deterioration of characteristics.

[0053] (Modification 1 of the first embodiment) 17 and 18 are cross-sectional views of a semiconductor device in Modification 1 of Example 1. Fig. 17 is a view corresponding to the AA cross section of Fig. 1, and Fig. 18 is a view corresponding to the DD cross section of Fig. 1.

[0054] 17 and 18, in the semiconductor device 101 of the first modification of the first embodiment, an organic insulating film 38 is provided so as to cover the insulating film 35b. The organic insulating film 38 is also provided between the gate wiring 28 and the insulating film 35a. The organic insulating film 38 is, for example, a polyimide resin or BCB (Benzocyclobutene). The other configurations are the same as those of the first embodiment, and therefore the description will be omitted.

[0055] An organic insulating film 38 is provided between the insulating film 35a and the gate wiring 28. In this case, the distance between the gate wiring 28 and the source electrode 12a can be increased, and therefore the gate-source capacitance can be reduced. The organic insulating film 38 may be a molding resin (e.g., epoxy resin) used for sealing. In order to reduce the gate-source capacitance, the relative dielectric constant of the organic insulating film 38 may be lower than the relative dielectric constants of the insulating films 35a and 35b.

[0056] (Modification 2 of Example 1) FIG. 19 is a plan view of a semiconductor device in Modification 2 of Example 1. FIG. 20 and FIG. 21 are a cross-sectional view taken along the line AA and a cross-sectional view taken along the line BB in FIG. 19, respectively. As shown in FIG. 19 to FIG. 21, in a semiconductor device 102 in Modification 2 of Example 1, the source wirings 22a and 22c extend in the negative direction in the Y direction and are connected to the source wiring 22b. An insulating film 35a is provided between the source wirings 22a and 22c and the connection wiring 29b, and the source wirings 22a and 22c are not in contact with the connection wiring 29b. The source wirings 22a and 22c are provided between the gate wiring 28 on the connection wiring 29b and the drain wirings 26a and 26b, respectively. The other configurations are the same as those in Example 1, and description thereof will be omitted.

[0057] In the semiconductor device 100 of the first embodiment, the source wirings 22a and 22b are not provided between the gate wiring 28 and the drain wirings 26a and 26b, respectively, between the FET groups 62a and 62b. This increases the gate-drain capacitance. In the semiconductor device 102 of the second modified example of the first embodiment, the source wirings 22a and 22c cross the connection wiring 29b without contacting each other and connect to the source wiring 22b. This allows the source wirings 22a and 22c to shield the electric field lines 64 (see FIG. 20) between the gate wiring 28 and the drain wirings 26a and 26b, respectively, between the FET groups 62a and 62b. This makes it possible to further suppress the gate-drain capacitance.

[0058] The source wirings 22a and 22c may be provided on the insulating film 35a with a space therebetween, like the gate wiring 28 on the source electrode 12a. If a space is provided between the source wirings 22a and 22c and the insulating film 35a, the effect of shielding the electric field lines between the gate wiring 28 and the drain wirings 26a and 26b is reduced. Therefore, the source wirings 22a and 22c may be in contact with the insulating film 35a.

[0059] (Modification 3 of Example 1) FIG. 22 is a plan view of a semiconductor device in the third modification of the first embodiment. FIG. 23 is a cross-sectional view taken along the line AA in FIG. 22. As shown in FIGS. 22 and 23, in the semiconductor device 103 in the third modification of the first embodiment, a unit FET 60e (fifth unit FET) includes a source electrode 12c (third source electrode), a gate electrode 14e (fifth gate electrode), and a drain electrode 16a. A source wiring 22d (fourth source wiring) is provided on the source electrode 12c, and the source wiring 22d is in electrical contact with the source electrode 12c. A connection wiring 17 (second connection wiring) electrically connects the source wirings 22a and 22d that sandwich the drain wiring 26a, and is provided between the gate bus bar 34 and the drain wiring 26a in the Y direction. The connection wiring 17 is provided on and in contact with the insulating film 35a. The other configurations are the same as those in the second modification of the first embodiment, and a description thereof will be omitted.

[0060] In the semiconductor devices 100 and 102 of the first embodiment and its modified example 2, a gate-drain capacitance occurs between the drain wiring 26a and the gate bus bar 34. In the semiconductor device 103 of the modified example 3 of the first embodiment, a connection wiring 17 that is electrically connected to and short-circuited with the source wirings 22a and 22d is provided between the gate bus bar 34 and the drain wiring 26a. This allows the connection wiring 17 to shield the electric field lines 64 (see FIG. 23) between the gate bus bar 34 and the drain wiring 26a. This makes it possible to suppress the gate-drain capacitance. Also, the potential of the source wirings 22a and 22d can be stabilized.

[0061] In the second and third modified examples of the first embodiment, the source potential may be supplied from the source electrode 12b through the source wirings 22a and 22c even if the via hole 30 is not provided in the source electrode 12a. Also, the via hole 30 may not be provided in the source electrode 12b, and a source pad may be provided outside the active region 11b.

[0062] (Variation 4 of the First Embodiment) 24 and 25 are cross-sectional views of a semiconductor device in Modification 4 of Example 1. FIGS. 24 and 25 correspond to cross sections of the gate wiring 28 in the Y direction. As shown in FIGS. 24 and 25, in the semiconductor devices 104 and 105 in Modification 4 of Example 1, the gate wiring 28 contacts the insulating film 35a at a portion 43a at the center of the source electrode 12a in the Y direction. In FIG. 24, one portion 43a is provided, and in FIG. 25, two portions 43a are provided. At portions 43b sandwiching the portion 43a in the Y direction, the gate wiring 28 sandwiches a space 31 between the insulating film 35a and the gate wiring 28. The other configurations are the same as those of Example 1 and its Modifications 1 to 3, and description thereof will be omitted.

[0063] When the gate wiring 28 is provided in the insulating film 35a with the space 31 therebetween, the shape of the gate wiring 28 becomes unstable. In such a case, a portion 43a (first portion) in the Y direction of the region where the gate wiring 28 overlaps with the source electrode 12a as viewed from the Z direction contacts the insulating film 35a without sandwiching the space 31 (e.g., an organic insulating film and a gap). At a portion 43b (second portion) sandwiching the portion 43a in the Y direction of the region where the gate wiring 28 overlaps with the source electrode 12a, the gate wiring 28 and the insulating film 35a sandwich the space 31 (an organic insulating film or a gap). This makes it possible to stabilize the shape of the gate wiring 28. The total width of the portions 43a in the Y direction is, for example, 1 / 20 times or more and 1 / 2 times or less of the width of the source electrode 12a in the Y direction.

[0064] (Modification 5 of the First Embodiment) FIG. 26 is a cross-sectional view of a semiconductor device in Modification 5 of Example 1. FIG. 26 is a view corresponding to the AA cross section in FIG. 1. As shown in FIG. 26, in a semiconductor device 106 in Modification 5 of Example 1, the drain wirings 26a and 26b include a plating layer 41 and a plating layer 42 provided on the plating layer 41. The plating layer 41 is formed simultaneously with the plating layer 41 of the gate wiring 28 (see FIGS. 10A and 10B), and the plating layer 42 is formed simultaneously with the plating layer 42 of the source wirings 22a to 22c (see FIGS. 12A and 12B). As a result, the thickness of the drain wirings 26a and 26b is approximately the same as the total thickness of the source wiring 22a and the gate wiring 28.

[0065] The source electrodes 12a and 12b can be supplied with current by the metal layers 32 and 32a through the via hole 30 in addition to the source wirings 22a to 22c. On the other hand, the drain electrodes 16a and 16b are supplied with current only from the drain wirings 26a and 26b. Therefore, by making the drain wirings 26a and 26b thicker than the source wirings 22a to 22c, a larger drain current can be passed, enabling high power operation. In addition, the drain resistance can be reduced. In this way, the height H3 of the upper surface of the drain wirings 26a and 26b based on the upper surface of the substrate 10 may be equal to or greater than the height H1 of the upper surface of the source wirings 22a to 22c based on the upper surface of the substrate 10. From the viewpoint of reducing the gate-drain capacitance, all straight lines from the gate wiring 28 to the drain wirings 26a and 26b may be hidden by the source wirings 22a and 22c. The other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

[0066] (Variation 6 of Example 1) FIG. 27 is a plan view of a semiconductor device according to the sixth modification of the first embodiment. FIG. 28 is a cross-sectional view taken along the line AA of FIG. 27. As shown in FIGS. 27 and 28, in the semiconductor device 113 according to the sixth modification of the first embodiment, the drain electrodes 16a and 16b are not provided between the active regions 11a and 11b. The drain electrodes 16a1 and 16b1 are provided in the active region 11a, and the drain electrodes 16a2 and 16b2 are provided in the active region 11b. The drain electrodes 16a1 and 16a2 are electrically connected by the drain wiring 26a, and the drain electrodes 16b1 and 16b2 are electrically connected by the drain wiring 26b. Between the active regions 11a and 11b, the drain wirings 26a and 26b are provided on the insulating film 35a. The other configurations are the same as those of the first embodiment, and the description thereof will be omitted. In the embodiments other than the first embodiment and their modifications, the drain electrodes may not be provided between the active regions 11a and 11b.

[0067] Example 2 FIG. 29 is a plan view of the semiconductor device in the second embodiment. FIG. 30 is a cross-sectional view taken along line AA in FIG. 29. In FIG. 30, the opening 25 is omitted. As shown in FIGS. 29 and 30, in the semiconductor device 107 of the second embodiment, a guard metal layer 44 is provided so as to cover the upper part of the gate wiring 28. A first end of the guard metal layer 44 is connected to the upper surface of the source wiring 22a, and a second end of the guard metal layer 44 is connected to the upper surface of the source wiring 22c. The guard metal layer 44 is, for example, a gold layer, a copper layer, or an aluminum layer. The other configurations are the same as those of the first embodiment, and description thereof will be omitted.

[0068] (Manufacturing method of Example 2) 31 to 35 are cross-sectional views showing a method for manufacturing a semiconductor device according to Example 2. In Fig. 31 to Fig. 35, the via hole 30 and the metal layers 32 and 32a are omitted.

[0069] As shown in Fig. 31, similarly to Fig. 14A, source wirings 22a and 22c are provided in contact with each other on source electrode 12a. Gate wiring 28 is provided between source wirings 22a and 22c on source electrode 12a. Insulating film 35b is provided to surround source wirings 22a, 22c and gate wiring 28.

[0070] 32, a mask layer 56 is formed on the substrate 10. The mask layer 56 has openings 57 that expose the insulating film 35b on the upper surfaces of the source wirings 22a and 22c. The mask layer 56 is, for example, a photoresist.

[0071] As shown in Fig. 33, an opening 25a is formed in the insulating film 35b using a mask layer 56 as a mask. A seed layer 45 is formed on the opening 25a and the mask layer 56. The seed layer 45 is formed on the entire surface of the substrate 10 by, for example, a sputtering method. The seed layer 45 has, for example, an adhesion layer and a low resistance layer on the adhesion layer. The low resistance layer is, for example, a metal layer made of the same material as the plating layer 46 described later.

[0072] 34, a mask layer 58 is formed on the seed layer 45. The mask layer 58 has an opening 59 between the source wirings 22a and 22b. The mask layer 58 is, for example, a photoresist. A plating layer 46 is formed in the opening 59 by electrolytic plating.

[0073] 35, the mask layer 58 is peeled off. The seed layer 45 is removed using the plating layer 46 as a mask. The mask layer 56 is then removed. As a result, the guard metal layer 44 is formed from the seed layer 45 and the plating layer 46.

[0074] In the semiconductor device 100 of the first embodiment, as shown in FIG. 2, the gate wiring 28 between the source wirings 22a and 22c is open above. Therefore, the electric field lines extend from the gate wiring 28 to the drain wirings 26a and 26b, bypassing the source wirings 22a and 22c. This generates a gate-drain capacitance. In the semiconductor device 107 of the second embodiment, the guard metal layer 44 is provided above the gate wiring 28 in a non-contact manner with the gate wiring 28, and electrically connects the source wiring 22a and the source wiring 22c. As a result, the guard metal layer 44 shields the electric field lines 64 (see FIG. 30) between the gate wiring 28 and the drain wirings 26a and 26b. This makes it possible to further suppress the gate-drain capacitance.

[0075] (Modification 1 of the second embodiment) FIG. 36 is a plan view of a semiconductor device in Modification 1 of Example 2. FIG. 37 and FIG. 38 are a cross-sectional view taken along line AA and a cross-sectional view taken along line BB of FIG. 36, respectively. As shown in FIG. 36 to FIG. 38, in a semiconductor device 108 in Modification 1 of Example 2, a plurality of guard metal layers 44 are provided above one gate wiring 28. Each of the plurality of guard metal layers 44 connects source wirings 22a and 22c. A portion 44a of the guard metal layer 44 is provided between the plurality of guard metal layers 44, and a gap 47 is provided above the gate wiring 28. The other configurations are the same as those in Example 2, and description thereof will be omitted.

[0076] In the semiconductor device 107 of the second embodiment, when the mask layer 56 under the guard metal layer 44 is stripped in FIG. 34 and FIG. 35, the stripping solution or oxygen plasma for ashing may not reach the center of the guard metal layer 44 in the Y direction. In this case, the mask layer 56 remains. In the semiconductor device 108 of the first modification of the second embodiment, the gap 47 is provided between the guard metal layers 44. This allows the stripping solution to reach the mask layer 56 under the guard metal layer 44, and the mask layer 56 can be prevented from remaining. From the viewpoint of shielding electric field lines, the area of ​​the guard metal layer 44 overlapping the region between the source wirings 22a and 22c as viewed from the Z direction may be 1 / 2 or more times, or 3 / 4 or more times, the area of ​​the region between the source wirings 22a and 22c. The guard metal layer 44 as in the second embodiment and its modifications may be provided in the modification of the first embodiment.

[0077] Example 3 Fig. 39 is a plan view of a semiconductor device in Example 3. Fig. 40 is a cross-sectional view taken along line AA in Fig. 39. In Figs. 39 and 40, the via hole 30 and the metal layers 32 and 32a are omitted.

[0078] As shown in FIG. 39 and FIG. 40, in the semiconductor device 109 of the third embodiment, the gate electrodes 14a to 14d have a width in the X direction farther from the semiconductor layer 10b than the width in the X direction closer to the semiconductor layer 10b. That is, the gate electrodes 14a to 14d are T-type or Γ-type gates. Field plates 15 are provided above the substrate 10 between the gate electrode 14a and the drain electrode 16a, between the gate electrode 14b and the drain electrode 16a, between the gate electrode 14c and the drain electrode 16b, and between the gate electrode 14d and the drain electrode 16b, with the insulating film 35a sandwiched therebetween. The field plates 15 are also provided on both sides of the connection wirings 29a and 29b in the Y direction. This can suppress the capacitance between the connection wirings 29a and 29b and the drain wirings 26a and 26b.

[0079] The field plate 15 is connected to the source wirings 22a and 22c at the negative ends in the Y direction of the source wirings 22a and 22c. This electrically connects the field plate 15 to the source electrodes 12a, 12b, and 12c, and a reference potential is supplied to the field plate 15. The field plate 15 is connected to the positive ends or both the negative and positive ends in the Y direction of the source wirings 22a and 22c.

[0080] The field plate 15 can reduce electric field concentration in the semiconductor layer 10b between the gate electrode 14a and the drain electrode 16a, between the gate electrode 14b and the drain electrode 16a, between the gate electrode 14c and the drain electrode 16b, and between the gate electrode 14d and the drain electrode 16b. This can suppress the current drift phenomenon. A part of the field plate 15 may be provided above the gate electrodes 14a to 14d. This can suppress the gate-drain capacitance. The other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

[0081] (Modification 1 of the third embodiment) Fig. 41 is a plan view of a semiconductor device according to the first modification of the third embodiment. As shown in Fig. 41, in a semiconductor device 110 according to the first modification of the third embodiment, a field plate 15 is provided on the positive sides in the Y direction of the connection wirings 29a and 29b. This makes it possible to suppress the gate-drain capacitance between the connection wiring 29a and the drain wirings 26a and 26b, and between the connection wiring 29b and the drain wirings 26a and 26b. The other configurations are the same as those of the third embodiment, and therefore a description thereof will be omitted.

[0082] (Modification 2 of Example 3) FIG. 42 is a plan view of a semiconductor device according to the second modification of the third embodiment. As shown in FIG. 42, in the semiconductor device 114 according to the second modification of the third embodiment, the field plate 15 crosses over the connection wirings 29a and 29b in a non-contact manner, and is connected to the source wirings 22a and 22c at the + ends in the Y direction of the source wirings 22a and 22c. The other configurations are the same as those of the first modification of the third embodiment, and the description is omitted. As in the second modification of the third embodiment, the field plate 15 may be connected to the source wirings 22a and 22c at both the + ends and - ends in the Y direction of the source wirings 22a and 22c. This allows the reference potential to be stably supplied to the entire field plate 15. The field plate 15 may be connected to the source wirings 22a and 22c at the + ends in the Y direction of the source wirings 22a and 22c.

[0083] (Modification 3 of the third embodiment) Fig. 43 is a plan view of a semiconductor device in Modification 3 of Example 3. As shown in Fig. 43, in a semiconductor device 111 in Modification 3 of Example 3, the field plate 15 of unit FET 60a and the field plate 15 of unit FET 60b are provided continuously. The field plate 15 of unit FET 60c and the field plate 15 of unit FET 60d are provided continuously. This makes it possible to suppress the gate-drain capacitance between the connection wiring 29a and the drain wirings 26a and 26b, and between the connection wiring 29b and the drain wirings 26a and 26b. The other configurations are the same as those in Example 3, and therefore description thereof will be omitted.

[0084] The field plate 15 may be provided in the first and second embodiments and their modifications.

[0085] Example 4 FIG. 44 is a plan view of a semiconductor device in Example 4. As shown in FIG. 44, in a semiconductor device 112 in Example 4, an active region 11c is provided between active regions 11a and 11b. An FET group 62c is provided in the active region 11c. A connection wiring 29c is provided between the FET groups 62a and 62c. A connection wiring 29b is provided between the FET groups 62c and 62b. The negative end in the Y direction of the gate wiring 28 of the FET group 62a and the positive end in the Y direction of the gate wiring 28 of the FET group 62c are connected to the connection wiring 29c. The negative end in the Y direction of the gate wiring 28 of the FET group 62c is connected to the connection wiring 29b. The other configurations are the same as those in Example 1, and description thereof will be omitted.

[0086] As in the fourth embodiment, three FET groups 62a to 62c may be provided in the Y direction. This can further reduce the gate resistance. Four or more FET groups may be provided in the Y direction. In the first to third embodiments and their modified examples, three or more FET groups may be provided.

[0087] In the first to fourth embodiments and their modified examples, four unit FETs are arranged in the X direction. However, the number of unit FETs in the X direction can be designed to be arbitrary.

[0088] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0089] 10, 10a Board 10b Semiconductor layer 10c Channel Layer 10d Barrier layer 11a, 11b, 11c active area 12, 12a, 12b, 12c Source electrode 13 Inactive area 14a, 14b, 14c, 14d, 14e Gate electrodes 15 Field Plate 16, 16a, 16b, 16a1, 16a2, 16b1, 16b2 Drain electrodes 17 Connection Wiring 22, 22a, 22b, 22c Source wiring 23a, 23b, 44 Guard metal layer 25, 25a opening 26, 26a, 26b Drain wiring 28 Gate wiring 29a, 29b, 29c Connection wiring 30 Beer Hall 31 Space 32, 32a metal layer 34 Gate bus bar 34a Gate metal layer 34b Pad metal layer 35a, 35b, 38a, 38b Insulating film 36 Drain busbar 38 Organic insulating film 40, 45 seed layer 41, 42 Plating layer 43a, 43b 44 Guard metal layer 44a Part of the guard metal layer 47 Gap 50, 52, 54, 56 Mask layers 51, 53, 55, 57 aperture 60, 60a, 60b, 60c, 60d, 60e Unit FET 62a, 62b, 62c FET group 64 Electric Field Lines 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 120, 122 Semiconductor device

Claims

1. A substrate; a first unit FET provided on the substrate, the first unit FET including: a first source electrode extending in a first direction; a first drain electrode extending in the first direction; and a first gate electrode provided between the first source electrode and the first drain electrode in a second direction extending in the first direction and intersecting the first direction; a second unit FET including a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction, the second unit FET being provided on the substrate in the first direction with respect to the first unit FET; a first source wiring extending in the first direction, provided on the first source electrode, and in electrical contact with the first source electrode; a gate bus bar provided so as to sandwich the first gate electrode between the second gate electrode and the first gate electrode in the first direction and electrically connected to the first gate electrode; a gate wiring provided above the first source electrode in a non-contact manner with the first source electrode, sandwiching the first source wiring between the first drain electrode and the first source wiring in the second direction, extending in the first direction, and electrically connecting the gate bus bar and the second gate electrode; Equipped with a maximum width in the first direction of a region where the first source wiring is in contact with the first source electrode, the maximum width being at least half the maximum width in the first direction of a region where the first source wiring overlaps with the first source electrode, as viewed in the thickness direction of the substrate.

2. 2 . The semiconductor device according to claim 1 , wherein a height of an upper surface of the gate wiring from the upper surface of the substrate is smaller than a height of an upper surface of the first source wiring from the upper surface of the substrate.

3. a first drain wiring extending in the first direction, provided on the first drain electrode, and in electrical contact with the first drain electrode; 3. The semiconductor device according to claim 1, wherein the thickness of the first source wiring is equal to or smaller than the thickness of the first drain wiring.

4. a second source wiring extending in the first direction, provided on the second source electrode, and in electrical contact with the second source electrode; 3. The semiconductor device according to claim 1, wherein a thickness of the first source wiring is equal to a thickness of the second source wiring.

5. an inorganic insulating film provided on the first source electrode; an organic insulating film or a gap provided between the inorganic insulating film and the gate wiring; The semiconductor device according to claim 1 , further comprising:

6. 6. The semiconductor device according to claim 5, wherein a first location of a portion of a region in the first direction where the gate wiring overlaps with the first source electrode as viewed from a thickness direction of the substrate contacts the inorganic insulating film without sandwiching the organic insulating film or the gap, and a second location of the region that sandwiches the first location in the first direction and the inorganic insulating film sandwiches the organic insulating film or the gap.

7. a second source wiring extending in the first direction, provided on the second source electrode, and in electrical contact with the second source electrode; a first connection wiring extending in the second direction, sandwiched between the first source electrode and the second source electrode in the first direction, and electrically connecting the gate wiring and the second gate electrode; Equipped with 3. The semiconductor device according to claim 1, wherein the first source wiring intersects the first connection wiring without contacting the first source wiring and is connected to the second source wiring.

8. a third unit FET provided on the substrate, the third unit FET including: the first source electrode; a third drain electrode extending in the first direction and sandwiching the first source electrode between the first drain electrode in the second direction; and a third gate electrode extending in the first direction and provided between the first source electrode and the third drain electrode in the second direction; a fourth unit FET including: the second source electrode; a fourth drain electrode extending in the first direction and sandwiching the second source electrode between the second drain electrode in the second direction; and a fourth gate electrode extending in the first direction and provided between the second source electrode and the fourth drain electrode in the second direction, the fourth unit FET being provided on the substrate in the first direction with respect to the third unit FET; a third source wiring extending in the first direction, provided on the first source electrode, sandwiching the gate wiring between the first source wiring and the third source wiring in the second direction, and electrically contacting the first source electrode; Equipped with 3. The semiconductor device according to claim 1, wherein a maximum width in the first direction of a region where the third source wiring contacts the first source electrode is at least half the maximum width in the first direction of a region where the third source wiring overlaps the first source electrode when viewed from a thickness direction of the substrate.

9. a first connection wiring that is sandwiched between the first source electrode and the second source electrode in the first direction and electrically connects the second gate electrode and the fourth gate electrode; The semiconductor device according to claim 8 , wherein an end of the gate wiring is connected to a center portion of the first connection wiring in the second direction.

10. The semiconductor device according to claim 8 , further comprising a guard metal layer provided above the gate wiring in a non-contact manner with the gate wiring, the guard metal layer connecting the first source wiring and the third source wiring.

11. a fifth unit FET provided on the substrate, the fifth unit FET including: a third source electrode extending in the first direction and sandwiching the first drain electrode between the first source electrode and the first drain electrode in the second direction; the first drain electrode; and a fifth gate electrode extending in the first direction and provided between the third source electrode and the first drain electrode in the second direction; a fourth source wiring extending in the first direction, provided on the third source electrode, and in electrical contact with the third source electrode; a second connection wiring provided between the first drain electrode and the gate bus bar in the first direction, the second connection wiring electrically connecting the first source wiring and the fourth source wiring; The semiconductor device according to claim 1 , further comprising:

12. a first unit FET including: a first source electrode extending in a first direction; a first drain electrode extending in the first direction; and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction that extends in the first direction and intersects with the first direction; a second unit FET including a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction, the second unit FET being positioned in the first direction with respect to the first unit FET; on a substrate; a step of simultaneously forming a first source wiring extending in the first direction, provided on the first source electrode, and in electrical contact with the first source electrode, a second source wiring extending in the first direction, provided on the second source electrode, and in electrical contact with the second source electrode, and a first drain wiring extending in the first direction, provided on the first drain electrode, and in electrical contact with the first drain electrode; forming a gate wiring provided above the first source electrode in a non-contact manner with the first source electrode, sandwiching the first source wiring between the first drain electrode in the second direction, extending in the first direction, and electrically connecting a gate bus bar and the second gate electrode; A method for manufacturing a semiconductor device comprising the steps of:

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