Semiconductor device

Abstract

To provide a semiconductor device having less degradation of characteristics.SOLUTION: A semiconductor device 104 includes: a substrate 10; a unit FET 35a in which a first drain electrode 16a, a first gate electrode 14a, and a first source electrode 12a are provided on the substrate in this order; a unit FET 35c in which a second source electrode 12c provided along and side by side with the first source electrode and electrically connected to the first source electrode, a second gate electrode 14c electrically connected to the first gate electrode, and a second drain electrode 16c electrically connected to the first drain electrode are provided on the substrate in this order; a gate line 23 electrically connected to the first electrode and the second gate electrode; a first cover metal layer 30b provided on and electrically connected to the first source electrode, at least at an upper part of the first cover metal layer projecting further towards the gate line than the first source electrode; and a second cover metal layer 30d provided on and electrically connected to the second source electrode, at least at an upper part of the second cover metal layer projecting further towards the gate line than the second source electrode.SELECTED DRAWING: Figure 17

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In a field effect transistor (FET) having finger-shaped source, gate and drain electrodes, it is known to arrange a plurality of unit FETs each having a source, gate and drain electrode in the extension direction of the electrodes (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-299351 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the width of the gate electrode in each unit FET can be shortened by arranging multiple unit FETs in the direction in which the electrodes extend. This makes it possible to suppress the gate resistance. However, the parasitic capacitance between the drain electrode and the gate wiring that electrically connects the gate pad and the gate electrode that is distant from the gate pad increases, degrading the characteristics.

[0005] The present disclosure has been made in consideration of the above problems, and aims to suppress deterioration of characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in that order on the substrate; a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, which are provided in that order on the substrate; a second transistor unit located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; a gate wiring provided on the substrate between the first source electrode and the second source electrode and adjacent to the first source electrode and the second source electrode, and electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer provided electrically connected on the first source electrode, at least an upper portion of which protrudes from the first source electrode toward the gate wiring; and a second cover metal layer provided electrically connected on the second source electrode, at least an upper portion of which protrudes from the second source electrode toward the gate wiring.

[0007] One embodiment of the present disclosure includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in this order on the substrate, a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, which are provided in this order on the substrate, and a second transistor unit located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged, and a first transistor unit having a first source electrode between the first source electrode and the second source electrode. the first source wiring is provided on the substrate adjacent to the first source electrode and the second source electrode, and is electrically connected to the first gate electrode and the second gate electrode; a first source wiring provided on and in electrical contact with the first source electrode; a second source wiring provided on and in electrical contact with the second source electrode; a first drain wiring provided on and in electrical contact with the first drain electrode, the height of its upper surface from the substrate being smaller than the height of the upper surface of the first source wiring from the substrate; and a second drain wiring provided on and in electrical contact with the second drain electrode, the height of its upper surface from the substrate being smaller than the height of the upper surface of the second source wiring from the substrate. Effect of the Invention

[0008] According to the present disclosure, deterioration of characteristics can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged view of a range D in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line AA in FIGS. [Figure 4] FIG. 4 is a cross-sectional view taken along line BB in FIGS. [Diagram 5] FIG. 5 is a cross-sectional view taken along line CC in FIG. [Figure 6] FIG. 6 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10A] FIG. 10A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10B] FIG. 10B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10C] FIG. 10C is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11A] FIG. 11A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11B] FIG. 11B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11C] FIG. 11C is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device according to a first comparative example. [Figure 13] FIG. 13 is an enlarged plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along line AA in FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along line BB of FIG. [Figure 16] FIG. 16 is an enlarged plan view of a semiconductor device according to a second modification of the first embodiment. [Figure 17] FIG. 17 is a cross-sectional view taken along line AA in FIG. [Figure 18] FIG. 18 is an enlarged plan view of a semiconductor device according to a third modification of the first embodiment. [Figure 19] FIG. 19 is a cross-sectional view taken along line AA in FIG. [Figure 20] FIG. 20 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 21] FIG. 21 is a diagram showing the K-factor versus frequency in semiconductor devices A and B. [Figure 22] FIG. 22 is a diagram showing |S12| versus frequency in semiconductor devices A and B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in that order on the substrate; a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, which are provided in that order on the substrate; a second transistor unit located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; a gate wiring provided on the substrate between the first source electrode and the second source electrode and adjacent to the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer provided on and electrically connected to the first source electrode, at least an upper portion of which protrudes beyond the first source electrode toward the gate wiring; and a second cover metal layer provided on and electrically connected to the second source electrode, at least an upper portion of which protrudes beyond the second source electrode toward the gate wiring. This makes it possible to suppress the gate-drain parasitic capacitance and thus to prevent deterioration of characteristics. (2) In the above (1), at least a part of the first cover metal layer and at least a part of the second cover metal layer may overlap the gate wiring in a non-contact manner in a plan view, thereby making it possible to further suppress gate-drain parasitic capacitance and deterioration of characteristics. (3) In the above (1) or (2), the first cover metal layer and the second cover metal layer may be in contact with each other above the gate wiring, thereby making it possible to further reduce gate-drain parasitic capacitance and to further prevent deterioration of characteristics. (4) In the above (3), the first cover metal layer and the second cover metal layer may be arranged alternately along the gate wiring between a portion where the first cover metal layer and the second cover metal layer are in contact with each other above the gate wiring and a portion where the first cover metal layer and the second cover metal layer are not arranged above the gate wiring. This allows the gate-drain parasitic capacitance and the gate-source parasitic capacitance to be set to desired values, and deterioration of characteristics can be further suppressed. (5) In the above (1) or (2), the first cover metal layer and the second cover metal layer may not be in contact with each other above the gate wiring. This can reduce gate-source parasitic capacitance and further suppress deterioration of characteristics. (6) In the above (5), an edge of the first cover metal layer may overlap the gate wiring in a plan view, and an edge of the second cover metal layer may overlap the gate wiring in a plan view, thereby suppressing gate-drain parasitic capacitance and gate-source parasitic capacitance, and further suppressing deterioration of characteristics. (7) In any one of the above (1) to (6), a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode may be provided in this order on the substrate, and the third transistor unit may be located on a side to which the first gate electrode extends with respect to the first transistor unit. This can further reduce gate-drain parasitic capacitance and further suppress deterioration of characteristics. (8) In the above (7), a connection wiring may be provided between the first transistor unit and the third transistor unit, electrically connecting the third gate electrode and the gate wiring, and a part of the first cover metal layer may overlap at least a part of the connection wiring in a plan view, thereby making it possible to further suppress gate-drain parasitic capacitance and deterioration of characteristics. (9) In any one of the above (1) to (8), a first drain wiring is provided on and in electrical contact with the first drain electrode, the height from the substrate to the top surface of the first drain wiring being smaller than the height from the substrate to the top surface of the first cover metal layer, and a second drain wiring is provided on and in electrical contact with the second drain electrode, the height from the substrate to the top surface of the second drain wiring being smaller than the height from the substrate to the top surface of the second cover metal layer. This makes it possible to suppress gate-drain parasitic capacitance and gate-source parasitic capacitance, and to suppress deterioration of characteristics. (10) One embodiment of the present disclosure includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in this order on the substrate, a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, which are provided in this order on the substrate, and a second transistor unit located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged, and a first transistor unit having a first gate electrode and a first source electrode provided between the first source electrode and the second source electrode. The semiconductor device includes a gate wiring provided on the substrate adjacent to the source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first source wiring provided on the first source electrode in electrical contact therewith, a second source wiring provided on the second source electrode in electrical contact therewith, a first drain wiring provided on the first drain electrode in electrical contact therewith and having a height of an upper surface from the substrate smaller than a height of an upper surface of the first source wiring from the substrate, and a second drain wiring provided on the second drain electrode in electrical contact therewith and having a height of an upper surface from the substrate smaller than a height of an upper surface of the second source wiring from the substrate. This makes it possible to suppress gate-drain parasitic capacitance and gate-source parasitic capacitance, and to suppress deterioration of characteristics. (11) In the above (10), a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode may be provided in this order on the substrate, and the third transistor unit may be located on a side to which the first gate electrode extends with respect to the first transistor unit. This can further reduce gate-drain parasitic capacitance and further suppress deterioration of characteristics.

[0011] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] A semiconductor device used in an amplifier for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a base station of a mobile communication will be described as an example. FIG. 1 is a plan view of the semiconductor device in the first embodiment. FIG. 2 is an enlarged view of the range D in FIG. 1, and FIG. 3 to FIG. 5 are AA, BB, and CC cross-sectional views in FIG. 1 or FIG. 2, respectively. The thickness direction of the substrate 10 is the Z direction, the extension direction of each finger-shaped electrode is the Y direction (first direction), and the arrangement direction of each electrode is the X direction (second direction intersecting the first direction). In the plan views of FIG. 1 and FIG. 2, if the cover metal layer 30 and the source wirings 22a to 22c overlap, it becomes difficult to see. For this reason, a thick dashed line showing only the outer periphery is illustrated inside the source wirings 22a to 22c by seeing through the cover metal layer 30.

[0013] In each figure, the source electrode 12, the gate electrode 14, the source wiring 22, and the unit FET 35 indicate general elements, and the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the source wirings 22a to 22c, and the unit FETs 35a to 35d indicate specific elements included in the general elements. In the following, the unit FETs 35a to 35d will be mainly described using the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the drain electrodes 16a, 16b, the source wirings 22a to 22c, and the drain wirings 26a and 26c.

[0014] 1 to 5, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In an XY plane parallel to the X and Y directions, regions of the semiconductor layer 10b that have been inactivated by ion implantation or the like are inactive regions 13a and 13b, and regions that have not been inactivated are active regions 11a to 11c.

[0015] The active regions 11a and 11b are arranged in the X direction. The active region 11c is provided in a region in the +Y direction from the active regions 11a and 11b. The region between the active regions 11a and 11b is an inactive region 13a. The region between the active regions 11a and 11c is an inactive region 13b. An FET group 36a including a plurality of unit FETs 35a and 35c arranged in the X direction is provided on the active regions 11a and 11b. An FET group 36b including a plurality of unit FETs 35b and 35d arranged in the X direction is provided in the active region 11c. The FET group 36a is sandwiched between the gate bus bar 25 and the FET group 36b. The FET group 36b is sandwiched between the drain bus bar 24 and the FET group 36a.

[0016] The unit FET 35a (first transistor unit) has a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode) that extend in the Y direction and are provided on the substrate 10. The drain electrode 16a, the gate electrode 14a, and the source electrode 12a are provided in this order. The unit FET 35c (second transistor unit) is located on the side of the unit EET 35a where the drain electrode 16a, the gate electrode 14a, and the source electrode 12a are arranged. The unit FET 35c has a source electrode 12c (second source electrode), a gate electrode 14c (second gate electrode), and a drain electrode 16c (second drain electrode) that extend in the Y direction and are provided on the substrate 10. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are provided in this order. The source electrode 12c is provided in line with the source electrode 12a, and is electrically connected to the source electrode 12a via the source electrode 12b. The gate electrode 14c is electrically connected to the gate electrode 14a via a gate bus bar 25. The drain electrode 16c is electrically connected to the drain electrode 16a via a drain bus bar .

[0017] A gate wiring 23 extending in the Y direction is provided on a region of the substrate 10 located in the +X direction of the unit FET 35a. The gate wiring 23 is provided adjacent to the source electrodes 12a and 12c on an inactive region 13a between the unit FETs 35a and 35c. That is, in the unit FET 35a, the source electrode 12a is closer to the gate wiring 23 than the drain electrode 16a. In the unit FET 35c, the source electrode 12c is closer to the gate wiring 23 than the drain electrode 16c. A gate metal layer 18a is provided between the gate wiring 23 and the substrate 10. The gate metal layer 18a does not necessarily have to be provided.

[0018] The unit FETs 35b (third transistor unit) and 35d are provided in regions on the substrate 10 located on the side where the gate electrode 14a extends with respect to the unit FETs 35a and 35c. The unit FET 35b has a source electrode 12b (third source electrode), a gate electrode 14b (third gate electrode), and a drain electrode 16b (third drain electrode) each extending in the Y direction and provided on the substrate 10. The drain electrode 16b, the gate electrode 14b, and the source electrode 12b are provided in this order. The drain electrode 16b is electrically connected to the drain electrode 16a. The gate electrode 14b is electrically connected to the gate wiring 23. The source electrode 12b is electrically connected to the source electrode 12a. The unit FET 35d has a source electrode 12b, a gate electrode 14d, and a drain electrode 16d each extending in the Y direction and provided on the substrate 10. The unit FETs 35b and 35d share the source electrode 12b. When viewed from the Y direction, the source electrodes 12a, 12c and the gate wiring 23 are provided so as to overlap the source electrode 12b and to be within the range in which the source electrode 12b is provided.

[0019] A gate wiring 18 extending in the X-direction is provided on the inactive region 13b. The gate wiring 18 electrically connects and shorts the gate wiring 23 and the gate electrodes 14b and 14d. The gate wiring 23 and the gate electrodes 14a and 14c are connected to a gate bus bar 25.

[0020] The source wirings 22a (first source wiring), 22b, and 22c (second source wiring) are provided on and in contact with the source electrodes 12a, 12b, and 12c, respectively. The source wirings 22a and 22c cross the gate wiring 18 without contacting each other with the insulating layer 32a sandwiched therebetween, and are connected to the source electrode 12b. The drain wiring 26a (first drain wiring) is provided on and in contact with the drain electrodes 16a and 16b, and electrically connects the drain electrodes 16a and 16b to the drain bus bar 24. The drain wiring 26c (second drain wiring) is provided on and in contact with the drain electrodes 16c and 16d, and electrically connects the drain electrodes 16c and 16d to the drain bus bar 24.

[0021] The cover metal layer 30 is provided on and in contact with the source wirings 22a to 22c. An insulating layer 32a is provided on the substrate 10 so as to cover the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the drain electrodes 16a and 16b, the source wirings 22a to 22c, the drain wirings 26a and 26c, and the cover metal layer 30. When viewed from the Z direction, the cover metal layer 30 is provided so as to overlap a part of the gate wiring 18 and a part of the gate wiring 23. As shown in FIG. 3, in the FET group 36a, the cover metal layer 30 includes metal layers 30a and 30c provided on the source wirings 22a and 22c, respectively, and a metal layer 30b connecting the metal layers 30a and 30c. The metal layers 30a to 30c are provided integrally and continuously.

[0022] The via hole 20 penetrates the substrate 10 and is connected to the source electrode 12b. A metal layer 28 is provided on the lower surface of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20. As a result, the metal layer 28 is electrically connected to the source electrode 12b through the via hole 20, and is short-circuited.

[0023] A source potential (e.g., a reference potential such as a ground potential) is supplied from the metal layer 28 to the source electrode 12b via the metal layer 28a in the via hole 20. Furthermore, the source potential is supplied to the source electrodes 12a to 12c and the cover metal layer 30 via the source wirings 22a to 22c. A gate potential (e.g., a high-frequency signal and a gate bias voltage) is supplied from the gate bus bar 25 to the gate electrodes 14a and 14c. Furthermore, the gate potential is supplied from the gate bus bar 25 to the gate electrodes 14b and 14d via the gate wirings 23 and 18. A drain bias voltage is supplied from the drain bus bar 24 to the drain electrodes 16a to 16d via the drain wirings 26a and 26c. The high-frequency signal amplified in each unit FET 35a to 35d is output to the drain bus bar 24 from the drain wirings 26a and 26c.

[0024] In the unit FETs 35a and 35c, the high frequency signal is input from the negative ends in the Y direction of the gate electrodes 14a and 14c. In the unit FETs 35b and 35d, the high frequency signal is input from the negative ends in the Y direction of the gate electrodes 14b and 14d. When the high frequency signal is input to the gate electrodes 14a and 14c from both the positive and negative ends in the Y direction of the gate electrodes 14a and 14c, the high frequency characteristics of the unit FETs 35a and 35c deteriorate due to a phase difference or the like. In the first embodiment, the positive ends in the Y direction of the gate electrodes 14a and 14c are not connected to the negative ends in the Y direction of the gate electrodes 14b and 14d, so that deterioration of the high frequency characteristics of the unit FETs 35a and 35c can be suppressed.

[0025] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the unit FETs 35a to 35d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes an arsenide semiconductor layer, such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer, etc. The semiconductor device 100 may be a silicon semiconductor device, such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS).

[0026] The source electrodes 12a to 12c and the drain electrodes 16a to 16d are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d and the gate metal layer 18a are metal films, for example, nickel films and gold films from the substrate 10 side. The source wirings 22a to 22c, the drain wirings 26a and 26c, the gate wiring 23 and the cover metal layer 30 are, for example, gold layers, copper layers or aluminum layers. The insulating layer 32a is, for example, an inorganic insulator layer such as a silicon nitride layer. The insulating layer 32 is, for example, an organic insulator layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.

[0027] The width of the source electrodes 12a and 12c in the X direction is, for example, 5 μm to 20 μm. The width of the source electrode 12b in the X direction is, for example, 50 μm to 150 μm. The gate lengths of the gate electrodes 14a to 14d in the X direction are, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a and 16c in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 23 in the X direction is, for example, 5 μm to 20 μm. The width of the gate wiring 18 in the Y direction is, for example, 3 μm to 20 μm. The gate width of the unit FETs 35a to 35d in the Y direction is, for example, 100 μm to 400 μm. The width of the via hole 20 in the X direction is, for example, 10 μm to 60 μm.

[0028] The widths of the source wirings 22a to 22c and the drain wirings 26a and 26c in the X direction are equal to or slightly smaller than the widths of the source electrodes 12a to 12c and the drain electrodes 16a and 16c in the X direction, respectively. The thicknesses of the source wirings 22a to 22c and the drain wirings 26a and 26c are, for example, 1 μm to 20 μm. The thickness of the gate wiring 23 is, for example, 0.5 μm to 5 μm. The thickness of the gate wiring 23 may be equal to or smaller than the thicknesses of the source wirings 22a to 22c and the drain wirings 26a and 26c. The thickness of the cover metal layer 30 is, for example, 1 μm to 5 μm.

[0029] [Production method of Example 1] 6 to 9 are plan views showing the method for manufacturing the semiconductor device according to the embodiment 1. Fig. 10A to Fig. 11C are cross-sectional views showing the method for manufacturing the semiconductor device according to the embodiment 1, and correspond to the cross section AA in Fig. 6 to Fig. 9.

[0030] As shown in Figures 6 and 10A, inactive regions 13a and 13b are formed in the semiconductor layer 10b by implanting ions into the semiconductor layer 10b. The regions in which the inactive regions 13a and 13b are not formed are the active regions 11a to 11c. The inactive region 13a is formed between the active regions 11a and 11b, and the inactive region 13b is formed between the active regions 11a and 11b and the active region 11c.

[0031] As shown in FIG. 6 and FIG. 10B, a source electrode 12a and a drain electrode 16a are formed on the active region 11a. A source electrode 12c and a drain electrode 16c are formed on the active region 11b. A source electrode 12b and drain electrodes 16b and 16d are formed on the active region 11c. The source electrodes 12a to 12c and the drain electrodes 16a and 16c are formed, for example, by vacuum deposition and lift-off. Then, a heat treatment is performed. As a result, the source electrodes 12a to 12c and the drain electrodes 16a to 16d are in ohmic contact with the active regions 11a, 11b, and 11c.

[0032] 7 and 10C, gate electrodes 14a to 14d, gate wiring 18, and gate metal layers 18a and 25a are formed on a substrate 10. The gate electrodes 14a to 14d, gate wiring 18, and gate metal layers 18a and 25a are formed by, for example, vacuum deposition and lift-off.

[0033] 11A, an insulating layer 32a is formed on a substrate 10 so as to cover source electrodes 12a to 12c, drain electrodes 16a and 16c, gate electrodes 14a to 14d, gate wiring 18, and gate metal layers 18a and 25a. The insulating layer 32a is formed by using, for example, a chemical vapor deposition (CVD) method.

[0034] As shown in Figures 8 and 11A, openings are formed in desired regions of insulating layer 32a by etching. Source wiring 22a to 22c and drain wiring 26a and 26c are formed on source electrodes 12a to 12c and drain electrodes 16a and 16c, respectively. Gate wiring 23 is formed on gate metal layer 18a. Gate bus bar 25 and drain bus bar 24 are formed. For example, plating is used to form source wiring 22a to 22c, drain wiring 26a and 26c, gate wiring 23, gate bus bar 25, and drain bus bar 24.

[0035] As shown in FIG. 9 and FIG. 11B, a cover metal layer 30 is formed on the source wirings 22a to 22c. For example, plating is used to form the cover metal layer 30. The space between the source wirings 22a and 22c is covered with the cover metal layer 30. As shown in FIG. 11C, an insulating layer 32 is formed on the substrate 10 so as to cover the source wirings 22a to 22c, the drain wirings 26a and 26c, the gate wiring 23, and the cover metal layer 30. The insulating layer 32 has, for example, an inorganic insulator layer and an organic insulator layer formed on the inorganic insulator layer. The inorganic insulator layer is formed by, for example, a CVD method. The organic insulator layer is formed by applying a solvent containing a resin and performing a heat treatment. An opening (not shown) is formed in the insulating layer 32 to expose the gate bus bar 25 and the drain bus bar 24.

[0036] Thereafter, the lower surface of the substrate 10 is thinned by polishing or grinding, and a via hole 20 is formed penetrating the substrate 10. Metal layers 28 and 28a are formed on the lower surface of the substrate 10 and the inner surface of the via hole 20. In this manner, the semiconductor device of Example 1 is manufactured.

[0037] [Comparative Example 1] 12 is a cross-sectional view of a semiconductor device according to Comparative Example 1. As shown in Fig. 12, a semiconductor device 110 of Comparative Example 1 does not include a cover metal layer 30. The other configurations are the same as those of Example 1.

[0038] The gate wirings 23 and 18 electrically connect the gate electrodes 14b and 14d to the gate bus bar 25. This allows the gate resistance of the unit FETs 35b and 35d to be low. However, as indicated by the solid arrow 50, the gate wiring 23 and the drain wirings 26a and 26c are capacitively coupled by electric field lines passing over the source wirings 22a and 22c. This increases the gate-drain parasitic capacitance. When the gate-drain parasitic capacitance increases, the gain decreases. Also, the K-factor, which is a stability coefficient, decreases. In this way, the high-frequency characteristics of the semiconductor device 110 deteriorate.

[0039] [Description of Example 1] As shown in FIG. 3, according to the first embodiment, a cover metal layer 30 is provided on the source wirings 22a and 22c, covering the entire area between the source wirings 22a and 22c. As a result, as shown by the dashed arrow 52, ​​the cover metal layer 30 shields the electric field lines between the gate wiring 23 and the drain wirings 26a and 26c. As a result, the capacitive coupling between the gate wiring 23 and the drain wirings 26a and 26c is suppressed. Therefore, the gate-drain parasitic capacitance can be suppressed, and the deterioration of the high-frequency characteristics of the semiconductor device 100 can be suppressed. Note that in the first embodiment, the gate-source parasitic capacitance and the drain-source parasitic capacitance increase. However, the gate-source capacitance and the drain-source capacitance are larger than the gate-drain capacitance. Therefore, the influence of the gate-source parasitic capacitance and the drain-source parasitic capacitance is small.

[0040] 4, in the inactive region 13a, the cover metal layer 30 is provided on the gate wiring 18 with an insulating layer 32a sandwiched therebetween. As a result, as indicated by dashed arrow 51, the cover metal layer 30 shields the electric field lines between part of the gate wiring 18 and the gate wiring 23 and the drain wirings 26a and 26c, suppressing capacitive coupling. This makes it possible to suppress the gate-drain parasitic capacitance and to suppress deterioration of the high-frequency characteristics of the semiconductor device 100.

[0041] [Modification 1 of Example 1] Fig. 13 is an enlarged plan view of a semiconductor device according to Modification 1 of Example 1. Fig. 14 and Fig. 15 are AA and BB cross-sectional views of Fig. 13, respectively. As shown in Fig. 13 to Fig. 15, in a semiconductor device 102 according to Modification 1 of Example 1, portions 34a where metal layer 30b is provided and portions 34b where metal layer 30b is not provided are alternately provided in the Y direction. The other configurations are the same as those of Example 1, and description thereof will be omitted.

[0042] 14, in the portion 34a where the metal layer 30b is provided, the metal layer 30b shields the electric field lines between the gate wiring 23 and the drain wirings 26a and 26c as indicated by the dashed arrow 52, ​​suppressing the capacitive coupling. This suppresses the gate-drain parasitic capacitance. However, the gate-source parasitic capacitance between the gate wiring 23 and the metal layer 30b increases.

[0043] 15, in a portion 34b where the metal layer 30b is not provided, the metal layers 30a and 30c shield part of the electric field lines between the gate wiring 23 and the drain wirings 26a and 26c, as indicated by the dashed arrow 53a. As indicated by the solid arrow 53b, part of the electric field lines between the gate wiring 23 and the drain wirings 26a and 26c are not shielded. As a result, the gate-drain parasitic capacitance increases more than in the first embodiment. However, in the portion 34b, the metal layer 30b does not cover the upper side of the gate wiring 23, so the gate-source parasitic capacitance decreases. As a result, the gate-source parasitic capacitance can be suppressed more than in the first embodiment.

[0044] The number of the portions 34a and 34b and the widths W1 and W2 of the portions 34a and 34b in the Y direction can be appropriately set depending on whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is to be emphasized. When the suppression of the gate-drain parasitic capacitance is to be emphasized, the sum of the widths W1 of the portions 34a in the Y direction can be set to 0.5 times or more, and 0.7 times or more, of the gate width Wg of the unit FETs 35a and 35c in the Y direction (the width of the active regions 11a and 11b in the Y direction). When the suppression of the gate-source parasitic capacitance is to be emphasized, the sum of the widths W1 can be set to 0.5 times or less, and 0.3 times or less, of the gate width Wg. The widths W1 and W2 are, for example, 1 μm or more and 100 μm or less.

[0045] In Example 1, when the insulating layer 32 is provided in FIG. 11C, the resin-containing solvent does not flow under the metal layer 30b, and voids may be formed. In Modification 1 of Example 1, the metal layer 30b is not provided at the location 34b. Therefore, the resin-containing solvent flows under the metal layer 30b at the location 34a. Therefore, it is possible to suppress the formation of voids in the insulating layer 32.

[0046] [Modification 2 of Example 1] FIG. 16 is an enlarged plan view of a semiconductor device according to the second modification of the first embodiment. FIG. 17 is an AA cross-sectional view of FIG. 16. As shown in FIG. 16 and FIG. 17, in the semiconductor device 104 according to the second modification of the first embodiment, the cover metal layer 30 has metal layers 30a to 30d. The metal layers 30a and 30c are provided on the source wirings 22a and 22c in contact with each other, respectively. The metal layer 30b protrudes from the metal layer 30a toward the source wiring 22c. The metal layer 30d protrudes from the metal layer 30c toward the source wiring 22a. A gap 38 is provided between the metal layers 30b and 30d. When viewed from the Z direction, the + side of the metal layer 30b in the X direction overlaps with the gate wiring 23, and the - side of the metal layer 30d in the X direction overlaps with the gate wiring 23. The other configurations are the same as those of the first embodiment, and description thereof will be omitted.

[0047] As indicated by dashed arrows 54 in Fig. 17, most of the electric field lines between the gate wiring 23 and the drain wirings 26a and 26c are shielded by the cover metal layer 30. Not many electric field lines pass through the gaps 38. This makes it possible to suppress the gate-drain parasitic capacitance. Meanwhile, part of the region of the cover metal layer 30 closest to the gate wiring 23 forms the gaps 38. This makes it possible to suppress the gate-source parasitic capacitance.

[0048] The width W3 in the X direction of the metal layers 30b and 30d can be set appropriately depending on whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is prioritized. When the suppression of the gate-drain parasitic capacitance is prioritized, each of the widths W3 in the X direction of the metal layers 30b and 30d can be set to 0.25 times or more, and 0.4 times or more, the distance W4 in the X direction between the source wirings 22a and 22c. When the suppression of the gate-source parasitic capacitance is prioritized, each of the widths W3 can be set to 0.4 times or less, and 0.25 times or less, the distance W4.

[0049] The width W5 of the gap 38 in the X direction can be appropriately set depending on whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is prioritized. When the suppression of the gate-drain parasitic capacitance is prioritized, the width W5 can be set to 0.8 times or less, and 0.5 times or less, the width W6 of the gate wiring 23 in the X direction. When the suppression of the gate-source parasitic capacitance is prioritized, the width W5 can be set to 0.5 times or more, and 0.8 times or more, the width W6. When viewed from the Z direction, the + side surface of the metal layer 30b in the X direction does not overlap the gate wiring 23, and the - side surface of the metal layer 30d in the X direction does not have to overlap the gate wiring 23.

[0050] 11C, when insulating layer 32 is provided, the resin-containing solvent passes through gap 38 and flows under metal layers 30b and 30d. Thus, formation of voids in insulating layer 32 can be suppressed.

[0051] In the first embodiment and its first and second modifications, the cover metal layer 30 is flat, but the central portion of the cover metal layer 30 in the X direction may be arched and bulged upward.

[0052] [Modification 3 of Example 1] Fig. 18 is an enlarged plan view of a semiconductor device according to Modification 3 of Example 1. Fig. 19 is a cross-sectional view taken along the line AA of Fig. 18. As shown in Figs. 18 and 19, in a semiconductor device 106 according to Modification 3 of Example 1, a cover metal layer 30 has metal layers 30a and 30c. The metal layers 30a and 30c are provided on and in contact with the source wirings 22a and 22c, respectively. The cover metal layer 30 is not provided between the source wirings 22a and 22c. The other configurations are the same as those of Example 1, and a description thereof will be omitted.

[0053] 19, as indicated by dashed arrow 53a, metal layers 30a and 30c shield part of the electric field lines between gate wiring 23 and drain wirings 26a and 26c. As indicated by solid arrow 53b, part of the electric field lines between gate wiring 23 and drain wirings 26a and 26c are not shielded. As a result, the gate-drain parasitic capacitance increases compared to Example 1, and the gate-source parasitic capacitance decreases.

[0054] From the viewpoint of suppressing the gate-drain parasitic capacitance, the height H1 of the upper surfaces of the metal layers 30a and 30c from the upper surface of the substrate 10 can be 1.5 times or more, 2.5 times or more, or 3 times or more than the height H2 of the upper surfaces of the drain wirings 26a and 26c from the upper surface of the substrate 10. From the viewpoint of the manufacturing process, the height H1 can be 10 times or less than the height H2. In the first embodiment and its first and second modifications, the height H1 may be larger than the height H2, and can be 1.5 times or more, 2.5 times or more, or 3 times or more than the height H2.

[0055] According to the first embodiment and its first and second modifications, as shown in Figs. 3, 14 and 17, the metal layers 30a and 30b (first cover metal layers) of the cover metal layer 30 are provided on and in contact with the source wiring 22a, and are electrically connected to the source electrode 12a via the source wiring 22a. The metal layer 30b protrudes from the source electrode 12a toward the gate wiring 23. As a result, the protruding metal layer 30b suppresses the capacitive coupling between the gate wiring 23 and the drain wiring 26a. This makes it possible to suppress the gate-drain parasitic capacitance, and thus to suppress deterioration of the characteristics of the semiconductor device.

[0056] The metal layers 30c and 30d (second cover metal layer) of the cover metal layer 30 are provided on and in contact with the source wiring 22c, and are electrically connected to the source electrode 12c via the source wiring 22c. The metal layer 30d protrudes from the source electrode 12c toward the gate wiring 23. As a result, the protruding metal layer 30d suppresses the capacitive coupling between the gate wiring 23 and the drain wiring 26c. This makes it possible to further suppress the gate-drain parasitic capacitance, and to further suppress deterioration of the characteristics of the semiconductor device. It is sufficient that at least the upper part of the cover metal layer 30 protrudes from the source electrodes 12a and 12c toward the gate wiring 23.

[0057] Furthermore, at least a portion of the cover metal layer 30 overlaps but is not in contact with the gate wiring 23 when viewed from the Z direction (i.e., in a plan view). This makes it possible to further reduce the gate-drain parasitic capacitance and further suppress deterioration of the characteristics of the semiconductor device.

[0058] 3 and 14, the metal layers 30b and 30c are in contact with each other above the gate wiring 23. This can further reduce the gate-drain parasitic capacitance and further suppress deterioration of the characteristics of the semiconductor device.

[0059] 2 and 3 of the first embodiment, the metal layer 30b may be provided in the entire region between the metal layers 30a and 30c when viewed in the Z direction, thereby making it possible to suppress the gate-drain parasitic capacitance and further suppress the deterioration of the characteristics of the semiconductor device.

[0060] 13 of Modification 1 of Example 1, portions 34a where the metal layers 30b and 30c are in contact with each other above the gate wiring 23 and portions 34b where the metal layers 30b and 30c are not provided above the gate wiring 23 are alternately provided along the gate wiring 23 in the Y direction. This allows the gate-drain parasitic capacitance and the gate-source parasitic capacitance to be set to desired values, and deterioration of the characteristics of the semiconductor device can be further suppressed.

[0061] 16 and 17 of the second modification of the first embodiment, the metal layers 30b and 30d do not contact each other above the gate wiring 23. This makes it possible to suppress the gate-source parasitic capacitance, and to further suppress the deterioration of the characteristics of the semiconductor device.

[0062] Furthermore, the ends of the metal layers 30b and 30d in the X direction overlap the gate wiring 23 when viewed in the Z direction. This makes it possible to suppress the gate-drain parasitic capacitance and the gate-source parasitic capacitance, thereby further suppressing deterioration of the characteristics of the semiconductor device.

[0063] 4 of the first embodiment, between the unit FETs 35a and 35b, the gate wiring 18 (connection wiring) extends in the X direction and electrically connects the gate electrode 14b and the gate wiring 23. A part of the cover metal layer 30 overlaps at least a part of the gate wiring 18 when viewed from the Z direction. This suppresses the capacitive coupling between the gate wiring 23 and the drain wiring 26a. This makes it possible to further suppress the gate-drain parasitic capacitance and to further suppress deterioration of the characteristics of the semiconductor device.

[0064] 19 of the third modification of the first embodiment, the height H2 of the drain wiring 26a from the substrate 10 is smaller than the heights of the source wiring 22a and the metal layer 30a from the substrate 10. This makes it possible to suppress the gate-drain parasitic capacitance and the gate-source parasitic capacitance, and thus to suppress deterioration of the characteristics of the semiconductor device.

[0065] A height H2 of the drain wiring 26c from the substrate 10 is smaller than a height H1 of the source wiring 22c and the metal layer 30c from the substrate 10. This makes it possible to further reduce the gate-drain parasitic capacitance and the gate-source parasitic capacitance, thereby further suppressing deterioration of the characteristics of the semiconductor device.

[0066] In the first embodiment and its modified example, the cover metal layer 30 is provided on the source wiring 22b, but the cover metal layer 30 does not have to be provided on the source wiring 22b. In addition, as shown in Fig. 8 and Fig. 9, the source wirings 22a and 22c and the cover metal layer 30 are formed in separate steps, but the source wirings 22a and 22c and the cover metal layer 30 may be formed integrally at the same time.

[0067] [Example 2] FIG. 20 is a plan view of a semiconductor device according to a second embodiment. As shown in FIG. 20, in a semiconductor device 108 of the second embodiment, FET groups 36c and 36d are provided between FET groups 36a and 36b. Source wirings 22a and 22c are electrically connected to the source electrodes of the FET groups 36a, 36c, and 36d. Drain wirings 26a and 26c are electrically connected to the drain electrodes of the FET groups 36a to 36d. Gate wirings 18 and 23 are electrically connected to the gate electrodes 14 of the FET groups 36b to 36d. A cover metal layer 30 is provided in the region between the source wirings 22a and 22c of the FET groups 36a, 36c, and 36d. The other configurations are the same as those of the first embodiment, and description thereof will be omitted.

[0068] As in Example 2, the number of FET groups arranged in the Y direction may be four. In Example 1 and its modified examples, the number of FET groups arranged in the Y direction can be set as appropriate. In Examples 1 and 2 and their modified examples, an example in which there are four unit FETs 35 in the X direction has been described, but the number of unit FETs 35 in the X direction may be any of one to three, or five or more, and can be set as appropriate.

[0069] [Measurement results] GaN HEMTs having the structures of Comparative Example 1 and Modification 1 of Example 1 were fabricated, and their high-frequency characteristics were measured. A high-frequency signal is input to the gate bus bar 25, and an amplified high-frequency signal is output from the drain bus bar 24. FIG. 21 is a diagram showing the K-factor versus frequency in the semiconductor devices A and B. FIG. 22 is a diagram showing |S12| versus frequency in the semiconductor devices A and B. The horizontal axis of FIG. 21 is frequency, and the vertical axis is K-factor, which is a stability coefficient. The smaller the K-factor, the less likely it is to oscillate, and the more stable it is. The horizontal axis of FIG. 22 is frequency, and the vertical axis is |S12|. S12 is the absolute value of the S parameter S12 when the gate is port 1 and the drain is port 2. |S12| represents the power fed back from the drain to the gate. The semiconductor device A corresponds to Modification 1 of Example 1, and the semiconductor device B corresponds to Comparative Example 1.

[0070] As shown in Figures 21 and 22, as the frequency increases, both the K-factor and |S12| increase. Compared to Semiconductor Device B, Semiconductor Device A has a smaller K-factor and |S12|. The gate-drain capacitance is a feedback capacitance, and as the gate-drain capacitance increases, both the K-factor and |S12| increase. Compared to Semiconductor Device B, Semiconductor Device A can reduce the gate-drain capacitance, thereby suppressing the K-factor and |S12|.

[0071] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0072] 10, 10a Board 10b Semiconductor layer 11a, 11b, 11c active area 12, 12a, 12b, 12c Source electrode 13a, 13b Inactive area 14, 14a, 14b, 14c, 14d Gate electrode 16a, 16b, 16c, 16d Drain electrodes 18, 23 Gate wiring 18a, 25a Gate metal layer 20 Beer Hall 22, 22a, 22b, 22c Source wiring 24 Drain busbar 25 Gate bus bar 26a, 26c, 26c Drain wiring 28, 28a, 30a, 30b, 30c, 30d metal layer 30 Cover metal layer 32, 32a Insulating layer 34a, 34b 35, 35a, 35b, 35c, 35d Unit FET (Transistor Unit) 36a, 36b, 36c, 36d FETs 38 Gap 50, 53b solid arrow 51, 52, 53a dashed arrow 100, 102, 104, 106, 108, 110 Semiconductor device

Claims

1. A substrate; a first transistor unit including a first drain electrode, a first gate electrode, and a first source electrode provided in that order on the substrate; a second transistor unit, which is provided in a line along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, in that order on the substrate, and which is located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; a gate wiring provided on the substrate between the first source electrode and the second source electrode and adjacent to the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer provided on and electrically connected to the first source electrode, at least an upper portion of which protrudes from the first source electrode toward the gate wiring; a second cover metal layer provided on and electrically connected to the second source electrode, at least an upper portion of which protrudes from the second source electrode toward the gate wiring; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein at least a portion of the first cover metal layer and at least a portion of the second cover metal layer overlap the gate wiring in a non-contact manner in a plan view.

3. 3. The semiconductor device according to claim 1, wherein the first cover metal layer and the second cover metal layer are in contact with each other above the gate wiring.

4. 4. The semiconductor device according to claim 3, wherein locations where the first cover metal layer and the second cover metal layer are in contact above the gate wiring and locations where the first cover metal layer and the second cover metal layer are not provided above the gate wiring are alternately provided along the gate wiring.

5. 3. The semiconductor device according to claim 1, wherein the first cover metal layer and the second cover metal layer are not in contact with each other above the gate wiring.

6. an end of the first cover metal layer overlaps with the gate line in a plan view; The semiconductor device according to claim 5 , wherein an end of the second cover metal layer overlaps with the gate wiring in a plan view.

7. 3. The semiconductor device according to claim 1, further comprising a third transistor unit, the third transistor unit being located on a side to which the first gate electrode extends, the third drain electrode being electrically connected to the first drain electrode, the third gate electrode being electrically connected to the gate wiring, and the third source electrode being electrically connected to the first source electrode, the third gate electrode being electrically connected to the gate wiring, and the third source electrode being electrically connected to the first source electrode, the third transistor unit being located on the side to which the first gate electrode extends relative to the first transistor unit.

8. a connection wiring electrically connecting the third gate electrode and the gate wiring between the first transistor unit and the third transistor unit, The semiconductor device according to claim 7 , wherein a portion of the first cover metal layer overlaps at least a portion of the connection wiring in a plan view.

9. a first drain wiring provided on and in electrical contact with the first drain electrode, the first drain wiring having a height from the substrate to an upper surface thereof smaller than a height from the substrate to an upper surface of the first cover metal layer; a second drain wiring provided on and in electrical contact with the second drain electrode, the second drain wiring having a height from the substrate to an upper surface thereof smaller than a height from the substrate to an upper surface of the second cover metal layer; The semiconductor device according to claim 1 , further comprising:

10. A substrate; a first transistor unit including a first drain electrode, a first gate electrode, and a first source electrode provided in that order on the substrate; a second transistor unit, which is provided in a line along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, in that order on the substrate, and which is located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; a gate wiring provided on the substrate between the first source electrode and the second source electrode and adjacent to the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first source wiring provided on and in electrical contact with the first source electrode; a second source wiring provided on and in electrical contact with the second source electrode; a first drain wiring provided on and in electrical contact with the first drain electrode, the first drain wiring having an upper surface having a height from the substrate that is smaller than a height from the substrate of an upper surface of the first source wiring; a second drain wiring provided on and in electrical contact with the second drain electrode, the second drain wiring having an upper surface having a height from the substrate that is smaller than a height from the substrate of an upper surface of the second source wiring; A semiconductor device comprising:

11. 11. The semiconductor device according to claim 10, further comprising a third transistor unit, in which a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode are provided in that order on the substrate, and the third transistor unit is located on a side to which the first gate electrode extends relative to the first transistor unit.

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