Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device with less degradation of characteristics.SOLUTION: A semiconductor device 102 includes a substrate 10, a unit FET 35a in which a first drain electrode 16a, a first gate electrode 14a, and a first source electrode 12c are provided on the substrate in this order, a unit FET 35c provided along and side by side with the first source electrode in which a second source electrode 12c electrically connected to the first source electrode and a second gate electrode 14c electrically connected to the first gate electrode are provided on the substrate in this order, a gate line 18a electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer 30a provided adjacent to the first source electrode and the gate line between the first source electrode and the gate line in an upper part of the substrate and electrically connected to the first source electrode, and a second metal cover layer 30c provided adjacent to the second source electrode and the gate line between the second source electrode and the gate line in the upper part of the substrate and electrically connected to the second source electrode.SELECTED DRAWING: Figure 17

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a field effect transistor (FET) having finger-shaped source, gate and drain electrodes, it is known to arrange a plurality of unit FETs each having a source, gate and drain electrode in the extension direction of the electrodes (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-299351 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the width of the gate electrode in each unit FET can be shortened by arranging multiple unit FETs in the direction in which the electrodes extend. This makes it possible to suppress the gate resistance. However, the parasitic capacitance between the drain electrode and the gate wiring that electrically connects the gate pad and the gate electrode that is distant from the gate pad increases, degrading the characteristics.

[0005] The present disclosure has been made in consideration of the above problems, and aims to suppress deterioration of characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in this order on the substrate; a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, which are provided in this order on the substrate, and the second transistor unit is positioned on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; a gate wiring provided on the substrate between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer provided above the substrate between the first source electrode and the gate wiring adjacent to the first source electrode and the gate wiring, and electrically connected to the first source electrode; and a second cover metal layer provided above the substrate between the second source electrode and the gate wiring adjacent to the second source electrode and the gate wiring, and electrically connected to the second source electrode.

[0007] One embodiment of the present disclosure includes a step of forming, on a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in this order, a second transistor unit having a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, in this order, the second transistor unit being located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; and forming, on the substrate, a gate wiring electrically connected to the second gate electrode and the first source electrode; and simultaneously forming: a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, the first cover metal layer being electrically connected to the first source electrode, a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, the second cover metal layer being electrically connected to the second source electrode, and a field plate provided above the substrate between the first gate electrode and the first drain electrode. Effect of the Invention

[0008] According to the present disclosure, deterioration of characteristics can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged view of a region E in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line AA in FIGS. [Figure 4] FIG. 4 is a cross-sectional view taken along line BB in FIGS. [Diagram 5]FIG. 5 is a cross-sectional view taken along line CC in FIGS. [Figure 6] FIG. 6 is a cross-sectional view taken along line DD in FIG. [Figure 7] FIG. 7 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11A] FIG. 11A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11B] FIG. 11B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12A] FIG. 12A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12B] FIG. 12B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13A] FIG. 13A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13B] FIG. 13B is a cross-sectional view illustrating the method for manufacturing the semiconductor device in accordance with the first embodiment. [Figure 14A] FIG. 14A is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14B] FIG. 14B is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device according to a first comparative example. [Figure 16] FIG. 16 is an enlarged plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 17] FIG. 17 is a cross-sectional view taken along line AA in FIG. [Figure 18] FIG. 18 is an enlarged plan view of a semiconductor device according to a second modification of the first embodiment. [Figure 19] FIG. 19 is a cross-sectional view taken along line AA in FIG. [Figure 20] FIG. 20 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 21] FIG. 21 is a diagram showing the K-factor versus frequency in semiconductor devices A and B. [Figure 22] FIG. 22 is a diagram showing |S12| versus frequency in semiconductor devices A and B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in this order on the substrate; a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, which are provided in this order on the substrate, the second transistor unit being positioned on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; a gate wiring provided on the substrate between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, the first cover metal layer being electrically connected to the first source electrode; and a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, the second cover metal layer being electrically connected to the second source electrode. This makes it possible to suppress the gate-drain parasitic capacitance and thus to prevent deterioration of characteristics. (2) In the above (1), at least a part of the first cover metal layer and at least a part of the second cover metal layer may overlap the gate wiring in a non-contact manner in a plan view, thereby making it possible to further suppress gate-drain parasitic capacitance and deterioration of characteristics. (3) In the above (1) or (2), the first cover metal layer and the second cover metal layer may be in contact with each other above the gate wiring, thereby making it possible to further reduce gate-drain parasitic capacitance and to further prevent deterioration of characteristics. (4) In the above (1) or (2), the first cover metal layer and the second cover metal layer may not be in contact with each other above the gate wiring. This can reduce gate-source parasitic capacitance and further suppress deterioration of characteristics. (5) In the above (4), an edge of the first cover metal layer may overlap the gate wiring in a plan view, and an edge of the second cover metal layer may overlap the gate wiring in a plan view, thereby suppressing gate-drain parasitic capacitance and gate-source parasitic capacitance, and further suppressing deterioration of characteristics. (6) In any one of the above (1) to (5), the height of the upper surface of the first cover metal layer from the substrate may be greater than the height of the upper surface of the gate wiring from the substrate, and the height of the lower surface of the first cover metal layer located outside the gate wiring from the substrate may be smaller than the height of the upper surface of the gate wiring from the substrate. This makes it possible to further suppress gate-drain parasitic capacitance and to further suppress deterioration of characteristics. (7) In any one of (1) to (6) above, a source wiring may be provided on the first source electrode in electrical contact therewith, and the height of the upper surface of the first cover metal layer from the substrate may be smaller than the height of the upper surface of the source wiring from the substrate, thereby suppressing gate-drain parasitic capacitance and gate-source parasitic capacitance and further suppressing deterioration of characteristics. (8) In any one of the above (1) to (7), a field plate may be provided above the substrate between the first gate electrode and the first drain electrode, and made of the same material as the first cover metal layer, thereby eliminating the manufacturing step of forming the cover metal layer. (9) In any one of the above (1) to (8), a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode may be provided in this order on the substrate, and a third transistor unit may be provided on a side to which the first gate electrode extends with respect to the first transistor unit. This can further reduce gate-drain parasitic capacitance and further suppress deterioration of characteristics. (10) One embodiment of the present disclosure includes a step of forming, on a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in this order, a second transistor unit having a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, in this order, the second transistor unit being located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; and forming, on the substrate, a gate wiring electrically connected to the first source electrode and the second gate electrode, and simultaneously forming a first cover metal layer disposed above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, the first cover metal layer being electrically connected to the first source electrode, a second cover metal layer disposed above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, the second cover metal layer being electrically connected to the second source electrode, and a field plate disposed above the substrate between the first gate electrode and the first drain electrode. This makes it possible to suppress deterioration of characteristics and eliminate the manufacturing step of forming a cover metal layer.

[0011] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] A semiconductor device used in an amplifier for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a base station for mobile communication will be described as an example. FIG. 1 is a plan view of the semiconductor device in Example 1. FIG. 2 is an enlarged view of range E in FIG. 1, and FIG. 3 to FIG. 6 are AA, BB, CC, and DD cross-sectional views in FIG. 1 or FIG. 2, respectively. The thickness direction of the substrate 10 is the Z direction, the extension direction of each finger-shaped electrode is the Y direction (first direction), and the arrangement direction of each electrode is the X direction (second direction intersecting the first direction). In FIG. 1, field plates 15a and 15c are omitted for simplification.

[0013] In each figure, the source electrode 12, the gate electrode 14, the source wiring 22, and the unit FET 35 indicate general elements, and the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the source wirings 22a to 22c, and the unit FETs 35a to 35d indicate specific elements included in the general elements. In the following, the unit FETs 35a to 35d will be mainly described using the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the drain electrodes 16a, 16b, the source wirings 22a to 22c, and the drain wirings 26a and 26c.

[0014] 1 to 6, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In an XY plane parallel to the X and Y directions, regions of the semiconductor layer 10b that have been inactivated by ion implantation or the like are inactive regions 13a and 13b, and regions that have not been inactivated are active regions 11a to 11c.

[0015] The active regions 11a and 11b are arranged in the X direction. The active region 11c is provided in a region in the +Y direction from the active regions 11a and 11b. The region between the active regions 11a and 11b is an inactive region 13a. The region between the active regions 11a and 11c is an inactive region 13b. An FET group 36a including a plurality of unit FETs 35a and 35c arranged in the X direction is provided on the active regions 11a and 11b. An FET group 36b including a plurality of unit FETs 35b and 35d arranged in the X direction is provided in the active region 11c. The FET group 36a is sandwiched between the gate bus bar 25 and the FET group 36b. The FET group 36b is sandwiched between the drain bus bar 24 and the FET group 36a.

[0016] The unit FET 35a (first transistor unit) has a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode) that extend in the Y direction and are provided on the substrate 10. The drain electrode 16a, the gate electrode 14a, and the source electrode 12a are provided in this order. The unit FET 35c (second transistor unit) is located on the side of the unit EET 35a where the drain electrode 16a, the gate electrode 14a, and the source electrode 12a are arranged. The unit FET 35c has a source electrode 12c (second source electrode), a gate electrode 14c (second gate electrode), and a drain electrode 16c (second drain electrode) that extend in the Y direction and are provided on the substrate 10. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are provided in this order. The source electrode 12c is provided in line with the source electrode 12a, and is electrically connected to the source electrode 12a via the source electrode 12b. The gate electrode 14c is electrically connected to the gate electrode 14a via a gate bus bar 25. The drain electrode 16c is electrically connected to the drain electrode 16a via a drain bus bar .

[0017] Between the gate electrode 14a and the drain electrode 16a, and between the gate electrode 14b and the drain electrode 16b, the field plate 15a is provided on the substrate 10 with the insulating layer 32a sandwiched therebetween. Between the gate electrode 14c and the drain electrode 16c, and between the gate electrode 14d and the drain electrode 16d, the field plate 15c is provided on the substrate 10 with the insulating layer 32a sandwiched therebetween. At least a part of the field plate 15a may overlap the gate electrodes 14a and 14b when viewed from the Z direction, or may not overlap them. At least a part of the field plate 15c may overlap the gate electrodes 14c and 14d when viewed from the Z direction, or may not overlap them. The field plates 15a and 15c are electrically connected to the source wirings 22a and 22c, respectively, via the wiring 17, and are short-circuited. The field plates 15a and 15c are provided to improve the drain breakdown voltage and suppress the gate-drain parasitic capacitance. The field plates 15a and 15c may not be provided.

[0018] A gate wiring 18a extending in the Y direction is provided on a region of the substrate 10 located in the +X direction of the unit FET 35a. The gate wiring 18a is provided on an inactive region 13a between the unit FETs 35a and 35c. That is, in the unit FET 35a, the source electrode 12a is closer to the gate wiring 18a than the drain electrode 16a. In the unit FET 35c, the source electrode 12c is closer to the gate wiring 18a than the drain electrode 16c.

[0019] The unit FETs 35b (third transistor unit) and 35d are provided in regions on the substrate 10 located on the side where the gate electrode 14a extends with respect to the unit FETs 35a and 35c. The unit FET 35b has a source electrode 12b (third source electrode), a gate electrode 14b (third gate electrode), and a drain electrode 16b (third drain electrode) each extending in the Y direction and provided on the substrate 10. The drain electrode 16b, the gate electrode 14b, and the source electrode 12b are provided in this order. The drain electrode 16b is electrically connected to the drain electrode 16a. The gate electrode 14b is electrically connected to the gate wiring 23. The unit FET 35d has a source electrode 12b, a gate electrode 14d, and a drain electrode 16d each extending in the Y direction and provided on the substrate 10. The unit FETs 35b and 35d share the source electrode 12b. When viewed from the Y direction, the source electrodes 12a, 12c and the gate wiring 18a are provided so as to overlap the source electrode 12b and to be within the range in which the source electrode 12b is provided.

[0020] Gate wiring 18b extending in the X direction is provided on inactive region 13b. Gate wiring 18b electrically connects gate wiring 18a to gate electrodes 14b and 14d, and shorts them. Gate wiring 18a and gate electrodes 14a and 14c are connected to gate bus bar 25.

[0021] The cover metal layer 30 is provided to cover the gate wiring 18a with the insulating layer 32a sandwiched therebetween. The width of the cover metal layer 30 in the X direction is larger than the width of the gate wiring 18a in the X direction. As shown in FIG. 5, the cover metal layer 30 is sandwiched between the source electrode 12b and the source wiring 22b, and is thereby electrically connected to and short-circuited with the source electrode 12b and the source wiring 22b. The cover metal layer 30 may be connected to the source wiring 22a and the source wiring 22c. In this way, the cover metal layer 30 is connected to the source wirings 22a to 22c at one or more points.

[0022] The source wirings 22a (first source wiring), 22b, and 22c (second source wiring) are provided on and in contact with the source electrodes 12a, 12b, and 12c, respectively. The source wirings 22a and 22c cross the gate wiring 18 without contacting each other with the insulating layer 32a sandwiched therebetween, and are connected to the source electrode 12b. The drain wiring 26a (first drain wiring) is provided on and in contact with the drain electrodes 16a and 16b, and electrically connects the drain electrodes 16a and 16b to the drain bus bar 24. The drain wiring 26c (second drain wiring) is provided on and in contact with the drain electrodes 16c and 16d, and electrically connects the drain electrodes 16c and 16d to the drain bus bar 24.

[0023] The via hole 20 penetrates the substrate 10 and is connected to the source electrode 12b. A metal layer 28 is provided on the lower surface of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20. As a result, the metal layer 28 is electrically connected to the source electrode 12b through the via hole 20, and is short-circuited.

[0024] A source potential (e.g., a reference potential such as a ground potential) is supplied from the metal layer 28 to the source electrode 12b via the metal layer 28a in the via hole 20. Furthermore, the source potential is supplied to the source electrodes 12a to 12c, the field plates 15a, 15c, and the cover metal layer 30 via the source wirings 22a to 22c. A gate potential (e.g., a high-frequency signal and a gate bias voltage) is supplied from the gate bus bar 25 to the gate electrodes 14a and 14c. Furthermore, the gate potential is supplied from the gate bus bar 25 to the gate electrodes 14b and 14d via the gate wirings 18a and 18b. A drain bias voltage is supplied from the drain bus bar 24 to the drain electrodes 16a to 16d via the drain wirings 26a and 26c. The high-frequency signals amplified in the unit FETs 35a to 35d are output to the drain bus bar 24 from the drain wirings 26a and 26c.

[0025] In the unit FETs 35a and 35c, the high frequency signal is input from the negative ends in the Y direction of the gate electrodes 14a and 14c. In the unit FETs 35b and 35d, the high frequency signal is input from the negative ends in the Y direction of the gate electrodes 14b and 14d. When the high frequency signal is input to the gate electrodes 14a and 14c from both the positive and negative ends in the Y direction of the gate electrodes 14a and 14c, the high frequency characteristics of the unit FETs 35a and 35c deteriorate due to a phase difference or the like. In the first embodiment, the positive ends in the Y direction of the gate electrodes 14a and 14c are not connected to the negative ends in the Y direction of the gate electrodes 14b and 14d, so that deterioration of the high frequency characteristics of the unit FETs 35a and 35c can be suppressed.

[0026] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the unit FETs 35a to 35d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes an arsenide semiconductor layer, such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer, etc. The semiconductor device 100 may be a silicon semiconductor device, such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS).

[0027] The source electrodes 12a to 12c and the drain electrodes 16a to 16d are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d and the gate wirings 18a and 18b are metal films, for example, nickel films and gold films from the substrate 10 side. The field plates 15a, 15c and the cover metal layer 30 are, for example, titanium films or nickel films, and gold films or aluminum films from the insulating layer 32a side. The source wirings 22a to 22c, the drain wirings 26a, 26c and the cover metal layer 30 are, for example, gold layers, copper layers or aluminum layers. The insulating layers 32a and 32b are inorganic insulator layers, for example, silicon nitride layers. The insulating layer 32 is, for example, an organic insulator layer, for example, a polyimide layer or a BCB (Benzocyclobutene) layer.

[0028] The width of the source electrodes 12a and 12c in the X direction is, for example, 5 μm to 20 μm. The width of the source electrode 12b in the X direction is, for example, 50 μm to 150 μm. The gate lengths of the gate electrodes 14a to 14d in the X direction are, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a and 16c in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 18a in the X direction is, for example, 5 μm to 20 μm. The width of the gate wiring 18b in the Y direction is, for example, 3 μm to 20 μm. The width of the field plates 15a and 15c in the X direction is, for example, 1 μm to 10 μm. The width of the cover metal layer 30 in the X direction is, for example, 7 μm to 25 μm. The gate width of the unit FETs 35a to 35d in the Y direction is, for example, 100 μm to 400 μm. The width of the via hole 20 in the X direction is, for example, 10 μm to 60 μm.

[0029] The widths in the X direction of the source wirings 22a to 22c and the drain wirings 26a and 26c are the same as or slightly smaller than the widths in the X direction of the source electrodes 12a to 12c and the drain electrodes 16a and 16c, respectively. The thicknesses of the source wirings 22a to 22c and the drain wirings 26a and 26c are, for example, 1 μm to 20 μm. The thicknesses of the field plates 15a, 15c and the cover metal layer 30 are, for example, 0.5 μm to 1 μm.

[0030] [Production method of Example 1] 7 to 10 are plan views showing the method for manufacturing the semiconductor device according to the embodiment 1. Fig. 11A to Fig. 14B are cross-sectional views showing the method for manufacturing the semiconductor device according to the embodiment 1, and correspond to the cross section AA in Fig. 7 to Fig. 10.

[0031] 7 and 11A, ions are implanted into the semiconductor layer 10b to form inactive regions 13a and 13b in the semiconductor layer 10b. The regions in which the inactive regions 13a and 13b are not formed are the active regions 11a to 11c. The inactive region 13a is formed between the active regions 11a and 11b, and the inactive region 13b is formed between the active regions 11a and 11b and the active region 11c.

[0032] As shown in FIG. 7 and FIG. 11B, a source electrode 12a and a drain electrode 16a are formed on the active region 11a. A source electrode 12c and a drain electrode 16c are formed on the active region 11b. A source electrode 12b and drain electrodes 16b and 16d are formed on the active region 11c. The source electrodes 12a to 12c and the drain electrodes 16a and 16c are formed, for example, by vacuum deposition and lift-off. Then, a heat treatment is performed. As a result, the source electrodes 12a to 12c and the drain electrodes 16a and 16c are in ohmic contact with the active regions 11a, 11b, and 11c.

[0033] 8 and 12A, gate electrodes 14a to 14d, gate wirings 18a and 18b, and gate metal layer 25a are formed on substrate 10. The gate electrodes 14a to 14d, gate wirings 18a and 18b, and gate metal layer 25a are formed by, for example, vacuum deposition and lift-off.

[0034] 12B, an insulating layer 32a is formed on the substrate 10 so as to cover the source electrodes 12a to 12c, the drain electrodes 16a and 16c, the gate electrodes 14a to 14d, the gate wirings 18a and 18b, and the gate metal layer 25a. The insulating layer 32a is formed by using, for example, a chemical vapor deposition (CVD) method.

[0035] 9 and 13A, field plates 15a, 15c and cover metal layer 30 are formed on insulating layer 32a. Vacuum deposition and lift-off are used, for example, to form field plates 15a, 15c and cover metal layer 30. The + end in the Y direction of cover metal layer 30 contacts source electrode 12b.

[0036] As shown in Figures 10 and 13B, openings are formed in desired regions of insulating layer 32a by etching. Source wiring 22a to 22c and drain wiring 26a and 26c are formed on source electrodes 12a to 12c and drain electrodes 16a and 16c, respectively, so as to be in contact with them. Gate bus bar 25 and drain bus bar 24 are formed. The source wiring 22a to 22c, gate bus bar 25, and drain bus bar 24 are formed by, for example, plating.

[0037] 14A, an insulating layer 32b is formed so as to cover field plates 15a, 15c, source wirings 22a to 22c, drain wirings 26a, 26c, and cover metal layer 30. Insulating layer 32b is formed by, for example, a CVD method.

[0038] 14B, an insulating layer 32 is formed on insulating layer 32b. Insulating layer 32 is formed by applying a solvent containing resin and performing a heat treatment. Openings (not shown) that expose gate bus bar 25 and drain bus bar 24 are formed in insulating layers 32 and 32b.

[0039] Thereafter, the lower surface of the substrate 10 is thinned by polishing or grinding, and a via hole 20 is formed penetrating the substrate 10. Metal layers 28 and 28a are formed on the lower surface of the substrate 10 and the inner surface of the via hole 20. In this manner, the semiconductor device of Example 1 is manufactured.

[0040] [Comparative Example 1] 15 is a cross-sectional view of a semiconductor device according to Comparative Example 1. As shown in Fig. 15, a semiconductor device 110 of Comparative Example 1 does not include a cover metal layer 30. The other configurations are the same as those of Example 1.

[0041] The gate wiring 18a electrically connects the gate electrodes 14b and 14d (see FIG. 2) to the gate bus bar 25. This makes it possible to reduce the gate resistance of the unit FETs 35b and 35d (see FIG. 2). However, as indicated by the solid arrow 50, the gate wiring 18a and the drain wirings 26a and 26c are capacitively coupled by electric field lines passing over the source wirings 22a and 22c. This increases the gate-drain parasitic capacitance. When the gate-drain parasitic capacitance increases, the gain decreases. Also, the K-factor, which is a stability coefficient, decreases. In this way, the high-frequency characteristics of the semiconductor device 110 deteriorate.

[0042] [Description of Example 1] As shown in FIG. 3, according to the first embodiment, the cover metal layer 30 is provided above the gate wiring 18a. As a result, as shown by the dashed arrow 52, ​​the cover metal layer 30 shields the electric field lines between the gate wiring 18a and the drain wirings 26a and 26c. As a result, the capacitive coupling between the gate wiring 18a and the drain wirings 26a and 26c is suppressed. Therefore, the gate-drain parasitic capacitance can be suppressed, and the deterioration of the high-frequency characteristics of the semiconductor device 100 can be suppressed. Note that in the first embodiment, the gate-source parasitic capacitance and the drain-source parasitic capacitance increase. However, the gate-source capacitance and the drain-source capacitance are larger than the gate-drain capacitance. Therefore, the influence of the gate-source parasitic capacitance and the drain-source parasitic capacitance is small.

[0043] Both ends of the cover metal layer 30 in the X direction are located outside the gate wiring 18a in the X direction when viewed from the Z direction. The height H1 of the lower surface of the end of the cover metal layer 30 in the X direction from the substrate 10 is smaller than the height H3 of the upper surface of the gate wiring 18a from the substrate 10. This allows the cover metal layer 30 to better shield the electric field lines between the gate wiring 18a and the drain wirings 26a and 26c, and to better suppress capacitive coupling. From the viewpoint of the shielding effect, the height H1 can be 3 / 4 or less, or 1 / 2 or less, of the height H3. From the viewpoint of suppressing contact between the cover metal layer 30 and the substrate 10, the height H1 is 1 / 10 or more of the height H3.

[0044] The height H2 of the upper surface of the cover metal layer 30 from the substrate 10 is smaller than the height H4 of the upper surfaces of the source wirings 22a and 22c from the substrate 10. This allows the source wirings 22a and 22c to also shield the electric field lines between the gate wiring 18a and the drain wirings 26a and 26c, suppressing capacitive coupling. From the viewpoint of the shielding effect, the height H2 can be set to 3 / 4 or less, or 1 / 2 or less, of the height H4. The height H2 is 1 / 10 or more of the height H4.

[0045] 4, in the inactive region 13b, the cover metal layer 30 is provided on the center of the gate wiring 18b in the X direction with the insulating layer 32a sandwiched therebetween. As a result, as indicated by the dashed arrow 51, the cover metal layer 30 shields the electric field lines between a part of the gate wiring 18b and the drain wirings 26a and 26c, suppressing capacitive coupling. This makes it possible to suppress parasitic capacitance between the gate and the drain, and to suppress deterioration of the high-frequency characteristics of the semiconductor device 100.

[0046] [Modification 1 of Example 1] FIG. 16 is an enlarged plan view of a semiconductor device according to Modification 1 of Example 1. FIG. 17 is an AA cross-sectional view of FIG. 16. As shown in FIGS. 16 and 17, in a semiconductor device 102 according to Modification 1 of Example 1, a cover metal layer 30 has cover metal layers 30a and 30c. A gap 38 is provided between the cover metal layers 30a and 30c. When viewed from the Z direction, the + side surface of the cover metal layer 30a in the X direction overlaps with the gate wiring 18a, and the - side surface of the cover metal layer 30c in the X direction overlaps with the gate wiring 18a. The other configurations are the same as those of Example 1, and description thereof will be omitted.

[0047] As indicated by the dashed arrow 54 in Fig. 17, most of the electric field lines between the gate wiring 18a and the drain wirings 26a and 26c are shielded by the cover metal layer 30. Not many electric field lines pass through the gaps 38. This makes it possible to suppress the gate-drain parasitic capacitance. Meanwhile, part of the region of the cover metal layer 30 closest to the gate wiring 18a forms the gaps 38. This makes it possible to suppress the gate-source parasitic capacitance.

[0048] The width W1 of the gap 38 in the X direction can be set appropriately depending on whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is prioritized. When the suppression of the gate-drain parasitic capacitance is prioritized, the width W1 can be set to 0.8 times or less, and 0.5 times or less, the width W2 of the gate wiring 18a in the X direction. When the suppression of the gate-source parasitic capacitance is prioritized, the width W1 can be set to 0.25 times or more, and 0.5 times or more, the width W2.

[0049] [Modification 2 of Example 1] Fig. 18 is an enlarged plan view of a semiconductor device according to Modification 2 of Example 1. Fig. 19 is a cross-sectional view taken along line AA in Fig. 18. As shown in Figs. 18 and 19, in a semiconductor device 104 according to Modification 2 of Example 1, a cover metal layer 30 has cover metal layers 30a and 30c. When viewed from the Z direction, the cover metal layers 30a and 30c do not overlap with the gate wiring 18a. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0050] 19, as indicated by dashed arrow 53a, cover metal layers 30a and 30c suppress part of the electric field lines between gate wiring 18a and drain wirings 26a and 26c. As indicated by solid arrow 53b, part of the electric field lines between gate wiring 18a and drain wirings 26a and 26c are not shielded. As a result, the gate-drain parasitic capacitance increases compared to Example 1, and the gate-source parasitic capacitance decreases.

[0051] From the viewpoint of suppressing the gate-drain parasitic capacitance, the height H2 of the upper surfaces of the cover metal layers 30a and 30c from the upper surface of the substrate 10 can be set to be equal to or greater than the height H3 of the upper surface of the gate wiring 18a from the upper surface of the substrate 10, can be set to be 1.2 times or greater, and can be set to be 1.5 times or greater. The height H2 may be equal to or greater than the height H4. From the viewpoint of the manufacturing process, the height H2 can be set to be 5 times or less than the height H3.

[0052] According to the first embodiment and its first and second modifications, as shown in Fig. 3, Fig. 17 and Fig. 19, the cover metal layer 30 or 30a (first cover metal layer) is provided above the substrate 10 between the source electrode 12a and the gate wiring 18a and adjacent to the source electrode 12a and the gate wiring 18a, and is electrically connected to the source electrode 12a via the source electrode 12b as shown in Fig. 2. As a result, the cover metal layer 30 or 30a suppresses the capacitive coupling between the gate wiring 18a and the drain wiring 26a. This makes it possible to suppress the gate-drain parasitic capacitance and to suppress the deterioration of the characteristics of the semiconductor device.

[0053] Furthermore, at least a portion of the cover metal layer 30 overlaps but does not contact the gate wiring 18a when viewed from the Z direction, which makes it possible to further reduce the gate-drain parasitic capacitance and further suppress deterioration of the characteristics of the semiconductor device.

[0054] The cover metal layer 30 or 30c (second cover metal layer) is provided above the substrate 10 between the source electrode 12c and the gate wiring 18a and adjacent to the source electrode 12c and the gate wiring 18a, and is electrically connected to the source electrode 12c via the source electrode 12b as shown in Fig. 2. This allows the cover metal layer 30 or 30c to suppress the capacitive coupling between the gate wiring 18a and the drain wiring 26c. This makes it possible to further suppress the gate-drain parasitic capacitance, and thus to further suppress the deterioration of the characteristics of the semiconductor device.

[0055] According to the first embodiment, as shown in FIG. 3, the cover metal layers 30a and 30c are in contact with each other above the gate wiring 18a. This makes it possible to further suppress the gate-drain parasitic capacitance and to further suppress deterioration of the characteristics of the semiconductor device. When viewed from the X direction, the cover metal layers 30a and 30c are in contact with each other at all points. This makes it possible to further suppress the gate-drain parasitic capacitance and to further suppress deterioration of the characteristics of the semiconductor device.

[0056] 17 and 19 of the first and second modifications of the first embodiment, the cover metal layers 30a and 30c are not in contact with each other above the gate wiring 18a, which can suppress the gate-source parasitic capacitance and further suppress the deterioration of the characteristics of the semiconductor device.

[0057] Furthermore, the ends of the cover metal layers 30a and 30c in the X direction overlap with the gate wiring 18a when viewed in the Z direction. This makes it possible to suppress the gate-drain parasitic capacitance and the gate-source parasitic capacitance, thereby further suppressing deterioration of the characteristics of the semiconductor device.

[0058] As shown in FIG. 3, FIG. 17, and FIG. 19 of the first embodiment and its modified examples 1 and 2, the height H2 of the upper surface of the cover metal layer 30 from the substrate 10 is greater than the height H3 of the upper surface of the gate wiring 18a from the substrate 10. The height H1 of the lower surface of the end of the cover metal layer 30 located outside the gate wiring 18a in the X direction as viewed from the Z direction from the substrate 10 is smaller than the height H3 of the upper surface of the gate wiring 18a from the substrate 10. As a result, the end of the cover metal layer 30 outside the gate wiring 18a in the X direction covers a part of the side of the gate wiring 18a. This suppresses the capacitive coupling between the gate wiring 18a and the drain wirings 26a and 26c. Therefore, the gate-drain parasitic capacitance can be further suppressed, and the deterioration of the characteristics of the semiconductor device can be further suppressed.

[0059] A height H2 of the upper surface of the cover metal layer 30 from the substrate 10 is smaller than a height H4 of the upper surfaces of the source wirings 22a and 22c from the substrate 10. This makes it possible to suppress the gate-drain parasitic capacitance and the gate-source parasitic capacitance, thereby further suppressing deterioration of the characteristics of the semiconductor device.

[0060] As shown in Fig. 9 and Fig. 13A, the cover metal layer 30 and the field plates 15a and 15c are formed at the same time. This allows the manufacturing process of forming the cover metal layer 30 to be reduced. The cover metal layer 30 and the field plates 15a and 15c are formed from the same material. In addition, the thickness of the cover metal layer 30 is equal to the thickness of the field plates 15a and 15c. At least a portion of the field plates 15a and 15c may not be provided.

[0061] [Example 2] FIG. 20 is a plan view of a semiconductor device according to a second embodiment. As shown in FIG. 20, in a semiconductor device 106 according to the second embodiment, FET groups 36c and 36d are provided between FET groups 36a and 36b. Source wirings 22a and 22c are electrically connected to the source electrodes of the FET groups 36a, 36c, and 36d. Drain wirings 26a and 26c are electrically connected to the drain electrodes of the FET groups 36a to 36d. Gate wirings 18a and 18b are electrically connected to the gate electrodes 14 of the FET groups 36b to 36d. A cover metal layer 30 is provided in the region between the source wirings 22a and 22c of the FET groups 36a, 36c, and 36d. The other configurations are the same as those of the first embodiment, and description thereof will be omitted.

[0062] As in Example 2, the number of FET groups arranged in the Y direction may be four. In Example 1 and its modified examples, the number of FET groups arranged in the Y direction can be set as appropriate. In Examples 1 and 2 and their modified examples, an example in which there are four unit FETs 35 in the X direction has been described, but the number of unit FETs 35 in the X direction may be any of one to three, or five or more, and can be set as appropriate.

[0063] [Measurement results] GaN HEMTs having the structures of Comparative Example 1 and Example 1 were fabricated, and their high-frequency characteristics were measured. A high-frequency signal is input to the gate bus bar 25, and an amplified high-frequency signal is output from the drain bus bar 24. FIG. 21 is a diagram showing the K-factor versus frequency in the semiconductor devices A and B. FIG. 22 is a diagram showing |S12| versus frequency in the semiconductor devices A and B. The horizontal axis of FIG. 21 is frequency, and the vertical axis is K-factor, which is a stability coefficient. The smaller the K-factor, the less likely it is to oscillate, and the more stable it is. The horizontal axis of FIG. 22 is frequency, and the vertical axis is |S12|. S12 is the absolute value of the S parameter S12 when the gate is port 1 and the drain is port 2. |S12| represents the power fed back from the drain to the gate. The semiconductor device A corresponds to the Example, and the semiconductor device B corresponds to Comparative Example 1.

[0064] As shown in Figures 21 and 22, as the frequency increases, both the K-factor and |S12| increase. Compared to Semiconductor Device B, Semiconductor Device A has a smaller K-factor and |S12|. The gate-drain capacitance is a feedback capacitance, and as the gate-drain capacitance increases, both the K-factor and |S12| increase. Compared to Semiconductor Device B, Semiconductor Device A can reduce the gate-drain capacitance, and can suppress the K-factor and |S12|.

[0065] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0066] 10, 10a Board 10b Semiconductor layer 11a, 11b, 11c active area 12, 12a, 12b, 12c Source electrode 13a, 13b Inactive area 14, 14a, 14b, 14c, 14d Gate electrode 15a, 15c field plate 16a, 16b, 16c, 16d Drain electrodes 17 Wiring 18a, 18b Gate wiring 20 Beer Hall 22, 22a, 22b, 22c Source wiring 24 Drain busbar 25 Gate bus bar 25a Gate metal layer 26a, 26c, 26c Drain wiring 28, 28a metal layer 30, 30a, 30c Cover metal layer 32, 32a, 32b Insulating layer 35, 35a, 35b, 35c, 35d Unit FET (Transistor Unit) 36a, 36b, 36c, 36d FETs 38 Gap 50, 53b solid arrow 51, 52, 53a dashed arrow 100, 102, 104, 106, 110 Semiconductor device

Claims

1. A substrate; a first transistor unit including a first drain electrode, a first gate electrode, and a first source electrode provided in that order on the substrate; a second transistor unit, which is provided in a line along the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, in that order on the substrate, and which is located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; a gate wiring provided on the substrate between the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, the first cover metal layer being electrically connected to the first source electrode; a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, the second cover metal layer being electrically connected to the second source electrode; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein at least a portion of the first cover metal layer and at least a portion of the second cover metal layer overlap the gate wiring in a non-contact manner in a plan view.

3. 3. The semiconductor device according to claim 1, wherein the first cover metal layer and the second cover metal layer are in contact with each other above the gate wiring.

4. 3. The semiconductor device according to claim 1, wherein the first cover metal layer and the second cover metal layer are not in contact with each other above the gate wiring.

5. an end of the first cover metal layer overlaps with the gate line in a plan view; The semiconductor device according to claim 4 , wherein an end of the second cover metal layer overlaps with the gate wiring in a plan view.

6. 3. The semiconductor device according to claim 1, wherein the height of the upper surface of the first cover metal layer from the substrate is greater than the height of the upper surface of the gate wiring from the substrate, and the height of the lower surface of the first cover metal layer located outside the gate wiring from the substrate is smaller than the height of the upper surface of the gate wiring from the substrate.

7. a source wiring provided on and in electrical contact with the first source electrode; 3. The semiconductor device according to claim 1, wherein a height of an upper surface of the first cover metal layer from the substrate is smaller than a height of an upper surface of the source wiring from the substrate.

8. 3. The semiconductor device according to claim 1, further comprising a field plate provided above the substrate between the first gate electrode and the first drain electrode, the field plate being made of the same material as the first cover metal layer.

9. 3. The semiconductor device according to claim 1, further comprising a third transistor unit, the third transistor unit being located on a side to which the first gate electrode extends, the third drain electrode being electrically connected to the first drain electrode, the third gate electrode being electrically connected to the gate wiring, and the third source electrode being electrically connected to the first source electrode, the third gate electrode being electrically connected to the gate wiring, and the third source electrode being electrically connected to the first source electrode, the third transistor unit being located on the side to which the first gate electrode extends relative to the first transistor unit.

10. forming, on a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode provided in this order, and a second transistor unit having a second source electrode provided in line with the first source electrode and electrically connected to the first source electrode, a second gate electrode electrically connected to the first gate electrode, and a second drain electrode electrically connected to the first drain electrode, in this order, the second transistor unit being located on a side of the first transistor unit where the first drain electrode, the first gate electrode, and the first source electrode are arranged; forming a gate wiring on the substrate between the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a step of simultaneously forming a first cover metal layer disposed above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, the first cover metal layer being electrically connected to the first source electrode, a second cover metal layer disposed above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, the second cover metal layer being electrically connected to the second source electrode, and a field plate disposed above the substrate between the first gate electrode and the first drain electrode; A method for manufacturing a semiconductor device comprising the steps of:

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