Manufacturing method of silicon carbide semiconductor device

Abstract

To provide a manufacturing method of a silicon carbide semiconductor device, capable of removing a carbon of front and back surfaces of a silicon carbide semiconductor substrate in one step, and obtaining a high efficiency percentage without contaminating the front surface of the silicon carbide semiconductor substrate.SOLUTION: On a front surface side of a first conductivity type starting substrate, a silicon carbide semiconductor substrate providing a first conductivity type first semiconductor layer of a concentration of an impurity that is lower than that of the starting substrate is prepared. Next, in the first semiconductor layer, an impurity ion is implanted. Subsequently, a front surface carbon film is formed onto a front surface on the front surface side of the silicon carbide semiconductor substrate. Next, an activation thermal processing is applied to the silicon carbide semiconductor substrate by using a front surface carbon film as a protection film. Subsequently, a back surface carbon film and a front surface carbon film that are deposited to the back surface of the silicon carbide semiconductor substrate by the activation thermal processing are removed. Firstly, the back surface carbon film is removed with a lift pin in a state where the silicon carbide semiconductor substrate is floated from a stage, and subsequently the front surface carbon film is removed in a state where the silicon carbide semiconductor substrate is contacted to the stage by dropping the lift pin.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material to replace silicon (Si). Compared to conventional semiconductor elements that use silicon carbide as a semiconductor material, semiconductor elements that use silicon carbide as a semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements that use silicon as a semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude larger than that of silicon.

[0003] Silicon carbide semiconductor devices that have been commercially available to date include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) having a planar gate structure or a trench gate structure.

[0004] The structure of a conventional silicon carbide semiconductor device will be described using a trench MOSFET as an example. + On the front surface of the starting substrate + A type buffer layer and an n-type silicon carbide epitaxial layer are deposited. + The surface side opposite to the starting substrate side is provided with an n-type high concentration region. + The surface layer on the opposite side to the starting substrate side is the first p + The n-type base region is selectively provided. The n-type high concentration region is provided with a second p + A mold base region is optionally provided.

[0005] In addition, conventional trench MOSFETs also have a p-type base region, + Type source region, p ++ The semiconductor device includes a contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, a back electrode, a trench, a source electrode pad, and a drain electrode pad. + Type source region, p ++ A source electrode pad is provided on the source electrode and on the mold contact region.

[0006] The problem with SiC is that the diffusion coefficient of impurities in SiC is extremely small compared to Si. When forming an impurity layer by ion implantation, it is difficult to form it deep in the depth direction. For this reason, when forming a structure in the vertical direction of the substrate, such as in a trench-type MOSFET, the impurity layer is formed by combining ion implantation and epitaxial growth.

[0007] Conventionally, in a trench MOSFET, the impurity layer is formed as follows. + On the front surface of the starting substrate + A silicon carbide semiconductor substrate is formed by depositing an n-type buffer layer and an n-type silicon carbide epitaxial layer. Next, an n-type high concentration region is formed by ion implantation of n-type impurities. Next, a first p-type high concentration region is formed by ion implantation of p-type impurities. + Type base region and second p + Next, an n-type silicon carbide layer is epitaxially grown. Next, a p-type base region is formed by ion implantation of p-type impurities. Next, an n-type silicon carbide layer is epitaxially grown. Next, a p-type base region is formed by ion implantation of n-type impurities. + Next, p-type source regions are formed by ion implantation of p-type impurities. ++ A mold contact region is formed. After this, an activation process is performed and a trench is formed. In this way, an impurity layer is formed by combining ion implantation and epitaxial growth.

[0008] Here, the impurities ion-implanted into the silicon carbide semiconductor substrate need to be activated. To activate the impurities, the silicon carbide semiconductor substrate is heat-treated at a very high temperature. It has been confirmed that this activation heat treatment causes Si to sublime from the surface of the silicon carbide semiconductor substrate, resulting in surface roughness. Therefore, in order to prevent Si from escaping from the surface of the silicon carbide semiconductor substrate, it is known to form a carbon film as a protective film on the surface of the silicon carbide semiconductor substrate before the activation heat treatment.

[0009] 14 is a diagram showing activation heat treatment in a conventional single wafer apparatus. In the activation heat treatment of silicon carbide semiconductor substrates, silicon carbide semiconductor substrates (SiC wafers) 134 are placed on a carbon tray 140 and processed single wafer. After the activation heat treatment, the carbon film formed on the surface of the silicon carbide semiconductor substrate 134 is removed. The carbon film is removed using an asher in the same manner as general resist removal.

[0010] Also, a method for manufacturing a silicon carbide semiconductor element is known that includes the steps of forming a protective film on a front surface of a SiC substrate, heat-treating the SiC substrate with the protective film formed thereon, and removing a carbon-rich layer formed on the rear surface of the SiC substrate during the heat treatment (see Patent Document 1 below).

[0011] Also, a method for manufacturing a silicon carbide semiconductor element is known that includes the steps of implanting impurity ions into the front surface of a silicon carbide substrate, forming carbon films on the front and back surfaces of the silicon carbide substrate, subjecting the silicon carbide substrate to an activation heat treatment using the carbon film as a protective film, and removing the carbon films on the front and back surfaces after the activation heat treatment step (see Patent Document 2 below). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Patent No. 6348430 [Patent Document 2] JP 2011-35257 A Summary of the Invention [Problem to be solved by the invention]

[0013] However, in order to improve throughput, the activation heat treatment may be performed in a furnace instead of a single wafer processing apparatus. Fig. 15 is a diagram showing a conventional activation heat treatment in a furnace. A plurality of silicon carbide semiconductor substrates 134 are placed on the claws of a carbon boat 141 and heat treated in the furnace. In this case, the back surface of the silicon carbide semiconductor substrate 134 is exposed, so that Si is removed from the SiC and carbon is precipitated on the back surface of the silicon carbide semiconductor substrate 134. For this reason, a step of removing the carbon precipitated on the back surface must be added, which poses a problem of increasing the number of removal steps.

[0014] Furthermore, if, after removing the carbon film on the front surface, silicon carbide semiconductor substrate 134 is turned over to remove the carbon deposited on the back surface, not only will the number of steps increase, but the front surface of silicon carbide semiconductor substrate 134 will come into contact with the high-temperature stage, causing particles to adhere to the front surface of silicon carbide semiconductor substrate 134, resulting in a decrease in the yield rate.

[0015] An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device that can remove carbon from the front and back surfaces of a silicon carbide semiconductor substrate in a single step, without contaminating the surface of the silicon carbide semiconductor substrate, and that can achieve a high yield rate. [Means for solving the problem]

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step is performed to prepare a silicon carbide semiconductor substrate having a first semiconductor layer of a first conductivity type, which has a lower impurity concentration than a starting substrate, on the front surface side of a first conductivity type starting substrate made of silicon carbide. Next, a second step is performed to implant impurity ions into the first semiconductor layer. Next, a third step is performed to form a front surface carbon film on the front surface side of the silicon carbide semiconductor substrate. Next, a fourth step is performed to perform an activation heat treatment on the silicon carbide semiconductor substrate using the front surface carbon film as a protective film. Next, a fifth step is performed to remove a back surface carbon film deposited on the back surface of the silicon carbide semiconductor substrate by the activation heat treatment and the front surface carbon film. In the fifth step, first, the back surface carbon film is removed while the silicon carbide semiconductor substrate is lifted off a stage by lift pins, and then the front surface carbon film is removed while the lift pins are lowered to bring the silicon carbide semiconductor substrate into contact with the stage.

[0017] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the fifth step, the back surface carbon film and the front surface carbon film are removed by generating plasma containing oxygen using a same plasma device.

[0018] Moreover, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it includes a sixth step of forming a trench in the first semiconductor layer after the fifth step or before the second step.

[0019] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the fifth step, a distance between the silicon carbide semiconductor substrate and the stage when the silicon carbide semiconductor substrate is lifted from the stage by the lift pins is 5 mm or more and 100 mm or less.

[0020] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the fifth step, the temperature of the stage is set to 150° C. or more and 350° C. or less.

[0021] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the fourth step, the activation heat treatment is performed using a furnace at a temperature of 1600° C. or higher and 1900° C. or lower.

[0022] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further comprises a seventh step of cleaning the surface of the silicon carbide semiconductor substrate with a mixed solution of sulfuric acid and hydrogen peroxide after the fifth step.

[0023] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the method further comprises an eighth step of performing cleaning with hydrogen fluoride after the fifth step.

[0024] According to the above-described invention, since the rear surface carbon film is first removed in the pin-up state, when the front surface carbon film is then removed in the pin-down state, the rear surface carbon film does not adhere to the stage, and it is possible to prevent particles from adhering to the front surface of the silicon carbide semiconductor substrate, thereby preventing a decrease in the yield rate. Effect of the Invention

[0025] According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, it is possible to remove carbon from the front and back surfaces of a silicon carbide semiconductor substrate in a single step, and it is possible to obtain an excellent yield without contaminating the surface of the silicon carbide semiconductor substrate. [Brief description of the drawings]

[0026] [Figure 1] 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to an embodiment; [Diagram 2] 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 3] 1A to 1C are cross-sectional views (part 1) illustrating schematic diagrams of a silicon carbide semiconductor device according to an embodiment during manufacture. [Figure 4] 5A to 5C are cross-sectional views (part 2) illustrating schematic diagrams of a silicon carbide semiconductor device according to the embodiment during manufacture. [Diagram 5] 5A to 5C are cross-sectional views (part 3) illustrating schematic configurations of the silicon carbide semiconductor device according to the embodiment during manufacture. [Figure 6] 4 is a cross-sectional view (part 4) illustrating a schematic diagram of a silicon carbide semiconductor device according to the embodiment during manufacture. FIG. [Figure 7] FIG. 2 is a cross-sectional view showing a carbon removal device. [Figure 8] 4 is a cross-sectional view showing a state of the silicon carbide semiconductor substrate when a rear surface carbon film is removed. FIG. [Figure 9] 1 is a graph showing an etching amount when removing a rear surface carbon film. [Figure 10] FIG. 2 is a plan view showing the position of a silicon carbide semiconductor substrate. [Figure 11] 1 is a graph showing the relationship between the stage temperature and the etching rate. [Figure 12] 4 is a cross-sectional view showing a state of the silicon carbide semiconductor substrate when a surface carbon film is removed. FIG. [Figure 13] 1 is a graph showing the relationship between the etching amount and the etching time when removing a surface carbon film. [Figure 14] FIG. 1 is a diagram showing an activation heat treatment in a conventional single wafer processing apparatus. [Figure 15] FIG. 1 is a diagram showing a conventional activation heat treatment in a furnace. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] A preferred embodiment of the method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before the index represents a negative index. In addition, the description of "same" or "equivalent" should include up to 5% in consideration of variations in manufacturing.

[0028] (Embodiment) The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a trench-type MOSFET 50 as an example. Fig. 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the embodiment. Fig. 1 shows only an active region of the trench-type MOSFET 50 through which a main current flows.

[0029] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has n + The first main surface (front surface) of the starting substrate 1, for example, the (0001) surface (Si surface), is + A first n-type buffer layer 16 and - A silicon carbide epitaxial layer 2 is deposited.

[0030] n + The starting substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). + The mold buffer layer 16 has a thickness of, for example, 1 μm or more and 5 μm or less, and a nitrogen concentration of 1×10 17 / cm 3 More than 1×10 18 / cm 3It is a highly doped layer doped at a high concentration of n + The buffer layer 16 is a 1n - This promotes the recombination of holes from the n-type silicon carbide epitaxial layer 2. + The concentration of holes reaching the starting mold substrate 1 is controlled to suppress the occurrence of stacking faults and their area expansion.

[0031] 1st n - The silicon carbide epitaxial layer 2 is + The starting substrate 1 is doped with a lower impurity concentration, for example, nitrogen. - The 1n-type drift layer - The n-type silicon carbide epitaxial layer 2 + The surface side opposite to the mold starting substrate 1 side is the 2nth - A 2n-th type silicon carbide layer 6 is formed. - The silicon carbide layer 6 is + The starting substrate 1 is lower than the first n - The high-concentration n-type silicon carbide epitaxial layer 2 is doped with an impurity concentration higher than that of the n-type silicon carbide epitaxial layer 2, for example with nitrogen. - This is the n-type drift layer. + Starting substrates 1 and n - A silicon carbide epitaxial layer 2 and a second n - The p-type silicon carbide layer 6 and a p-type base layer 3 (described later) together constitute a silicon carbide semiconductor substrate.

[0032] n + A back electrode (drain electrode) is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base) of the mold starting substrate 1. The back electrode constitutes a drain electrode. A drain electrode pad 14 is provided on the surface of the back electrode.

[0033] A trench gate structure is formed on the first main surface side (p-type base layer 3 side) of the silicon carbide semiconductor substrate. + n from the surface on the first main surface side of the mold starting substrate 1 + The second n-type source region 7 and the p-type base layer 3 are connected to the -The gate insulating film 9 is formed on the bottom and side walls of the trench 18 along the inner wall of the trench 18, and the gate electrode 10 is formed on the inside of the gate insulating film 9 in the trench 18. The gate electrode 10 is formed by the gate insulating film 9. - Type silicon carbide epitaxial layer 2, 2n - The gate electrode 10 is insulated from the p-type silicon carbide layer 6 and the p-type base layer 3. A part of the gate electrode 10 may protrude from above the trench 18 (the source electrode pad 15 side) towards the source electrode pad 15.

[0034] 1st n - The n-type silicon carbide epitaxial layer 2 and the n-th - The inside of the first silicon carbide layer 6 is + Type region 4 and 2p + A mold region 5 is selectively provided. + The type region 4 reaches a position deeper on the drain side than the bottom of the trench 18. + The lower end (drain side end) of the mold region 4 is located closer to the drain side than the bottom of the trench 18. + The mold region 4 is provided between the trenches 18. As shown in FIG. + The type region 4 is a p ++ The p-type contact region 8 is in contact with the p ++ It is also possible for the first p-type contact region 8 not to be in contact with the first p-type contact region 8. + The 2n-th type region 4 - The p-type silicon carbide layer 6 has a surface layer and is in contact with the p-type base layer 3 .

[0035] 2nd p. + The lower end of the mold region 5 is located closer to the drain side than the bottom of the trench 18. + The mold region 5 is formed at a position facing the bottom of the trench 18 in the depth direction z. + The width of the mold region 5 is wider than the width of the trench 18. The bottom of the trench 18 is the second p + The p-type region 5 may extend between the p-type base layer 3 and the second p + The 2nth mold region 5 is sandwiched between -The second p + It is not necessary for the first p to be in contact with the mold region 5. + Type region 4 and 2p + The mold region 5 is doped with, for example, aluminum (Al).

[0036] 1st p. + A part of the mold region 4 is extended to the trench 18 side to form a second p + In this case, the first p + A part of the mold region 4 is the first p + Type region 4 and 2p + In the direction x in which the mold regions 5 are arranged (hereinafter referred to as the first direction) and in the direction y perpendicular to the direction x (hereinafter referred to as the second direction), - The first p-type silicon carbide layers 6 may be arranged alternately in a plane layout. + Part of type region 4 and 2p + It is sufficient that a part of the mold region 5 is connected at least at one or more places. + Type 5 and 1n regions - Holes generated when avalanche breakdown occurs at the junction of the silicon carbide epitaxial layer 2 can be efficiently evacuated to the source electrode 13, and the load on the gate insulating film 9 is reduced, thereby improving reliability.

[0037] 1st n - A p-type base layer 3 is provided on the first main surface side of the silicon carbide epitaxial layer 2. The impurity concentration of the p-type base layer 3 is, for example, + The impurity concentration of the p-type base layer 3 may be lower than that of the n-type region 4. This makes it possible to prevent a decrease in breakdown voltage due to punch-through by suppressing the spread of the depletion layer in the p-type base layer 3 even if the concentration is reduced to lower the threshold voltage. + Type source region 7 and p ++ A contact region 8 is selectively provided. + Type source region 7 and p ++ The mold contact regions 8 abut each other.

[0038] Although FIG. 1 illustrates only two trench MOS structures, more trench MOS gate (insulated gate made of metal-oxide-semiconductor) structures may be arranged in parallel.

[0039] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the trench 18. The source electrode 13 is connected to the n-type + Type source region 7 and p ++ The source electrode 13 is in contact with the type contact region 8. The source electrode 13 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. On the source electrode 13, a source electrode pad 15 is provided.

[0040] (Method of Manufacturing Silicon Carbide Semiconductor Device According to an Embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Fig. 2 is a flowchart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figs. 3 to 6 are cross-sectional views each showing a schematic state during the manufacturing process of a silicon carbide semiconductor device according to an embodiment.

[0041] First, n-type silicon carbide + A mold starting substrate 1 is - The n-type silicon carbide epitaxial layer 2 and + A silicon carbide semiconductor substrate 34 (see FIG. 1) on which a type buffer layer 16 is deposited is prepared (first step). This silicon carbide semiconductor substrate 34 may be purchased or may be purchased from a third party. + Purchase a substrate containing only the starting substrate 1 and grow n + The first n-type buffer layer 16 and - The n-type silicon carbide epitaxial layer 2 may be formed to form the above-mentioned silicon carbide semiconductor substrate 34. In this case, + On the first main surface of the starting substrate 1, an n-type impurity such as nitrogen (N) is doped into a silicon carbide n-type semiconductor layer. + The n-type buffer layer 16 is then epitaxially grown.+ A first n-type buffer layer 16 is formed on the buffer layer 16 by doping with n-type impurities, such as nitrogen atoms, and the first n-type buffer layer 16 is formed on the buffer layer 16 by doping with n-type impurities, such as nitrogen atoms. - A silicon carbide epitaxial layer 2 is grown.

[0042] Next, impurity ions are implanted into the surface of the silicon carbide semiconductor substrate 34 (step S1: second step). As a result, impurity regions (for example, the p-type base layer 3, the first p + Type area 4, 2nd p + Type area 5, 2nd n - Type silicon carbide layer 6, n + Type source region 7, p ++ These impurity regions are formed as follows.

[0043] First, the 1nth - A resist mask (not shown) having desired openings is formed on the surface of the silicon carbide epitaxial layer 2 by photolithography. Then, p-type impurities, for example, aluminum atoms, are ion-implanted to form a first n-type silicon carbide epitaxial layer. - A first p-type silicon carbide epitaxial layer 2 is formed to a depth of about 0.6 μm. + Type area 4, 2nd p + The mold region 5 is, for example, 1 to 5 × 10 18 / cm 3 The impurity concentration is .

[0044] Next, the 1nth - A resist mask (not shown) having a desired opening is formed by photolithography on the surface of the silicon carbide epitaxial layer 2. Then, a second n-type epitaxial layer having a thickness of about 0.7 μm and doped with n-type impurities such as nitrogen by ion implantation is formed. - The silicon carbide layer 6 is, for example, 1 to 3×10 17 / cm 3 The 2nth - The silicon carbide layer 6 is a 1n - The second epitaxial layer 2 may be formed by epitaxial growth on the surface of the second silicon carbide epitaxial layer 2 .

[0045] Next, n - A resist mask (not shown) having desired openings is formed by photolithography on the surface of the silicon carbide epitaxial layer 2. Then, a p-type base layer 3 having a thickness of about 0.5 μm is formed by ion implantation, for example, with 1 to 5×10 17 / cm 3 The p-type base layer 3 is formed with an impurity concentration of 2n - The second insulating layer 14 may be formed on the surface of the silicon carbide layer 6 by epitaxial growth.

[0046] Next, a resist mask (not shown) having desired openings is formed by photolithography on the surface of the p-type base layer 3. Then, n-type ions having a thickness of about 0.5 μm are implanted by ion implantation. + The mold source layer 7 is, for example, 1 to 3 × 10 19 / cm 3 The impurity concentration is .

[0047] Next, an ion implantation mask having a predetermined opening is formed, and n + A p-type impurity such as aluminum is ion-implanted into a part of the p-type source layer 7 and a part of the p-type base layer 3. ++ The contact region 8 is, for example, 1 to 3 × 10 20 / cm 3 The state up to this point is shown in FIG.

[0048] Next, a surface carbon film 21 is formed on the surface of the silicon carbide semiconductor substrate 34 (Step S2: third process). The surface carbon film 21 is preferably formed using a sputtering method or a CVD (Chemical Vapor Deposition) method, but may also be formed by applying an organic film such as a resist and then heating and carbonizing it. The state up to this point is shown in FIG. 4. The thickness of the surface carbon film 21 is preferably 30 nm or more and 100 nm or less. If it is thinner than 30 nm, the surface of the silicon carbide semiconductor substrate 34 cannot be sufficiently protected, and the surface of the silicon carbide semiconductor substrate 34 becomes rough during activation heat treatment. If it is thicker than 100 nm, etching takes a long time during the carbon removal process, increasing manufacturing costs.

[0049] Next, a heat treatment is performed in an inert gas atmosphere to perform an activation heat treatment of the impurity region formed by ion implantation (step S3: fourth process). By performing the activation heat treatment, Si is removed from the back surface of the silicon carbide semiconductor substrate 34, carbon (C) is precipitated, and a back surface carbon film 22 is formed. The state up to this point is shown in FIG. 5. For the activation heat treatment, a plurality of silicon carbide semiconductor substrates 34 are placed on the claws of a carbon boat and heat treated in a furnace (see FIG. 15). The heat treatment is performed at 1600°C or higher and 1900°C or lower. This is because the impurities are not sufficiently activated at temperatures lower than 1600°C. This is because too much Si is removed from the back surface at temperatures higher than 1900°C. The thickness of the back surface carbon film 22 varies depending on the time and temperature of the activation heat treatment, but is approximately 2 nm to 20 nm.

[0050] Next, the carbon on the back surface and the carbon on the front surface are removed (step S4: fifth process). FIG. 7 is a cross-sectional view showing an example of a carbon removal device. A carbon removal device (plasma device) 30 supplies a gas containing oxygen from the arrow S and generates a plasma 31 containing oxygen by microwaves. The plasma 31 is uniformly sprayed onto a silicon carbide semiconductor substrate 34 (SiC wafer) placed on a stage 33 by a shower plate 32 having a countless number of uniform through holes, and is discharged from the arrow E. The oxygen radicals (active oxygen) generated by the plasma 31 etch the front and back surfaces of the silicon carbide semiconductor substrate 34, thereby removing the carbon films on the front and back surfaces of the silicon carbide semiconductor substrate 34. Here, a microwave plasma device is taken as an example, but an etching device using another plasma generation method may be used. Also, the shower plate 32 may not be provided between the plasma 31 and the wafer.

[0051] In the embodiment, first, the rear surface carbon film 22 is removed. FIG. 8 is a cross-sectional view showing the state of the silicon carbide semiconductor substrate when the rear surface carbon film is removed. The silicon carbide semiconductor substrate 34 is placed on the lift pins 35 so that the rear surface carbon film 22 faces the stage 33. When removing the rear surface carbon film 22, plasma containing oxygen is generated in a state in which the silicon carbide semiconductor substrate 34 is lifted from the stage 33 by the lift pins 35 (pin-up state). Then, oxygen radicals generated by the oxygen plasma penetrate into the gap between the silicon carbide semiconductor substrate 34 and the stage 33 and remove the rear surface carbon film 22. At this time, the front surface carbon film 21 is also removed, but since the front surface carbon film 21 is thicker than the rear surface carbon film 22, it cannot be completely removed. If the gap h between the silicon carbide semiconductor substrate 34 and the stage 33 is too narrow, the penetration of oxygen radicals is insufficient. On the other hand, if the gap h is too wide, the chamber capacity increases and the etching efficiency decreases, so the gap h is preferably 5 mm or more and 100 mm or less. For example, when the rear surface of the silicon carbide semiconductor substrate 34 is heated by the stage 33, the distance h may be set to 5 mm or more and 10 mm or less. When increasing the amount of plasma that reaches the rear surface of the silicon carbide semiconductor substrate 34, the distance h may be set to 40 mm or more and 100 mm or less. In this case, in order to make oxygen radicals reach the rear surface of the silicon carbide semiconductor substrate 34, the gas pressure may be set to 10 to 60 Pa.

[0052] Fig. 9 is a graph showing the amount of etching when removing the back surface carbon film. Fig. 10 is a plan view showing the position of the silicon carbide semiconductor substrate. In Fig. 9, the vertical axis shows the amount of carbon etching in nm. The horizontal axis shows the position of the silicon carbide semiconductor substrate 34 in Fig. 10. As shown in Fig. 9, at 60 seconds, silicon carbide semiconductor substrate 34 is in a state of being lifted off stage 33 by lift pins 35, so it takes time for temperature transfer from stage 33 and almost no etching is performed.

[0053] On the other hand, at 120 seconds, the oxygen radicals move from the outer periphery to the center of the back surface of the silicon carbide semiconductor substrate 34, so the etching rate is slow at the center of the silicon carbide semiconductor substrate 34 and the etching rate at the outer periphery is four times faster than the center. Even at the center of the silicon carbide semiconductor substrate 34, where the etching rate is the slowest, the etching amount is 100 nm or more, and the thickness of the back surface carbon film 22 is about 2 nm to 20 nm, so that the back surface carbon film 22 can be completely removed by performing carbon removal for 120 seconds.

[0054] Fig. 11 is a graph showing the relationship between the stage temperature and the etching rate. In Fig. 11, the vertical axis shows the carbon etching rate in nm / min. The horizontal axis shows the temperature of the stage 33 in °C. As shown in Fig. 11, the carbon etching rate depends on the temperature of the stage 33, and the higher the temperature, the faster the etching rate. A faster etching rate improves throughput and reduces costs, so it is desirable to perform the etching at a high temperature of 150°C or higher and 350°C or lower.

[0055] In the embodiment, secondly, next, the front surface carbon film 21 is removed. FIG. 12 is a cross-sectional view showing a state of the silicon carbide semiconductor substrate when the front surface carbon film is removed. When removing the front surface carbon film 21, the lift pins 35 are lowered and the silicon carbide semiconductor substrate 34 is in a state of contact with the stage 33 (pin-down state), and then a plasma containing oxygen is generated to remove the front surface carbon film 21. The state after the front surface carbon film 21 and the back surface carbon film 22 have been removed is the same as that shown in FIG. 3. At this time, the gas pressure may be 60 to 100 Pa. By using a gas pressure higher than the gas pressure in the pin-up state in this manner, the etching rate can be increased.

[0056] In this way, because the back surface carbon film 22 is removed first in the pin-up state, when the front surface carbon film 21 is then removed in the pin-down state, the back surface carbon film 22 does not adhere to the stage 33, and it is possible to prevent particles from adhering to the front surface of the silicon carbide semiconductor substrate 34, which would deteriorate the yield rate. On the other hand, if the silicon carbide semiconductor substrate 34 is brought into contact with the stage 33 first in the pin-down state, the back surface carbon film 22 will adhere to the stage 33, which will later cause product particles and reduce the yield. For this reason, the order of raising the lift pins 35 first and then lowering them is required, as described above.

[0057] Fig. 13 is a graph showing the relationship between the etching amount and etching time when removing the surface carbon film. In Fig. 13, the vertical axis shows the etching amount of carbon in nm. The horizontal axis shows the etching time in seconds (sec). With an etching time of 15 seconds, the average etching amount is 192 nm, and with an etching time of 30 seconds, most of the surface carbon film 21 (about 500 nm thick) is gone, but from the etching amounts at 15 and 30 seconds, it can be estimated that the etching amount increases linearly from the start of processing.

[0058] However, the etching time largely depends on the etching rate of the carbon removal device 30, and the etching time in the pin-up state should be set to a time sufficient for removing the back surface carbon film 22, and the etching time in the pin-down state should be set to a time sufficient for removing the front surface carbon film 21.

[0059] After carbon removal by plasma treatment, polymers may remain on the surface of the silicon carbide semiconductor substrate 34, so cleaning with a mixture of sulfuric acid and hydrogen peroxide (step 7) is desirably performed. After cleaning with a mixture of sulfuric acid and hydrogen peroxide, cleaning with HF (hydrogen fluoride) (step 8) can be performed to remove oxides formed on the surface of the silicon carbide semiconductor substrate 34 by oxygen plasma. The order of steps 7 and 8 may be reversed, and the oxides may be removed first by HF cleaning, and then the polymers may be removed with a mixture of sulfuric acid and hydrogen peroxide.

[0060] Next, n + A trench forming mask having a predetermined opening is formed on the surface of the source region 7 by photolithography, for example, an oxide film. + The second p-type source region 7 and the p-type base layer 3 are penetrated. + A trench 18 is formed so as to reach the mold region 5 (step S5: sixth step). Next, the mask for forming the trench is removed. The state up to this point is shown in FIG.

[0061] After forming the trench 18, isotropic etching may be performed to remove damage to the trench 18, and sacrificial oxidation may be performed to round the corners of the bottom of the trench 18 and the opening of the trench 18. Only one of isotropic etching and sacrificial oxidation may be performed. Also, sacrificial oxidation may be performed after isotropic etching. This makes it possible to present a clean surface of the silicon carbide, and by rounding the corners, electric field concentration at the bottom and opening of the trench 18 can be suppressed.

[0062] In the above embodiment, the front surface carbon film 21 is formed, and the front surface carbon film 21 and the back surface carbon film 22 are removed, and then the trench 18 is formed. However, the trench 18 may be formed first. For example, after trench etching, p-type impurities are ion-implanted into the bottom of the trench 18 to form a second p + A mold region 5 may be formed.

[0063] In this case, the second p+ After forming the mold region 5, the front surface carbon film 21 must be formed and subjected to activation heat treatment. At this time, in order to form the front surface carbon film 21 capable of withstanding the activation heat treatment on the inner surface of the trench 18, the front surface carbon film 21 must be thicker than that in the above embodiment on the front surface of the silicon carbide semiconductor substrate 34. The process of removing the front surface carbon film 21 and the back surface carbon film 22 is similar to that in the above embodiment, but if the front surface carbon film 21 is thick, the etching time after pinning down must be set longer.

[0064] Next, n + Type source region 7 and p ++ A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1300° C. in a gas atmosphere containing oxygen. Alternatively, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0065] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 18 to form the gate electrode 10.

[0066] Next, an insulating film is formed on the surface of the gate electrode 10. For example, annealing is performed in an oxygen atmosphere at 1000°C to form a thermal oxide film. Next, the surface is protected with a protective film, for example, formed of a photoresist. Next, the insulating film formed on the back surface, the gate electrode, and the gate insulating film are all removed by dry etching. Next, the protective film formed on the surface is removed in an ashing and stripping process. This time, ashing in oxygen plasma and stripping using an SPM were performed.

[0067] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. Next, the interlayer insulating film 11 and the gate insulating film 10 are patterned by photolithography. + Type source region 7 and p ++ A contact hole is formed to expose the n-type contact region 8. Next, a conductive film, for example, nickel, which becomes the source electrode 13 is formed in the contact hole and on the interlayer insulating film 11 by, for example, a sputtering method. Next, a heat treatment of about 700° C. is performed to selectively react the conductive film with silicon carbide, and then the unreacted conductive film is selectively removed to leave the source electrode 13 only in the contact hole, and the n-type contact region 8 is formed. + Type source region 7 and p ++ The contact region 8 is brought into contact with a source electrode 13 .

[0068] Next, a metal film to become the source electrode pad 15 is formed on the source electrode 13 and the interlayer insulating film 11 on the front surface of the silicon carbide semiconductor substrate by, for example, sputtering. At this time, a barrier metal (not shown) made of titanium or titanium nitride may be formed first. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 3 to 7 μm. The electrode pad may be formed of, for example, aluminum containing silicon at a rate of 1% (Al-Si). Next, the metal film is selectively removed to form the source electrode pad 15.

[0069] Next, n + After the front surface of the mold starting substrate 1 is covered with a protective film (not shown) for protection, + The starting substrate 1 is polished from the back side to form a n + The starting mold substrate 1 may be thinned to the product thickness.

[0070] Next, n + On the second main surface of the starting substrate 1, a conductive film that will become a drain electrode (not shown), such as a molybdenum film and a nickel film, is successively formed by, for example, a sputtering method. Then, a heat treatment such as laser annealing is performed to form a n +The starting mold substrate 1 and a conductive film are reacted to form an ohmic junction, thereby forming a drain electrode.

[0071] Next, on the surface of the drain electrode, films of, for example, titanium, nickel and gold are formed in this order as drain electrode pad 14. In this manner, the silicon carbide semiconductor device shown in FIG.

[0072] As described above, according to the embodiment, the back surface carbon film formed during the activation heat treatment in the pin-up state is first removed. Therefore, when the front surface carbon film is then removed in the pin-down state, the back surface carbon film does not adhere to the stage, and it is possible to prevent particles from adhering to the front surface of the silicon carbide semiconductor substrate and thereby preventing a decrease in the yield rate.

[0073] The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-mentioned embodiments, for example, the dimensions and impurity concentration of each part are set in various ways according to the required specifications. In each of the embodiments, a trench-type MOSFET is used as an example, but the present invention can also be applied to a planar-type MOSFET, and further, to various semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor) and a diode. In each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0074] INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, igniters for automobiles, and the like. [Explanation of symbols]

[0075] 1n + Starting substrate 2 1stn - Silicon carbide epitaxial layer 3 p-type base layer 4 1st p. + type area 5 2nd p. + type area 6 2nd n - mold silicon carbide layer 7 n + Type Source Area 8 p ++ Mold Contact Area 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 13 Source electrode 14 Drain electrode pad 15 Source electrode pad 16n + Mold Buffer Layer 18 Trench 21 Surface carbon film 22 Back carbon film 30 Carbon removal device 31 Plasma 32 Shower Plate 33 Stages 34, 134 Silicon carbide semiconductor substrate 35 Lift pin 50 Trench MOSFET 140 Carbon Tray 141 Carbon Boat

Claims

1. A first step of preparing a silicon carbide semiconductor substrate, the silicon carbide semiconductor substrate including a first conductivity type starting substrate made of silicon carbide and a first semiconductor layer having a first conductivity type and a lower impurity concentration than the starting substrate, provided on a front surface side of the starting substrate; a second step of implanting impurity ions into the first semiconductor layer; a third step of forming a surface carbon film on a front surface of the silicon carbide semiconductor substrate; a fourth step of subjecting the silicon carbide semiconductor substrate to an activation heat treatment using the surface carbon film as a protective film; a fifth step of removing a back surface carbon film deposited on the back surface of the silicon carbide semiconductor substrate by the activation heat treatment and the front surface carbon film; Including, a silicon carbide semiconductor device manufacturing method, characterized in that in the fifth step, first, the back surface carbon film is removed while the silicon carbide semiconductor substrate is lifted off a stage by lift pins, and then, the lift pins are lowered to bring the silicon carbide semiconductor substrate into contact with the stage, and the front surface carbon film is removed.

2. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein in the fifth step, the back surface carbon film and the front surface carbon film are removed by generating plasma containing oxygen using a same plasma device.

3. After the fifth step or before the second step, The method for manufacturing a silicon carbide semiconductor device according to claim 1 , further comprising a sixth step of forming a trench in the first semiconductor layer.

4. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the fifth step, a distance between the silicon carbide semiconductor substrate and the stage when the silicon carbide semiconductor substrate is lifted off the stage by the lift pins is 5 mm or more and 100 mm or less.

5. 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein in the fifth step, a temperature of the stage is set to 150° C. or more and 350° C. or less.

6. 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein in the fourth step, the activation heat treatment is performed using a furnace at a temperature of 1600° C. or higher and 1900° C. or lower.

7. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a seventh step of cleaning the surface of the silicon carbide semiconductor substrate with a mixed solution of sulfuric acid and hydrogen peroxide after the fifth step.

8. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, further comprising, after the fifth step, an eighth step of performing cleaning with hydrogen fluoride.

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