Manufacturing method of silicon carbide semiconductor device and the silicon carbide semiconductor device

Abstract

To provide a manufacturing method of a silicon carbide semiconductor device, capable of preventing a passage of Ni of an ohmic electrode from passing a barrier metal, and leaking it to an Al film or an Al-Si film by improving a barrier performance of the barrier metal, and provide the silicon carbide semiconductor device.SOLUTION: A manufacturing method of a silicon carbide semiconductor device, prepares a silicon carbide semiconductor substrate to which a first conductivity type first semiconductor layer in an impurity concentration that is lower than a starting substrate is provided to a front surface side of the starting substrate of the first conductivity type. Next, a second conductivity type second semiconductor layer is formed onto a front surface of the first semiconductor layer opposite to the starting substrate. Subsequently, an ohmic electrode is formed onto the front surface of the second semiconductor layer, and a Ti film and a TiN film are laminated in this order to the front surface of the ohmic electrode. Next, a barrier metal is formed by performing a thermal processing of the Ti film and the TiN film. The thermal processing is performed at a temperature of 550°C or more and 750°C or less.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material to replace silicon (Si). Compared to conventional semiconductor elements that use silicon carbide as a semiconductor material, semiconductor elements that use silicon carbide as a semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements that use silicon as a semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude larger than that of silicon.

[0003] Silicon carbide semiconductor devices that have been commercially available to date include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) having a planar gate structure or a trench gate structure.

[0004] The structure of a conventional silicon carbide semiconductor device will be described using a trench MOSFET as an example. + On the front surface of the starting substrate + A type buffer layer and an n-type silicon carbide epitaxial layer are deposited. + The surface side opposite to the starting substrate side is provided with an n-type high concentration region. + The surface layer on the opposite side to the starting substrate side is the first p + The n-type base region is selectively provided. The n-type high concentration region is provided with a second p + A mold base region is optionally provided.

[0005] In addition, conventional trench MOSFETs also have a p-type base region, + Type source region, p ++ The semiconductor device is provided with a contact region, a gate insulating film, a gate electrode, an interlayer insulating film, an ohmic electrode (source electrode), a back electrode, a trench, a source electrode pad, and a drain electrode pad. + Type source region, p ++ A source electrode pad is provided on the mold contact region and on the ohmic electrode.

[0006] In addition, a barrier metal is provided between the ohmic electrode and the interlayer insulating film on the one hand and the source electrode pad on the other hand to prevent diffusion of metal atoms from the ohmic electrode to the gate electrode side on the other hand. In the process of forming the front surface electrode of the silicon carbide semiconductor device, the ohmic electrode, the barrier metal, and the source electrode pad are formed as follows. First, n + Type source region and p ++ An ohmic electrode of NiSi (nickel silicide) is formed by annealing the nickel (Ni) film formed on the contact region. Next, a barrier metal film made of Ti (titanium) and TiN (titanium nitride) is formed on the ohmic electrode. Next, the barrier metal is exposed to the atmosphere once, and then an Al (aluminum) film or an Al-Si film is formed to form a source electrode pad. In this way, the barrier metal is exposed to the atmosphere once after it is formed, thereby improving the barrier properties of the barrier metal.

[0007] In addition, a method for manufacturing a silicon carbide semiconductor element is known in which a contact electrode made of Ni silicide is formed, Ti / TiN / Ti films are formed in that order on the contact electrode to form a barrier metal, and then a source electrode made of an Al-Si film is formed (see Patent Document 1 below).

[0008] In addition, a method for manufacturing a silicon carbide semiconductor element is known in which, for example, a sputtering method is used to stack a Ti film, a TiN film, and a Ti film in that order over the entire surface, followed by a predetermined heat treatment (sintering) to form a barrier metal layer and an Al-Si alloy film (see Patent Document 2 below).

[0009] Also, a method for manufacturing a silicon carbide semiconductor element is known in which a titanium nitride film is formed along the surface of an interlayer insulating film and the inner wall of a contact hole, for example by sputtering, a first nickel film is formed along the surface of the titanium nitride film and the inner wall of a contact hole, and rapid heat treatment is performed to enlarge the crystal grains of the titanium nitride film and prevent nickel from penetrating between the columnar crystal grains of the titanium nitride film from the first nickel film on the titanium nitride film (see Patent Document 3 below). [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2018-182032 A [Patent Document 2] JP 2016-111135 A [Patent Document 3] JP 2017-168684 A Summary of the Invention [Problem to be solved by the invention]

[0011] As described above, in the past, in order to improve the barrier properties of the barrier metal, after forming a barrier metal made of Ti and TiN, it was once exposed to the atmosphere and then an Al film or an Al-Si film was formed. However, this method has a problem that the barrier properties of the barrier metal are insufficient, and Ni in the ohmic electrode made of NiSi under the barrier metal passes through the barrier metal and seeps into the Al film or Al-Si film.

[0012] An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device that can improve the barrier properties of a barrier metal and prevent Ni of an ohmic electrode from passing through the barrier metal and seeping into an Al film or an Al-Si film. [Means for solving the problem]

[0013] In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step is performed to prepare a silicon carbide semiconductor substrate having a first semiconductor layer of a first conductivity type having a lower impurity concentration than the starting substrate on the front surface side of a starting substrate of a first conductivity type. Next, a second step is performed to form a second semiconductor layer of a second conductivity type on the surface of the first semiconductor layer opposite to the starting substrate. Next, a third step is performed to form an ohmic electrode on the surface of the second semiconductor layer. Next, a fourth step is performed to deposit a Ti film and a TiN film in this order on the surface of the ohmic electrode. Next, a fifth step is performed to heat-treat the Ti film and the TiN film to form a barrier metal. Next, a sixth step is performed to form a front surface electrode on the surface of the barrier metal. Next, a seventh step is performed to form a back surface electrode on the back surface of the silicon carbide semiconductor substrate. In the sixth step, the heat treatment is performed at a temperature of 550°C to 750°C.

[0014] In addition, the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, is characterized in that it includes an eighth step of forming a second TiN film on a surface of the barrier metal after the fifth step and before the sixth step, and in the sixth step, a surface electrode is formed on the surface of the second TiN film.

[0015] In addition, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the fourth step, the Ti film is formed to a thickness of 10 nm or more and 100 nm or less, and the TiN film is formed to a thickness of 50 nm or more and 200 nm or less.

[0016] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the fifth step, the heat treatment is performed in an inert gas or nitrogen atmosphere.

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A silicon carbide semiconductor substrate includes a first semiconductor layer of a first conductivity type, which has a lower impurity concentration than a starting substrate, on a front surface side of the starting substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. An ohmic electrode is provided on a surface of the second semiconductor layer. A barrier metal is provided on a surface of the ohmic electrode. A front surface electrode is provided on a surface of the barrier metal. A rear surface electrode is provided on a rear surface of the silicon carbide semiconductor substrate. The barrier metal is a TiN film and has a region where the concentration of N decreases within a range where the concentration of Ti is uniform.

[0018] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-mentioned invention, it further comprises a second TiN film provided between the barrier metal and the surface electrode, and the average crystallite diameter of the second TiN film is smaller than the average crystallite diameter of the barrier metal.

[0019] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a grain boundary extending from a surface of the barrier metal toward a bottom surface does not penetrate to the bottom surface.

[0020] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the average crystal grain size of the TiN film is not less than 12 nm and not more than 18 nm.

[0021] In addition, in the silicon carbide semiconductor device according to the present invention, the ohmic electrode is made of NiSi.

[0022] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the front surface electrode is made of Al or Al-Si.

[0023] According to the above-mentioned invention, after the Ti film and the TiN film are formed in this order, the Ti film and the TiN film are heat-treated to form a barrier metal. This randomizes the columnar structure of the barrier metal, increases the crystallite diameter, and prevents the growth of grain boundaries from the surface to the bottom of the TiN film, preventing the grain boundaries from penetrating to the bottom of the TiN film. The grain boundaries that serve as the path of Ni in the NiSi ohmic electrode are blocked, improving the barrier properties of the barrier metal. The improved barrier properties prevent Ni in the ohmic electrode from passing through the barrier metal and seeping into the source electrode pad made of an Al film or an Al-Si film. Effect of the Invention

[0024] The manufacturing method of a silicon carbide semiconductor device and the silicon carbide semiconductor device of the present invention have the effect of improving the barrier properties of the barrier metal and preventing Ni of the ohmic electrode from passing through the barrier metal and seeping into the Al film or Al-Si film. [Brief description of the drawings]

[0025] [Figure 1] 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to an embodiment; [Diagram 2] 1 is a cross-sectional view showing an observation result of a barrier metal of a conventional silicon carbide semiconductor device. [Diagram 3] 4 is a cross-sectional view showing an observation result of a barrier metal of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 4] 1 is a graph showing titanium concentrations under various conditions in which the annealing temperature of the barrier metal is changed in silicon carbide semiconductor devices according to the conventional art and the embodiment. [Diagram 5]1 is a graph showing nitrogen concentrations under various conditions in which the annealing temperature of the barrier metal of silicon carbide semiconductor devices according to the conventional and embodiments is changed. [Figure 6] 1 is a graph showing average crystallite diameters of TiN(111) under various conditions of annealing temperatures of barrier metals in silicon carbide semiconductor devices according to the conventional and embodiments; [Figure 7] FIG. 2 is a cross-sectional view showing another configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 8] 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views (part 1) illustrating schematic diagrams of a silicon carbide semiconductor device according to an embodiment during manufacture. [Figure 10] 5A to 5C are cross-sectional views (part 2) illustrating schematic diagrams of a silicon carbide semiconductor device according to the embodiment during manufacture. [Figure 11] 5A to 5C are cross-sectional views (part 3) illustrating schematic configurations of the silicon carbide semiconductor device according to the embodiment during manufacture. [Figure 12] 4 is a cross-sectional view (part 4) illustrating a schematic diagram of a silicon carbide semiconductor device according to the embodiment during manufacture. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] A preferred embodiment of the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before the index represents a negative index. In addition, the description of "same" or "equivalent" should include within ±5% in consideration of variations in manufacturing.

[0027] (Embodiment) The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a trench-type MOSFET 50 as an example. Fig. 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the embodiment. Fig. 1 shows only an active region of the trench-type MOSFET 50 through which a main current flows.

[0028] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has n + A first main surface (front surface) of a starting substrate (a silicon carbide semiconductor substrate of a first conductivity type) 1, for example, a (0001) surface (Si surface), is provided with an n + A first n-type buffer layer 16 and - A silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 2 is deposited on the semiconductor substrate.

[0029] n + The starting substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). + The mold buffer layer 16 has a thickness of, for example, 1 μm or more and 5 μm or less, and a nitrogen concentration of 1×10 17 / cm3 More than 1×10 18 / cm 3 It is a highly doped layer doped at a high concentration of n + The buffer layer 16 is a 1n - This promotes the recombination of holes from the n-type silicon carbide epitaxial layer 2. + The concentration of holes reaching the starting mold substrate 1 is controlled to suppress the occurrence of stacking faults and their area expansion.

[0030] 1st n - The silicon carbide epitaxial layer 2 is + The starting substrate 1 is doped with a lower impurity concentration, for example, nitrogen. - The 1n-type drift layer - The n-type silicon carbide epitaxial layer 2 + The surface side opposite to the mold starting substrate 1 side is the 2nth - A 2n-th type silicon carbide layer 6 is formed. - The silicon carbide layer 6 is + The starting substrate 1 is lower than the first n - The high-concentration n-type silicon carbide epitaxial layer 2 is doped with an impurity concentration higher than that of the n-type silicon carbide epitaxial layer 2, for example with nitrogen. - This is the n-type drift layer. + Starting substrates 1 and n - A silicon carbide epitaxial layer 2 and a second n - The p-type silicon carbide layer 6 and a p-type base layer 3 (described later) together constitute a silicon carbide semiconductor substrate.

[0031] n + A back electrode (drain electrode) is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base) of the mold starting substrate 1. The back electrode constitutes a drain electrode. A drain electrode pad (back electrode) 14 is provided on the surface of the back electrode.

[0032] A trench gate structure is formed on the first main surface side (p-type base layer 3 side) of the silicon carbide semiconductor substrate. + n from the surface on the first main surface side of the mold starting substrate 1 +The second n-type source region 7 and the p-type base layer 3 are connected to the - The gate insulating film 9 is formed on the bottom and side walls of the trench 18 along the inner wall of the trench 18, and the gate electrode 10 is formed on the inside of the gate insulating film 9 in the trench 18. The gate electrode 10 is formed by the gate insulating film 9. - Type silicon carbide epitaxial layer 2, 2n - The gate electrode 10 is insulated from the p-type silicon carbide layer 6 and the p-type base layer 3. A part of the gate electrode 10 may protrude from above the trench 18 (the source electrode pad 15 side) towards the source electrode pad 15.

[0033] 1st n - The n-type silicon carbide epitaxial layer 2 and the n-th - The inside of the first silicon carbide layer 6 is + Type region 4 and 2p + A mold region 5 is selectively provided. + The type region 4 reaches a position deeper on the drain side than the bottom of the trench 18. + The lower end (drain side end) of the mold region 4 is located closer to the drain side than the bottom of the trench 18. + The mold region 4 is provided between the trenches 18. As shown in FIG. + The type region 4 is a p ++ The p-type contact region 8 is in contact with the p ++ It is also possible for the first p-type contact region 8 not to be in contact with the first p-type contact region 8. + The 2n-th type region 4 - The first p + The upper surface of the type region 4 is in contact with the p-type base layer 3 .

[0034] 2nd p. + The lower end of the mold region 5 is located closer to the drain side than the bottom of the trench 18. + The mold region 5 is formed at a position facing the bottom of the trench 18 in the depth direction z. + The width of the mold region 5 is wider than the width of the trench 18. The bottom of the trench 18 is the second p +The p-type region 5 may extend between the p-type base layer 3 and the second p + The 2nth mold region 5 is sandwiched between - The second p + It is not necessary for the first p to be in contact with the mold region 5. + Type region 4 and 2p + The mold region 5 is doped with, for example, aluminum (Al).

[0035] 1st p. + A part of the mold region 4 is extended to the trench 18 side to form a second p + In this case, the first p + A part of the mold region 4 is the first p + Type region 4 and 2p + In the direction x in which the mold regions 5 are arranged (hereinafter referred to as the first direction) and in the direction y perpendicular to the direction x (hereinafter referred to as the second direction), - The first p-type silicon carbide layers 6 may be arranged alternately in a plane layout. + Part of type region 4 and 2p + It is sufficient that a part of the mold region 5 is connected at least at one or more places. + Type 5 and 1n regions - Holes generated when avalanche breakdown occurs at the junction of the silicon carbide epitaxial layer 2 can be efficiently evacuated to the ohmic electrode 13, and the load on the gate insulating film 9 is reduced, thereby improving reliability.

[0036] 1st n - A p-type base layer (a second semiconductor layer of a second conductivity type) 3 is provided on the first main surface side of the silicon carbide epitaxial layer 2. The impurity concentration of the p-type base layer 3 is, for example, + The impurity concentration of the p-type base layer 3 may be lower than that of the n-type region 4. This makes it possible to prevent a decrease in breakdown voltage due to punch-through by suppressing the spread of the depletion layer in the p-type base layer 3 even if the concentration is reduced to lower the threshold voltage. + Type source region 7 and p ++A contact region 8 is selectively provided. + Type source region 7 and p ++ The mold contact regions 8 abut each other.

[0037] Although FIG. 1 illustrates only two trench MOS structures, more trench MOS gate (insulated gate made of metal-oxide-semiconductor) structures may be arranged in parallel.

[0038] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the trench 18. The ohmic electrode (source electrode) 13 is connected to the n-type ohmic electrode 10 via a contact hole opened in the interlayer insulating film 11. + Type source region 7 and p ++ The ohmic electrode 13 is in contact with the type contact region 8. The ohmic electrode 13 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. On the ohmic electrode 13, a source electrode pad (front surface electrode) 15 is provided.

[0039] In addition, a barrier metal 20 for preventing diffusion of metal atoms from, for example, the ohmic electrode 13 toward the gate electrode 10 is provided between the ohmic electrode 13 and the interlayer insulating film 11 on the one hand and the source electrode pad 15 on the other. The barrier metal 20 is formed by depositing a Ti film and a TiN film in this order and then performing a heat treatment, so that the Ti film is nitrided to become a TiN film.

[0040] FIG. 2 is a cross-sectional view showing the observation result of the barrier metal of a conventional silicon carbide semiconductor device. FIG. 3 is a cross-sectional view showing the observation result of the barrier metal of a silicon carbide semiconductor device according to the embodiment. FIG. 2 shows a case where a barrier metal 120 consisting of a Ti film 121 having a thickness of about 20 nm and a TiN film 122 having a thickness of about 70 nm is formed, and then exposed to the atmosphere once, and then a source electrode pad 115 consisting of an Al film or an Al-Si film is formed. As shown in FIG. 2, the barrier metal 120 has a columnar structure consisting of columnar crystal grains grown in a direction perpendicular to the front surface of the substrate in both the TiN film 122 and the Ti film 121, and a grain boundary 125 extending from the surface to the bottom surface in the TiN film 122 penetrates to the bottom surface of the TiN film 122 and reaches the surface of the Ti film 121.

[0041] In contrast, Fig. 3 shows a case where, in the manufacturing method according to the embodiment, a barrier metal 20 consisting of a Ti film 21 having a thickness of about 20 nm and a TiN film 22 having a thickness of about 70 nm is formed, annealed at 650°C, and then a source electrode pad 15 consisting of an Al film or an Al-Si film is formed. As shown in Fig. 3, the columnar structure of the barrier metal 20 becomes random, the boundary between the TiN film 22 and the Ti film 21 is not visible, and the grain boundary 25 extending from the surface to the bottom surface in the TiN film 22 is blocked by other crystal grains and does not penetrate to the bottom surface of the TiN film 22. Also, while the TiN film 22 has a columnar structure, the Ti film 21 has a granular structure.

[0042] Fig. 4 is a graph showing titanium concentrations under various conditions of annealing temperatures of the barrier metal of silicon carbide semiconductor devices according to the conventional and embodiments. In Fig. 4, the vertical axis shows Ti concentration in units of at% (atomic percent). The horizontal axis shows depth from the surface of the barrier metal 20. Fig. 4 shows Ti concentrations without annealing (conventional) after deposition of the barrier metal 20, and at annealing temperatures of 450°C, 550°C, and 650°C.

[0043] Fig. 5 is a graph showing the nitrogen concentration under various conditions of annealing temperatures of the barrier metal of silicon carbide semiconductor devices according to the conventional and embodiments. In Fig. 5, the vertical axis shows the N concentration in at%. The horizontal axis shows the depth from the surface of the barrier metal 20. Fig. 5 shows the N concentration when no annealing is performed (conventional) after the barrier metal 20 is formed, and when the annealing temperatures are 450°C, 550°C, and 650°C.

[0044] 4 and 5, in the region of the barrier metal 20 that was the TiN film 22, the concentrations of Ti and N are almost constant, while in the region that was the Ti film 21, N is diffused and nitrided, and the concentration of N gradually decreases with increasing depth from the surface. When no annealing is performed or when annealing is performed at 450°C, the concentration of N is constant in the range (E1) where the concentration of Ti is uniform. On the other hand, when annealing is performed at 550°C and 650°C, the nitridation of the Ti film 21 progresses, and there is a region (E3) where the concentration of N decreases in the range (E2) where the concentration of Ti is uniform. Furthermore, the concentration of N is 30 at% or more at a position half the thickness of the Ti film 21.

[0045] Fig. 6 is a graph showing the average crystallite diameter of TiN(111) under various conditions of annealing temperature of the barrier metal of silicon carbide semiconductor devices according to the conventional and embodiments. In Fig. 6, the vertical axis shows the average crystallite diameter of TiN(111) in units of nm. The horizontal axis shows the annealing temperature and the film thickness of Ti film 21 and TiN film 22. For example, 20 / 70 nm indicates that the film thickness of Ti film 21 is 20 nm and the film thickness of TiN film 22 is 70 nm.

[0046] 6, when annealed under conditions of 550° C. to 650° C., the average crystallite diameter of TiN is 12 nm to 16 nm. Also, although not shown, when annealed under conditions of 550° C. to 750° C., the average crystallite diameter of TiN(111) is 12 nm to 18 nm. By increasing the crystallite diameter in this way, it is possible to prevent the growth of the grain boundaries 25 from the surface toward the bottom surface in the TiN film 22, and to prevent the grain boundaries 25 from penetrating to the bottom surface of the TiN film 22.

[0047] As described above, in the embodiment, the grain boundaries 25 of the barrier metal 20, which serve as paths for Ni in the underlying NiSi ohmic electrode 13, are blocked, improving the barrier properties of the barrier metal 20. The improved barrier properties can prevent Ni in the ohmic electrode 13 from passing through the barrier metal 20 and seeping out into the source electrode pad 15 made of an Al film or an Al-Si film.

[0048] 7 is a cross-sectional view showing another configuration of the silicon carbide semiconductor device according to the embodiment. As shown in FIG. 7, a second TiN film 23 may be provided between the barrier metal 20 and the source electrode pad 15. The second TiN film 23 is preferably thinner than the barrier metal 20. The second TiN film 23 is formed after the barrier metal 20 is formed, and is not annealed. Therefore, the average crystallite diameter of TiN(111) in the second TiN film 23 is less than 12 nm, which is smaller than the average crystallite diameter of TiN(111) in the barrier metal 20. The barrier property of the barrier metal 20 can be further improved by the second TiN film 23.

[0049] (Method of Manufacturing Silicon Carbide Semiconductor Device According to an Embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Fig. 8 is a flowchart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figs. 9 to 12 are cross-sectional views each showing a schematic state during the manufacturing process of a silicon carbide semiconductor device according to an embodiment.

[0050] First, n-type silicon carbide + A mold starting substrate 1 is - The n-type silicon carbide epitaxial layer 2 and + A silicon carbide semiconductor substrate 34 (see FIG. 1) on which a type buffer layer 16 is deposited is prepared (first step). This silicon carbide semiconductor substrate 34 may be purchased or may be purchased from a third party. + Purchase a substrate containing only the starting substrate 1 and grow n + The first n-type buffer layer 16 and - The n-type silicon carbide epitaxial layer 2 may be formed to form the above-mentioned silicon carbide semiconductor substrate 34. In this case, + On the first main surface of the starting substrate 1, an n-type impurity such as nitrogen (N) is doped into a silicon carbide n-type semiconductor layer. + The n-type buffer layer 16 is then epitaxially grown. + A first n-type buffer layer 16 is formed on the buffer layer 16 by doping with n-type impurities, such as nitrogen atoms, and the first n-type buffer layer 16 is formed on the buffer layer 16 by doping with n-type impurities, such as nitrogen atoms. - A silicon carbide epitaxial layer 2 is grown.

[0051] Next, impurity ions are selectively implanted into the surface of the silicon carbide semiconductor substrate 34 (step S1: second step). As a result, impurity regions (for example, the p-type base layer 3, the first p + Type area 4, 2nd p + Type area 5, 2nd n - Type silicon carbide layer 6, n + Type source region 7, p ++ These impurity regions are formed as follows.

[0052] First, the 1nth - A resist mask (not shown) having desired openings is formed on the surface of the silicon carbide epitaxial layer 2 by photolithography. Then, p-type impurities, for example, aluminum atoms, are ion-implanted to form a first n-type silicon carbide epitaxial layer. - A first p-type silicon carbide epitaxial layer 2 has a thickness of about 0.6 μm. + Type area 4, 2nd p + The mold region 5 is, for example, 1 to 5 × 1018 / cm 3 The impurity concentration is .

[0053] Next, the 1nth - A resist mask (not shown) having a desired opening is formed by photolithography on the surface of the silicon carbide epitaxial layer 2. Then, a second n-type epitaxial layer having a thickness of about 0.7 μm and doped with n-type impurities such as nitrogen by ion implantation is formed. - The silicon carbide layer 6 is, for example, 1 to 3×10 17 / cm 3 The 2nth - The silicon carbide layer 6 is a 1n - The second epitaxial layer 2 may be formed by epitaxial growth on the surface of the second silicon carbide epitaxial layer 2 .

[0054] Next, n - A resist mask (not shown) having desired openings is formed by photolithography on the surface of the silicon carbide epitaxial layer 2. Then, a p-type base layer 3 having a thickness of about 0.5 μm is formed by ion implantation, for example, with 1 to 5×10 17 / cm 3 The p-type base layer 3 is formed with an impurity concentration of 2n - The second insulating layer 14 may be formed on the surface of the silicon carbide layer 6 by epitaxial growth.

[0055] Next, a resist mask (not shown) having desired openings is formed by photolithography on the surface of the p-type base layer 3. Then, n-type ions having a thickness of about 0.5 μm are implanted by ion implantation. + The mold source layer 7 is, for example, 1 to 3 × 10 19 / cm 3 The impurity concentration is .

[0056] Next, an ion implantation mask having a predetermined opening is formed, and n + A p-type impurity such as aluminum is ion-implanted into a part of the p-type source layer 7 and a part of the p-type base layer 3. ++ The contact region 8 is, for example, 1 to 3 × 10 20 / cm 3The state up to this point is shown in FIG.

[0057] Next, a heat treatment is performed in an inert gas atmosphere at about 1750° C. to activate the impurity regions formed by ion implantation. Note that each ion implantation region may be activated collectively by a single heat treatment, or activation may be performed by performing a heat treatment each time an ion implantation is performed.

[0058] Next, n + A trench forming mask having a predetermined opening is formed on the surface of the source region 7 by photolithography, for example, an oxide film. + The second p-type source region 7 and the p-type base layer 3 are penetrated. + A trench 18 is formed so as to reach the mold region 5 (step S2). Next, the trench forming mask is removed. The state up to this point is shown in FIG.

[0059] After forming the trench 18, isotropic etching may be performed to remove damage to the trench 18, and sacrificial oxidation may be performed to round the corners of the bottom of the trench 18 and the opening of the trench 18. Only one of isotropic etching and sacrificial oxidation may be performed. Also, sacrificial oxidation may be performed after isotropic etching. This makes it possible to present a clean surface of the silicon carbide, and by rounding the corners, electric field concentration at the bottom and opening of the trench 18 can be suppressed.

[0060] Next, the gate insulating film 9, the gate electrode 10, the interlayer insulating film 11, and the ohmic electrode 13 are formed (Step S3: third process). These are formed as follows. + Type source region 7 and p ++A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1300° C. in a gas atmosphere containing oxygen. Alternatively, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0061] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 18 to form the gate electrode 10.

[0062] Next, an insulating film is formed on the surface of the gate electrode 10. For example, annealing is performed in an oxygen atmosphere at 1000°C to form a thermal oxide film. Next, the surface is protected with a protective film, for example, formed of a photoresist. Next, the insulating film formed on the back surface, the gate electrode, and the gate insulating film are all removed by dry etching. Next, the protective film formed on the surface is removed in an ashing and stripping process. This time, ashing in oxygen plasma and stripping using an SPM were performed.

[0063] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. Next, the interlayer insulating film 11 and the gate insulating film 10 are patterned by photolithography. + Type source region 7 and p ++ A contact hole is formed to expose the n-type contact region 8. Next, a conductive film, for example, nickel, which becomes the ohmic electrode 13 is formed in the contact hole and on the interlayer insulating film 11 by, for example, a sputtering method. Next, a heat treatment at about 1000° C. is performed to selectively react the conductive film with silicon carbide, and then the unreacted conductive film is selectively removed to leave the ohmic electrode 13 only in the contact hole, and the n-type contact region 8 is formed. + Type source region 7 and p ++ The contact region 8 is brought into contact with an ohmic electrode 13 .

[0064] Next, the Ti film 21 and the TiN film 22 are formed in this order (step S4: fourth process). The Ti film 21 is formed on the surfaces of the ohmic electrode 13 and the interlayer insulating film 11, and then the TiN film 22 is formed on the surface of the Ti film 21. For example, the Ti film 21 is formed to a thickness of 10 nm or more and 100 nm or less, and the TiN film 22 is formed to a thickness of 50 nm or more and 200 nm or less. The state up to this point is shown in FIG. 11.

[0065] Next, the Ti film 21 and the TiN film 22 are annealed (heat treated) to form the barrier metal 20 (step S5: fifth process). For example, the Ti film 21 and the TiN film 22 are annealed in a vertical furnace. The annealing conditions are preferably in an Ar (argon) or N2 atmosphere, at 550°C to 750°C, and for 5 minutes to 20 minutes. The annealing temperature must be lower than the heat treatment temperature of about 1000°C when forming the ohmic electrode 13. The state up to this point is shown in FIG. 12. This heat treatment makes the columnar structure of the barrier metal 20 random as shown in FIG. 3, and the average crystallite diameter of TiN (111) of the barrier metal 20 becomes 12 nm to 18 nm as shown in FIG. 6. After this annealing, a second TiN film 23 having a thickness thinner than that of the Ti film 21 may be formed on the surface of the TiN film 22.

[0066] Next, a metal film to become the source electrode pad 15 is formed on the barrier metal 20 by, for example, a sputtering method. For example, an Al-Si film is formed by a DC magnetron sputtering film forming apparatus. The sputtering conditions are Ar gas, gas pressure of 0.1 to 1.0 Pa, wafer heating temperature of 300 to 450°C, DC sputtering power of 12 kW, and film formation time is adjusted so that the film thickness is 3 to 7 μm.

[0067] The thickness of the electrode pad on the interlayer insulating film 11 may be, for example, 5.5 μm. The electrode pad may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the metal film is selectively removed to form the source electrode pad 15 (step S6: sixth process).

[0068] Next, n + After the front surface of the mold starting substrate 1 is covered with a protective film (not shown) for protection, + The starting substrate 1 is polished from the back side to form a n + The starting mold substrate 1 may be thinned to the product thickness.

[0069] Next, n + On the second main surface of the starting substrate 1, a conductive film that will become a drain electrode (not shown), such as a molybdenum film and a nickel film, is successively formed by, for example, a sputtering method. Then, a heat treatment such as laser annealing is performed to form a n + The starting mold substrate 1 and a conductive film are reacted to form an ohmic junction, thereby forming a drain electrode.

[0070] Next, on the surface of the drain electrode, films of, for example, titanium, nickel and gold are formed in this order as drain electrode pad 14 (seventh step) In this manner, the silicon carbide semiconductor device shown in FIG.

[0071] As described above, according to the embodiment, after the Ti film and the TiN film are formed in this order, the Ti film and the TiN film are heat-treated to form the barrier metal. This randomizes the columnar structure of the barrier metal, increases the crystallite diameter, and prevents the grain boundary from growing from the surface to the bottom in the TiN film, so that the grain boundary does not penetrate to the bottom of the TiN film. The grain boundary that serves as the path of Ni in the NiSi ohmic electrode is blocked, improving the barrier property of the barrier metal. The improved barrier property prevents Ni in the ohmic electrode from passing through the barrier metal and seeping into the source electrode pad made of an Al film or an Al-Si film.

[0072] The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-mentioned embodiments, for example, the dimensions and impurity concentration of each part are set in various ways according to the required specifications. In each of the embodiments, a trench-type MOSFET is used as an example, but the present invention can also be applied to a planar-type MOSFET, and further, to various semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor) and a diode. In each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0073] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and manufacturing method thereof according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and automobile igniters. [Explanation of symbols]

[0074] 1n + Starting substrate 2 1stn - Silicon carbide epitaxial layer 3 p-type base layer 4 1st p. + type area 5 2nd p. + type area 6 2nd n - mold silicon carbide layer 7 n + Type Source Area 8 p ++ Mold Contact Area 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 13 Ohmic electrode (source electrode) 14 Drain electrode pad 15 Source electrode pad 16n + Mold Buffer Layer 18 Trench 20, 120 Barrier metal 21, 121 Ti film 22, 122 TiN film 23 Second TiN film 25, 125 grain boundaries 34 Silicon carbide substrate Semiconductor substrate 50 Trench MOSFET

Claims

1. A first step of preparing a silicon carbide semiconductor substrate having a first conductivity type starting substrate and a first semiconductor layer having a lower impurity concentration than the starting substrate provided on a front surface side of the first conductivity type starting substrate; a second step of forming a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer opposite to the starting substrate; a third step of forming an ohmic electrode on a surface of the second semiconductor layer; a fourth step of depositing a Ti film and a TiN film in this order on a surface of the ohmic electrode; a fifth step of heat treating the Ti film and the TiN film to form a barrier metal; a sixth step of forming a surface electrode on the surface of the barrier metal; A seventh step of forming a back surface electrode on a back surface of the silicon carbide semiconductor substrate; Including, The sixth step comprises performing the heat treatment at a temperature of 550° C. or more and 750° C. or less.

2. After the fifth step and before the sixth step, an eighth step of forming a second TiN film on a surface of the barrier metal; 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein in said sixth step, a surface electrode is formed on a surface of said second TiN film.

3. 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein in the fourth step, the Ti film is formed to a thickness of 10 nm or more and 100 nm or less, and the TiN film is formed to a thickness of 50 nm or more and 200 nm or less.

4. 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein in the fifth step, the heat treatment is performed in an inert gas or nitrogen atmosphere.

5. a silicon carbide semiconductor substrate having a first conductivity type starting substrate and a first semiconductor layer having a lower impurity concentration than the starting substrate provided on a front surface side of the first conductivity type starting substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; an ohmic electrode provided on a surface of the second semiconductor layer; a barrier metal provided on a surface of the ohmic electrode; a surface electrode provided on a surface of the barrier metal; a back surface electrode provided on a back surface of the silicon carbide semiconductor substrate; Equipped with The silicon carbide semiconductor device according to claim 1, wherein the barrier metal is a TiN film and has a region in which the concentration of N decreases within a range in which the concentration of Ti is uniform.

6. a second TiN film provided between the barrier metal and the front surface electrode; 6. The silicon carbide semiconductor device according to claim 5, wherein an average crystallite diameter of the second TiN film is smaller than an average crystallite diameter of the barrier metal.

7. 6. The silicon carbide semiconductor device according to claim 5, wherein a grain boundary extending from a surface of the barrier metal toward a bottom surface does not penetrate to the bottom surface.

8. 6. The silicon carbide semiconductor device according to claim 5, wherein the TiN film has an average crystal grain size of 12 nm or more and 18 nm or less.

9. The silicon carbide semiconductor device according to claim 5 , wherein the ohmic electrode is made of NiSi.

10. 6. The silicon carbide semiconductor device according to claim 5, wherein the surface electrode is made of Al or Al--Si.

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