Wiring board

Abstract

To improve reliability of a wiring board.SOLUTION: A wiring board 1 of an embodiment includes a first surface 1F, and contains: a first build-up part 10; and a second build-up part 20. The first build-up part 10 is laminated onto the first surface 1F of the second build-up part 20, and is smaller than the second build-up part 20 in a plan view, and is embedded into an insulation layer 21a thereof. A conductive layer 12 in the first build-up part 10 and a conductive layer 22 in the second build-up part 20 are alternately connected, and the second build-up part 20 contains a wiring 22w formed over a region overlapping the first build-up part 10 and a region of the outside thereof. A minimum wiring width of a wiring 12f in the first build-up part 10 is smaller than a minimum wiring width of a wiring 22a in the second build-up part 20, and is 3 μm or less. The minimum interval of both the wirings 12f is smaller than that of both the wirings 22a, and is 3 μm or less, and an aspect ratio of the wiring 12f is 2.0 or more and 4.0 or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a wiring board including a second wiring board made of a build-up wiring layer and a first wiring board joined to the second wiring board and including a wiring pattern that is finer than the wiring pattern formed on the second wiring board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-4926 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board disclosed in Patent Document 1, the first wiring board and the second wiring board are connected via solder bumps. Thermal stress caused by temperature change may cause cracks in the solder bumps, which may result in insufficient connection reliability of the wiring boards. [Means for solving the problem]

[0005] The wiring board of the present invention has a first surface and a second surface opposite the first surface, and includes a first build-up portion including alternating stacked insulating layers and conductor layers, and a second build-up portion including alternating stacked insulating layers and conductor layers and via conductors. the first buildup portion is laminated on the first surface side of the second buildup portion, the first buildup portion is smaller than the second buildup portion in a planar view and is embedded in an insulating layer of the second buildup portion, a conductor layer in the first buildup portion and a conductor layer in the second buildup portion are connected to each other by the via conductor, the second buildup portion includes wiring formed across an area overlapping with the first buildup portion and an area outside the first area and connected to the via conductor, a surface on the first surface side of the first buildup portion is exposed on the first surface and includes one or more component areas to be covered by mounted components when the wiring board is used, a minimum wiring width of the wiring included in the first buildup portion is smaller than the minimum wiring width of the wiring included in the second buildup portion and is 3 μm or less, a minimum spacing between the wiring included in the first buildup portion is smaller than the minimum spacing between the wiring included in the second buildup portion and is 3 μm or less, and an aspect ratio of the wiring included in the first buildup portion is 2.0 or more and 4.0 or less.

[0006] According to an embodiment of the present invention, it may be possible to improve the reliability of a wiring board including a plurality of conductor layers having different wiring densities. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a plan view of the wiring board of FIG. [Diagram 3] An enlarged view of part III in Fig. 1 . [Figure 4] 1. FIG. 4 is a cross-sectional view showing a modified example of the wiring board of FIG. [Diagram 5] 1. FIG. 4 is an enlarged cross-sectional view showing a modification of the first buildup portion of the wiring board of FIG. [Figure 6A]4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 6B] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 6C] FIG. 4 is an enlarged cross-sectional view showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 6D] FIG. 4 is an enlarged cross-sectional view showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 6E] FIG. 4 is an enlarged cross-sectional view showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 6F] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 6G] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 7] FIG. 4 is a plan view showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 8A] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 8B] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 8C] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 8D] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 8E] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 8F] 4A to 4C are cross-sectional views showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 9] FIG. 4 is a plan view showing an example of a state during manufacturing of the wiring board according to the embodiment. [Figure 10A] 11 is an enlarged cross-sectional view showing another example of a state during manufacturing of the wiring board according to the embodiment. FIG. [Figure 10B] 11 is an enlarged cross-sectional view showing another example of a state during manufacturing of the wiring board according to the embodiment. FIG. [Figure 10C] 11 is an enlarged cross-sectional view showing another example of a state during manufacturing of the wiring board according to the embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] <Structure of wiring board according to embodiment> A wiring board according to an embodiment will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1, which is an example of a wiring board according to an embodiment. FIG. 2 shows an example of the appearance of the wiring board 1 in a plan view as a plan view of the wiring board 1 in FIG. 1. FIG. 1 is a cross-sectional view taken along a line II in FIG. 2. Furthermore, FIG. 3 shows an enlarged view of part III in FIG. 1. "Planar view" means that an object is viewed with a line of sight along the thickness direction of the wiring board 1. Note that the wiring board 1 is merely an example of the wiring board according to this embodiment. The number and thickness of each of the conductor layers and insulating layers in the wiring board according to this embodiment, and the conductor patterns included in each conductor layer are not limited to the number and thickness of each of the conductor layers and insulating layers included in the wiring board 1 in FIG. 1, and the conductor patterns. In addition, in each drawing referred to in the following description, a specific portion may be drawn enlarged so that the disclosed embodiment can be easily understood, and the components may not be drawn at the exact ratio between each other in terms of size and length.

[0009] As shown in FIG. 1 and FIG. 2, the wiring board 1 includes a first buildup section 10 and a second buildup section 20 that are laminated. The wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite to the first surface 1F) that are perpendicular to the thickness direction of the wiring board 1. The first buildup section 10 entirely overlaps with the second buildup section 20 in a plan view. The second buildup section 20 partially overlaps with the first buildup section 10 in a plan view. The first buildup section 10 is smaller than the second buildup section 20 in a plan view. The first buildup section 10 is located closer to the first surface 1F of the wiring board 1 than the portion of the second buildup section 20 that overlaps with the first buildup section 10. That is, the first buildup section 10 is laminated on the first surface 1F side of the second buildup section 20. 1 further includes a third buildup section 30 laminated on the second surface 1B side of the wiring board 1 in the second buildup section 20, and a solder resist 40 covering the surface of the third buildup section 30. The wiring board of the present embodiment is preferably a coreless wiring board that does not include a core layer, like the wiring board 1 of FIG.

[0010] In the description of the wiring board 1 of this embodiment, the first surface 1F side of the wiring board 1 is also referred to as the "top" or "upper side", and the second surface 1B side of the wiring board 1 is also referred to as the "bottom" or "lower side". In addition, the surface of each component facing the first surface 1F side of the wiring board 1 is also referred to as the "top surface", and the surface facing the second surface 1B side of the wiring board 1 is also referred to as the "bottom surface".

[0011] The first buildup section 10 has a first surface 10F, which is the surface on the first surface 1F side of the wiring board 1, and a second surface 10B, which is the surface opposite to the first surface 10F. The first buildup section 10 includes conductor layers 12 and insulating layers 11, which are alternately stacked, and via conductors 13 that penetrate each insulating layer 11. The first buildup section 10 further includes a conductor layer 12a, which is the conductor layer in the first buildup section 10 closest to the first surface 1F of the wiring board 1. Each of the conductor layers 12 and the conductor layer 12a includes an arbitrary conductor pattern. The conductor layer 12a is embedded in the insulating layer 11 closest to the first surface 1F of the wiring board 1 in the first buildup section 10, and the upper surface of the conductor layer 12a is exposed to the first surface 10F. The exposed upper surface of the conductor layer 12a and the upper surface of the insulating layer 11 closest to the first surface 1F of the wiring board 1 in the first buildup section 10 form the first surface 10F of the first buildup section 10.

[0012] Each conductor layer 12 is formed on the lower surface of the insulating layer 11 adjacent to the upper side. Each insulating layer 11 covers a portion of the lower surface of the insulating layer 11 adjacent to the upper side that is not covered by the conductor layer 12, and covers the lower surface and side surfaces of each conductor pattern of the conductor layer 12 covering the lower surface. Each via conductor 13 connects the lower conductor layer 12 of each insulating layer 11 including the via conductor 13 to the upper conductor layer 12 or conductor layer 12a. Each via conductor 13 is formed integrally with the conductor layer 12 that is in contact with it on the second surface 1B side of the wiring board 1.

[0013] The second buildup section 20 has a first surface 20F, which is the surface on the first surface 1F side of the wiring board 1, and a second surface 20B, which is the surface opposite to the first surface 20F. The second buildup section 20 includes conductor layers 22 and insulating layers 21, which are alternately stacked, and via conductors 23 that penetrate each insulating layer 21. The second buildup section 20 further includes an insulating layer 21a, which is the insulating layer closest to the first surface 20F side of the second buildup section 20, and a via conductor 23a that penetrates the insulating layer 21a. Each conductor layer 22 is formed on the lower surface of the insulating layer 21 or insulating layer 21a adjacent to the upper side of the respective conductor layers 22. In addition, each insulating layer 21 covers a portion of the lower surface of the insulating layer 21 or insulating layer 21a adjacent to the upper side of the respective conductor layers 22 that is not covered by the conductor layer 22, and covers the lower surface and side surfaces of each conductor pattern of the conductor layer 22 that covers the lower surface.

[0014] Each conductor layer 22 in the second buildup section 20 includes an arbitrary conductor pattern. In the example of Fig. 1 and Fig. 2, the conductor layer 22 in the second buildup section 20 closest to the first buildup section 10 includes wiring 22w. The wiring 22w is formed across a region overlapping with the first buildup section 10 in a plan view and a region outside the region (i.e., a region outside the first buildup section 10). The wiring 22w is connected to each conductor layer 12 and conductor layer 12a of the first buildup section 10 through via conductors 23a.

[0015] Each via conductor 23 connects the lower conductor layer 22 of the insulating layer 21 in which the via conductor 23 is included to the upper conductor layer 22. The via conductor 23a connects the conductor layer 12 and the conductor layer 22 as described later. Each via conductor 23 and the via conductor 23a are integrally formed with the conductor layer 22 that contacts them on the second surface 1B side of the wiring board 1. The first surface 20F of the second buildup section 20 is formed by the surface of the insulating layer 21a on the first surface 1F side of the wiring board 1. On the other hand, the second surface 20B of the second buildup section 20 is formed by the lower surfaces of the insulating layer 21 and the conductor layer 22 that are closest to the second surface 1B side of the wiring board 1 in the second buildup section 20. The second surface 20B of the second buildup section 20 faces the surface (upper surface) of the third buildup section 30 on the first surface 1F side of the wiring board 1.

[0016] The first buildup section 10 is embedded in the insulating layer 21a of the second buildup section 20, and the first surface 10F is exposed on the first surface 1F of the wiring board 1. In a plan view, the first buildup section 10 is surrounded by the second buildup section 20 (specifically, by the insulating layer 21a). The first surface 1F of the wiring board 1 is composed of the first surface 10F of the first buildup section 10 and the first surface 20F of the second buildup section 20. The first surface 10F of the first buildup section 10 includes one or more component regions (component regions Ea1 and Ea2 in the example of FIG. 1) that are covered by mounted components (components E1 and E2 in the example of FIG. 1) when the wiring board 1 is used. That is, the first surface 1F of the wiring board 1 is a component mounting surface of the wiring board 1.

[0017] Therefore, the first buildup section 10 includes a component mounting pad 12p made of a conductor pad in the conductor layer 12a. The component mounting pad 12p is embedded in the insulating layer 11 constituting the first surface 10F of the first buildup section 10, and one surface of the component mounting pad 12p is exposed on the first surface 10F. The exposed surface of the component mounting pad 12p may be connected to an electrode of a mounted component by, for example, a conductive bonding material (not shown) such as solder. A surface treatment layer (not shown) made of a plating layer containing, for example, nickel, palladium, and gold may be formed on the exposed surface of the component mounting pad 12p. A conductor pattern such as a wiring 12w that connects adjacent component regions Ea1 and Ea2 may be formed on the conductor layer 12 in the first buildup section 10. When the wiring board of the embodiment is used, it is considered that mounted components such as the components E1 and E2 in FIG. 1 are electrically connected to each other through a short path.

[0018] Examples of the components E1 and E2 that can be mounted on the wiring board 1 include electronic components such as active components such as semiconductor integrated circuit devices and transistors. As some examples, the components E1 and E2 can be integrated circuit devices such as logic chips, processing devices such as MPUs (Micro Processor Units), and memory devices such as HBMs (High Bandwidth Memory).

[0019] On the other hand, the second surface 10B and side surfaces of the first buildup portion 10 are covered with an insulating layer 21a of the second buildup portion 20. The conductor layer 12 in the first buildup portion 10 closest to the second buildup portion 20 (i.e., closest to the second surface 1B of the wiring board 1) and the conductor layer 22 in the second buildup portion 20 closest to the first buildup portion 10 are connected to each other by via conductors 23a in the second buildup portion 20. The second surface 10B of the first buildup portion 10 faces the upper surfaces of the via conductors 23a.

[0020] The third buildup section 30 includes an insulating layer 31, a conductor layer 32, and a via conductor 33, which are stacked one on the other. The conductor layer 32 includes an arbitrary conductor pattern such as a conductor pad 32p. The via conductor 33 connects the conductor layer 32 to the conductor layer 22 closest to the second surface 20B among the conductor layers 22 included in the second buildup section 20. The via conductor 33 is formed integrally with the conductor layer 32.

[0021] The solder resist 40 is formed on the surface of each of the insulating layer 31 and the conductor layer 32 on the second surface 1B side of the wiring board 1. Openings 41 are formed in the solder resist 40, and the conductor pads 32p of the third build-up section 30 are exposed from the openings 41. The solder resist 40 is formed using, for example, a photosensitive polyimide resin or an epoxy resin.

[0022] 1, second side 1B of wiring board 1 consists of the surface of solder resist 40 on the second side 1B side of wiring board 1 and an exposed surface of conductor layer 32 exposed from solder resist 40. The wiring board of this embodiment does not necessarily include third buildup portion 30 and / or solder resist 40. Second side 1B of a wiring board of an embodiment that does not include third buildup portion 30 consists of second side 20B of second buildup portion 20, or solder resist 40 and an exposed portion of second side 20B of second buildup portion 20 that is exposed from solder resist 40.

[0023] The second surface 1B of the wiring board 1 can be a connection surface to be connected to an external element when the wiring board 1 itself is mounted on an external element such as an external wiring board (for example, a motherboard of an electric device). In the example of Fig. 1, the conductor pad 32p of the third buildup section 30 can be connected to an arbitrary board, electric component, mechanical component, or the like.

[0024] The insulating layer 11 of the first buildup section 10, the insulating layers 21 and 21a of the second buildup section 20, and the insulating layer 31 of the third buildup section 30 may be formed using a thermosetting insulating resin such as an epoxy resin, a bismaleimide triazine resin (BT resin), and a phenol resin. The insulating layers 11, 21, 21a, and 31 may be formed using a thermoplastic insulating resin such as a fluororesin, a liquid crystal polymer (LCP), a fluoroethylene resin (PTFE), a polyester resin (PE), or a modified polyimide resin (MPI). The insulating layers 11, 21, 21a, and 31 may contain the same insulating resin or different insulating resins. The first buildup section 10 and the second buildup section 20 may each contain an insulating layer containing a different insulating resin.

[0025] The insulating layers 11, 21, 21a, and 31 may contain a core material (reinforcing material) made of glass fiber or the like. In the example of FIG. 1, the insulating layer 31 contains a core material 31a. The core material 31a may impart appropriate rigidity to the wiring board 1. The core material 31a may be, for example, glass fiber or aramid fiber. On the other hand, each insulating layer that does not contain a core material such as glass fiber may facilitate the formation of fine wiring on its surface or increase adhesion with a conductor layer. In the example of FIG. 1, the insulating layers 11, 21, and 21a of the first buildup section 10 or the second buildup section 20 do not contain a core material.

[0026] Although omitted in FIG. 1, the insulating layers 11, 21, 21a, and 31 may further include an inorganic filler made of fine particles such as silica (SiO2), alumina, or mullite. As shown in FIG. 3, in the wiring board 1, the insulating layer 11 included in the first buildup section 10 includes an inorganic filler 11f, and the insulating layers 21 and 21a included in the second buildup section 20 both include an inorganic filler 21f. In the example of FIG. 3, the maximum particle size of the inorganic filler 11f included in the first buildup section 10 is smaller than the maximum particle size of the inorganic filler 21f included in the second buildup section 20. Note that the "particle size" of each of the inorganic fillers 11f and 21f is the longest distance between two points on the surface of each inorganic filler. For example, the insulating layer 11 may include a plurality of inorganic fillers 11f having a maximum particle size of 1 μm or less.

[0027] When the particle size of the inorganic filler contained in each insulating layer is small, short-circuit defects due to leak paths along the inorganic filler may be less likely to occur between wirings arranged at fine intervals in the conductor layer in contact with each insulating layer. Also, it may be easier to form minute via conductors such as the via conductor 13. The first buildup section 10 containing the inorganic filler 11f having a smaller particle size has good reliability in terms of insulation between wirings and can include wirings arranged at a fine pitch.

[0028] The conductor layers 12, 12a and via conductors 13 of the first buildup section 10, the conductor layer 22 and via conductors 23, 23a of the second buildup section 20, and the conductor layer 32 and via conductors 33 of the third buildup section 30 may be formed using any metal having suitable electrical conductivity, such as copper or nickel. Although each of these conductor layers and via conductors is depicted as a single layer in Fig. 1, each of the conductor layers and via conductors may have a multi-layer structure, such as the conductor layer 12, the conductor layer 22, and the via conductor 13 shown in Fig. 3.

[0029] In the example of Fig. 3, the conductor layers 12, 12a, and the via conductors 13 include a first metal film 12α located on the first surface 1F side of the wiring board 1, and a second metal film 12β formed on the second surface 1B side of the wiring board 1 (see Fig. 1) of the first metal film 12α and laminated on the first metal film 12α. Similarly, the conductor layer 22 (and the via conductors 23, 23a not shown in Fig. 3) includes a first metal film 22α, and a second metal film 22β formed on the second surface 1B side of the first metal film 22α of the wiring board 1. The first metal films 12α, 22α are made of, for example, a sputtering film or an electroless plating film, and the second metal films 12β, 22β are made of, for example, an electrolytic plating film. When the first metal films 12α, 22α are made of sputtered films, although not shown, the first metal films 12α, 22α may each include, as an example, a first film made of a copper alloy on the first surface 1F side and a second film made essentially of copper on the second surface 1B side.

[0030] As an example, the first metal film 12α included in the first buildup section 10 may be a sputtered film, and the first metal film 22α included in the second buildup section 20 may be an electroless plating film. The adhesive strength between the insulating layer 11 and the conductor layer 12 in the first buildup section 10 may be sufficiently high. Also, the conductor layer 22 may be easily formed in the formation of the second buildup section 20.

[0031] On the other hand, in the example of Fig. 3, the conductor layer 12a has only a single layer, and may be, for example, an electrolytic plating film. Although not shown in Fig. 3, the conductor layer 32 and the via conductor 33 may each have a layer made of a material similar to the first metal film 22α of the conductor layer 22 and a layer made of a material similar to the second metal film 22β. The conductor layer 32 may further include a layer made of a metal foil located closer to the insulating layer 31 than these two layers.

[0032] The via conductors 13, 23, 23a, and 33 are formed by filling through holes that penetrate the insulating layers in which the via conductors are formed with a conductor. The via conductors 13, 23, 23a, and 33 all have a tapered shape that reduces in diameter from the second surface 1B to the first surface 1F of the wiring board 1. Because the via conductors 13, 23, 23a, and 33 have such a tapered shape, the conductor layer on the first surface 1F side, which may be a component mounting surface, may include wirings arranged at a finer pitch. For convenience, the term "reduced diameter" is used, but the shape of the cross section (horizontal cross section) of each of the via conductors 13, 23, 23a, and 33 that is perpendicular to the stacking direction of the wiring board 1 is not necessarily limited to a circle. "Reduced diameter" simply means that the distance between the longest two points on the circumference of each via conductor in the horizontal cross section (hereinafter, this distance is also referred to as the "width" of each via conductor) becomes smaller.

[0033] The via conductors 13 included in the first buildup section 10 have, for example, an aspect ratio (distance between the top surface of the lower conductor layer 12 to which the via conductor 13 is connected and the bottom surface of the upper conductor layer 12 or conductor layer 12a / width of the via conductor 13 on the top surface of the lower conductor layer 12) of 0.5 or more and 1.0 or less. The first buildup section 10 may include via conductors 13 that include wiring arranged at a fine pitch and that are unlikely to break and have low conductor resistance. The width of each of the via conductors 13 on the top surface of the lower conductor layer 12 is, for example, about 10 μm.

[0034] 3, first buildup section 10 of wiring board 1 includes, in conductor layer 12, wiring 12f that is arranged at a relatively fine pitch among the wirings included in wiring board 1. Wiring 12f is arranged at a relatively high density among the wirings included in wiring board 1. On the other hand, second buildup section 20 includes wiring 22a in conductor layer 22.

[0035] In the wiring board 1, the minimum wiring width among the wiring widths W1 of the wirings 12f included in the first buildup section 10 is smaller than the minimum wiring width W2 of the wirings 22a included in the second buildup section 20. The minimum wiring width of the wirings 12f is approximately 1 μm or more and 3 μm or less. Furthermore, the minimum spacing among the spacings G1 between the wirings 12f included in the first buildup section 10 is smaller than the minimum spacing among the spacings G2 between the wirings 22a included in the second buildup section 20. The minimum spacing between the wirings 12f is approximately 1 μm or more and 3 μm or less.

[0036] Because the first buildup section 10 has wiring 12f arranged at such a fine pitch, wiring having more suitable characteristics may be provided in response to the electrical signals carried by the wiring in the first buildup section 10. Also, the density of the wiring in the first buildup section 10 may be high, and therefore a small wiring board 1 may be obtained.

[0037] Furthermore, in the wiring board 1 of this embodiment, the aspect ratio of the wiring 12f included in the first buildup section 10 is 2.0 or more and 4.0 or less. The wiring 12f having such an aspect ratio can have a low conductor resistance for a small wiring width, and can become a signal transmission path with low insertion loss. For example, signals can be transmitted between components mounted on the wiring board 1 with little transmission loss. In addition, a desired characteristic impedance can be easily obtained, and therefore, the insertion loss can be further reduced.

[0038] The wiring 12f included in the conductor layer 12 of the first buildup section 10 may have the smallest wiring width among the wirings included in the wiring board 1, and adjacent wirings 12f may be arranged at the smallest interval among adjacent wirings in the wiring board 1. One or more any number of conductor layers among the conductor layers 12 constituting the first buildup section 10 may include one or more sets of wirings that have the smallest wiring width and are arranged at the smallest interval in the wiring board 1.

[0039] The wiring board 1 of the present embodiment includes the first buildup section 10 and the second buildup section 20, each of which is constituted by conductor layers having different minimum wiring widths and minimum wiring intervals, i.e., conductor layers designed with different wiring rules. As described above, the first buildup section 10 and the second buildup section 20 are connected to each other by the via conductor 23a. The via conductor 23a is integrally formed with the conductor layer 22 in the second buildup section 20, as described above. Furthermore, the via conductor 23a may be formed of the same metal, such as copper, as the conductor layer 12 of the first buildup section 10. Therefore, it is considered that the connection reliability between the first buildup section 10 and the second buildup section 20 is higher than the connection reliability between the first wiring board and the second wiring board of the above-mentioned Patent Document 1. Therefore, according to the embodiment, the reliability of the wiring board including multiple conductor layers having different wiring densities may be improved.

[0040] In addition, the first buildup section 10 including the wiring 12f arranged at a fine pitch in the wiring board 1 of this embodiment includes a component area covered by mounted components (component areas Ea1, Ea2 covered by components E1, E2, respectively, in FIG. 1), as described above, and is smaller than the second buildup section 20 in a plan view. That is, the conductor layer including the fine wiring is provided only in the component area that is likely to require the fine wiring, not on the entire surface of the wiring board 1. Since the conductor layer including the fine wiring, which is difficult to manufacture, is provided only in a limited area, not on the entire surface of the wiring board 1, it is presumed that a good manufacturing yield can be obtained while including the necessary fine wiring. Furthermore, the occurrence of defects due to migration after the start of use is also limited, and therefore it is presumed that the reliability and market quality are also high.

[0041] 1 and 2, some of the multiple component mounting pads 12p are connected to wiring 22w of the second buildup section 20 through via conductors 13 and 23a. Furthermore, wiring 22w is connected to conductive pads 32p through via conductors 23 and 33. That is, the conductive pattern that is electrically connected to the component mounting pads 12p is drawn out to an area outside the first buildup section 10 in a plan view, and is connected to a pad on the second surface 1B that is the opposite surface to the first surface 1F that is the component mounting surface.

[0042] The second build-up section 20 and the third build-up section 30, which are larger than the first build-up section 10 in a plan view, can be provided with conductor pads such as the conductor pads 32p at a pitch larger than the component mounting pads 12p of the first build-up section 10. Therefore, the conductive path connected to the component mounting pads 12p in the first build-up section 10 can be fanned out to the second build-up section 20 and the third build-up section 30 by the wiring 22w or the like. In this way, the wiring board 1 of the example of FIG. 1 and FIG. 2 can include particularly fine wiring only in a limited area (the first build-up section 10), while fanning out the component mounting pads 12p arranged at a fine pitch using the other area (at least the second build-up section 20). It may be possible to adopt a wiring board that is inexpensive and easy to manufacture, designed with rough wiring rules, as a motherboard or the like to be connected to the second surface 1B of the wiring board 1.

[0043] In the wiring board 1, the thickness of the wiring included in the first buildup section 10, such as the wiring 12f, may be, for example, 4 μm or more and 7 μm or less. This is less likely to leave etching residue during manufacturing, and may be advantageous for arranging the wiring 12f and the like at fine intervals. On the other hand, the thickness of the insulating layer 11 included in the first buildup section 10 may be, for example, about 7.5 to 10 μm.

[0044] The surface of the conductor layer 12 of the first build-up section 10 on the second surface 1B side of the wiring board 1 may be a polished surface having a polished finish. In the example of FIG. 1, the surface of the second surface 1B side of all three conductor layers 12 is a polished surface. The polished surface may have a surface roughness lower than that of a plating film formed by metal deposition, for example. Therefore, it is considered that the wiring 12f included in each conductor layer 12 having a polished surface is less likely to suffer from a decrease in signal transmission characteristics or an increase in voltage drop due to an increase in substantial conductor resistance caused by the skin effect during transmission of a high-frequency signal. For example, the polished surface that each conductor layer 12 has as the surface on the second surface 1B side may have an arithmetic mean roughness of 0.3 μm or less. When such a surface roughness is obtained, the above-mentioned preferable effect on the transmission characteristics may be obtained.

[0045] As described above, the minimum values ​​of the wiring width W2 and wiring interval G2 of the wiring included in the conductor layer 22 of the second buildup section 20 are greater than the wiring width W1 and wiring interval G1 of the wiring included in the conductor layer 12 of the first buildup section 10, respectively. For example, the minimum value of the wiring width W2 of the wiring included in the second buildup section 20 is about 4 μm, and the minimum value of the interval G2 between the wirings is about 6 μm. The via diameter of the via conductors 23, 23a in the second buildup section 20 (the width of each via conductor on the upper surface of the lower conductor layer 22 to which each via conductor is connected) is about 50 μm. Furthermore, the thickness of the conductor layer 22 may be thicker than the thickness of the conductor layer 12, and for example, the thickness of the wiring 22a included in the second buildup section 20 may be 10 μm or more.

[0046] In the wiring board 1 of FIG. 1, the wiring width of the wiring of the conductor layer 32 included in the third buildup section 30 is larger than the wiring width of the wiring included in the second buildup section 20, and the wiring interval of the wiring of the conductor layer 32 is larger than the wiring interval of the wiring included in the second buildup section 20. In addition, both the insulating layer 31 and the conductor layer 32 in the third buildup section 30 are formed thicker than the insulating layer 21 and the conductor layer 22 in the second buildup section 20. For example, the thickness of the insulating layer 31 is about 100 μm or more and 250 μm or less. In addition, the thickness of the conductor layer 32 is about 20 μm. The width of the via conductor 33 formed in the insulating layer 31 (the width at the top surface of the conductor layer 32) is about 100 μm.

[0047] <Modifications of the wiring board according to the embodiment> FIG. 4 shows a cross-sectional view of a wiring board 1a which is a modified example of the wiring board of the embodiment. The wiring board 1a includes a solid member 5 in addition to the components included in the wiring board 1 of FIG. 1. The solid member 5 is disposed outside the first buildup section 10 in a plan view. The solid member 5 is embedded in the insulating layer 21a of the second buildup section 20. The surface of the solid member 5 on the first surface 1F side of the wiring board 1a is exposed to the first surface 1F. The solid member 5 is formed of a material having a higher rigidity than the insulating layer 21 included in the second buildup section 20. Therefore, in the wiring board 1a provided with the solid member 5, the mechanical strength of the wiring board 1a is enhanced. It is considered that the warping of the wiring board 1a is suppressed.

[0048] An example of the material of the solid member 5 is a metal such as copper. However, the material of the solid member 5 is not limited to copper, and is not limited to metal. In the example of FIG. 4, the thickness of the solid member 5 is approximately the same as that of the first buildup portion 10, but the solid member 5 may be thicker than the first buildup portion 10 (the lower surface of the solid member 5 may be located closer to the second surface 1B of the wiring board 1a than the second surface 10B of the first buildup portion 10). The solid member 5 may be disposed around the entire outer periphery of the first buildup portion 10, and therefore the solid member 5 may have a frame-like shape in a plan view. In addition, a plurality of solid members 5 may be discontinuously disposed around the entire periphery of the first buildup portion 10. Furthermore, the solid member 5 may be disposed only on a part of the periphery of the first buildup portion 10 (for example, on two opposing sides or on any one side).

[0049] Wiring board 1a in Fig. 4 differs from wiring board 1 in Fig. 1 in that it includes solid member 5. In wiring board 1a in Fig. 4, components similar to those in wiring board 1 in Fig. 1 are given the same reference numerals as those in Fig. 1 or are omitted as appropriate, and redundant explanations of those similar components will be omitted.

[0050] <Modification of the first buildup section> Fig. 5 shows a part of a first buildup portion 10a which is a modified example of the first buildup portion 10 of the wiring board 1 in Fig. 1. Fig. 5 is an enlarged view of a portion of the first buildup portion 10a which corresponds to portion III shown in Fig. 1.

[0051] 5, in the first buildup section 10a of this modification, each conductor layer 12 is embedded in the insulating layer 11 that contacts the first surface 10F side of the first buildup section 10, i.e., the first surface 1F side (see FIG. 1) of the wiring board 1. The conductor layer 12 is embedded in the insulating layer 11 near the surface 11a on the second buildup section 20 side, and the underside of the conductor layer 12 (the surface on the second buildup section 20 side) is exposed to the surface 11a.

[0052] Each insulating layer 11 has a recess 111 on its surface 11a. The via conductor 13 is formed in a through hole 13a that penetrates each insulating layer and communicates with the recess 111. Meanwhile, each conductor layer 12 is composed of a conductor that fills the recess 111 of each insulating layer 11. That is, each conductor layer 12 is formed in the recess 111 of each insulating layer 11. In each conductor layer having such a structure, it is considered that conductor residue is unlikely to exist between each conductor pattern such as the wiring 12f, and therefore short circuit defects are unlikely to occur. In addition, it may be possible to realize wiring arranged at a finer pitch.

[0053] 1 to 3, the conductor layer 12 and the via conductors 13 are composed of a first metal film 12α, which is, for example, a sputtered film, and a second metal film 12β formed on the first metal film 12α facing the second buildup section 20. In the first buildup section 10a of this modification, the first metal film 12α is formed along the bottom and wall surfaces of the recess 111. That is, in a conductor pattern such as the wiring 12f, the first metal film 12α covers the top and side surfaces of the second metal film 12β.

[0054] In this modification, the lower surface of each conductor layer 12 may be a polished surface. The surface 11a of each insulating layer 11 may also be a polished surface. The lower surface of each conductor layer 12 is substantially flush with the surface 11a of each insulating layer 11. In this manner, since the lower surface (polished surface) of each conductor layer 12 exposed on the surface 11a of the insulating layer 11 is flush with the surface 11a of the insulating layer 11, it is considered that high flatness can be obtained on the second surface 10B of the first buildup section 10. Therefore, good flatness can also be obtained on the second surface 1B (see FIG. 1) of the wiring board 1.

[0055] In this modification, each insulating layer 11 may include a barrier layer 112 as shown in Fig. 5. The surface of the barrier layer 112 on the second surface 10B side of the first buildup section 10 is in contact with the bottom surface of the recess 111, i.e., the surface of each conductor layer 12 on the first surface 10F side. Each insulating layer 11 in the example of Fig. 5 is composed of the barrier layer 112 and a main body layer 113 that constitutes the upper and lower parts of the barrier layer 112. The main body layer 113 is formed from a thermosetting resin such as an epoxy resin or various thermoplastic resins exemplified as the material of each insulating layer of the wiring board 1 in Fig. 1.

[0056] On the other hand, the barrier layer 112 is formed of a material that is more resistant to the processing means used to form the recesses 111 in each insulating layer than the constituent material of the main layer 113. For example, when the recesses 111 are formed by laser processing using an excimer laser beam, the barrier layer 112 may be formed of silicon oxide or silicon nitride. When each insulating layer 11 includes such a barrier layer 112, it may be easy to form the recesses 111 having a desired depth. Note that in this modification, each insulating layer 11 does not necessarily include the barrier layer 112. For example, the recesses 111 having a desired depth may be formed by adjusting the processing conditions for forming the recesses 111, such as the power of the laser beam.

[0057] When the insulating layer 11 including the barrier layer 112 is formed, lamination and thermocompression bonding of a film-like resin are performed twice in the process of forming the insulating layer 11 described below, and the barrier layer 112 is formed during that time. That is, the first lamination and thermocompression bonding of the film-like resin forms a main body layer 113 on the first surface 10F side of the barrier layer 112 in the insulating layer 11. Thereafter, a silicon oxide film or a silicon nitride film is formed as the barrier layer 112 on the main body layer 113 by, for example, sputtering. The second lamination and thermocompression bonding of the film-like resin on the barrier layer 112 forms the main body layer 113 on the second surface 10B side of the barrier layer 112.

[0058] Next, with reference to FIGS. 6A to 6G, 7, 8A to 8F, and 9, an example of a method for manufacturing the wiring board of this embodiment will be described, taking the case where the wiring board 1 illustrated in FIG. 1 is manufactured as an example. Unless there is a different explanation from the explanation of the material of each component of the wiring board 1 previously made, each component can be formed using any of the materials previously described for each component. In addition, in the explanation of the method for manufacturing the wiring board of the following embodiment, the side close to the support substrate S1 or the support substrate S2 is also referred to as "bottom" or "lower side", and the side far from the support substrate S1 or the support substrate S2 is also referred to as "upper" or "upper side". Therefore, the surface facing the support substrate S1 side or the support substrate S2 side of each component of the wiring board to be manufactured is also referred to as the "lower surface", and the surface facing the opposite side to the support substrate S1 or the opposite side to the support substrate S2 is also referred to as the "upper surface".

[0059] As shown in FIG. 6A, a support substrate S1, for example a glass substrate, is prepared. An adhesive layer AL1 containing, for example, a photoplastic azobenzene-based polymer adhesive is formed on the surface of the support substrate S1 by coating, lamination, or the like. Then, a conductor layer 12a is formed on the adhesive layer AL1. In the example of FIG. 6A, the conductor layer 12a is formed only on one surface S1a of the support substrate S1. However, the conductor layer 12a may also be formed on the surface S1b opposite to the surface S1a in FIG. 6A. Then, the processing and formation of each component described with reference to FIGS. 6B to 6G may be performed on the surface S1b, but the illustration of the surface S1b side is omitted in FIGS. 6B to 6G.

[0060] In forming the conductor layer 12a, first, a metal film layer made of, for example, copper or nickel is formed on the adhesive layer AL1 by electroless plating or sputtering, or by attaching a metal foil using the adhesive layer AL1. A plating resist (not shown) having an opening corresponding to the formation area of ​​the conductor pattern to be included in the conductor layer 12a is formed on the metal film layer by laminating a dry film and exposing and developing it. Then, the conductor layer 12a is formed by electrolytic plating using the metal film layer as a power supply layer. Thereafter, the plating resist is removed. The conductor layer 12a in the state shown in FIG. 6A is obtained.

[0061] As shown in Fig. 6B, an insulating layer 11 is formed to cover the conductor layer 12a. The insulating layer 11 is formed, for example, by laminating a film-like epoxy resin on the conductor layer 12a and thermocompressing the laminate. As described above, the insulating layer 11 (as well as the insulating layers 21, 21a, and 31 (see Figs. 8C to 8E) formed in a later step) may be formed using a thermosetting resin such as BT resin or phenol resin, or a thermoplastic resin such as fluororesin or LCP, in addition to epoxy resin.

[0062] In the insulating layer 11, through holes 13a are formed by irradiation with carbon dioxide laser light or the like at the positions where the via conductors 13 (see FIG. 1) are to be formed. Although not shown, the formation of the through holes 13a by irradiation with carbon dioxide laser light or the like may be performed while protecting the surface of the insulating layer 11 with a protective film such as a polyethylene terephthalate (PET) film. In this case, the through holes 13a may be formed penetrating the protective film and the insulating layer 11.

[0063] After the through-hole 13a is formed, a desmear process is preferably performed to remove resin debris (smear) remaining in the through-hole 13a. The desmear process may be a wet process including immersion in a chemical solution such as a permanganate solution, or may be a dry process such as a plasma process using a plasma gas such as argon, tetrafluoromethane, a mixture of tetrafluoromethane and oxygen, or sulfur hexafluoride. For example, the desmear process using a plasma process may suppress erosion of the surface of the insulating layer 11 compared to the wet process. The desmear process may also be performed in a state where the surface of the insulating layer 11 is protected by a protective film such as a PET film.

[0064] Then, a metal film 121 made of, for example, copper or nickel is formed in the through hole 13a and on the entire surface of the insulating layer 11 by sputtering or electroless plating. When the metal film 121 is formed by sputtering, the metal film 121 may have high adhesion with the insulating layer 11. A part of the metal film 121 may become a first metal film 12α (see FIG. 3) constituting the conductor layer 12 formed on the insulating layer 11. Note that, if a protective film is provided on the surface of the insulating layer 11 during the formation of the through hole 13a and / or during the desmear process, the protective film is removed by peeling before the formation of the metal film 121.

[0065] As shown in Fig. 6C, a plating resist R1 having an opening R11 is provided on the metal film 121. Fig. 6C and Figs. 6D and 6E, which will be referred to below, show enlarged views of the state after each process in the portion corresponding to the VIC portion shown in Fig. 6B. The conductor layer 12a is formed on the metal film MF, which is a power supply layer when the conductor layer 12a is formed by electrolytic plating. The plating resist R1 is formed, for example, by laminating a dry film on the metal film 121, and the opening R11 is formed, for example, by photolithography. The opening R11 is formed in a pattern corresponding to the conductor pattern to be included in the conductor layer 12 (see Fig. 6F) to be formed on the insulating layer 11.

[0066] As described above, each conductor pattern such as the wiring 12f (see FIG. 3) included in the conductor layer 12 may have a wiring width of 3 μm or less. Each opening R11 is formed with an opening width according to the wiring width that each conductor pattern such as the wiring 12f formed in each opening R11 should have. Also, as described above, the wiring 12f of the conductor layer 12 may have an aspect ratio of 2.0 or more and 4.0 or less. Therefore, in the method illustrated in FIG. 6C, a plating resist R1 is formed that preferably has a thickness (height) greater than or equal to the thickness (height) of the wiring that satisfies the aspect ratio that the wiring to be formed should have.

[0067] As shown in FIG. 6D, a metal film 122 made of, for example, copper or nickel is formed in the opening R11 of the plating resist R1 by electrolytic plating using the metal film 121 as a power supply layer. A part of the metal film 122 can become a second metal film 12β (see FIG. 3) constituting the conductor layer 12 formed on the insulating layer 11. A via conductor 13 is formed in the through hole 13a of the insulating layer 11. As in the example of FIG. 6D, the metal film 122 may be formed so as to fill the entire opening R11 and further have a curved upper surface that protrudes upward from the upper surface of the plating resist R1. It may be possible to more reliably form wiring having a desired thickness and aspect ratio.

[0068] As shown in FIG. 6E, a part of the upper surface side of the metal film 122 is removed by polishing. At least the protruding part of the metal film 122 from the upper surface of the plating resist R1 is removed. The metal film 122 is polished until the total thickness of the metal film 122 and the metal film 121 reaches the thickness required for the conductor layer 12 (see FIG. 6F) formed on the insulating layer 11, for example, to 7 μm or less. As in the example of FIG. 6E, a part of the upper surface side of the plating resist R1 may also be removed together with a part of the metal film 122. The polishing of the metal film 122 is performed by any method such as chemical mechanical polishing (CMP). As a result of the polishing, the upper surface of the metal film 122 (the surface opposite to the insulating layer 11 side) may have an arithmetic mean roughness of 0.3 μm or less.

[0069] After polishing the metal film 122, the plating resist R1 is removed. Furthermore, the portion of the metal film 121 that is not covered by the metal film 122 is removed by, for example, quick etching.

[0070] As shown in Fig. 6F, a conductor layer 12 including predetermined conductor patterns such as wiring 12f separated from one another is obtained. In Fig. 6F, like Fig. 1, the conductor layer 12 is shown to have only one layer, but the conductor layer 12 is composed of the metal film 122 shown in Fig. 6E and the metal film 121 after a part of the metal film 122 is removed from the state of Fig. 6E as described above.

[0071] As shown in Figure 6F, on the insulating layer 11 and conductor layer 12 formed in the steps up to Figure 6E, two sets of insulating layers 11 and conductor layers 12, and via conductors 13 are further formed in a manner similar to that described with reference to Figures 6B to 6E.

[0072] As shown in FIG. 6G, the support substrate S1 is removed. For example, the adhesive layer AL1 is irradiated with a laser beam, the adhesive layer AL1 is softened, and then the support substrate S1 is peeled off from the conductor layer 12a and the insulating layer 11. Specifically, the adhesive layer AL1 and the metal film MF (see FIG. 6C) are separated, and the exposed metal film layer MF is removed by etching or the like. The lower surface of the conductor layer 12a and the lower surface of the insulating layer 11 are exposed. Individual conductor patterns such as component mounting pads 12p in the conductor layer 12a are separated from each other. The first build-up section 10 is completed.

[0073] After removing the support substrate S1, an open / short check may be performed on the conductor layers 12 and 12a in the first buildup section 10 and the via conductors 13. Defective products can be removed before further materials and man-hours are consumed in the later processes described below.

[0074] 7, in forming the first buildup sections 10, multiple first buildup sections 10 may be formed simultaneously on a support substrate S1 that is at least twice the size of each individual first buildup section 10 in a plan view. Then, the connected first buildup sections 10 may be cut together with the support substrate S1 along cutting lines C1 using a router or the like to be individualized.

[0075] As shown in FIG. 8A to FIG. 8F, the second buildup section 20 (see FIG. 8D) and the third buildup section 30 (see FIG. 8E) are formed. As shown in FIG. 8A, the support substrate S2 is prepared. An adhesive is laminated or applied to the surface of the support substrate S2 to form an adhesive layer AL2. In the example of FIG. 8A, the support substrate S2 is a double-sided copper-clad laminate composed of a base material S21 formed of, for example, epoxy resin, and a metal layer S22 made of, for example, copper foil, which is pressure-bonded to both sides of the base material S21. However, the support substrate S2 may be a glass plate exemplified as the material of the support substrate S1 in FIG. 6A, and may be composed of any material. The adhesive layer AL2 may be formed of, for example, a thermoplastic or photoplastic adhesive so that the support substrate S2 can be peeled off in a later process.

[0076] Then, the first buildup section 10 formed through the steps illustrated in Figs. 6A to 6G is mounted on the adhesive layer AL2 and held in place by the adhesive force of the adhesive layer AL2. The first buildup section 10 is mounted with the surface on which the conductor layer 12a is formed (first surface 10F) facing the support substrate S2. Note that while Figs. 8A to 8E show an example in which the second buildup section 20 and the third buildup section 30 are formed on both surfaces of the support substrate S2, the second buildup section 20 and the third buildup section 30 may be formed on only one surface of the support substrate S2. In Figs. 8B to 8E, the reference numerals for the components shown on the upper surface side of the support substrate S2 are omitted.

[0077] 8B and 8C, an insulating layer 21a is formed to cover the first buildup section 10. As shown in Fig. 8B, the insulating layer 21a is formed by laminating a film-like resin 21aa on the first buildup section 10 and the adhesive layer AL2 and thermocompressing the laminate. As described above as the material for the insulating layer 21a, the film-like resin 21aa may be a thermosetting resin such as an epoxy resin, a BT resin, or a phenolic resin, or a thermoplastic resin such as a fluororesin or an LCP.

[0078] Because the film-like resin 21aa covers the first buildup section 10 mounted on the support substrate S2, the insulating layer 21a after thermocompression bonding may have a protrusion 211 on its surface as shown by the two-dot chain line L1 in Fig. 8C. Therefore, after the film-like resin 21aa is thermocompression bonded, the surface of the insulating layer 21a may be polished by any method such as CMP, if necessary. It is believed that the polishing can provide a surface 212 having good flatness as shown in Fig. 8C.

[0079] The surface of the insulating layer 21a after thermocompression bonding may be polished until the conductor layer 12 constituting the surface (second surface 10B) opposite to the first surface 10F in the first buildup section 10 is exposed. That is, the surface of the insulating layer 21a may be polished to a position where the surface of the conductor layer 12 on the second surface 10B side and the surface of the insulating layer 21a are flush with each other, as shown by the two-dot chain line L2 in FIG. 8C. The amount of polishing (polishing end position) may be easily controlled. In addition, the surface roughness of the surface of the conductor layer 12 may be further reduced, and the transmission characteristics of the high-frequency signal of the conductor layer 12 may be further improved. In this way, when the insulating layer 21a is polished until the conductor layer 12 is exposed, a film-like resin such as the film-like resin 21aa shown in FIG. 8B, preferably a film-like resin thinner than the film-like resin 21aa, may be laminated and thermocompression bonded again after polishing. As a result, the insulating layer 21a in the state shown in FIG. 8C may be formed.

[0080] As shown in Fig. 8D, a conductor layer 22 is formed on the insulating layer 21a, and a via conductor 23a is formed in the insulating layer 21a. The conductor layer 22 and the via conductor 23a are formed using any method for forming a conductor layer and a via conductor. For example, the conductor layer 22 and the via conductor 23a are formed using a semi-additive method.

[0081] Then, similarly to insulating layer 21a, insulating layer 21 is formed by thermocompression bonding of a film-like resin, and via conductors 23 and conductor layer 22 are formed by a semi-additive method or the like inside and on the surface of insulating layer 21. Furthermore, the formation of insulating layer 21, via conductors 23, and conductor layer 22 is repeated as many times as necessary to complete second buildup section 20 shown in Fig. 8D.

[0082] As shown in FIG. 8E, the insulating layer 31, the conductor layer 32, and the via conductors 33 penetrating the insulating layer 31 of the third buildup section 30 are formed on the surface (second surface 20B) of the second buildup section 20 opposite to the support substrate S2 side. The insulating layer 31 in FIG. 8E is formed by laminating and thermocompression bonding prepregs containing an insulating resin such as epoxy resin impregnated in a core material 31a made of glass fiber or the like. The insulating layer 31 may be formed by thermocompression bonding of a film-like resin, similar to the insulating layer 21a. The conductor layer 32 and the via conductors 33 may be formed, for example, by a semi-additive method, similar to the method for forming the conductor layer 22 and the via conductors 23, or may be formed by any other method for forming a conductor layer, such as a subtractive method. The formation of the third buildup section 30 is completed.

[0083] Furthermore, a solder resist 40 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 31 and the conductor layer 32. Then, openings 41 that define the conductor pads 32p are formed by photolithography.

[0084] Thereafter, the support substrate S2 is removed. For example, the adhesive layer AL2 is softened by heating or irradiating it with laser light, and in this state, the support substrate S2 is peeled off from the first buildup section 10 and the insulating layer 21a. If the adhesive layer AL2 remains, the remaining adhesive layer AL2 is removed using an appropriate solvent.

[0085] By removing the support substrate S2, the first surface 10F of the first buildup portion 10 and the first surface 20F of the second buildup portion 20, including the surfaces of the component mounting pads 12p, are exposed as shown in Fig. 8F. In other words, the first surface 1F of the wiring board 1 is exposed. The wiring board 1 shown in Fig. 1 is completed.

[0086] 9, in the manufacturing process of the wiring board 1, a plurality of first buildup sections 10 may be mounted on a support substrate S2 having a size at least twice the size of each of the wiring boards 1 in a plan view. A plurality of wiring boards 1, each including the first buildup sections 10 and the second buildup sections 20, may be manufactured simultaneously on the support substrate S2. The interconnected wiring substrates 1 may then be cut into individual pieces together with the support substrate S2 along cutting lines C2 using a router or the like.

[0087] 4 is manufactured, a solid member 5 is mounted on the outside of the first buildup portion 10 together with the first buildup portion 10 in the process described with reference to FIG. 8A. The solid member 5 is placed on the adhesive layer AL2 and held in place by the adhesive force of the adhesive layer AL. Then, in the process described with reference to FIGS. 8B and 8C, the solid member 5 is embedded in the insulating layer 21a together with the first buildup portion 10.

[0088] A method of forming first buildup section 10a of the modified example shown in previously referenced Figure 5 will be described with reference to Figures 10A to 10C. Figures 10A to 10C show the state of a portion of first buildup section 10a in the process of being formed, which portion corresponds to the portion shown in Figures 6C to 6E, after each process.

[0089] As shown in FIG. 10A, from the state shown in FIG. 6A referred to earlier, an insulating layer 11 and a through hole 13a are formed in this order, and further a recess 111 is formed. At the stage shown in FIG. 10A, the insulating layer 11 may be formed thicker than the thickness that the insulating layer 11 should have when the wiring board 1 (see FIG. 1) is completed. In addition, in forming the insulating layer 11, the barrier layer 112 may be formed by the method described above. In FIGS. 10A to 10C, the barrier layer 112 is indicated by a two-dot chain line. The through hole 13a is formed at the formation position of the via conductor 13 (see FIG. 5) by, for example, irradiation with a carbon dioxide laser beam. When the barrier layer 112 is formed, the through hole 13a is formed so as to penetrate the barrier layer 112 and reach the conductor layer 12a.

[0090] After the through holes 13a are formed, the recesses 111 are formed at the positions where the conductor patterns are to be formed in the conductor layer 12 (see FIG. 5). For example, the recesses 111 are formed to a predetermined depth by irradiation with an excimer laser beam. When the barrier layer 112 is formed, the barrier layer 112 prevents the laser beam from passing through, so that the recesses 111 may be easily formed to a desired depth. Even if the barrier layer 112 is not formed, the recesses 111 may be formed to a desired depth by, for example, adjusting the conditions of the excimer laser beam. After the recesses 111 are formed, a desmear process is preferably performed by a plasma process or the like.

[0091] A metal film 121 is formed on the entire exposed surface of the insulating layer 11 including the inside of the through hole 13a and the recess 111. When the barrier layer 112 is formed, the metal film 121 is also formed on the exposed surface of the barrier layer 112. The metal film 121 is formed by, for example, sputtering or electroless plating.

[0092] 10B, a metal film 122 is formed on the metal film 121 inside the through hole 13a, inside the recess 111, and on the entire surface of the insulating layer 11 opposite to the conductor layer 12a. The metal film 122 is preferably formed to have a desired thickness on an area of ​​the surface of the insulating layer 11 where the recess 111 is not formed. The metal film 122 is formed, for example, by electrolytic plating using the metal film 121 as a power supply layer. The recess 111 is filled with the metal film 122. The through hole 13a is also filled with the metal film 122 to form the via conductor 13.

[0093] 10C, the metal film 122 and the metal film 121 on the surface of the insulating layer 11 in the region where the recess 111 is not formed are removed by polishing using any method such as CMP. The metal film 122 is polished until the total thickness of the metal film 122 and the metal film 121 on the bottom surface of the recess 111 reaches the thickness required for the conductor layer 12. When polishing the metal film 122, the vicinity of the surface of the insulating layer 11 may also be removed by polishing together with the metal film 122. A surface 11a of the insulating layer 11 that is flush with the surface of the conductor layer 12 is obtained.

[0094] By removing the metal film 122 and the metal film 121 on the surface of the insulating layer 11, the conductor patterns of the conductor layer 12 are separated from each other. The other conductor layers 12 of the first buildup section 10a in FIG. 5 are formed in the same manner as that described for the conductor layer 12 shown in FIG. 10C. In the method described with reference to FIGS. 10A to 10C, conductors such as the metal film 121 formed between the conductor patterns included in the conductor layer 12 are more reliably removed by polishing rather than by etching or the like. It is therefore considered that short-circuiting between the conductor patterns is unlikely to occur. Furthermore, because short-circuiting is unlikely to occur in this way, the wirings may be arranged at a finer pitch.

[0095] The wiring board of the embodiment is not limited to those having the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. Each build-up portion included in the wiring board of the embodiment may have any number of insulating layers and conductor layers as described above. In addition, each insulating layer may not contain an inorganic filler as shown in FIG. 3. The insulating layer and conductor layer of the outermost layer on the opposite side to the component mounting surface of the wiring board of the embodiment may not be formed thicker than the insulating layer and conductor layer in the second build-up portion, and the insulating layer of the outermost layer on the opposite side to the component mounting surface of the wiring board may not contain a core material. [Explanation of symbols]

[0096] 1, 1a Wiring board 1F First side of the wiring board 1B Second side of wiring board 10, 10a First build-up section 10F Surface of the first build-up section (first surface) 11 Insulating layer of first build-up section 11f Inorganic filler in the first build-up section 12, 12a Conductive layer of first build-up section 12f First build-up section wiring 12p component mounting pad 12α 1st metal film 12β second metal film 13 Via conductor of the first buildup section 20 Second Build-up Section 21, 21a Insulating layer of second build-up section 21f Inorganic filler in the second buildup section 22 Conductive layer of the second build-up section 22a, 22w Wiring for the second build-up section 22α First metal film of the second build-up section 22β Second metal film of the second build-up section 23, 23a Via conductor of second buildup section 30 Third Build-up Section 31 Insulating layer of the third build-up section 31a Core material 32 Conductive layer of the third build-up section 33 Via conductor of the third buildup section 5 Solid parts E1, E2 parts (mounted parts) Ea1, Ea2 parts area W1 Wiring width of the first build-up section G1: Distance between wires in the first build-up section W2 Wiring width of the second build-up section G2 Spacing between wires in the second build-up section

Claims

1. a first surface and a second surface opposite the first surface; a first buildup section including insulating layers and conductor layers alternately stacked on top of each other; a second buildup section including insulating layers, conductor layers, and via conductors that are alternately stacked; A wiring board comprising: the first buildup section is laminated on the first surface side of the second buildup section, the first buildup portion is smaller than the second buildup portion in a plan view and is embedded in an insulating layer of the second buildup portion; the conductor layer in the first buildup portion and the conductor layer in the second buildup portion are connected to each other by the via conductor; the second buildup portion includes wiring that is formed across a region overlapping with the first buildup portion and a region outside the first buildup portion and is connected to the via conductor; a surface of the first build-up portion on the first surface side is exposed to the first surface and includes one or more component regions that are to be covered by mounted components when the wiring board is used; a minimum wiring width of the wiring included in the first buildup portion is smaller than a minimum wiring width of the wiring included in the second buildup portion and is equal to or smaller than 3 μm; a minimum distance between the wirings included in the first buildup portion is smaller than a minimum distance between the wirings included in the second buildup portion and is equal to or less than 3 μm; The aspect ratio of the wiring included in the first buildup portion is not less than 2.0 and not more than 4.

0.

2. 2. The wiring board according to claim 1, wherein a surface of the conductor layer included in the first buildup portion on the second surface side is a polished surface.

3. 2. The wiring board according to claim 1, further comprising a third buildup section on the second surface side of the second buildup section, the third buildup section including an insulating layer and a conductor layer, The third buildup section includes a via conductor that connects a conductive layer included in the third buildup section and a conductive layer included in the second buildup section.

4. 4. The wiring board according to claim 3, wherein the insulating layer included in the third buildup portion includes a core material.

5. 5. The wiring board according to claim 4, wherein the core material is glass fiber.

6. 2. The wiring board according to claim 1, wherein the thickness of the wiring included in the first buildup portion is 7 [mu]m or less, and the thickness of the wiring included in the second buildup portion is 10 [mu]m or more.

7. 2. The wiring board according to claim 1, the first buildup portion includes a via conductor penetrating the insulating layer of the first buildup portion, The via conductors included in the first buildup section and the via conductors included in the second buildup section each have a shape whose diameter decreases from the second surface to the first surface.

8. 2. The wiring board according to claim 1, wherein the aspect ratio of the via conductor included in the first buildup portion is not less than 0.5 and not more than 1.

0.

9. 2. The wiring board according to claim 1, the conductor layer included in the first buildup portion and the conductor layer included in the second buildup portion each include a first metal film and a second metal film formed on the second surface side of the first metal film, the first metal film included in the first build-up portion is a sputtering film, The first metal film included in the second buildup portion is an electroless plating film.

10. 2. The wiring board according to claim 1, wherein each conductor layer in the first buildup portion is embedded in an insulating layer on the first surface side.

11. 2. The wiring board according to claim 1, wherein the first build-up portion includes a component mounting pad embedded in an insulating layer constituting the surface and having one surface exposed on the surface.

12. 2. The wiring board according to claim 1, further comprising a solid member formed of a material having a higher rigidity than an insulating layer included in the second buildup portion and disposed outside the first buildup portion in a planar view.

13. 2. The wiring board according to claim 1, the insulating layer included in the first buildup section and the insulating layer included in the second buildup section each contain an inorganic filler; The maximum particle size of the inorganic filler contained in the first buildup section is smaller than the maximum particle size of the inorganic filler contained in the second buildup section.

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