Printed wiring board

Abstract

To provide a printed wiring board which secures operation of an electronic component on a re-wiring part and enhances reliability.SOLUTION: A printed wiring board has a core substrate, a first build-up layer, a second build-up layer, and an IC chip. The first build-up layer has a first resin insulation layer, a first conductor layer and a first via conductor, the second build-up layer has a second resin insulation layer, a second conductor layer and a second via conductor, the first conductor layer has a plurality of first conductor circuits, of the plurality of first conductor circuits, the first conductor circuit having a minimum width is a minimum first conductor circuit, the second conductor layer has a plurality of second conductor circuits, of the plurality of second conductor circuits, the second conductor circuit having a minimum width is a minimum second conductor circuit, the width of the minimum second conductor circuit is smaller than the width of the minimum first conductor circuit, thickness of the second resin insulation layer is thinner than thickness of the first resin insulation layer, a diameter of the second via conductor is smaller than a diameter of the first via conductor, and thickness of the second conductor layer is thinner than thickness of the first conductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a printed wiring board. [Background technology]

[0002] Patent Document 1 discloses a wiring board. As shown in Fig. 1 of Patent Document 1, Patent Document 1 discloses a wiring board having a base wiring board having a wiring layer and an insulating layer, and a rewiring section having an insulating layer and a rewiring layer. The rewiring layer is formed of a seed layer and a metal plating layer thereon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-154800 A Summary of the Invention

[0004] <Issues in Patent Document 1> In the technology of Patent Document 1, electronic components are mounted on the rewiring section. Therefore, it is considered that the distance of the path for supplying power to the electronic components on the rewiring section is long. Since the wiring in the rewiring section is thin and narrow, it is considered that the wiring resistance is high. Therefore, it is considered that the electronic components on the rewiring section are prone to power shortage. In the wiring board according to the technology of Patent Document 1, it is considered that the electronic components on the rewiring section will malfunction or will not function. [Means for solving the problem]

[0005] The printed wiring board of the present invention comprises a core substrate having a core material having a first surface, a second surface opposite the first surface, and an opening for accommodating an electronic component extending from the first surface to the second surface, the electronic component accommodated in the opening, a first conductor layer on the core material formed on the first surface, and a second conductor layer on the core material formed on the second surface, a first buildup layer formed on the first surface, a second buildup layer formed on the first buildup layer, and an IC chip mounted on the second buildup layer. The first buildup layer has a first resin insulating layer laminated on the first surface, a first conductor layer formed on the first resin insulating layer, and a first via conductor penetrating the first resin insulating layer and electrically connecting the first conductor layer and the first conductor layer on the core material, and the second buildup layer has a second resin insulating layer laminated on the first resin insulating layer, a second conductor layer formed on the second resin insulating layer, and a second via conductor penetrating the second resin insulating layer and electrically connecting the second conductor layer and the first conductor layer, and the first conductor layer is a plurality of the first conductor circuit having a smallest width among the plurality of first conductor circuits is the smallest first conductor circuit, the second conductor layer has a plurality of second conductor circuits having a smallest width among the plurality of second conductor circuits is the smallest second conductor circuit, the width of the smallest second conductor circuit is smaller than the width of the smallest first conductor circuit, the thickness of the second resin insulation layer is thinner than the thickness of the first resin insulation layer, the diameter of the second via conductor is smaller than the diameter of the first via conductor, and the thickness of the second conductor layer is thinner than the thickness of the first conductor layer.

[0006] In an embodiment of the present invention, a first buildup layer is formed on a first surface of a core substrate. A second buildup layer is formed on the first buildup layer. An IC chip is mounted on the second buildup layer. The first buildup layer has a first resin insulating layer, a first conductor layer, and a first via conductor. The second buildup layer has a second resin insulating layer, a second conductor layer, and a second via conductor. The second conductor layer has a plurality of second conductor circuits, and the first conductor layer has a plurality of first conductor circuits. The width of the smallest second conductor circuit in the second conductor circuit is smaller than the width of the smallest first conductor circuit in the first conductor circuit. The thickness of the second resin insulating layer is smaller than the thickness of the first resin insulating layer. The diameter of the second via conductor is smaller than the diameter of the first via conductor. The thickness of the second conductor layer is thinner than the thickness of the first conductor layer. The second buildup layer forms a so-called rewiring portion. The electronic components are accommodated in the openings in the core substrate for accommodating electronic components. Therefore, the distance between the IC chip on the second build-up layer, which is the rewiring portion, and the electronic components in the core substrate is short. Therefore, it is possible to sufficiently supply power to the IC chip via the electronic components in the core substrate. In the printed wiring board of the embodiment, the IC chip on the rewiring portion does not malfunction. The IC chip on the rewiring portion operates normally. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view illustrating a printed wiring board according to an embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view illustrating a printed wiring board according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] <Embodiment> FIG. 1 is a cross-sectional view of a printed wiring board 10 according to an embodiment. As shown in FIG. 1, the printed wiring board 10 includes a core substrate 30, an upper buildup layer Bu1, a lower buildup layer Bu2, a first solder resist layer 90F, and a second solder resist layer 90S. The core substrate 30 includes a core material 20. The core material 20 includes a first surface F and a second surface S opposite to the first surface F. The upper buildup layer Bu1 is formed on the first surface F of the core substrate 30. The lower buildup layer Bu2 is formed on the second surface S of the core substrate 30. The first solder resist layer 90F is formed on the upper buildup layer Bu1. The second solder resist layer 90S is formed on the lower buildup layer Bu2.

[0009] The upper buildup layer Bu1 is formed of a buildup layer 50F (first buildup layer) and a buildup layer 70F (second buildup layer). The buildup layer 50F is formed on the first surface F of the core material 20. The buildup layer 70F is formed on the buildup layer 50F. The rewiring section 100 is formed by the buildup layer 70F.

[0010] The core material 20 has a plurality of openings. A via conductor 20A is formed in each opening. The via conductor 20A penetrates the core material 20 and reaches from the first surface F to the second surface S. The core substrate 30 has a conductor layer 21 (a first conductor layer on the core material) and a conductor layer 22 (a second conductor layer on the core material). The conductor layer 21 is formed on the first surface F of the core material 20. The conductor layer 22 is formed on the second surface S of the core material 20. The conductor layers 21 and 22 adjacent to each other across the core material 20 are connected by a via conductor 20A sandwiched between the adjacent conductor layers 21 and 22.

[0011] The core material 20 has an opening 23 for accommodating an electronic component. The opening 23 penetrates the core material 20 and reaches from the first surface F to the second surface S. An electronic component 200 is accommodated in the opening 23. The electronic component 200 has an external electrode 201 and an external electrode 202. The external electrode 201 protrudes from within the opening 23 to the outside of the first surface F. The external electrode 202 protrudes from within the opening 23 to the outside of the second surface S.

[0012] The buildup layer (50F) has a first resin insulating layer (150F), a first conductor layer (158F), and a first via conductor (156F). The first resin insulating layer (150F) is formed on the first surface (F) of the core material (20) or on the first conductor layer (158F). The first conductor layer (158F) is formed on the first resin insulating layer (150F). The first via conductor (156F) penetrates the first resin insulating layer (150F) and is connected to the first conductor layer (158F).

[0013] The first conductor layer 158F has a first via land 156FL. The first via land 156FL is formed directly above and around the first via conductor 156F. The first via land 156FL and the first via conductor 156F are integrally formed. An opening 156FO for the first via conductor 156F penetrates the first resin insulating layer 150F. The first via conductor 156F is formed in the opening 156FO.

[0014] In the example of FIG. 1, the number of first resin insulating layers (150F) and the number of first conductor layers (158F) are plural. The number of first resin insulating layers (150F) is seven, and the number of first conductor layers (158F) is seven. The first resin insulating layers (150F) and the first conductor layers (158F) are alternately laminated. When the number of first resin insulating layers (150F) is plural, the first via conductors (156F) are formed in each first resin insulating layer (150F). The conductor layers sandwiching the first resin insulating layer (150F) are electrically connected by the first via conductors (156F).

[0015] When there are a plurality of first resin insulating layers, the buildup layer (50F) has a first resin insulating layer (150FB) formed directly on the core material (20) and other first resin insulating layers (150FU).

[0016] The first resin insulating layer (150FB) is sandwiched between the first conductor layer (158F) and the conductor layer 21 or the external electrode 201. The first resin insulating layer (150FB) is formed on the first surface (F) of the core material 20. The first via conductor (156F) penetrating the first resin insulating layer (150FB) electrically connects the conductor layer (21) or the external electrode (201) of the core substrate 30 to the first conductor layer (158F) directly above it.

[0017] First resin insulating layer (150FU) is sandwiched between first conductor layers (158F). First resin insulating layer (150FU) is formed on first conductor layer (158F). First via conductors (156F) penetrating first resin insulating layer (150FU) electrically connect adjacent first conductor layers (158F).

[0018] The wiring density (L / S) of the buildup layer 50F is 7 / 7 to 30 / 30. The wiring density (L / S) is represented by the smallest L / S of the first conductor layer 158F of the buildup layer 50F.

[0019] The buildup layer 70F has a second resin insulating layer 170F, a second conductor layer 178F, and a second via conductor 376F. The second resin insulating layer 170F is formed on the first resin insulating layer 150F and the first conductor layer 158F that form the buildup layer 50F. The second conductor layer 178F is formed on the second resin insulating layer 170F. The second via conductor 376F penetrates the second resin insulating layer 170F and connects to the second conductor layer 178F.

[0020] The second conductor layer (178F) has a second via land (376FL). The second via land (376FL) is formed directly above and around the second via conductor (376F). The second via conductor (376F) and the second via land (376FL) are integrally formed. An opening (376FO) for the second via conductor (376F) penetrates the second resin insulating layer (170F). The second via conductor (376F) is formed in the opening (376FO).

[0021] In the example of FIG. 1, the number of second resin insulating layers (170F) and the number of second conductor layers (178F) are plural. The number of second resin insulating layers (170F) is six, and the number of second conductor layers (178F) is six. The second resin insulating layers (170F) and the second conductor layers (178F) are alternately laminated. When the number of second resin insulating layers (170F) is plural, the second via conductors (376F) are formed in each second resin insulating layer (170F). The conductor layers sandwiching the second resin insulating layer (170F) are electrically connected by the second via conductors (376F).

[0022] When there are a plurality of second resin insulating layers, the buildup layer (70F) has a second resin insulating layer (170FB) formed directly on the buildup layer (50F) and other second resin insulating layers (170FU).

[0023] The second resin insulating layer (170FB) is sandwiched between the second conductor layer (178F) and the first conductor layer (158F). The second resin insulating layer (170FB) is formed on the first resin insulating layer (150FU) and the first conductor layer (158F). A second via conductor (376F) penetrating the second resin insulating layer (170FB) electrically connects the first conductor layer (158F) and the second conductor layer (178F).

[0024] The second resin insulating layer (170FU) is sandwiched between the second conductor layers (178F). The second resin insulating layer (170FU) is formed on the second conductor layer (178F). The second via conductors (376F) that penetrate the second resin insulating layer (170FU) electrically connect the adjacent second conductor layers (178F).

[0025] The wiring density (L / S) of the buildup layer 70F is 1 / 1 to 5 / 5. The wiring density (L / S) is represented by the smallest L / S of the second conductor layer 178F of the buildup layer 70F.

[0026] FIG. 2 is a partial enlarged view of FIG. 1. As shown in FIG. 2, second resin insulating layer 170F of buildup layer 70F has thickness t2. First resin insulating layer 150F of buildup layer 50F has thickness t1. Thickness t2 is thinner than thickness t1. Second conductor layer 178F has thickness T2. First conductor layer 158F has thickness T1. Thickness T2 is thinner than thickness T1. Second via conductor 376F has diameter D2. First via conductor 156F has diameter D1. Diameter D2 is smaller than diameter D1. First conductor layer 158F has a plurality of conductor circuits (first conductor circuits). Of the plurality of first conductor circuits, the first conductor circuit with the smallest width has width L1. Second conductor layer 178F has a plurality of conductor circuits (second conductor circuits). Of the plurality of second conductor circuits, the second conductor circuit with the smallest width has width L2. Width L2 is smaller than width L1.

[0027] 1, a first solder resist layer 90F is formed on the build-up layer 70F. The first solder resist layer 90F has a first opening 92F that exposes the second conductor layer 178F.

[0028] The printed wiring board 10 has a metal post 98F. The metal post 98F is formed on the second conductor layer 178F exposed from the first opening 92F. An IC chip (not shown) is mounted on the metal post 98F. A metal film 94F made of Ni / Pd / Au is formed on the upper surface of the metal post 98F.

[0029] An electronic component 200 is accommodated in an opening 23 for accommodating an electronic component in the core substrate 30. Therefore, the distance between the IC chip on the buildup layer 70F, which is the rewiring portion 100, and the electronic component 200 in the core substrate 30 is short. Therefore, it is possible to sufficiently supply power to the IC chip via the electronic component 200 in the core substrate 30. In the printed wiring board 10 of the embodiment, the IC chip on the buildup layer 70F does not malfunction. The IC chip on the buildup layer 70F operates normally.

[0030] The lower buildup layer Bu2 is formed of a buildup layer 50S and a buildup layer 70S. The buildup layer 50S is formed on the second surface S of the core material 20. The buildup layer 70S is formed on the buildup layer 50S.

[0031] The buildup layer 50S has a third resin insulating layer 150S, a third conductor layer 158S, and a third via conductor 156S. The third resin insulating layer 150S is formed on the second surface S of the core material 20 or on the third conductor layer 158S. The third conductor layer 158S is formed on the third resin insulating layer 150S. The third via conductor 156S penetrates the third resin insulating layer 150S and is connected to the third conductor layer 158S.

[0032] In the example of FIG. 1, the number of the third resin insulating layers 150S and the number of the third conductor layers 158S are plural. The number of the third resin insulating layers 150S is seven, and the number of the third conductor layers 158S is seven. The third resin insulating layers 150S and the third conductor layers 158S are alternately laminated. When the number of the third resin insulating layers 150S is plural, the third via conductors 156S are formed in each of the third resin insulating layers 150S. The conductor layers sandwiching the third resin insulating layer 150S are electrically connected by the third via conductors 156S. The third resin insulating layer 150S and the first resin insulating layer 150F have the same composition.

[0033] When there are a plurality of third resin insulation layers, the buildup layer (50S) has a third resin insulation layer (150SB) formed directly on the core material (20), an outermost third resin insulation layer (150SM), and other third resin insulation layers (150SU).

[0034] The third resin insulating layer (150SB) is sandwiched between the third conductor layer (158S) and the conductor layer 22 or the external electrode 202. The third resin insulating layer (150SB) is formed on the second surface (S) of the core material 20. The third via conductor (156S) penetrating the third resin insulating layer (150SB) electrically connects the conductor layer 22 or the external electrode 202 of the core substrate 30 to the third conductor layer (158S) directly above it.

[0035] The third resin insulating layer (150SU) is sandwiched between the third conductor layers (158S). The third resin insulating layer (150SU) is formed on the third conductor layer (158S). The third via conductors (156S) penetrating the third resin insulating layer (150SU) electrically connect adjacent third conductor layers (158S).

[0036] The third resin insulating layer (150SM) is formed on the third conductor layer (158S).

[0037] The buildup layer 70S has a fourth resin insulating layer 170S, a fourth conductor layer 178S, and a fourth via conductor 376S. The fourth resin insulating layer 170S is formed on the third resin insulating layer 150SM forming the buildup layer 50S. When the number of the fourth resin insulating layers 170S is plural, the buildup layer 70S has a fourth resin insulating layer 170SB formed directly on the third resin insulating layer 150SM, an outermost fourth resin insulating layer 170SM, and the other fourth resin insulating layers 170SU. A fourth conductor layer 178S is formed on the outermost fourth resin insulating layer 170SM.

[0038] The fourth via conductor (376S) penetrates the outermost first resin insulating layer (150SM), the fourth resin insulating layer (170SB), the fourth resin insulating layer (170SU), and the fourth resin insulating layer (170SM). The fourth via conductor (376S) electrically connects the third conductor layer (158S) and the fourth conductor layer (178S) on the first resin insulating layer (150SM).

[0039] 1, the number of fourth resin insulating layers 170S is plural. The number of fourth resin insulating layers 170S is 6. The fourth resin insulating layer 170S and the second resin insulating layer 170F have the same composition.

[0040] The fourth conductor layer 178S has a fourth via land 376SL formed directly above the fourth via conductor 376S. The fourth via land 376SL is formed directly above and around the fourth via conductor 376S. The fourth via conductor 376S and the fourth via land 376SL are formed simultaneously, and the two are integrally formed.

[0041] A second solder resist layer 90S is formed on the build-up layer Bu2. The second solder resist layer 90S has a second opening 92S that exposes the fourth conductor layer 178S. The fourth conductor layer 178S forms a second pad 93S for connecting to a motherboard. A metal film 94S is formed on the surface of the second pad 93S. [Explanation of symbols]

[0042] 10: Printed wiring board 20: Core material 20A: Via conductor 21: Conductive layer 22: Conductive layer 23 :Aperture 30: Core board 50F: Build-up layer 50S: Build-up layer 70F: Build-up layer 70S: Build-up layer 90F: First solder resist layer 90S: Second solder resist layer 92F: 1st opening 92S: 2nd opening 93S: 2nd pad 94F: Metal film 98S: Metal post 100: Rewiring section 150F: First resin insulation layer 150FB: First resin insulation layer 150FU: First resin insulation layer 150S: Third resin insulation layer 150SB: Third resin insulation layer 150SM: 3rd resin insulation layer 150SU: Third resin insulation layer 156F: First via conductor 156FL: First Beer Land 156FO:Aperture 156S: 3rd via conductor 158F: First conductor layer 158S: Third conductor layer 170F: Second resin insulation layer 170FB: Second resin insulation layer 170FU: Second resin insulation layer 170S: Fourth resin insulation layer 170SB: 4th resin insulation layer 170SM: 4th resin insulation layer 170SU: 4th resin insulation layer 178F: Second conductor layer 178S: 4th conductor layer 200: Electronic parts 201: External electrode 202: External electrode 250F: Second resin insulation layer 256F: Second via conductor 258F: Second conductor layer 376F: Second via conductor 376FL: 2nd Beer Land 376FO:Aperture 376S: 4th via conductor 376SL: 4th Bealand Bu1: Build-up layer Bu2: Build-up layer D1: Diameter of the first via conductor D2: Diameter of the second via conductor F: 1st page L: Wiring density L1: Width of the first conductor circuit at its smallest width L2: Width of the second conductor circuit at its smallest width S: 2nd side T1: Thickness of the first conductor layer t1: Thickness of the first resin insulation layer T2: Thickness of the second conductor layer t2: Thickness of the second resin insulation layer

Claims

1. a core substrate including a core material having a first surface, a second surface opposite to the first surface, and an opening for accommodating an electronic component extending from the first surface to the second surface, the electronic component accommodated in the opening, a first conductor layer on the core material formed on the first surface, and a second conductor layer on the core material formed on the second surface; a first buildup layer formed on the first surface; a second buildup layer formed on the first buildup layer; and an IC chip mounted on the second buildup layer, The first buildup layer has a first resin insulating layer laminated on the first surface, a first conductor layer formed on the first resin insulating layer, and a first via conductor penetrating the first resin insulating layer and electrically connecting the first conductor layer and the first conductor layer on the core material, and the second buildup layer has a second resin insulating layer laminated on the first resin insulating layer, a second conductor layer formed on the second resin insulating layer, and a second via conductor penetrating the second resin insulating layer and electrically connecting the second conductor layer and the first conductor layer, and the first conductor layer is a plurality of the second conductor layer has a first conductor circuit, and among the plurality of first conductor circuits, the first conductor circuit having the smallest width is the smallest first conductor circuit, the second conductor layer has a plurality of second conductor circuits, and among the plurality of second conductor circuits, the second conductor circuit having the smallest width is the smallest second conductor circuit, the width of the smallest second conductor circuit is smaller than the width of the smallest first conductor circuit, the thickness of the second resin insulation layer is thinner than the thickness of the first resin insulation layer, the diameter of the second via conductor is smaller than the diameter of the first via conductor, and the thickness of the second conductor layer is thinner than the thickness of the first conductor layer.

2. 2. The printed wiring board according to claim 1, wherein the wiring density (L / S) of the first buildup layer is 7 / 7 to 30 / 30, and the wiring density (L / S) of the second buildup layer is 1 / 1 to 5 / 5.

Images