Semiconductor device, manufacturing method of semiconductor device, and electronic device

Abstract

To realize a semiconductor device of a high output, having an excellent high-frequency property.SOLUTION: A semiconductor device 1A contains: a gate electrode 20 group that is provided to an active region 10a surrounded by an element separation region 10b of a substrate 10 in a plan view, is extended in a direction D1 and is arranged in parallel in a direction D2 orthogonal to the direction D1; a source electrode 30 group; and a drain electrode 40 group. The semiconductor device 1A further contains a via 33 that is provided to each of the active region 10a and the element separation region 10b so as to penetrate the substrate 10. The source electrode 30 group contains: a source electrode 31 that overlaps the via 33 of the active region 10a in the plan view, and is connected thereto; and a source electrode 32 connected to the via 33 of the element separation region 10b. A high output is realized in the semiconductor device 1A by increasing the number of gate electrode 20 groups by reducing an occupied area of the second electrode 30 group in the active region 10a, and a high frequency property is improved by suppressing an increase of a source inductance or the like involved in a GND connection.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] A field effect transistor is known as an example of a semiconductor device. For example, a high-power field effect transistor having a comb-shaped finger-shaped gate electrode structure is known. For such a field effect transistor, a technology is known that employs a source island via hole structure in which the source electrode is connected to a plated heat sink (PHS) on the back side by a via hole of a predetermined shape and arrangement (Patent Document 1).

[0003] Also, there is known a high-frequency MESFET in which a plurality of drain electrodes, gate electrodes, and source electrodes are alternately arranged in the gate width direction in an operating region provided on the surface of a semiconductor substrate. Regarding such a high-frequency MESFET, there is known a technique in which the gate electrodes and drain electrodes are spanned by an air bridge and each source electrode is connected by wiring, and a technique in which both end source electrodes are connected via through holes to a PHS provided on the back surface of the semiconductor substrate (Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2000-332030 A [Patent Document 2] JP 2006-156902 A Summary of the Invention [Problem to be solved by the invention]

[0005] A semiconductor device is known in which a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes are arranged in parallel in a plan view in a substrate having an active region surrounded by an element isolation region. A technique is known for such a semiconductor device, in which a via is provided through the substrate to connect to the source electrode in the active region, and the source electrode is connected to the ground (GND) through the via, thereby reducing the wiring path length of the GND connection. This technique improves high frequency characteristics by reducing source inductance.

[0006] However, when such a technique is adopted, the width of the source electrode and the distance between the pair of gate electrodes facing each other across the source electrode are limited to a certain size due to the width (diameter) of the via connected to the source electrode in the active region. As a result, the number of gate electrodes that can be arranged in an active region of a given dimension decreases, which may reduce the output of the semiconductor device.

[0007] In one aspect, the present invention aims to provide a high-output semiconductor device having excellent high-frequency characteristics. [Means for solving the problem]

[0008] In one aspect, a semiconductor device is provided, comprising: a substrate having, in a planar view, a first region and a second region surrounding the first region; a plurality of gate electrodes, a plurality of source electrodes and a plurality of drain electrodes provided in the first region, extending in a first direction in a planar view and arranged in parallel in a second direction perpendicular to the first direction; a first via provided in the first region and penetrating the substrate; and a second via provided in the second region and penetrating the substrate, wherein the plurality of source electrodes overlap with the first via in a planar view, and include a first source electrode connected to the first via and a second source electrode connected to the second via.

[0009] In another aspect, there is provided a method for manufacturing the semiconductor device as described above, and an electronic device including the semiconductor device as described above. Effect of the Invention

[0010] In one aspect, it is possible to realize a high-output semiconductor device having excellent high-frequency characteristics. [Brief description of the drawings]

[0011] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Diagram 2] FIG. 2 is a diagram illustrating a first example of a layout of a semiconductor device. [Diagram 3] FIG. 11 is a diagram illustrating a second example of a layout of the semiconductor device. [Figure 4] FIG. 1 is a diagram (part 1) for explaining an example of a semiconductor device according to a first embodiment. [Diagram 5] FIG. 2 is a diagram (part 2) illustrating an example of the semiconductor device according to the first embodiment. [Figure 6] FIG. 3 is a diagram (part 3) illustrating an example of the semiconductor device according to the first embodiment. [Figure 7] FIG. 4 is a diagram (part 4) illustrating an example of the semiconductor device according to the first embodiment. [Figure 8] FIG. 5 is a diagram (part 5) for explaining an example of the semiconductor device according to the first embodiment. [Figure 9] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device according to a first embodiment; [Figure 10] FIG. 2 is a second view for explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; [Figure 11] FIG. 11 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 4 is a view (part 4) illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] FIG. 5 is a diagram (part 5) illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] 10A to 10C are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 15]13A to 13C are diagrams illustrating an example of a semiconductor device according to a third embodiment. [Figure 16] 13A to 13C are diagrams illustrating an example of a semiconductor package according to a fourth embodiment. [Figure 17] FIG. 13 is a diagram illustrating an example of a power factor correction circuit according to a fifth embodiment. [Figure 18] FIG. 13 is a diagram illustrating an example of a power supply device according to a sixth embodiment. [Figure 19] FIG. 13 is a diagram illustrating an example of an amplifier according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] First, an example of a semiconductor device will be described. As an example of a semiconductor device, one using a nitride semiconductor is known. Semiconductor devices using nitride semiconductors are being developed as high-voltage, high-power devices by utilizing characteristics such as high saturation electron velocity and wide band gap. For example, gallium nitride (GaN) has a band gap of 3.4 eV, which is larger than the band gap of silicon (Si) of 1.1 eV and the band gap of gallium arsenide (GaAs) of 1.4 eV, and has a high dielectric breakdown field. Therefore, nitride semiconductors such as GaN are promising materials for semiconductor devices that operate at high voltages and have high power, such as semiconductor devices applied to amplifiers, power supplies, communication devices, radar devices, etc. As a semiconductor device using a nitride semiconductor, a field effect transistor (FET), for example, a high electron mobility transistor (HEMT), is known.

[0013] Fig. 1 is a diagram for explaining an example of a semiconductor device, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device. The semiconductor device 1 shown in Fig. 1 is an example of a HEMT. The semiconductor device 1 includes a substrate 10 including an underlying substrate 11 and a semiconductor layer 12 provided thereon. The semiconductor device 1 further includes a gate electrode 20, a source electrode 30, and a drain electrode 40 provided on the substrate 10.

[0014] The base substrate 11 may be made of various materials such as silicon carbide (SiC), Si, GaN, aluminum nitride (AlN), sapphire, diamond, etc. The base substrate 11 may have a single layer structure of one material, or a laminate structure of one or more materials.

[0015] A nitride semiconductor such as GaN or aluminum gallium nitride (AlGaN) is used for the semiconductor layer 12. The semiconductor layer 12 includes, for example, a channel layer 12a, a barrier layer 12b, and a cap layer 12c as shown in FIG.

[0016] The channel layer 12a is provided on the base substrate 11. The channel layer 12a is made of, for example, GaN. The channel layer 12a may be made of a nitride semiconductor such as AlGaN, indium gallium nitride (InGaN), or indium aluminum gallium nitride (InAlGaN). The channel layer 12a may be a single-layer structure of one type of nitride semiconductor, or a multilayer structure of one or more types of nitride semiconductors. The channel layer 12a is formed on the base substrate 11 by using a metal organic chemical vapor deposition (MOCVD) or metal organic vapor phase epitaxy (MOVPE) method, a molecular beam epitaxy (MBE) method, or the like. The channel layer 12a is also called an electron transport layer, a carrier transport layer, or the like.

[0017] The barrier layer 12b is provided on the channel layer 12a. For example, AlGaN is used for the barrier layer 12b. Alternatively, a nitride semiconductor such as indium aluminum nitride (InAlN), InAlGaN, or AlN may be used for the barrier layer 12b. The barrier layer 12b may have a single-layer structure of one type of nitride semiconductor, or a laminate structure of one or more types of nitride semiconductors. The barrier layer 12b is formed on the channel layer 12a by using a MOVPE method or the like. The barrier layer 12b is also called an electron supply layer, a carrier supply layer, or the like.

[0018] Here, the channel layer 12a and the barrier layer 12b are made of nitride semiconductors with different bandgaps. A two-dimensional electron gas (2DEG) region 101 is generated in the channel layer 12a by spontaneous polarization of the nitride semiconductor of the barrier layer 12b and piezoelectric polarization generated in the barrier layer 12b due to strain caused by a lattice constant difference between the barrier layer 12b and the nitride semiconductor of the channel layer 12a. The channel layer 12a and the barrier layer 12b are made of nitride semiconductors in such a combination that the 2DEG region 101 is generated in the channel layer 12a.

[0019] The cap layer 12c is provided on the barrier layer 12b. The cap layer 12c is made of a doped (p-type or n-type) or non-doped nitride semiconductor such as GaN. The cap layer 12c may have a single-layer structure of one type of nitride semiconductor, or a laminate structure of one or more types of nitride semiconductors. The cap layer 12c has a function of protecting the barrier layer 12b and the like. In addition, the cap layer 12c may have a function of modulating the electron concentration of the 2DEG region 101 of the channel layer 12a.

[0020] Although not shown here, a layer of AlN or the like may be provided between the base substrate 11 and the channel layer 12a as an initial layer, a layer of AlGaN or the like may be provided as a buffer layer, or a layer of GaN or the like doped with iron (Fe) may be provided. In addition, a layer of AlN, AlGaN or the like may be provided between the base substrate 11 and the channel layer 12a as a barrier layer (back barrier layer) for realizing a quantum well (quantum confinement) structure. A layer of AlGaN, InGaN or the like may be provided between the channel layer 12a and the barrier layer 12b as a spacer layer. The semiconductor layer 12 may include one or more of such initial layers, buffer layers, spacer layers, back barrier layers, etc., in addition to the channel layer 12a, the barrier layer 12b, and the cap layer 12c.

[0021] The gate electrode 20 is provided on the semiconductor layer 12. A metal material is used for the gate electrode 20. For example, a laminate having nickel (Ni) and gold (Au) provided thereon is provided as the gate electrode 20. The gate electrode 20 is formed by using a deposition method or the like. The gate electrode 20 is provided so as to function as, for example, a Schottky electrode. Alternatively, the gate electrode 20 may be provided on the semiconductor layer 12 via a gate insulating film (not shown) to form a MIS (Metal Insulator Semiconductor) type gate structure.

[0022] The source electrode 30 and the drain electrode 40 are provided on the semiconductor layer 12 on both sides of the gate electrode 20, on the cap layer 12c in this example, at a distance from the gate electrode 20. A metal material is used for the source electrode 30 and the drain electrode 40. For example, a laminate having tantalum (Ta) and aluminum (Al) provided thereon is provided as the source electrode 30 and the drain electrode 40. The source electrode 30 and the drain electrode 40 are formed by using a deposition method or the like. The source electrode 30 and the drain electrode 40 are provided so as to function as ohmic electrodes. As long as the source electrode 30 and the drain electrode 40 function as ohmic electrodes, they may be connected to the barrier layer 12b without being limited to the cap layer 12c, or may be connected to the channel layer 12a through the barrier layer 12b. A contact layer (regrowth layer) using a nitride semiconductor such as n-type GaN or n-type AlGaN may be provided at the portion of the semiconductor layer 12 where the source electrode 30 and the drain electrode 40 are connected.

[0023] When the semiconductor device 1 is in operation, a predetermined voltage is applied between the source electrode 30 and the drain electrode 40, and a predetermined voltage is applied to the gate electrode 20. The amount of charge passing through the 2DEG region 101 immediately below the gate electrode 20 between the source electrode 30 and the drain electrode 40 is controlled by the electric field effect caused by the voltage applied to the gate electrode 20, thereby controlling the output drain current. In this manner, the transistor function of the semiconductor device 1 is realized.

[0024] Incidentally, as a layout of a semiconductor device equipped with a HEMT, for example, the following one shown in FIG. 2 is known. Fig. 2 is a diagram for explaining a first example of the layout of a semiconductor device, Fig. 2 is a schematic plan view of a main part of an example of a semiconductor device.

[0025] 2 has a plurality of finger-shaped gate electrodes 120 (also referred to as "gate fingers"), a plurality of island-shaped source electrodes 130, and a plurality of finger-shaped drain electrodes 140 (also referred to as "drain fingers"). The group of gate electrodes 120, the group of source electrodes 130, and the group of drain electrodes 140 are each shaped to extend in a direction D1, and at least a portion of each is provided on an active region 110a (also referred to as "element region") that is surrounded and defined by an element isolation region 110b formed in the substrate 110.

[0026] The group of source electrodes 130 and the group of drain electrodes 140 extending in the direction D1 are provided such that the source electrodes 130 and the drain electrodes 140 are alternately arranged at a distance from each other in a direction D2 perpendicular to the direction D1 in a plan view. Each of the group of gate electrodes 120 extending in the direction D1 is provided between adjacent source electrodes 130 and drain electrodes 140 of the group of source electrodes 130 and the group of drain electrodes 140 alternately arranged in the direction D2 in a plan view, and at a distance from each other. The portions between the source electrodes 130 and the drain electrodes 140 sandwiching each gate electrode 120 function as transistor elements (or transistor cells).

[0027] It should be noted that the numbers of the gate electrodes 120, the source electrodes 130 and the drain electrodes 140 of the semiconductor device 100A, that is, the number of transistor elements, are not limited to those shown in FIG.

[0028] The gate electrodes 120 are connected to gate wiring 121 (also called "gate bus line"). The gate wiring 121 is provided on the substrate 110 outside the active region 110a, and in the layout of Fig. 2, on the element isolation region 110b on one side (the left side in Fig. 2) of the active region 110a in the direction D1. The gate wiring 121 extends in the direction D2.

[0029] The drain electrodes 140 are connected to a drain wiring 141 (also called a "drain pad"). The drain wiring 141 is provided on the substrate 110 outside the active region 110a, and in the layout of Fig. 2, on the element isolation region 110b on the other side (the right side in Fig. 2) of the active region 110a in the direction D1. The drain wiring 141 extends in the direction D2.

[0030] The source electrodes 130 are provided in an island shape on the substrate 110 inside the active region 110a. In the semiconductor device 100A, each source electrode 130 is connected to a via 133 provided so as to penetrate the substrate 110 at a position directly below the source electrode 130 and overlap with the via 133. Each via 133 is connected to a metal layer (not shown) provided on the back surface of the substrate 110 (the surface 110d opposite to the surface 110c on which the source electrodes 130 and the like are provided). This metal layer is set to a GND potential. The source electrode 130 is connected to the GND through the via 133 provided directly below it and the metal layer to which it is connected. In the semiconductor device 100A, the source electrode 130 is connected to the GND by the via 133 and the metal layer, so that an increase in the wiring path length for the GND connection is suppressed and the source inductance is reduced. This improves the high-frequency characteristics and other performance of the semiconductor device 100A. The via 133 that connects the source electrode 130 to GND in this manner is also called an ISV (Inner Source Via).

[0031] In the semiconductor device 100A, a drain current flowing through a group of transistor elements in the active region 110a is output from the group of drain electrodes 140 through drain wiring 141 as an output of the group of transistor elements.

[0032] In this manner, in the semiconductor device 100A, each source electrode 130 is connected to the GND through the via 133, thereby reducing the source inductance and improving the high frequency characteristics of the semiconductor device 100A. However, in the semiconductor device 100A, since each source electrode 130 is connected to the via 133 at a position directly below where it overlaps, the width W1 of the source electrode 130 in the direction D2 is limited to a size equal to or larger than the width (diameter) W0 of the via 133 in the direction D2. Therefore, the distance L1 between the pair of gate electrodes 120 facing each other in the direction D2 across the source electrode 130 becomes larger than the distance (e.g., distance L3) between the pair of gate electrodes 120 facing each other in the direction D2 when the source electrode 130 is not connected to the via 133 and has the same width as the drain electrode 140. As a result, the number of gate electrodes 120 that can be arranged in the active region 110a of a given dimension decreases, and the number of transistor elements decreases, which may prevent the semiconductor device 100A from achieving a sufficiently high output.

[0033] For example, in the semiconductor device 100A applied to a high-power amplifier, it may be desired to arrange a large number of gate electrodes 120, such as several hundred, in the active region 110a to realize a desired output. However, as described above, in the semiconductor device 100A, due to the diameter W0 of the via 133 connected to the source electrode 130 in the active region 110a, the width W1 of the source electrode 130 and the distance L1 between the pair of gate electrodes 120 facing each other across the via are limited to a certain size or more. Therefore, the number of gate electrodes 120 that can be arranged in the active region 110a of a given dimension is limited. In order to increase the number of gate electrodes 120 to increase the output, it is necessary to increase the dimension of the active region 110a, and as a result, the semiconductor device 100A becomes larger in the direction D2. In the semiconductor device 100A, it may be difficult to arrange a desired number of gate electrodes 120 in the active region 110a of an allowable dimension, and to increase the number of gate electrodes 120 to increase the output.

[0034] In contrast, consider the layout shown in Figure 3 below. Fig. 3 is a diagram for explaining a second example of the layout of a semiconductor device, Fig. 3 is a schematic plan view of a main part of an example of a semiconductor device.

[0035] 3 has a configuration in which, as a group of source electrodes 130 provided in an active region 110a of a substrate 110, source electrodes 131 provided directly below a via 133 penetrating the substrate 110 and source electrodes 132 not provided directly below a via 133 are mixed. The source electrode 131 provided directly below the via 133 has a shape such that a width W1 in a direction D2 thereof is equal to or greater than a width (diameter) W0 in the direction D2 of the via 133. The source electrode 132 not provided directly below the via 133 has a shape such that a width W2 in the direction D2 thereof is less than the diameter W0 of the via 133, for example, is the same as or equivalent to a width W3 in the direction D2 of the drain electrode 140.

[0036] The source electrode 131 directly below which the via 133 is provided is connected to the via 133. The source electrode 131 is connected to GND through the via 133 and a metal layer (not shown) provided on the back surface (surface 110d) of the substrate 110 and connected to the via 133. The source electrode 131 directly below which the via 133 is provided and the source electrode 132 not directly below which the via 133 is provided are connected to each other by a source wiring 135 drawn out from them. The source electrode 132 not directly below which the via 133 is provided is connected to the source electrode 131 directly below which the via 133 is provided through the source wiring 135, and is connected to GND through the via 133 directly below the source electrode 131 and the metal layer on the back surface of the substrate 110.

[0037] The semiconductor device 100B differs from the semiconductor device 100A (FIG. 2) in that it has such a configuration. Note that the numbers of the gate electrodes 120, the source electrodes 130, and the drain electrodes 140 of the semiconductor device 100B, i.e., the number of transistor elements, are not limited to those shown in FIG.

[0038] In the semiconductor device 100B, the active region 110a includes a mixture of source electrodes 131 with vias 133 provided directly below and source electrodes 132 with no vias 133 provided directly below. The width W1 in the direction D2 of the source electrode 131 with the vias 133 provided directly below is equal to or greater than the diameter W0 of the vias 133, while the width W2 in the direction D2 of the source electrode 132 with no vias 133 provided directly below is less than the diameter W0 of the vias 133. Therefore, the distance L2 between the pair of gate electrodes 120 facing each other across the source electrode 132 with no vias 133 provided directly below is narrower than the distance L1 between the pair of gate electrodes 120 facing each other across the source electrode 131 with the vias 133 provided directly below. Therefore, in the semiconductor device 100B, it is possible to increase the number of gate electrodes 120 that can be arranged in the active region 110a of a given dimension, compared to the semiconductor device 100A (FIG. 2) in which the vias 133 are provided directly below each of the source electrodes 130. In the semiconductor device 100B, the number of gate electrodes 120 arranged in the active region 110a of a given dimension can be increased, and the semiconductor device 100B can be made to have a higher output.

[0039] However, in the semiconductor device 100B, the source electrode 131 under which the via 133 is provided and the source electrode 132 under which the via 133 is not provided are connected by the source wiring 135. The source wiring 135 is drawn onto the substrate 110, for example, to the gate wiring 121 side to which the gate electrodes 120 are connected, and routed on the gate wiring 121 via an insulating film (not shown). In the semiconductor device 100B, since the source electrode 131 and the source electrode 132 are connected by the source wiring 135, the wiring path length for GND connection increases, and there is a risk of an increase in source inductance. Furthermore, if the source wiring 135 is disposed on the gate wiring 121 via an insulating film, there is a risk of an increase in gate-source capacitance Cgs. The increase in source inductance and the increase in gate-source capacitance Cgs can be factors that degrade the high-frequency characteristics of the semiconductor device 100B. In the semiconductor device 100B, while it is possible to increase the output by increasing the number of gate electrodes 120 in terms of layout, it is possible that sufficient high frequency characteristics cannot be obtained due to the source wiring 135.

[0040] In view of the above, a configuration as shown in the following embodiment is adopted to realize a high-output semiconductor device having excellent performance. [First embodiment] 4 to 8 are diagrams illustrating an example of a semiconductor device according to the first embodiment. FIG. 4 is a schematic plan view of a main part of an example of a semiconductor device. FIG. 5 is a schematic cross-sectional view of a main part taken along line VV in FIG. 4. FIG. 6 is a schematic cross-sectional view of a main part taken along line VI-VI in FIG. 4. FIG. 7 is a schematic cross-sectional view of a main part taken along line VII-VII in FIG. 4. FIG. 8 is a schematic cross-sectional view of a main part taken along line VIII-VIII in FIG. 4.

[0041] A semiconductor device 1A shown in FIGS. 4 to 8 is an example of a HEMT. As shown in FIG. 4, the semiconductor device 1A has a substrate 10, a plurality of finger-shaped gate electrodes 20 (gate fingers), a plurality of source electrodes 30, and a plurality of finger-shaped drain electrodes 40 (drain fingers) provided on the substrate 10. The substrate 10 has an active region 10a (element region) and an element isolation region 10b surrounding the active region 10a in a plan view. As shown in FIGS. 5 to 8, the substrate 10 has an underlying substrate 11 and a semiconductor layer 12 provided thereon. The semiconductor layer 12 includes a channel layer 12a, a barrier layer 12b, a cap layer 12c, and the like as shown in FIG. 1 above. A 2DEG region 101 (FIG. 1) is generated in the semiconductor layer 12 (its channel layer 12a) of the active region 10a. The gate electrodes 20, the source electrodes 30 and the drain electrodes 40 are each shaped to extend in a direction D1, and at least a portion of each is provided on an active region 10a defined by being surrounded by an element isolation region 10b of the substrate 10.

[0042] As shown in Figures 5 to 8, the gate electrodes 20, the source electrodes 30, and the drain electrodes 40 provided on the substrate 10, as well as the gate wirings 21, the source wirings 35, and the drain wirings 41 described below, are covered with an insulating film 50. For convenience, the insulating film 50 shown in Figures 5 to 8 is omitted in Figure 4.

[0043] As shown in Fig. 4, the source electrodes 30 and the drain electrodes 40 extending in the direction D1 are arranged so that the source electrodes 30 and the drain electrodes 40 are alternately arranged at a distance from each other in a direction D2 perpendicular to the direction D1 in a plan view. Each of the gate electrodes 20 extending in the direction D1 is arranged between adjacent source electrodes 30 and drain electrodes 40 of the source electrodes 30 and the drain electrodes 40 alternately arranged in the direction D2 in a plan view, and is spaced from each other. The portions between the source electrodes 30 and the drain electrodes 40 sandwiching each gate electrode 20 function as transistor elements (transistor cells). In a plan view, the gate electrodes 20, the source electrodes 30, and the drain electrodes 40 extending in the direction D1 are arranged in parallel in a direction D2 perpendicular to the direction D1.

[0044] It should be noted that the numbers of the gate electrodes 20, the source electrodes 30 and the drain electrodes 40 of the semiconductor device 1A, that is, the number of transistor elements, are not limited to those shown in FIG. The gate electrodes 20 are made of a metal material such as Ni or Au. As shown in FIG. 4, the gate electrodes 20 are connected to a gate wiring 21 (gate bus line). The gate wiring 21 is provided on the substrate 10 outside the active region 10a, and in the layout of FIG. 4, on the element isolation region 10b on one side (left side in FIG. 4) of the active region 10a in the direction D1. The gate electrodes 20 extend from the active region 10a to the element isolation region 10b on one side in the direction D1, and are connected to the gate wiring 21 on the element isolation region 10b. The gate wiring 21 extends on the substrate 10 in the direction D2. The gate wiring 21 is made of a metal material such as Ni or Au.

[0045] The drain electrodes 40 are made of a metal material such as Ta or Al. As shown in FIG. 4, the drain electrodes 40 are connected to a drain wiring 41 (drain pad). The drain wiring 41 is provided on the substrate 10 outside the active region 10a, and in the layout of FIG. 4, on the element isolation region 10b on the other side (the right side in FIG. 4) of the active region 10a in the direction D1. The drain electrodes 40 extend from the active region 10a to the element isolation region 10b on the other side in the direction D1, and are connected to the drain wiring 41 on the element isolation region 10b. The drain wiring 41 includes an air bridge wiring 41c at a position where it intersects with a source wiring 35 described later. The drain wiring 41 extends on the substrate 10 in the direction D2. The drain wiring 41 is made of a metal material such as Ta, Al, or Au.

[0046] Metal materials such as Ta and Al are used for the source electrodes 30. As shown in Fig. 4 and Fig. 5, the semiconductor device 1A includes, as the source electrodes 30 provided in the active region 10a of the substrate 10, a source electrode 31 provided directly below with a via 33 penetrating the substrate 10 and a source electrode 32 not provided directly below with a via 33 penetrating the substrate 10.

[0047] As shown in FIG. 4, the source electrode 31 under which the via 33 is provided is provided in an island shape on the substrate 10 inside the active region 10a. As shown in FIG. 4 and FIG. 5, the source electrode 31 is connected to the via 33 provided under it, that is, the via 33 provided to penetrate the substrate 10 at a position overlapping with the source electrode 31. A metal material such as Au or copper (Cu) is used for the via 33. The source electrode 31 under which the via 33 is provided has a shape such that the width W1 (FIG. 4) in the direction D2 is equal to or larger than the width (diameter) W0 of the via 33 in the direction D2. As shown in FIG. 5, the via 33 is connected to a metal layer 34 provided on the back surface of the substrate 10 (the surface 10d opposite to the surface 10c on which the source electrodes 31 and the like are provided). A metal material such as Au or Cu is used for the metal layer 34. The metal layer 34 is set to a GND potential. The source electrode 31 is connected to GND through a via 33 provided directly below it and a metal layer 34 to which it is connected.

[0048] As shown in Fig. 4, the source electrode 32 not directly below the via 33 is connected to the source wiring 35. The source wiring 35 is provided on the substrate 10 outside the active region 10a, on the element isolation region 10b on the drain wiring 41 side in the direction D1 of the active region 10a in the layout of Fig. 4. The source wiring 35 is provided on the element isolation region 10b, on an extension line extending from the source electrode 32 to the drain wiring 41 side in the direction D1. The source electrode 32 extends from the active region 10a to the element isolation region 10b on the drain wiring 41 side, and is connected to the source wiring 35 on the element isolation region 10b. The source wiring 35 is made of a metal material such as Ta, Al, or Au.

[0049] 4, 7, and 8, the source wiring 35 is connected to the via 33 provided directly below it, i.e., the via 33 provided so as to penetrate the substrate 10 at a position overlapping with the source wiring 35. The source wiring 35 provided directly below the via 33 has a shape such that its width W4 (FIG. 4) in the direction D2 is equal to or greater than the diameter W0 of the via 33, for example, the same as or equivalent to the width W1 (FIG. 4) in the direction D2 of the source electrode 31 provided directly below the via 33. The source electrode 32 not provided directly below the via 33 has a shape such that its width W2 (FIG. 4) in the direction D2 is less than the diameter W0 of the via 33, for example, the same as or equivalent to the width W3 (FIG. 4) in the direction D2 of the drain electrode 40. The width W2 in the direction D2 of the source electrode 32 not provided directly below the via 33 is narrower than the width W4 in the direction D2 of the source wiring 35 provided directly below the via 33 and the width W1 of the source electrode 31 provided directly below the via 33.

[0050] 4, 7 and 8, the via 33 provided directly below the source wiring 35 is connected to a metal layer 34 provided on the back surface of the substrate 10 (surface 10d opposite to surface 10c on which the source electrode 32, source wiring 35, etc. are provided). The metal layer 34 is at GND potential. The source wiring 35 is connected to GND through the via 33 directly below it and the metal layer 34 to which it is connected. The source electrode 32 connected to the source wiring 35 and not provided directly below by the via 33 is connected to GND through the source wiring 35, the via 33, and the metal layer 34.

[0051] In this manner, in the semiconductor device 1A, the source electrode 31 directly below the via 33 is connected to GND by the via 33 in the active region 10a and the metal layer 34 on the back surface of the substrate 10. The source electrode 32 not directly below the via 33 is connected to GND by the source wiring 35 in the element isolation region 10b, the via 33 in the element isolation region 10b, and the metal layer 34 on the back surface of the substrate 10. This prevents the increase in the wiring path length for GND connection in the semiconductor device 1A, and reduces the source inductance. This improves the high-frequency characteristics and other performance of the semiconductor device 1A. The via 33 that connects the source electrode 31 and the source electrode 32 to GND is also called an ISV.

[0052] The number of vias 33 provided directly below each source electrode 31 and the number of vias 33 provided directly below each source wiring 35 are not limited to one and may be two or more. The planar shape of the vias 33 provided directly below each source electrode 31 and the planar shape of the vias 33 provided directly below each source wiring 35 are not limited to an ellipse and may be various planar shapes such as a circle, a rectangle, or a polygon.

[0053] The source wiring 35 to which the source electrode 32 not provided directly below the via 33 is connected is provided at a position to intersect (partially overlap) with the drain wiring 41 extending in the direction D2, as shown in Fig. 4, for example. At a position where the source wiring 35 does not intersect with the drain wiring 41, the drain electrode 40 extending in the direction D1 from the active region 10a to the element isolation region 10b is connected to the drain wiring 41 extending in the direction D2, as shown in Fig. 4 and Fig. 6, for example. At a position where the source wiring 35 intersects with the drain wiring 41, the source electrode 32 extending in the direction D1 from the active region 10a to the element isolation region 10b is connected to the source wiring 35, as shown in Fig. 4 and Fig. 7, for example.

[0054] For example, as shown in FIGS. 4, 7, and 8, the drain wiring 41 has an air bridge wiring 41c at a position where the source wiring 35 intersects with the drain wiring 41, which connects the portions of the drain wiring 41 on both sides of the source wiring 35 across the source wiring 35. The air bridge wiring 41c connects the portions of the drain wiring 41 on both sides of the source wiring 35, and overlaps with the source wiring 35 via the insulating film 50 and the cavity 60. In the semiconductor device 1A, the drain wiring 41 is configured to include such an air bridge wiring 41c, so that the source wiring 35 can be arranged at a position where it intersects with the drain wiring 41 (the air bridge wiring 41c). By arranging the source wiring 35 at a position where it intersects with the drain wiring 41, it is possible to prevent the semiconductor device 1A from becoming large in size in the direction D1.

[0055] In the semiconductor device 1A, the drain current flowing through the group of transistor elements in the active region 10a is output from the group of drain electrodes 40 through the drain wiring 41 as the output of the group of transistor elements.

[0056] The active region 10a of the substrate 10 is also referred to as the "first region", and the element isolation region 10b surrounding it is also referred to as the "second region". The direction D1 is also referred to as the "first direction", and the direction D2 perpendicular to the direction D1 is also referred to as the "second direction". In the direction D1, the side (one side) where the gate wiring 21 is arranged with respect to the active region 10a is also referred to as the "first side", and the side (the other side) where the drain wiring 41 is arranged with respect to the active region 10a is also referred to as the "second side". The via 33 provided in the active region 10a is also referred to as the "first via", and the via 33 provided in the element isolation region 10b is also referred to as the "second via". Of the source electrodes 30, the source electrode 31 that overlaps and is connected to the via 33 in the active region 10a is also referred to as the "first source electrode," and the source electrode 32 that does not overlap with the via 33 in the active region 10a and is connected to the via 33 in the element isolation region 10b via a source wiring 35 is also referred to as the "second source electrode."

[0057] In the semiconductor device 1A, the active region 10a includes a mixture of source electrodes 31 with vias 33 provided directly below and source electrodes 32 with vias 33 not provided directly below. The width W1 in the direction D2 of the source electrode 31 with the vias 33 provided directly below is equal to or larger than the diameter W0 of the vias 33, while the width W2 in the direction D2 of the source electrode 32 with the vias 33 not provided directly below is smaller than the diameter W0 of the vias 33. Therefore, the distance L2 between the pair of gate electrodes 20 facing each other across the source electrode 32 with the vias 33 not provided directly below is narrower than the distance L1 between the pair of gate electrodes 20 facing each other across the source electrode 31 with the vias 33 provided directly below. Therefore, in the semiconductor device 1A, it is possible to increase the number of gate electrodes 20 that can be arranged in the active region 10a of a given dimension, compared to the case where vias are provided directly below all of the source electrode groups (for example, the semiconductor device 100A in FIG. 2).

[0058] In this manner, in the semiconductor device 1A, the area occupied by the group of source electrodes 31 and the group of source electrodes 32 in the active region 10a of a given dimension can be reduced, and the number of groups of gate electrodes 20 arranged in the active region 10a can be increased, thereby enabling the semiconductor device 1A to have a higher output.

[0059] In the semiconductor device 1A, the source electrode 31 directly below which the via 33 is provided is connected to the GND through the via 33 and the metal layer 34 on the back surface of the substrate 10 to which it is connected. Therefore, the wiring path length for the GND connection is realized at the shortest distance, and inductance is reduced. On the other hand, the source electrode 32 directly below which the via 33 is not provided is connected to the source wiring 35 arranged on the drain wiring 41 side. The via 33 connected to the source wiring 35 is provided directly below the source wiring 35. The source wiring 35 is connected to the metal layer 34 on the back surface of the substrate 10 through the via 33 directly below it. The source electrode 32 directly below which the via 33 is not provided is connected to the GND through the source wiring 35, the via 33 to which it is connected, and the metal layer 34. As a result, the wiring path length for the GND connection is longer than that of the source electrode 31. However, in the case of the source electrode 32, the increase in the wiring path length for the GND connection is suppressed compared to when the source electrode groups are connected to each other by source wiring (for example, the semiconductor device 100B in Figure 3 above), and the source inductance is reduced.

[0060] Furthermore, in the semiconductor device 1A, the source wiring 35 connected to the source electrode 32 that does not have a via 33 provided directly below is drawn to the drain wiring 41 side, and not drawn to the gate wiring 21 side. This prevents the source wiring 35 from being disposed at a position where it overlaps with the gate wiring 21, that is, prevents the source wiring 135 from being disposed on the gate wiring 121 with an insulating film interposed therebetween, as in the semiconductor device 100B (FIG. 3). Therefore, in the semiconductor device 1A, an increase in the gate-source capacitance Cgs is suppressed, and the cutoff frequency (f T = gm / (2π × Cgs), gm: mutual conductance) and other high frequency characteristics are improved.

[0061] In this way, in the semiconductor device 1A, increases in source inductance and gate-source capacitance Cgs due to GND connection can be suppressed, and the high frequency characteristics of the semiconductor device 1A can be improved.

[0062] Furthermore, in the semiconductor device 1A, the source wiring 35, which is drawn from the source electrode 32 not directly below the via 33 to the drain wiring 41 side, is disposed at a position where it intersects (partially overlaps) with the drain wiring 41. The drain wiring 41 is configured to include an air bridge wiring 41c that straddles the source wiring 35. This prevents the semiconductor device 1A from becoming larger in size in the direction D1 compared to a case where the source wiring 35 does not intersect with the drain wiring 41. In addition, the air bridge wiring 41c prevents the drain wiring 41 and the source wiring 35 from coming close to each other, thereby preventing an increase in the drain-source capacitance Cds.

[0063] According to the above-mentioned configuration, a high-output semiconductor device 1A having excellent high-frequency characteristics is realized while preventing its size from increasing. In the above description, the semiconductor device 1A is exemplified in which the source electrodes 31 with the vias 33 provided directly below and the source electrodes 32 with the vias 33 not provided directly below are alternately arranged in the direction D2 in a plan view, but the arrangement of the source electrodes 31 and 32 is not limited to this. The source electrodes 31 and 32 do not necessarily need to be alternately arranged in the direction D2 in a plan view. Even if the source electrodes 31 and 32 are not alternately arranged in the direction D2 in this way, the above-mentioned effects can be obtained.

[0064] Next, a method for manufacturing the semiconductor device 1A will be described. Figures 9 to 13 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 9(A), 9(B), 9(C), 10(A), 10(B), and 10(C) each show a schematic cross-sectional view of an example of a main part of each step in the manufacture of an active region of a semiconductor device. Figures 11(A), 11(B), 11(C), 12(A), 12(B), 12(C), 13(A), and 13(B) each show a schematic cross-sectional view of an example of a main part of each step in the manufacture of an isolation region of a semiconductor device.

[0065] First, the manufacture of the active region 10a of the semiconductor device 1A will be described with reference to Figures 9(A) to 9(C) and 10(A) to 10(C). Figures 9(A) to 9(C) and 10(A) to 10(C) each show a schematic cross section of a portion of the active region 10a taken along direction D2.

[0066] First, a substrate 10 as shown in Fig. 9(A) is prepared. That is, the channel layer 12a, the barrier layer 12b, the cap layer 12c, and the like as shown in Fig. 1 are formed as the semiconductor layer 12 on a base substrate 11 by using a method such as MOVPE, thereby preparing the substrate 10.

[0067] A metal material having a laminated structure of Ta and Al or the like is formed on the surface 10c (front surface) of the prepared substrate 10 on the semiconductor layer 12 side by using lithography, deposition, and lift-off techniques. As a result, the lower layer 31a of the source electrode 31, the lower layer 32a of the source electrode 32, and the lower layer 40a of the drain electrode 40 are formed. The lower layer 32a is formed so that the width in the direction D2 is narrower than the width in the direction D2 of the lower layer 31a. The lower layer 32a is formed so that the width in the direction D2 is the same or equivalent to the width in the direction D2 of the lower layer 40a. For example, the lower layer 31a, the lower layer 32a, and the lower layer 40a are formed at the same time.

[0068] Before forming the lower layer portion 31a, the lower layer portion 32a, and the lower layer portion 40a, a contact layer (regrowth layer) may be formed in a recess provided in the semiconductor layer 12. After forming the lower layer portion 31a, the lower layer portion 32a, and the lower layer portion 40a, a heat treatment may be performed to establish an ohmic connection. After forming the lower layer portion 31a, the lower layer portion 32a, and the lower layer portion 40a, a passivation film such as silicon nitride (SiN) may be formed on the substrate 10 on which the lower layer portion 31a, the lower layer portion 32a, and the lower layer portion 40a have been formed, using a chemical vapor deposition (CVD) method or the like.

[0069] After the lower layer 31a, the lower layer 32a, and the lower layer 40a are formed, a metal material having a laminated structure of Ni and Au or the like is formed between the lower layer 31a and the lower layer 40a, and between the lower layer 32a and the lower layer 40a, using lithography, deposition, and lift-off techniques. This forms the gate electrode 20. If a passivation film is formed on the substrate 10 after the lower layer 31a, the lower layer 32a, and the lower layer 40a are formed, an opening is formed in the passivation film, and the gate electrode 20 is formed in the opening.

[0070] After the gate electrode 20 is formed, an insulating film 50a covering the gate electrode 20, the lower portion 31a, the lower portion 32a, and the lower portion 40a is formed on the substrate 10 by using a CVD method or the like, as shown in Fig. 9(B). Then, openings 51 leading to the lower portion 31a, the lower portion 32a, and the lower portion 40a are formed in the insulating film 50a by using lithography and etching techniques, as shown in Fig. 9(B).

[0071] Next, as shown in FIG. 9(C), an upper layer portion 31b of the source electrode 31, an upper layer portion 32b of the source electrode 32, and an upper layer portion 40b of the drain electrode 40 are formed using lithography and plating techniques. The upper layer portion 31b is formed on the lower layer portion 31a, the upper layer portion 32b is formed on the lower layer portion 32a, and the upper layer portion 40b is formed on the lower layer portion 40a. A metal material such as Au is used for the upper layer portion 31b, the upper layer portion 32b, and the upper layer portion 40b. A metal material different from that of the lower layer portion 31a, the lower layer portion 32a, and the lower layer portion 40a may be used for the upper layer portion 31b, the upper layer portion 32b, and the upper layer portion 40b, respectively. The upper layer portion 32b is formed so that the width in the direction D2 is narrower than the width in the direction D2 of the upper layer portion 31b. The upper layer 32b is formed so that the width in the direction D2 is the same as or equivalent to the width in the direction D2 of the upper layer 40b. For example, the upper layer 31b, the upper layer 32b, and the upper layer 40b are formed at the same time.

[0072] A laminate of a lower layer portion 31a and an upper layer portion 31b formed in the active region 10a functions as a source electrode 31. A laminate of a lower layer portion 32a and an upper layer portion 32b formed in the active region 10a functions as a source electrode 32. A laminate of a lower layer portion 40a and an upper layer portion 40b formed in the active region 10a functions as a drain electrode 40. The gate electrode 20, as well as the source electrode 31, the source electrode 32, and the drain electrode 40 are formed by the steps of Fig. 9(A) to Fig. 9(C).

[0073] After the gate electrode 20, the source electrode 31, the source electrode 32, and the drain electrode 40 are formed, for example, as shown in Fig. 10(A), an insulating film 50b is formed by using a CVD method or the like to cover the gate electrode 20, the source electrode 31, the source electrode 32, and the drain electrode 40. The insulating film 50b and the previously formed insulating film 50a form the insulating film 50.

[0074] 10(B), a through hole 33a is formed in the substrate 10 in the active region 10a so as to reach the surface 10d (back surface) on the side of the underlying substrate 11 to the surface 10c (front surface) on the side of the semiconductor layer 12. The through hole 33a is formed at a position overlapping with the source electrode 31 provided in the active region 10a, i.e., at a position directly below the source electrode 31, so as to communicate with the source electrode 31 (its lower layer 31a). The through hole 33a is formed by etching from the surface 10d side of the substrate 10. The lower layer 31a of the source electrode 31 can function as an etching stopper when the through hole 33a is formed by etching from the surface 10d side of the substrate 10.

[0075] After the through hole 33a is formed, a metal material such as Au or Cu is formed in the through hole 33a and on the surface 10d of the substrate 10, as shown in Fig. 10(C). The metal material formed in the through hole 33a forms a via 33. The metal material formed on the surface 10d of the substrate 10 forms a metal layer 34. This provides a structure in which the via 33 connected to the metal layer 34 is provided directly below the source electrode 31 so as to overlap the source electrode 31.

[0076] 9(A) to 9(C) and 10(A) to 10(C), a transistor element is formed in the active region 10a, in which the gate electrode 20 is provided between the source electrode 31, directly below which the via 33 connected to the metal layer 34 is provided, and the drain electrode 40. Furthermore, a transistor element is formed in the active region 10a, in which the gate electrode 20 is provided between the source electrode 32, directly below which the via 33 is not provided, and the drain electrode 40.

[0077] Next, the manufacturing of the element isolation region 10b of the semiconductor device 1A will be described with reference to Figures 11(A) to 11(C), 12(A) to 12(C), 13(A) and 13(B), as well as Figures 9(A) to 9(C) and 10(A) to 10(C). Figures 11(A) to 11(C), 12(A) to 12(C), 13(A) and 13(B) each show a schematic cross section along a direction D2 passing through a position where the source wiring 35 and the drain wiring 41 of the element isolation region 10b intersect.

[0078] In the element isolation region 10b, a metal material is formed on the surface 10c of the prepared substrate 10 on the semiconductor layer 12 side by using lithography, deposition, and lift-off techniques. As a result, the lower portion 35a of the source wiring 35 and the lower portion 41a of the drain wiring 41 are formed. For example, the lower portion 35a and the lower portion 41a are formed simultaneously.

[0079] For example, the lower layer 35a of the source wiring 35 in the element isolation region 10b is formed simultaneously with the lower layer 32a (FIG. 9(A)) of the source electrode 32 in the active region 10a. In this case, the lower layer 35a is formed of the same material as the lower layer 32a, for example, a metal material having a laminated structure of Ta and Al. For example, the lower layer 35a is formed as a pattern continuous with the lower layer 32a. The lower layer 35a and the lower layer 32a can also be formed as patterns separated from each other. The lower layer 35a is formed so that the width in the direction D2 is wider than the width in the direction D2 of the lower layer 32a. For example, the lower layer 35a is formed so that the width in the direction D2 is the same as or equivalent to the width in the direction D2 of the lower layer 31a (FIG. 9(A)) of the source electrode 31 connected to the via 33 in the active region 10a.

[0080] For example, the lower layer portion 41a of the drain wiring 41 in the element isolation region 10b is formed simultaneously with the lower layer portion 40a of the drain electrode 40 in the active region 10a (FIG. 9(A)). In this case, the lower layer portion 41a is formed of the same material as the lower layer portion 40a, for example, a metal material having a laminated structure of Ta and Al. For example, the lower layer portion 41a is formed as a pattern continuous with the lower layer portion 40a. Note that the lower layer portion 41a and the lower layer portion 40a can also be formed as patterns separated from each other.

[0081] After the lower layer portion 35a and the lower layer portion 41a are formed, a passivation film such as SiN may be formed by using a CVD method or the like on the substrate 10 on which they are formed. After the formation of the lower portion 35a and the lower portion 41a of the element isolation region 10b and after the formation of the gate electrode 20 (FIG. 9(A)) of the active region 10a, an insulating film 50a having an opening portion 52 communicating with the lower portion 35a and the lower portion 41a is formed on the substrate 10 as shown in FIG. 11(B). The insulating film 50a is formed on the substrate 10 of the element isolation region 10b at the same time as on the substrate 10 of the active region 10a, using a CVD method or the like. The opening portion 52 is formed so as to communicate with each of the lower portion 35a and the lower portion 41a, using lithography and etching techniques.

[0082] 11(C), an upper layer portion 35b of the source wiring 35 and an upper layer portion 41b of the drain wiring 41 are formed using lithography and plating techniques. A metal material such as Au is used for the upper layer portion 35b and the upper layer portion 41b. A metal material different from that of the lower layer portion 35a and the lower layer portion 41a may be used for the upper layer portion 35b and the upper layer portion 41b, respectively. For example, the upper layer portion 35b and the upper layer portion 41b are formed at the same time.

[0083] The upper layer portion 35b of the source wiring 35 in the element isolation region 10b is formed simultaneously with the upper layer portion 32b (FIG. 9(C)) of the source electrode 32 in the active region 10a. The upper layer portion 35b is formed as a pattern continuous with the upper layer portion 32b. When the lower layer portion 35a and the lower layer portion 32a (FIG. 9(C)) are formed as patterns separated from each other, they are connected by the continuous upper layer portion 35b and upper layer portion 32b. The upper layer portion 35b is formed so that the width in the direction D2 is wider than the width in the direction D2 of the upper layer portion 32b. For example, the upper layer portion 35b is formed so that the width in the direction D2 is the same as or equivalent to the width of the upper layer portion 31b (FIG. 9(C)) of the source electrode 31 connected to the via 33 in the active region 10a.

[0084] The upper layer portion 41b of the drain wiring 41 in the element isolation region 10b is formed simultaneously with the upper layer portion 40b (FIG. 9(C)) of the drain electrode 40 in the active region 10a. The upper layer portion 41b is formed as a pattern continuous with the upper layer portion 40b. When the lower layer portion 41a and the lower layer portion 40a (FIG. 9(C)) are formed as patterns separated from each other, they are connected by the continuous upper layer portion 41b and the upper layer portion 40b.

[0085] A laminate of a lower layer portion 35a and an upper layer portion 35b formed in the element isolation region 10b functions as a source wiring 35. A laminate of a lower layer portion 41a and an upper layer portion 41b formed in the element isolation region 10b functions as a drain wiring 41. The source wiring 35 and the drain wiring 41 are formed by the steps shown in Fig. 11(A) to Fig. 11(C). The source wiring 35 and the drain wiring 41 are formed together with the source electrode 31, the source electrode 32, and the drain electrode 40 obtained by the steps shown in Fig. 9(A) to Fig. 9(C).

[0086] After the source wiring 35 and the drain wiring 41 (as well as the source electrode 31, the source electrode 32, and the drain electrode 40) are formed, an insulating film 50b is formed to cover them, as shown in FIG. 12(A), for example. The insulating film 50b is formed on the substrate 10 in the element isolation region 10b at the same time as on the substrate 10 in the active region 10a, using a CVD method or the like. The insulating film 50b and the previously formed insulating film 50a form the insulating film 50.

[0087] Next, as shown in FIG. 12(B), a through hole 33a is formed in the substrate 10 in the element isolation region 10b so as to reach the surface 10d (back surface) on the underlying substrate 11 side and the surface 10c (front surface) on the semiconductor layer 12 side. The through hole 33a is formed at a position overlapping with the source wiring 35 provided in the element isolation region 10b, i.e., at a position directly below the source wiring 35, so as to communicate with the source wiring 35 (its lower layer portion 35a). The through hole 33a is formed by etching from the surface 10d side of the substrate 10. The lower layer portion 35a of the source wiring 35 can function as an etching stopper when the through hole 33a is formed by etching from the surface 10d side of the substrate 10. For example, the through hole 33a communicating with the source wiring 35 in the element isolation region 10b is formed simultaneously with the through hole 33a communicating with the source electrode 31 in the active region 10a (FIG. 10(B)).

[0088] After the through holes 33a are formed, a metal material such as Au or Cu is formed in the through holes 33a and on the surface 10d of the substrate 10, as shown in FIG. 12(C). The vias 33 are formed from the metal material formed in the through holes 33a. The metal material formed on the surface 10d of the substrate 10 forms a metal layer 34. This results in a structure in which the vias 33 connected to the metal layer 34 are provided directly below the source wiring 35 in an overlapping manner. For example, the vias 33 and metal layer 34 in the element isolation region 10b are formed simultaneously with the vias 33 and metal layer 34 in the active region 10a (FIG. 10(C)).

[0089] An air bridge wiring 41c is formed on the drain wiring 41. When forming the air bridge wiring 41c, as shown in FIG. 13(A), an opening 53 is formed in the insulating film 50 (the insulating film 50b) that leads to the portions of the drain wiring 41 on both sides sandwiching the source wiring 35. Then, as shown in FIG. 13(B), the air bridge wiring 41c is formed so as to connect the portions of the drain wiring 41 on both sides sandwiching the source wiring 35 exposed from the opening 53. For example, a sacrificial layer is formed using a resist or the like in a region sandwiched between the portions of the drain wiring 41 exposed from the opening 53. Next, a metal material such as Au is formed on the portion of the drain wiring 41 exposed from the opening 53 and the sacrificial layer. After that, the sacrificial layer is removed. As a result, the air bridge wiring 41c is formed as shown in FIG. 13(B), which connects the portions of the drain wiring 41 on both sides sandwiching the source wiring 35 and overlaps with the source wiring 35 via the insulating film 50 and the cavity 60.

[0090] By processes such as those shown in Figures 11(A) to 11(C), Figures 12(A) to 12(C), Figures 13(A) and 13(B), a source wiring 35 is formed directly below a via 33 connected to a metal layer 34, and a drain wiring 41 is formed spanning the source wiring 35 with an air bridge wiring 41c.

[0091] For example, the semiconductor device 1A is manufactured by the above-mentioned steps. The above-described method for manufacturing the semiconductor device 1A is merely an example, and the present invention is not limited to this.

[0092] For example, the vias 33 in the active region 10a and the element isolation region 10b are not limited to a form in which a metal material is filled into the through hole 33a, but may be a so-called conformal via in which a metal material is formed on the inner surface of the through hole 33a and a cavity is formed in the center of the through hole 33a.

[0093] Furthermore, the via 33 may be formed in the substrate 10 before and not only after the formation of the source electrode 31 and the source wiring 35. For example, the via 33 is formed in advance at a predetermined position of the prepared substrate 10, and the source electrode 31 and the source wiring 35 are formed on the substrate 10 on which the via 33 has been formed, according to the examples of Figures 9(A) to 9(C) and Figures 11(A) to 11(C). Using such a method, the source electrode 31 and the source wiring 35 directly below the via 33 may be formed.

[0094] The vias 33 may be formed not only before the air bridge wiring 41c is formed, but also after the air bridge wiring 41c is formed. That is, after the process of Fig. 12(A), the air bridge wiring 41c may be formed according to the process examples of Fig. 13(A) and Fig. 13(B), and then the vias 33 may be formed according to the process examples of Fig. 12(B) and Fig. 12(C).

[0095] Furthermore, the insulating film 50 is not limited to a two-layer structure of insulating films 50a and 50b, and may be a single-layer structure of only the lower insulating film 50a, omitting the upper insulating film 50b. By omitting the upper insulating film 50b, it is possible to omit the formation of the opening 53 when forming the air bridge wiring 41c. When the upper insulating film 50b is omitted, the air bridge wiring 41c overlaps with the source wiring 35 via the cavity 60.

[0096] [Second embodiment] Fig. 14 is a diagram illustrating an example of a semiconductor device according to the second embodiment. Fig. 14(A) and Fig. 14(B) each show a schematic cross-sectional view of a main part of an example of a semiconductor device.

[0097] Fig. 14(A) is a schematic cross-sectional view taken along a direction D1 passing through a position where the source wiring 35 and the drain wiring 41 of the element isolation region 10b intersect. Fig. 14(B) is a schematic cross-sectional view taken along a direction D2 passing through a position where the source wiring 35 and the drain wiring 41 of the element isolation region 10b intersect. Fig. 14(A) corresponds to a cross-sectional view taken along a direction D1 passing through a position of the line XIVa-XIVa in Fig. 14(B), and Fig. 14(B) corresponds to a cross-sectional view taken along a direction D2 passing through a position of the line XIVb-XIVb in Fig. 14(A).

[0098] 14(A) and 14(B), the semiconductor device 1B according to the second embodiment has a configuration in which the drain wiring 41, which does not include the air bridge wiring 41c, crosses the source wiring 35. The semiconductor device 1B differs from the semiconductor device 1A described in the first embodiment in that it has such a configuration. The other configurations of the semiconductor device 1B can be similar to those of the semiconductor device 1A.

[0099] In the semiconductor device 1B, as shown in FIG. 14(A), a lower layer portion 32a of the source electrode 32 extending from the active region 10a to the element isolation region 10b is provided, and a lower layer portion 35a of the source wiring 35 continuous with the lower layer portion 32a is provided in the element isolation region 10b. Furthermore, as shown in FIG. 14(B), a lower layer portion 41a of the drain wiring 41 is provided in the element isolation region 10b. Then, as shown in FIG. 14(A) and FIG. 14(B), an insulating film 50a having an opening 51 communicating with the lower layer portion 32a of the source electrode 32 and an opening 52 communicating with the lower layer portion 41a of the drain wiring 41 is provided so as to cover them. The lower layer portion 35a of the source wiring 35 is covered with the insulating film 50a.

[0100] In the semiconductor device 1B, as shown in Fig. 14(A), an upper layer portion 32b of the source electrode 32 is provided in an opening 51 of the insulating film 50a, and as shown in Fig. 14(B), an upper layer portion 41b of the drain wiring 41 is provided in an opening 52 of the insulating film 50a. As shown in Figs. 14(A) and 14(B), the upper layer portion 41b of the drain wiring 41 is provided not only on the lower layer portion 41a but also on the insulating film 50a covering the lower layer portion 35a of the source wiring 35.

[0101] In the semiconductor device 1B, the lower layer portion 32a and the upper layer portion 32b function as the source electrode 32, the lower layer portion 35a functions as the source wiring 35, and the lower layer portion 41a and the upper layer portion 41b function as the drain wiring 41. As shown in Figures 14(A) and 14(B), the source electrode 32, the source wiring 35, and the drain wiring 41 are covered with an insulating film 50b. The insulating film 50b and the insulating film 50a form an insulating film 50.

[0102] In the semiconductor device 1B, a via 33 penetrating the substrate 10 is provided directly below a lower layer 35a of the source wiring 35. The via 33 is connected to a metal layer 34 provided on the surface 10d of the substrate 10. The source electrode 32 is connected to GND through a lower layer 35a of the source wiring 35 continuous with the lower layer 32a thereof, and the via 33 and metal layer 34 connected thereto.

[0103] The semiconductor device 1B can have the same configuration as the semiconductor device 1A described in the first embodiment, except for the cross structure of the source wiring 35 and the drain wiring 41 in the element isolation region 10b as shown in Figures 14(A) and 14(B). The semiconductor device 1B can be manufactured in the same procedure as the manufacturing method (Figures 9 to 12) described in the first embodiment, except for the formation of the cross structure of the source wiring 35 and the drain wiring 41 in the element isolation region 10b as shown in Figures 14(A) and 14(B). The semiconductor device 1B can also obtain the same effects as the semiconductor device 1A.

[0104] That is, in the semiconductor device 1B, the source electrode 31 with the via 33 provided directly below and the source electrode 32 with a narrower width and no via 33 provided directly below are also arranged in the active region 10a. This reduces the area occupied by the source electrodes 31 and 32 in the active region 10a of a given size, and increases the number of gate electrodes 20 arranged in the active region 10a, thereby enabling the semiconductor device 1B to have a high output. Furthermore, the source electrode 31 in the active region 10a is connected to the GND by the via 33 provided directly below it. The narrower source electrode 32 in the active region 10a has a source wiring 35 connected to it provided in the element isolation region 10b on the drain wiring 41 side, and the source wiring 35 is connected to the GND by the via 33 provided directly below it. This makes it possible to suppress the increase in source inductance and gate-source capacitance Cgs associated with the GND connection, and improve the high-frequency characteristics of the semiconductor device 1B.

[0105] In the semiconductor device 1B, the lower layer portion 35a of the source wiring 35 and the upper layer portion 41b of the drain wiring 41 are further laminated with an insulating film 50a interposed therebetween. That is, in the semiconductor device 1B, the source wiring 35 overlaps with the drain wiring 41 with the insulating film 50a interposed therebetween. In the semiconductor device 1B, an intersecting structure of the source wiring 35 and the drain wiring 41 is realized without using the air bridge wiring 41c as in the semiconductor device 1A. In the semiconductor device 1B, the formation of the air bridge wiring 41c can be omitted, so that the number of manufacturing steps can be reduced.

[0106] [Third embodiment] Fig. 15 is a diagram illustrating an example of a semiconductor device according to the third embodiment. Fig. 15 is a schematic plan view of a main part of the example of the semiconductor device.

[0107] The semiconductor device 1C shown in FIG. 15 has a configuration in which a layout is adopted in which the source wiring 35 and the drain wiring 41 do not intersect. The non-intersecting source wiring 35 (the lower layer portion 35a and the upper layer portion 35b) and the drain wiring 41 (the lower layer portion 41a and the upper layer portion 41b) are provided in the same layer. The source wiring 35 is disposed between the active region 10a and the drain wiring 41 in the direction D1 in a plan view. The semiconductor device 1C differs from the semiconductor device 1A described in the first embodiment in that it has such a configuration. The other configurations of the semiconductor device 1C can be the same as those of the semiconductor device 1A. The semiconductor device 1C can be manufactured in the same procedure as the manufacturing method described in the first embodiment (FIGS. 9 to 12) except that the non-intersecting source wiring 35 and the drain wiring 41 are provided in the same layer as shown in FIG. 15. The semiconductor device 1C can also obtain the same effects as the semiconductor device 1A.

[0108] That is, in the semiconductor device 1C, the source electrode 31 with the via 33 provided directly below and the source electrode 32 with a narrower width and no via 33 provided directly below are also arranged in the active region 10a. This reduces the area occupied by the source electrodes 31 and 32 in the active region 10a of a given size, and increases the number of gate electrodes 20 arranged in the active region 10a, thereby enabling the semiconductor device 1C to have a high output. Furthermore, the source electrode 31 in the active region 10a is connected to the GND by the via 33 provided directly below it. The narrower source electrode 32 in the active region 10a has a source wiring 35 connected to it provided in the element isolation region 10b on the drain wiring 41 side, and the source wiring 35 is connected to the GND by the via 33 provided directly below it. This makes it possible to suppress the increase in source inductance and gate-source capacitance Cgs associated with the GND connection, and improve the high-frequency characteristics of the semiconductor device 1C.

[0109] In the semiconductor device 1C, the source wiring 35 and the drain wiring 41 do not cross each other, but can be provided in the same layer. The semiconductor device 1C does not use the air bridge wiring 41c as in the semiconductor device 1A, and the formation of the air bridge wiring 41c can be omitted, so that the number of manufacturing steps can be reduced. Also, in the semiconductor device 1C, the source wiring 35 and the drain wiring 41 are not stacked, but can be spaced apart by a certain distance. This can suppress an increase in the drain-source capacitance Cds and improve the high-frequency characteristics of the semiconductor device 1C.

[0110] The first to third embodiments have been described above. The semiconductor devices 1A, 1B, 1C, etc. described above can be applied to various electronic devices. As an example, the following describes the case where the semiconductor device having the above configuration is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier.

[0111] [Fourth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a semiconductor package will be described as the fourth embodiment.

[0112] Fig. 16 is a diagram illustrating an example of a semiconductor package according to the fourth embodiment. Fig. 16 is a schematic plan view of a main part of the example of the semiconductor package. The semiconductor package 200 shown in Fig. 16 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 1A (Fig. 4, etc.) as described in the first embodiment, a lead frame 210 on which the semiconductor device 1A is mounted, and a resin 220 that seals them.

[0113] The semiconductor device 1A is mounted on a die pad 210a of a lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 20c connected to the gate electrode 20, a pad 30c connected to the source electrode 30, and a pad 40c connected to the drain electrode 40. The pads 20c, 30c, and 40c are connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 using wires 230 made of Au, Al, or the like, respectively. The lead frame 210, the semiconductor device 1A mounted thereon, and the wires 230 connecting them are sealed with a resin 220 so that parts of the gate lead 211, the source lead 212, and the drain lead 213 are exposed.

[0114] An external connection electrode connected to the source electrode 30, such as the metal layer 34, may be provided on the surface of the semiconductor device 1A opposite to the surface on which the pad 20c connected to the gate electrode 20 and the pad 40c connected to the drain electrode 40 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 by using a conductive bonding material such as solder.

[0115] For example, the semiconductor device 1A described in the first embodiment is used, and a semiconductor package 200 having such a configuration is obtained. As described above, in the semiconductor device 1A, the source electrode 31 with the via 33 provided directly below and the source electrode 32 with a narrower width and no via 33 provided directly below are provided in the active region 10a. This reduces the area occupied by the source electrodes 31 and 32 in the active region 10a of a given size, and increases the number of gate electrodes 20 arranged in the active region 10a, making it possible to increase the output of the semiconductor device 1A. Furthermore, the source electrode 31 in the active region 10a is connected to the GND by the via 33 provided directly below it. The narrower source electrode 32 in the active region 10a has a source wiring 35 connected to it provided in the element isolation region 10b on the drain wiring 41 side, and the via 33 is provided directly below the source wiring 35 and connected to the GND. This makes it possible to suppress the increase in source inductance and gate-source capacitance Cgs associated with the GND connection, and improve the high-frequency characteristics of the semiconductor device 1A. Therefore, a high-output semiconductor device 1A with excellent high-frequency characteristics is realized. By using such a semiconductor device 1A, a high-performance semiconductor package 200 is realized.

[0116] Although the semiconductor device 1A is taken as an example here, it is possible to obtain a semiconductor package in a similar manner using other semiconductor devices 1B, 1C, etc. [Fifth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a power factor correction circuit will be described as the fifth embodiment.

[0117] Fig. 17 is a diagram for explaining an example of a power factor correction circuit according to the fifth embodiment. Fig. 17 shows an equivalent circuit diagram of the example of the power factor correction circuit. A power factor correction (PFC) circuit 300 shown in FIG. 17 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0118] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to a cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out from between both terminals of the capacitor 350.

[0119] For example, the semiconductor devices 1A, 1B, 1C, etc. are used for the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in the semiconductor devices 1A, 1B, 1C, etc., the source electrode 31 with the via 33 provided directly below and the source electrode 32 with a narrower width and no via 33 provided directly below are provided in the active region 10a. This reduces the area occupied by the source electrodes 31 and 32 in the active region 10a of a given size, increases the number of gate electrodes 20 arranged in the active region 10a, and enables the semiconductor devices 1A, 1B, 1C, etc. to have high output. Furthermore, the source electrode 31 in the active region 10a is connected to the GND by the via 33 provided directly below it. The narrower source electrode 32 in the active region 10a has a source wiring 35 connected to it provided in the element isolation region 10b on the drain wiring 41 side, and the source wiring 35 is connected to the GND by the via 33 provided directly below it. This suppresses the increase in source inductance and gate-source capacitance Cgs associated with the GND connection, and enables the high-frequency characteristics of the semiconductor devices 1A, 1B, 1C, etc. to be improved. Therefore, it is possible to realize the high-output semiconductor devices 1A, 1B, 1C, etc. having excellent high-frequency characteristics. A high-performance PFC circuit 300 is realized by using such semiconductor devices 1A, 1B, 1C, etc.

[0120] [Sixth embodiment] Here, an example in which the semiconductor device having the above-mentioned configuration is applied to a power supply device will be described as the sixth embodiment.

[0121] Fig. 18 is a diagram illustrating an example of a power supply device according to the sixth embodiment. Fig. 18 shows an equivalent circuit diagram of the example of the power supply device. The power supply device 400 shown in FIG. 18 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0122] The primary side circuit 410 includes the PFC circuit 300 as described in the fifth embodiment above, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of switch elements, for example, four switch elements 441, 442, 443, and 444.

[0123] The secondary side circuit 420 includes a plurality of switch elements, three of which, as an example here, are a switch element 421, a switch element 422, and a switch element 423. For example, the semiconductor devices 1A, 1B, 1C, etc. are used for the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 of the power supply device 400 having such a configuration, and for the switch elements 441-444 of the full bridge inverter circuit 440. For example, normal MIS type field effect transistors using Si are used for the switch elements 421, 422, 423 of the secondary side circuit 420 of the power supply device 400.

[0124] As described above, in the semiconductor devices 1A, 1B, 1C, etc., the source electrode 31 with the via 33 provided directly below and the source electrode 32 with a narrower width and no via 33 provided directly below are provided in the active region 10a. This reduces the area occupied by the source electrodes 31 and 32 in the active region 10a of a given size, increases the number of gate electrodes 20 arranged in the active region 10a, and enables the semiconductor devices 1A, 1B, 1C, etc. to have high output. Furthermore, the source electrode 31 in the active region 10a is connected to the GND by the via 33 provided directly below it. The narrower source electrode 32 in the active region 10a has a source wiring 35 connected to it provided in the element isolation region 10b on the drain wiring 41 side, and the source wiring 35 is connected to the GND by the via 33 provided directly below it. This suppresses the increase in source inductance and gate-source capacitance Cgs associated with the GND connection, and enables the high-frequency characteristics of the semiconductor devices 1A, 1B, 1C, etc. to be improved. Therefore, it is possible to realize high-output semiconductor devices 1A, 1B, 1C, etc. having excellent high-frequency characteristics. A high-performance power supply device 400 is realized by using such semiconductor devices 1A, 1B, 1C, etc.

[0125] [Seventh embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to an amplifier will be described as the seventh embodiment.

[0126] Fig. 19 is a diagram for explaining an example of an amplifier according to the seventh embodiment, showing an equivalent circuit diagram of the example of the amplifier. The amplifier 500 shown in FIG. 19 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0127] The digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the input signal SI, for which the nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0128] The above-mentioned semiconductor devices 1A, 1B, 1C, etc. are used in the power amplifier 540 of the amplifier 500 having such a configuration. As described above, in the semiconductor devices 1A, 1B, 1C, etc., the source electrode 31 with the via 33 provided directly below and the source electrode 32 with a narrower width and no via 33 provided directly below are provided in the active region 10a. This reduces the area occupied by the source electrodes 31 and 32 in the active region 10a of a given size, increases the number of gate electrodes 20 arranged in the active region 10a, and enables the semiconductor devices 1A, 1B, 1C, etc. to have high output. Furthermore, the source electrode 31 in the active region 10a is connected to the GND by the via 33 provided directly below it. The narrower source electrode 32 in the active region 10a has a source wiring 35 connected to it provided in the element isolation region 10b on the drain wiring 41 side, and the source wiring 35 is connected to the GND by the via 33 provided directly below it. This suppresses the increase in source inductance and gate-source capacitance Cgs associated with the GND connection, and enables the high-frequency characteristics of the semiconductor devices 1A, 1B, 1C, etc. to be improved. Therefore, it is possible to realize high-output semiconductor devices 1A, 1B, 1C, etc. having excellent high-frequency characteristics. A high-performance amplifier 500 is realized by using such semiconductor devices 1A, 1B, 1C, etc.

[0129] Various electronic devices to which the semiconductor devices 1A, 1B, 1C and the like are applied (such as the semiconductor package 200, the PFC circuit 300, the power supply device 400, and the amplifier 500 described in the fourth to seventh embodiments) can be mounted in various electronic devices or electronic devices. For example, they can be mounted in various electronic devices or electronic devices such as computers (personal computers, supercomputers, servers, and the like), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing devices, transmitters, receivers, and radar devices.

[0130] The following supplementary notes are further provided with respect to the above-described embodiment. (Note 1) A substrate having a first region and a second region surrounding the first region in a plan view; A plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes are provided in the first region, extend in a first direction in a plan view, and are arranged in parallel in a second direction perpendicular to the first direction; a first via provided in the first region and penetrating the substrate; a second via provided in the second region and penetrating the substrate; Including, The plurality of source electrodes include a first source electrode overlapping the first via in a plan view and connected to the first via; a second source electrode connected to the second via; 13. A semiconductor device comprising:

[0131] (Appendix 2) The semiconductor device described in Appendix 1, wherein the multiple gate electrodes, the multiple source electrodes, and the multiple drain electrodes are arranged such that the source electrodes and drain electrodes are alternately arranged in the second direction and a gate electrode is arranged between adjacent source electrodes and drain electrodes.

[0132] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1, wherein the second source electrode has a width in the second direction that is smaller than a width in the second direction of the second via. (Supplementary Note 4) The semiconductor device according to Supplementary Note 1, wherein the second source electrode has a width in the second direction smaller than a width in the second direction of the first source electrode.

[0133] (Additional Note 5) The semiconductor device described in Additional Note 1, wherein the distance in the second direction between a pair of gate electrodes opposing each other across the second source electrode is smaller than the distance in the second direction between a pair of gate electrodes opposing each other across the first source electrode.

[0134] (Note 6) A gate wiring provided in the second region on a first side in the first direction, extending in the second direction, and connected to the plurality of gate electrodes; a source wiring provided in the second region on a second side opposite to the first side in the first direction, overlapping with the second via in a plan view, connected to the second via, and connecting the second via and the second source electrode; a drain wiring provided in the second region on the second side in the first direction, extending in the second direction, and connected to the plurality of drain electrodes; 2. The semiconductor device of claim 1, further comprising:

[0135] (Supplementary Note 7) The semiconductor device according to Supplementary Note 6, wherein the source wiring is provided on an extension line extending to the second side in the first direction of the second source electrode. (Supplementary Note 8) The semiconductor device according to Supplementary Note 6, wherein a width of the second source electrode in the second direction is smaller than a width of the source wiring in the second direction.

[0136] (Supplementary Note 9) The semiconductor device according to Supplementary Note 6, wherein the source wiring overlaps with the drain wiring in a plan view via an insulating film or a cavity covering the source wiring. (Supplementary Note 10) The semiconductor device according to Supplementary Note 6, wherein the source wiring is provided between the first region and the drain wiring in the first direction in a plan view.

[0137] (Additional Note 11) A step of preparing a substrate having a first region and a second region surrounding the first region in a plan view; forming a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes in the first region, the gate electrodes, the plurality of source electrodes, and the drain electrodes extending in a first direction in a plan view and arranged in parallel in a second direction perpendicular to the first direction; forming a first via penetrating the substrate in the first region; forming a second via in the second region through the substrate; Including, The step of forming the plurality of source electrodes includes: forming a first source electrode overlapping the first via in a plan view and connected to the first via; forming a second source electrode connected to the second via; A method for manufacturing a semiconductor device comprising the steps of:

[0138] (Additional Note 12) A substrate having a first region and a second region surrounding the first region in a plan view; A plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes are provided in the first region, extend in a first direction in a plan view, and are arranged in parallel in a second direction perpendicular to the first direction; a first via provided in the first region and penetrating the substrate; a second via provided in the second region and penetrating the substrate; Including, The plurality of source electrodes include a first source electrode overlapping the first via in a plan view and connected to the first via; a second source electrode connected to the second via; An electronic device comprising a semiconductor device including: [Explanation of symbols]

[0139] 1, 1A, 1B, 1C, 100A, 100B Semiconductor device 10, 110 Board 10a, 110a active area 10b, 110b element isolation area 10c, 10d, 110c, 110d plane 11 Underlying substrate 12 Semiconductor layer 12a Channel Layer 12b Barrier layer 12c Cap Layer 20, 120 Gate electrode 20c, 30c, 40c pads 21, 121 Gate wiring 30, 31, 32, 130, 131, 132 Source electrode 31a, 32a, 35a, 40a, 41a Lower part 31b, 32b, 35b, 40b, 41b Upper part 33, 133 Via 33a Through hole 34 Metal layer 35, 135 Source wiring 40, 140 Drain electrode 41, 141 Drain wiring 41c Air Bridge Wiring 50, 50a, 50b Insulating film 51, 52, 53 Openings 60 hollow 101 2DEG area 200 Semiconductor Packages 210 Lead Frame 210a Die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch elements 320 Diode 330 Choke Coil 340, 350 Capacitor 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 Trans 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520, 530 Mixer 540 Power Amplifier D1, D2 direction L1, L2, L3 distance W0 width (diameter) W1, W2, W3, W4 width

Claims

1. A substrate having a first region and a second region surrounding the first region in a plan view; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes provided in the first region, extending in a first direction in a plan view, and arranged in parallel in a second direction perpendicular to the first direction; a first via provided in the first region and penetrating the substrate; a second via provided in the second region and penetrating the substrate; Including, The plurality of source electrodes include a first source electrode overlapping the first via in a plan view and connected to the first via; a second source electrode connected to the second via; 13. A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the width of said second source electrode in said second direction is smaller than the width of said second via in said second direction.

3. The semiconductor device according to claim 1 , wherein the width of said second source electrode in said second direction is smaller than the width of said first source electrode in said second direction.

4. 2. The semiconductor device according to claim 1, wherein a distance in the second direction between a pair of gate electrodes opposing each other across the second source electrode is smaller than a distance in the second direction between a pair of gate electrodes opposing each other across the first source electrode.

5. a gate wiring provided in the second region on a first side in the first direction, extending in the second direction, and connected to the plurality of gate electrodes; a source wiring provided in the second region on a second side opposite to the first side in the first direction, overlapping with the second via in a plan view, connected to the second via, and connecting the second via and the second source electrode; a drain wiring provided in the second region on the second side in the first direction, extending in the second direction, and connected to the plurality of drain electrodes; The semiconductor device according to claim 1 , further comprising:

6. The semiconductor device according to claim 5 , wherein the source wiring is provided on an extension of the second source electrode that extends to the second side in the first direction.

7. The semiconductor device according to claim 5 , wherein the source wiring overlaps with the drain wiring in a plan view via an insulating film or a cavity covering the source wiring.

8. preparing a substrate having, in a plan view, a first region and a second region surrounding the first region; forming a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes in the first region, the gate electrodes, the plurality of source electrodes, and the drain electrodes extending in a first direction in a plan view and arranged in parallel in a second direction perpendicular to the first direction; forming a first via penetrating the substrate in the first region; forming a second via in the second region through the substrate; Including, The step of forming the plurality of source electrodes includes: forming a first source electrode overlapping the first via in a plan view and connected to the first via; forming a second source electrode connected to the second via; A method for manufacturing a semiconductor device comprising the steps of:

9. A substrate having a first region and a second region surrounding the first region in a plan view; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes provided in the first region, extending in a first direction in a plan view, and arranged in parallel in a second direction perpendicular to the first direction; a first via provided in the first region and penetrating the substrate; a second via provided in the second region and penetrating the substrate; Including, The plurality of source electrodes include a first source electrode overlapping the first via in a plan view and connected to the first via; a second source electrode connected to the second via; An electronic device comprising a semiconductor device including:

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