Semiconductor device

Abstract

To provide a semiconductor device which can secure positional accuracy of a plurality of terminals, in a case in which the plurality of terminals are adjacently arranged.SOLUTION: A semiconductor device includes: insulation circuit boards 1a and 1b having insulation plates 7a and 7b, and conductive plates 10a to 10c provided on an upper face sides of the insulation plates 7a and 7b; semiconductor chips 3a to 3l provided on the upper face sides of the conductive plates 10a to 10c; a first external terminal 2b electrically connected to the semiconductor chips 3a to 3l; a first insulation member 91 having a coating part 94 coating a part of the first external terminal 2b and first engagement parts 96a and 96b provided on the upper face side of the coating part 94; a second external terminal 2a which is provided on the upper face side of the first external terminal 2b through the coating part 94, and has second engagement parts 25a and 25b engaged with the first engagement parts 96a and 96b; and a sealing resin 10 for sealing the semiconductor chips 3a to 3l, and sealing parts of the respective first external terminal 2b, the first insulation member 91 and the second external terminal 2a.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device (power semiconductor module). [Background technology]

[0002] Patent Document 1 discloses a holding tape for fixing each clip in a semiconductor package. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0105707 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional power semiconductor modules, the close arrangement (laminate arrangement) of multiple terminals has been considered in order to reduce the wiring inductance. However, due to the assembly tolerance of the power semiconductor module, it is difficult to ensure the positional accuracy of the multiple terminals.

[0005] In view of the above problems, an object of the present disclosure is to provide a semiconductor device capable of ensuring the positional accuracy of a plurality of terminals when the plurality of terminals are arranged closely to each other. [Means for solving the problem]

[0006] One aspect of the present invention is a semiconductor device comprising: an insulating circuit board having an insulating plate and a conductive plate provided on an upper surface of the insulating plate; a semiconductor chip provided on the upper surface of the conductive plate; a first external terminal electrically connected to the semiconductor chip; a first insulating member having a covering portion covering a portion of the first external terminal and a first engaging portion provided on the upper surface of the covering portion; a second external terminal electrically connected to the semiconductor chip, provided on the upper surface of the first external terminal via the covering portion, and having a second engaging portion that engages with the first engaging portion; and a sealing resin that seals the semiconductor chip and seals portions of the first external terminal, the first insulating member, and the second external terminal.

[0007] In one aspect of the present invention, the first locking portion may be a protrusion, and the second locking portion may be a recess.

[0008] In one aspect of the present invention, the first locking portion and the second locking portion may be covered with a sealing resin.

[0009] In an aspect of the present invention, the first insulating member may have a frame portion surrounding a part of a side surface of the second external terminal.

[0010] In one embodiment of the present invention, the semiconductor device may further include a third external terminal electrically connected to the semiconductor chip and spaced apart from the first external terminal and the second external terminal, and a second insulating member covering a portion of the third external terminal.

[0011] In one aspect of the present invention, the insulating member may further include a third insulating member provided between the first insulating member and the second insulating member and integrally with the first insulating member and the second insulating member.

[0012] In one embodiment of the present invention, the semiconductor device may further include a control terminal electrically connected to the semiconductor chip, and the third insulating member may have an opening for positioning the control terminal.

[0013] In one aspect of the present invention, a slit may be provided on the upper surface side of the covering portion.

[0014] In an aspect of the present invention, the second insulating member may have a fixing portion for fixing the second external terminal.

[0015] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. Effect of the Invention

[0016] According to the present disclosure, it is possible to provide a semiconductor device capable of ensuring the positional accuracy of a plurality of terminals when the plurality of terminals are arranged closely to each other. [Brief description of the drawings]

[0017] [Figure 1] 1 is a perspective view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a perspective view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 5] 1 is a perspective view of a component of a semiconductor device according to a first embodiment; [Figure 6] FIG. 2 is a plan view of a component of the semiconductor device according to the first embodiment. [Figure 7] 1 is a perspective view of a component of a semiconductor device according to a first embodiment; [Figure 8] 1 is a perspective view of a component of a semiconductor device according to a first embodiment; [Figure 9] 1 is a perspective view of a component of a semiconductor device according to a first embodiment; [Figure 10] 1 is a perspective view of a component of a semiconductor device according to a first embodiment; [Figure 11] 1 is a side view of the semiconductor device according to the first embodiment. [Figure 12] 1 is a side view of the semiconductor device according to the first embodiment. [Figure 13] 1 is a side view of a mounting structure of a semiconductor device according to a first embodiment. [Figure 14] 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment. [Figure 15] FIG. 11 is a plan view of a semiconductor device according to a second embodiment. [Figure 16] FIG. 13 is a plan view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, the first to third embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0019] In addition, the definitions of directions such as "up", "down", "up and down", "left", "right", and "left and right" in the following description are merely definitions for the convenience of description and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right", and of course, if it is rotated 180 degrees and observed, "up and down" is read inverted. In addition, "upper surface" and "lower surface" may be read as "front surface" and "rear surface", respectively. In addition, the "first main surface" and "second main surface" of each member are main surfaces facing each other, and for example, if the "first main surface" is the upper surface, the "second main surface" is the lower surface. In addition, the "first main surface" and "second main surface" may be read as "one main surface" and "the other main surface", respectively.

[0020] (First embodiment) <Structure of Semiconductor Device> Fig. 1 is a perspective view of a semiconductor device (power semiconductor module) according to a first embodiment, and Fig. 2 is a plan view of the semiconductor device according to the first embodiment. As shown in Fig. 1 and Fig. 2, the semiconductor device according to the first embodiment includes an external terminal (negative terminal) 2a, an external terminal (positive terminal) 2b, an external terminal (output terminal) 2c, and external terminals (control terminals) 4a to 4g, and a sealing resin 10 that seals a semiconductor chip (not shown) and also seals parts of the negative terminal 2a, the positive terminal 2b, the output terminal 2c, and the control terminals 4a to 4g.

[0021] Fig. 1 shows the assembled state of the semiconductor device according to the first embodiment, in which the positive electrode terminal 2b and the output terminal 2c are integral with the tie bar wirings 2x, 2y, which are metal wirings. The tie bar wirings 2x, 2y have a U-shaped planar pattern and are provided so as to surround the side surfaces of the sealing resin 10. Fig. 2 shows the completed state of the semiconductor device according to the first embodiment, in which the tie bar wirings 2x, 2y are cut and the positive electrode terminal 2b and the output terminal 2c are separated from each other.

[0022] 1 and 2, the sealing resin 10 has a substantially rectangular parallelepiped shape. The sealing resin 10 is made of an insulating resin material such as an epoxy resin.

[0023] A portion of the positive electrode terminal 2b and the negative electrode terminal 2a protrudes from the common side surface of the sealing resin 10. The positive electrode terminal 2b and the negative electrode terminal 2a are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy.

[0024] The negative electrode terminal 2a is provided on the upper surface side of the positive electrode terminal 2b via an insulating member 91. The negative electrode terminal 2a and the positive electrode terminal 2b are arranged in close proximity (laminated arrangement). Here, "arranged in close proximity" means that the negative electrode terminal 2a and the positive electrode terminal 2b at least partially overlap each other via an insulating member such as the insulating member 91. The insulating member 91 has a covering portion 94 that covers a part of the positive electrode terminal 2b, and a frame portion 95 that is provided on the upper surface side of the covering portion 94 and surrounds the periphery of the negative electrode terminal 2a. A part of the insulating member 91 is covered with a sealing resin 10. The insulating member 91 is made of an insulating material such as resin, rubber, or ceramics.

[0025] A portion of the output terminal 2c protrudes from a side surface of the sealing resin 10 opposite to the side surface from which the negative electrode terminal 2a and the positive electrode terminal 2b protrude. The output terminal 2c is made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al) or an Al alloy. The output terminal 2c, the positive electrode terminal 2b and the tie bar wirings 2x and 2y may be made of the same material.

[0026] The output terminal 2c is partially covered with an insulating member 93. The insulating member 93 is partially covered with a sealing resin 10. The insulating member 93 is made of an insulating material such as resin, rubber, or ceramics.

[0027] A portion of the control terminals 4a to 4g protrudes from the upper surface of the sealing resin 10. The control terminals 4a to 4g are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. Although Figs. 1 and 2 show an example in which the control terminals 4a to 4g are made of press-fit pins, the shape of the control terminals 4a to 4g is not particularly limited. The lower portions of the control terminals 4a to 4d are fixed by an insulating member 41. The lower portions of the control terminals 4e to 4g are covered by an insulating member 42. The insulating members 41 and 42 are made of an insulating material such as resin, rubber, or ceramics.

[0028] 1 and 2, the direction parallel to the upper surface of the sealing resin 10 and in which the negative terminal 2a, the positive terminal 2b, and the output terminal 2c protrude from the sealing resin 10 is defined as the X-axis, and the rightward direction in the plan view of FIG. 2 is defined as the positive direction of the X-axis. In addition, in FIG. 1 and 2, the direction parallel to the upper surface of the sealing resin 10 and perpendicular to the X-axis is defined as the Y-axis, and the upward direction in the plan view of FIG. 2 is defined as the positive direction of the Y-axis. In addition, in FIG. 1 and 2, the direction perpendicular to the X-axis and Y-axis is defined as the Z-axis, and the front side in the plan view of FIG. 2 is defined as the positive direction of the Z-axis. The definitions of the directions in FIG. 3 and subsequent figures are the same as those in FIG. 1 and 2.

[0029] FIG. 3 is an oblique view of the semiconductor device according to the first embodiment shown in FIG. 1, with the sealing resin 10 omitted, and FIG. 4 is a plan view of the semiconductor device according to the first embodiment shown in FIG. 2, with the sealing resin 10 omitted.

[0030] As shown in Figures 3 and 4, the semiconductor device according to the first embodiment includes insulating circuit boards 1a, 1b and semiconductor chips 3a-3l provided on the upper surface sides of the insulating circuit boards 1a, 1b. An integrated structure (2a, 6, 8) is provided on the upper surface sides of the insulating circuit boards 1a, 1b and the semiconductor chips 3a-3l, in which a negative terminal 2a, a conductive member 6 (also called an "intermediate clip" or a "lead frame"), and an insulating member 8 are integrated. An integrated structure (2b, 2c, 91-93) is provided on the upper surface sides of the insulating circuit boards 1a, 1b, in such a way that it surrounds the periphery of the semiconductor chips 3a-3l and the integrated structure (2a, 6, 8) in a plan view, in which a positive terminal 2b, an output terminal 2c, and insulating members 91-93 are integrated.

[0031] FIG. 5 is a perspective view of insulating circuit boards 1a, 1b and semiconductor chips 3a-3l, which are components of the semiconductor device according to the first embodiment, and FIG. 6 is a plan view of insulating circuit boards 1a, 1b, semiconductor chips 3a-3l, and integrated structure (2b, 2c, 91-93), which are components of the semiconductor device according to the first embodiment.

[0032] As shown in Fig. 5 and Fig. 6, the insulating circuit boards 1a and 1b are provided at a distance from each other. The insulating circuit board 1a includes an insulating plate 7a, conductive plates 10a and 10b provided on the upper surface side of the insulating plate 7a, and a conductive plate 10d (see Fig. 11 and Fig. 12) provided on the lower surface side of the insulating plate 7a. The insulating circuit board 1b includes an insulating plate 7b, a conductive plate 10c provided on the upper surface side of the insulating plate 7b, and a conductive plate 10e (see Fig. 11 and Fig. 12) provided on the lower surface side of the insulating plate 7b. The insulating circuit boards 1a and 1b may be, for example, a direct copper bonded (DCB) board or an active metal bonding (AMD) board.

[0033] The insulating plates 7a and 7b are composed of, for example, a resin insulating layer using a polymer material or a ceramic plate mainly made of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), etc. The insulating plates 7a and 7b have a substantially rectangular planar pattern.

[0034] The conductive plates 10a to 10e are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. The conductive plate 10a has a substantially rectangular planar pattern, and a recess is provided in a portion of the planar pattern on the output terminal 2c side. The conductive plate 10b is located in the recess of the planar pattern of the conductive plate 10a, and has a substantially rectangular planar pattern. The conductive plate 10c has a substantially rectangular planar pattern. The conductive plates 10d and 10e (see FIGS. 11 and 12) have substantially rectangular planar patterns. The lower surfaces of the conductive plates 10d and 10e are exposed from the sealing resin 10 shown in FIGS. 1 and 2.

[0035] 5 and 6, a plurality (six) of power semiconductor elements (semiconductor chips) 3a to 3f are bonded to the upper surface side of the conductive plate 10a via a bonding material such as solder, a conductive adhesive, a sintered material, etc. The semiconductor chips 3a to 3f are electrically connected in parallel to the conductive plate 10a, and are arranged such that the semiconductor chips 3a to 3c form a first row and the semiconductor chips 3d to 3f form a second row.

[0036] Examples of solder that can be used as a joining material for joining the various components of the semiconductor device according to the first embodiment include lead-free solders such as tin-antimony (Sn-Sb)-based, tin-copper (Sn-Cu)-based, tin-copper-silver (Sn-Cu-Ag)-based, tin-silver (Sn-Ag)-based, tin-silver-copper (Sn-Ag-Cu)-based, tin-silver-bismuth-copper (Sn-Ag-Bi-Cu)-based, tin-indium-silver-bismuth (Sn-In-Ag-Bi)-based, tin-zinc (Sn-Zn)-based, tin-zinc-bismuth (Sn-Zn-Bi)-based, tin-bismuth (Sn-Bi)-based, and tin-indium (Sn-In)-based solders, and lead solders such as tin-lead (Sn-Pb)-based solders can be used. As the conductive adhesive of the bonding material used to bond each member of the semiconductor device according to the first embodiment, for example, an adhesive in which metal particles such as silver (Ag) are mixed with resin such as epoxy resin can be used. As the sintered material of the bonding material used to bond each member of the semiconductor device according to the first embodiment, for example, a sheet-like sintered sheet or a paste-like conductive paste containing metal particles with a fine particle size of about several nm to several μm such as gold (Au), silver (Ag) or copper (Cu) and an organic component (binder) can be used which is heated, pressurized and sintered.

[0037] A plurality (six) of power semiconductor elements (semiconductor chips) 3g to 3l are bonded to the upper surface side of the conductive plate 10c via a bonding material such as solder, a conductive adhesive, a sintered material, etc. The semiconductor chips 3g to 3l are electrically connected in parallel to the conductive plate 10c, and are arranged such that the semiconductor chips 3g to 3i form a first row and the semiconductor chips 3j to 3l form a second row.

[0038] In the semiconductor device according to the first embodiment, MOSFETs are exemplified as the semiconductor chips 3a to 3l, and a 2-in-1 type power semiconductor module is exemplified in which 6 MOSFETs are connected in parallel and 2 pairs in series. The semiconductor chips 3a to 3f form the lower arm of a half-bridge circuit for one phase of a three-phase inverter circuit, and the semiconductor chips 3g to 3l form the upper arm.

[0039] The semiconductor chips 3a to 3l each have a semiconductor substrate, a first main electrode (drain electrode) provided on the lower surface of the semiconductor substrate, and second main electrodes (source electrodes) 31a to 31l, a control electrode (gate electrode), and an auxiliary source electrode provided on the upper surface of the semiconductor substrate. The drain electrodes of the semiconductor chips 3a to 3f are electrically connected to the conductive plate 10a. The drain electrodes of the semiconductor chips 3g to 3l are electrically connected to the conductive plate 10c.

[0040] The semiconductor substrate of the semiconductor chips 3a to 3l is made of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or the like. The arrangement positions and the number of the semiconductor chips 3a to 3l are not particularly limited. The semiconductor chips 3a to 3l may be field effect transistors (FETs) such as MOSFETs, insulated gate bipolar transistors (IGBTs), reverse conducting insulated gate bipolar transistors (RC-IGBTs) in which a diode is connected in reverse parallel to an IGBT, static induction (SI) thyristors, gate turn-off (GTO) thyristors, or the like.

[0041] 5 and 6, a pad portion 15 is provided on the upper surface of the conductive plate 10a facing the conductive plate 10c. Pad portions 17a and 17b are provided on the upper surface of the conductive plate 10a facing the output terminal 2c. A pad portion 16 is provided on the upper surface of the conductive plate 10b. A pad portion 18 is provided on the upper surface of the conductive plate 10c facing the positive terminal 2b.

[0042] The pads 15, 16, 17a, 17b, and 18 are bonded to the upper surfaces of the conductive plates 10a to 10c using a bonding material such as solder, a conductive adhesive, or a sintered material. The pads 15, 16, 17a, 17b, and 18 are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. The pads 15, 16, 17a, 17b, and 18 may be convex portions formed integrally with the conductive plates 10a to 10c.

[0043] 5 and 6, a temperature detection chip 5 is provided on the upper surface of the conductive plate 10a, which faces the conductive plate 10c. The temperature detection chip 5 is bonded to the upper surface of the conductive plate 10a using a bonding material such as solder, a conductive adhesive, or a sintered material.

[0044] As shown in Fig. 5 and Fig. 6, a printed circuit board (also called a "control wiring board") (11, 12a to 12d) for control wiring is disposed on the upper surface side of the conductive plate 10a. The printed circuit board (11, 12a to 12d) includes an insulating layer 11, conductive layers 12a to 12d disposed spaced apart from each other on the upper surface side of the insulating layer 11, and a conductive layer (not shown) provided on the lower surface side of the insulating layer 11. The conductive layer on the lower surface side of the insulating layer 11 is joined to the conductive plate 10a via a bonding material such as solder, a conductive adhesive, or a sintered material.

[0045] The insulating layer 11 is composed of a ceramic plate mainly made of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), etc., or a resin insulating layer using a polymer material, etc. The resin insulating layer may be a layer in which glass fiber is impregnated with epoxy resin. The insulating layer 11 has a first region extending in one direction (vertical direction in FIG. 6) between the semiconductor chips 3a to 3c and the semiconductor chips 3d to 3f, and a second region extending in a direction perpendicular to the first region (horizontal direction in FIG. 6). In FIG. 5 and FIG. 6, the insulating layer 11 has a T-shaped planar pattern as an example, but is not limited thereto, and the insulating layer 11 may have an L-shaped planar pattern, for example.

[0046] The conductive layers 12a to 12d are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), an Al alloy, etc. The conductive layers 12a to 12d are provided in a line on the second region of the insulating layer 11. The conductive layers 12a and 12b are provided across the first and second regions of the insulating layer 11.

[0047] The conductive layers 12a and 12b are provided so as to extend from the end of the conductive plate 10a between the semiconductor chips 3a to 3c and the semiconductor chips 3d to 3f. The conductive layers 12a and 12b have wide regions that are alternately arranged with each other.

[0048] The gate electrodes of the semiconductor chips 3a-3f are electrically connected to the wide region of the conductive layer 12a via control wiring (bonding wires) 72a-72f. The control terminal 4a is bonded to the conductive layer 12a using a bonding material such as solder, a conductive adhesive, or a sintered material. The control terminal 4a extends in a direction perpendicular to the upper surface of the conductive layer 12b. The control terminal 4a applies a control signal to the gate electrodes of the semiconductor chips 3a-3f via the conductive layer 12a and the bonding wires 72a-72f.

[0049] A part (not shown) of each source electrode of the semiconductor chips 3a to 3f is electrically connected to the wide region of the conductive layer 12b via the control wiring (bonding wires) 71a to 71f. The control terminal 4b is bonded to the conductive layer 12b using a bonding material such as solder, conductive adhesive, or sintered material. The control terminal 4b extends in a direction perpendicular to the upper surface of the conductive layer 12b. The control terminal 4b is electrically connected to the source electrodes of the semiconductor chips 3a to 3f via the bonding wires 71a to 71f and the conductive layer 12b. When the semiconductor chips 3a to 3f are turned on, a voltage is applied to the control terminal 4b, and a voltage obtained by adding a voltage value of the control terminal 4b to a voltage value equal to or higher than the threshold value of the semiconductor chips 3a to 3f is applied to the control terminal 4a.

[0050] One electrode of the temperature detection chip 5 is connected to the conductive layer 12c via a control wiring (bonding wire) 73a. For example, a temperature detection diode is used as the temperature detection chip 5. A control terminal 4c is bonded to the conductive layer 12c using a bonding material such as solder, a conductive adhesive, or a sintered material. The control terminal 4c extends in a direction perpendicular to the upper surface of the conductive layer 12c. The control terminal 4c is connected to the ground and transmits a ground voltage to the temperature detection chip 5 via the conductive layer 12c and the bonding wire 73a.

[0051] The other electrode of the temperature detection chip 5 is connected to the conductive layer 12d via a control wiring (bonding wire) 73b. A control terminal 4d is bonded to the conductive layer 12d using a bonding material such as solder, a conductive adhesive, or a sintered material. The control terminal 4d extends in a direction perpendicular to the upper surface of the conductive layer 12d. The control terminal 4d is connected to the temperature detection chip 5 via the conductive layer 12d and the bonding wire 73b, and the temperature is detected, for example, by measuring the forward voltage of the temperature detection diode.

[0052] A printed circuit board (13, 14a, 14b) for control wiring is disposed on the upper surface side of the conductive plate 10c. The printed circuit board (13, 14a, 14b) includes an insulating layer 13 and conductive layers 14a, 14b disposed spaced apart from each other on the upper surface side of the insulating layer 13. The insulating layer 13 can be made of the same material as the insulating layer 11, and the conductive layers 14a, 14b can be made of the same material as the conductive layers 12a to 12d.

[0053] The insulating layer 13 includes a first region extending in one direction (the vertical direction in FIG. 6) between the semiconductor chips 3g-3i and the semiconductor chips 3j-3l, and a second region extending in a direction perpendicular to the first region (the horizontal direction in FIG. 6). In FIG. 5 and FIG. 6, the insulating layer 13 has a T-shaped planar pattern, but is not limited thereto, and for example, the insulating layer 13 may have an L-shaped planar pattern.

[0054] The conductive layers 14a and 14b are provided across the first and second regions of the insulating layer 13. The conductive layers 14a and 14b are provided to extend from the end of the conductive plate 10c between the semiconductor chips 3g-3i and the semiconductor chips 3j-3l. The conductive layers 14a and 14b have wide regions that are alternately arranged with each other.

[0055] The wide region of the conductive layer 14a is electrically connected to the gate electrodes of the semiconductor chips 3g-3l via control wiring (bonding wires) 72g-72l. A control terminal 4e is bonded to the conductive layer 14a using a bonding material such as solder, a conductive adhesive, or a sintered material. The control terminal 4e extends in a direction perpendicular to the upper surface of the conductive layer 14a. The control terminal 4e applies a control signal to the gate electrodes of the semiconductor chips 3g-3l via the conductive layer 14a and the bonding wires 72g-72l.

[0056] The wide region of the conductive layer 14b is electrically connected to a part (not shown) of each source electrode of the semiconductor chips 3g-3l via the control wiring (bonding wires) 71g-71l. The control terminal 4f is bonded to the conductive layer 14b using a bonding material such as solder, conductive adhesive, or sintered material. The control terminal 4f extends in a direction perpendicular to the upper surface of the conductive layer 14b. The control terminal 4f is electrically connected to the source electrodes of the semiconductor chips 3g-3l via the bonding wires 71g-71l and the conductive layer 14b. When the semiconductor chips 3g-3l are turned on, a voltage is applied to the control terminal 4f, and a voltage obtained by adding a voltage value of the control terminal 4f to a voltage value equal to or higher than the threshold value of the semiconductor chips 3g-3l is applied to the control terminal 4e.

[0057] A control terminal 4g is bonded to the upper surface of the conductive plate 10c using a bonding material such as solder, a conductive adhesive, a sintered material, etc. The control terminal 4g extends in a direction perpendicular to the upper surface of the conductive plate 10c.

[0058] Fig. 7 is a perspective view of an integrated structure (2b, 2c, 91-93) which is a component of the semiconductor device according to the first embodiment. Fig. 7 shows the integrated structure (2b, 2c, 91-93) in an assembled state, in which the positive electrode terminal 2b and the output terminal 2c are provided integrally with the tie bar wirings 2x and 2y.

[0059] 6 and 7, the integrated structure (2b, 2c, 91-93) includes a positive electrode terminal 2b, an output terminal 2c, and insulating members 91-93. The positive electrode terminal 2b and the output terminal 2c are partially covered with the insulating members 91, 93, so that the positive electrode terminal 2b, the output terminal 2c, and the insulating members 91-93 are integrated together.

[0060] The positive electrode terminal 2b has a flat plate shape and a substantially rectangular planar pattern. As shown in Fig. 5 and Fig. 6, the positive electrode terminal 2b is joined to a pad portion 18 on the upper surface side of the conductive plate 10c via a joining material such as solder, a conductive adhesive, or a sintered material, or by direct joining.

[0061] The output terminal 2c has a flat plate shape and a U-shaped planar pattern. As shown in Figures 5 and 6, the output terminal 2c is joined to the pads 17a and 17b on the upper surface of the conductive plate 10a via a joining material such as solder, a conductive adhesive, or a sintered material, or by direct joining.

[0062] 6 and 7, insulating members 91 to 93 are integrally formed. Insulating member 92 is provided continuous with insulating member 91, and insulating member 93 is provided continuous with insulating member 92. The semiconductor device according to the first embodiment is required to include at least insulating member 91, and may not include insulating members 92 and 93. The semiconductor device according to the first embodiment may include insulating members 91 and 92 without including insulating member 93, or may include insulating members 91 and 93 without including insulating member 92. Insulating members 91 to 93 may not be integrally formed, but may be provided separately from one another.

[0063] As shown in Fig. 6 and Fig. 7, the insulating member 91 has a covering portion 94, and a frame portion 95 and locking portions 96a, 96b provided on the upper surface side of the covering portion 94. The covering portion 94 covers a part of the positive electrode terminal 2b over the entire periphery (top, bottom and both side surfaces). As shown in Fig. 3 and Fig. 4, the negative electrode terminal 2a is disposed on the upper surface side of the covering portion 94. The covering portion 94 has a function of ensuring an insulation distance between the positive electrode terminal 2b and the negative electrode terminal 2a, and also ensuring an insulation distance between the positive electrode terminal 2b and the ground.

[0064] 6 and 7, the frame 95 has a substantially U-shaped planar pattern. As shown in Figures 3 and 4, when the negative terminal 2a is placed on the upper surface of the covering 94, the side surface of the negative terminal 2a at the position on the upper surface of the covering 94 is surrounded by the frame 95. The frame 95 has the function of positioning the negative terminal 2a and ensuring an insulation distance between the negative terminal 2a and the positive terminal 2b.

[0065] As shown in Figs. 6 and 7, the locking portions 96a and 96b are provided at both ends of the frame portion 95. The locking portions 96a and 96b are, for example, convex portions facing each other. As shown in Figs. 3 and 4, the side surface of the negative terminal 2a is provided with locking portions 25a and 25b, which are recesses. When the negative terminal 2a is placed on the upper surface side of the covering portion 94, the locking portions 96a and 96b of the insulating member 91 are locked to the locking portions 25a and 25b of the negative terminal 2a, thereby positioning and fixing the negative terminal 2a. The locking portions 96a and 96b of the insulating member 91 and the locking portions 25a and 25b of the negative terminal 2a are sealed with the sealing resin 10 shown in Figs. 1 and 2.

[0066] The position, number and shape of the locking portions 96a, 96b of the insulating member 91 and the locking portions 25a, 25b of the negative electrode terminal 2a are not particularly limited. For example, the locking portion of the insulating member 91 may be configured as a recess, and the locking portion of the negative electrode terminal 2a may be configured as a protrusion. The locking portion of the insulating member 91 may be configured as a protrusion in the center of the upper surface side of the covering portion 94 of the insulating member 91, and the locking portion of the negative electrode terminal 2a may be configured as a recess on the lower surface side of the negative electrode terminal 2a or a through hole penetrating the upper and lower surfaces. Also, only one of the locking portions 96a, 96b of the insulating member 91 and the corresponding locking portions 25a, 25b of the negative electrode terminal 2a may be provided. That is, the position, number and shape may be such that the locking portion of the insulating member 91 can be locked with the locking portion of the negative electrode terminal 2a to position the negative electrode terminal 2a.

[0067] As shown in Figs. 6 and 7, the insulating member 92 has a substantially linear ("striped" or "beam-shaped") planar pattern. The thickness of the insulating member 92 is thinner than the thickness of the covering portion 94 of the insulating member 91. The height of the upper surface of the insulating member 92 is substantially the same as that of the covering portion 94 of the insulating member 91 and the upper surface of the insulating member 93. The insulating member 92 is provided with openings 92a-92g penetrating the insulating member 92 in the thickness direction. The openings 92a-92g have the function of positioning the control terminals 4a-4g. As shown in Figs. 3, 4 and 6, the control terminals 4a-4g are inserted into the openings 92a-92g, positioned, and fixed.

[0068] As shown in Figs. 6 and 7, the insulating member 93 covers a part of the output terminal 2c over the entire circumference. Both ends of the U-shape formed by the planar pattern of the output terminal 2c protrude from the side surface of the insulating member 93 on the positive terminal 2b side. The thickness of the insulating member 93 is approximately the same as the thickness of the covering portion 94 of the insulating member 91, and is thicker than the thickness of the insulating member 92. The insulating member 93 ensures an insulation distance between the output terminal 2c and the ground. In addition, the insulating member 93 is integrally formed with the insulating members 91 and 92, so that the insulating member 92 can be prevented from bending.

[0069] Fig. 8 is a perspective view of an integrated structure (2a, 6, 8) which is a component of the semiconductor device according to the first embodiment. As shown in Fig. 8, the integrated structure (2a, 6, 8) includes a negative electrode terminal 2a, a conductive member 6, and an insulating member 8. The negative electrode terminal 2a is provided on the upper surface side of the conductive member 6. The negative electrode terminal 2a and a portion of the conductive member 6 are covered with the insulating member 8, so that the negative electrode terminal 2a, the conductive member 6, and the insulating member 8 are integrated together.

[0070] FIG. 9 shows a perspective view of the negative electrode terminal 2a, which is a component of the integrated structure (2a, 6, 8) shown in FIG. 8. FIG. 10 shows a perspective view of the conductive member 6, which is a component of the integrated structure (2a, 6, 8) shown in FIG. 8. FIG. 11 shows a side view of the semiconductor device according to the first embodiment, omitting the integrated structures (2b, 2c, 91-93). FIG. 12 shows a side view of the semiconductor device according to the first embodiment, omitting the integrated structures (2b, 2c, 91-93) and further omitting the insulating member 8, which is a component of the integrated structure (2a, 6, 8).

[0071] As shown in Figures 8 to 12, the negative electrode terminal 2a includes a pad joint 29, a connection portion 28 connected to the pad joint 29, chip joint portions 21a to 21c connected to the connection portion 28, connection portions 22a to 22c connected to the chip joint portions 21a to 21c, chip joint portions 21d to 21f connected to the connection portions 22a to 22c, a connection portion 23 connected to the chip joint portions 21d to 21f, connection portions 24a to 24c connected to the connection portion 23, and a terminal portion 27 connected to the connection portions 24a to 24c.

[0072] The pad bonding portion 29 is a portion bent so as to be convex downward with respect to the connection portion 28. The pad bonding portion 29 is bonded to the pad portion 16 on the upper surface side of the conductive plate 10b shown in Figures 5 and 6 by using a bonding material such as solder, a conductive adhesive, or a sintered material.

[0073] The connection portion 28 has a substantially rectangular planar pattern. The chip bonding portions 21a-21f are bent so as to be convex downward with respect to the connection portion 28 and the connection portions 22a-22c. The chip bonding portions 21a-21f are bonded to the source electrodes 31a-31f of the semiconductor chips 3a-3f shown in Fig. 5 and Fig. 6, respectively, using a bonding material such as solder, a conductive adhesive, or a sintered material.

[0074] The connecting portions 22a to 22c have a striped planar pattern that is spaced apart from each other and extends in parallel. The connecting portion 23 has a planar pattern with a substantially rectangular outer shape. The connecting portions 24a to 24c have a striped planar pattern that is spaced apart from each other and extends in parallel. The connecting portion 23 and a portion of the connecting portions 24a to 24c are covered with the insulating member 8 shown in FIG. 8.

[0075] The terminal portion 27 has a substantially rectangular planar pattern. Locking portions 25a and 25b are provided on the side surface of the terminal portion 27. As shown in Figs. 3 and 4, the terminal portion 27 is disposed on the upper surface side of the positive electrode terminal 2b via an insulating member 91. As shown in Figs. 1 and 2, the terminal portion 27 protrudes from the side surface of the sealing resin 10.

[0076] In addition, instead of calling the negative electrode terminal 2a shown in FIG. 9 the "negative electrode terminal," terminal portion 27 of negative electrode terminal 2a may be called the "negative electrode terminal," and the parts other than terminal portion 27, namely pad bonding portion 29, connection portion 28, chip bonding portions 21a to 21c, connection portions 22a to 22c, chip bonding portions 21d to 21f, connection portion 23, and connection portions 24a to 24c, may be called a "lead frame" or a "clip" integrated with the "negative electrode terminal."

[0077] As shown in Figures 10 to 12, the conductive member 6 includes a pad joint portion 61, a connection portion 62 connected to the pad joint portion 61, chip joint portions 63a to 63c connected to the connection portion 62, connection portions 64a to 64c connected to the chip joint portions 63a to 63c, and chip joint portions 63d to 63f connected to the connection portions 64a to 64c.

[0078] The pad bonding portion 61 is a portion bent so as to be convex downward with respect to the connection portion 62. The pad bonding portion 61 is exposed from the lower surface of the insulating member 8 shown in Fig. 8. The pad bonding portion 61 is bonded to the pad portion 15 on the upper surface side of the conductive plate 10a shown in Fig. 5 and Fig. 6 using a bonding material such as solder, a conductive adhesive, or a sintered material.

[0079] The connection portion 62 has a substantially rectangular planar pattern and is covered with the insulating member 8 shown in FIG.

[0080] The chip bonding portions 63a to 63f are bent so as to be convex downward with respect to the connection portion 62 and the connection portions 64a to 64c. The chip bonding portions 63a to 63f are exposed from the lower surface of the insulating member 8 shown in Fig. 8. The chip bonding portions 63a to 63f are bonded to the source electrodes 31g to 31l of the semiconductor chips 3g to 3l in Figs. 5 and 6 using a bonding material such as solder, a conductive adhesive, or a sintered material.

[0081] The connection portions 64a to 64c have a striped planar pattern that is spaced apart from one another and extends in parallel to one another, and are covered with the insulating member 8 shown in FIG.

[0082] 10, a plate-shaped (sheet-shaped) insulating member (insulating sheet) 60 is provided so as to cover the upper surface side of the connection portion 62 and the connection portions 64a to 64c of the conductive member 6. The insulating member 60 is sandwiched between the conductive member 6 and the negative electrode terminal 2a, and is covered by the insulating member 8. As the insulating member 60, for example, insulating paper or an insulating material having high insulating properties and heat resistance, such as polyimide or polyamide, can be used.

[0083] As shown in Fig. 8, the insulating member 8 includes a covering portion 81 having an outer shape of a substantially rectangular parallelepiped, and covering portions 82a to 82c connected to the covering portion 81. The covering portion 81 covers the connection portion 23 of the negative electrode terminal 2a shown in Fig. 9 and the connection portion 62 of the conductive member 6 shown in Fig. 10 with the insulating member 60 sandwiched therebetween. The covering portions 82a to 82c respectively cover the connection portions 24a to 24c of the negative electrode terminal 2a shown in Fig. 9 and the connection portions 64a to 64c of the conductive member 6 shown in Fig. 10 with the insulating member 60 sandwiched therebetween.

[0084] As shown in Figures 11 and 12, support parts (sleeves) 5a to 5g are joined to the upper surfaces of the conductive layers 12a to 12d, 14a, and 14b and the conductive plate 10c shown in Figure 5 using a joining material such as solder, a conductive adhesive, or a sintered material. The sleeves 5a to 5g are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy. The lower parts of the control terminals 4a to 4g protruding from the lower surfaces of the insulating members 41 and 42 are press-fitted and fixed into the sleeves 5a to 5g.

[0085] Fig. 13 is a schematic side view of a mounting structure of semiconductor devices 101a-101c according to the first embodiment. Each of the semiconductor devices 101a-101c corresponds to the semiconductor device shown in Fig. 1 and Fig. 2. The lower surfaces of the conductive plates 10d, 10e shown in Fig. 11 and Fig. 12 are exposed on the lower surface side of each of the semiconductor devices 101a-101c. A cooler (base) 103 is disposed on the lower surface side of the semiconductor devices 101a-101c via sheet-like resin layers (resin sheets) 102a-102c.

[0086] The resin sheets 102a-102c ensure heat dissipation from the semiconductor devices 101a-101c to the cooler 103, while providing insulation and adhesion between the semiconductor devices 101a-101c and the cooler 103. The resin sheets 102a-102c can be made of, for example, epoxy resin. The cooler 103 can be made of, for example, copper (Cu), aluminum (Al), a composite material of Al and silicon carbide (AlSiC), a composite material of magnesium (Mg) and silicon carbide (MgSiC), etc.

[0087] FIG. 14 shows an equivalent circuit of the semiconductor device according to the first embodiment. As shown in FIG. 14, the semiconductor device according to the first embodiment constitutes a part of a three-phase bridge circuit. A drain electrode of the transistor T1 on the upper arm side is connected to a positive terminal P, and a source electrode of the transistor T2 on the lower arm side is connected to a negative terminal N. A source electrode of the transistor T1 and a drain electrode of the transistor T2 are connected to an output terminal U and an auxiliary source terminal S1. An auxiliary source terminal S2 is connected to a source electrode of the transistor T2. Gate control terminals G1 and G2 are connected to gate electrodes of the transistors T1 and T2. Body diodes D1 and D2, which serve as freewheeling diodes (FWD), are built into the transistors T1 and T2 and are connected in inverse parallel.

[0088] The output terminal U, the positive terminal P, and the negative terminal N shown in FIG. 14 correspond to the output terminal 2c, the positive terminal 2b, and the negative terminal 2a shown in FIG. 1 and FIG. 2. The transistor T1 and the body diode D1 shown in FIG. 14 correspond to the semiconductor chips 3g to 3l shown in FIG. 5 and FIG. 6. The transistor T2 and the body diode D2 shown in FIG. 14 correspond to the semiconductor chips 3a to 3f shown in FIG. 5 and FIG. 6. The gate control terminals G1 and G2 shown in FIG. 14 correspond to the control terminals 4a and 4e shown in FIG. 1 and FIG. 2. The auxiliary source terminals S1 and S2 shown in FIG. 14 correspond to the control terminals 4b and 4f shown in FIG. 1 and FIG. 2.

[0089] <Method of Manufacturing Semiconductor Device> Next, an example of a manufacturing method (assembly method) for the semiconductor device according to the first embodiment will be described.

[0090] First, the positive terminal 2b, the output terminal 2c, and the insulating members 91-93 are integrally molded by transfer molding or the like using a mold to form an integrated structure (2b, 2c, 91-93) as shown in Fig. 7. The positive terminal 2b and the output terminal 2c are integrally formed with the tie bar wirings 2x and 2y.

[0091] In addition, with the insulating member 60 sandwiched between the conductive member 6 and the insulating member 8, the negative terminal 2a, the conductive member 6 and the insulating member 8 are integrally molded by transfer molding or the like using a mold to produce an integrated structure (2a, 6, 8) as shown in Figure 8.

[0092] 5, the semiconductor chips 3a-3f, printed circuit boards (11, 12a-12d), temperature detection chip 5, pads 15, 16, 17a, 17b, sleeves 5a-5d, etc. are bonded to the upper surfaces of the conductive plates 10a, 10b of the insulating circuit board 1a using a bonding material such as solder, a conductive adhesive, or a sintered material. Furthermore, the semiconductor chips 3a-3f, printed circuit boards (11, 12a-12d), and temperature detection chip 5 are electrically connected to each other using bonding wires 71a-71f, 72a-72f, 73a, 73b.

[0093] 5, the semiconductor chips 3g-3l, printed circuit boards (13, 14a, 14b), pads 18, sleeves 5e-5g, etc. are bonded to the upper surface of the conductive plate 10c of the insulating circuit board 1b using a bonding material such as solder, a conductive adhesive, or a sintered material. Furthermore, the semiconductor chips 3g-3l and printed circuit boards (13, 14a, 14b) are electrically connected to each other using bonding wires 71g-71l, 72g-72l.

[0094] Next, as shown in Fig. 6, the upper surface side of the insulating circuit boards 1a and 1b is aligned with the integrated structure (2b, 2c, 91-93), and the output terminal 2c of the integrated structure (2b, 2c, 91-93) is joined to the pad portion 17a and 17b using a bonding material such as solder, conductive adhesive, or sintered material. Also, the positive terminal 2b of the integrated structure (2b, 2c, 91-93) is joined to the pad portion 18 using a bonding material such as solder, conductive adhesive, or sintered material. Although not shown in Fig. 6, tie bar wiring 2x and 2y are connected to the positive terminal 2b and the output terminal 2c.

[0095] Next, the control terminals 4a-4d supported by the insulating member 41 and the control terminals 4e-4g supported by the insulating member 42 are aligned with the upper surface side of the openings 92a-92g of the insulating member 92 of the integrated structure (2b, 2c, 91-93), and the lower parts of the control terminals 4a-4g are inserted into the openings 92a-92g to position them. Then, the lower parts of the control terminals 4a-4g are press-fitted into the sleeves 5a-5g to be fixed.

[0096] 3, the integrated structure (2a, 6, 8) is aligned with the upper surface sides of the insulating circuit boards 1a, 1b and the integrated structure (2b, 2c, 91-93), and the terminal portion 27 of the negative electrode terminal 2a of the integrated structure (2a, 6, 8) is disposed on the upper surface side of the covering portion 94 of the insulating member 91. At this time, the negative electrode terminal 2a is positioned by the frame portion 95 of the insulating member 91. Furthermore, the locking portions 96a, 96b of the insulating member 91 are locked with the locking portions 25a, 25b of the negative electrode terminal 2a, whereby the negative electrode terminal 2a is positioned.

[0097] In addition, the pad joint portion 29 of the negative electrode terminal 2a is joined to the pad portion 16 using a joint material such as solder, a conductive adhesive, or a sintered material. In addition, the chip joint portions 21a-21f of the negative electrode terminal 2a are joined to the source electrodes 31a-31f of the semiconductor chips 3a-3f using a joint material such as solder, a conductive adhesive, or a sintered material. In addition, the pad joint portion 61 of the conductive member 6 is joined to the pad portion 16 using a joint material such as solder, a conductive adhesive, or a sintered material. In addition, the chip joint portions 61a-61f of the conductive member 6 are joined to the source electrodes 31g-31l of the semiconductor chips 3g-3l using a joint material such as solder, a conductive adhesive, or a sintered material.

[0098] Next, as shown in Fig. 1, the semiconductor chips 3a to 3l are sealed with sealing resin 10 by transfer molding, and the negative terminal 2a, the positive terminal 2b, the output terminal 2c, and parts of the control terminals 4a to 4g are also sealed with sealing resin 10. Then, as shown in Fig. 2, the tie bar wiring 2x, 2y are cut to separate the positive terminal 2b and the output terminal 2c from each other. This completes the semiconductor device according to the first embodiment.

[0099] According to the semiconductor device of the first embodiment, the main wiring circuit is three-dimensionally wired using an integrated structure (2a, 6, 8) in which the negative electrode terminal 2a, the conductive member 6, and the insulating member 8 are integrally formed, and the control wiring circuit is formed as a separate substrate using printed circuit boards (11, 12a to 12d) and printed circuit boards (13, 14a, 14b). As a result, compared to a conventional semiconductor device in which a semiconductor chip is mounted on a circuit pattern of an insulating circuit board and the semiconductor chip and the circuit pattern of the insulating circuit board are electrically connected by a lead frame, a bonding wire, or the like, the wiring area can be reduced, and the increase in chip size and cost can be reduced, and low inductance characteristics can be achieved. Furthermore, compared to a conventional semiconductor device in which an insulating circuit board is surrounded by a case and resin is injected by potting to seal it, a case is not required, and space, labor, and cost can be reduced.

[0100] Furthermore, according to the semiconductor device of the first embodiment, insulation between the positive terminal 2b and the negative terminal 2a and between them and the ground can be ensured by using an integrated structure (2b, 2c, 91-93) in which the positive terminal 2b, the output terminal 2c, and the insulating members 91-93 are integrally formed. In addition, by forming the positive terminal 2b and the output terminal 2c using the tie bar wiring 2x, 2y, the positional accuracy of the positive terminal 2b and the output terminal 2c can be ensured without using a jig for the internal wiring.

[0101] Furthermore, according to the semiconductor device of the first embodiment, the insulating member 91 is provided with the locking portions 96a, 96b, and the negative terminal 2a is provided with the locking portions 25a, 25b, so that the locking portions 96a, 96b and the locking portions 25a, 25b are locked together. This ensures the positional accuracy of the positive terminal 2b and the negative terminal 2a without using a jig for the internal wiring, and allows the positive terminal 2b and the negative terminal 2a to be arranged closely together (laminate arrangement). This improves transfer manufacturability, and realizes a low inductance structure that can make the most of the characteristics of SiC chips, etc.

[0102] Furthermore, according to the semiconductor device of the first embodiment, by providing openings 92a-92g in the insulating member 92 of the integrated structure (2b, 2c, 91-93), the control terminals 4a-4g can be positioned, and the positional accuracy of the control terminals 4a-4g can be improved.

[0103] Second embodiment Fig. 15 is a plan view of the semiconductor device according to the second embodiment. As shown in Fig. 15, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that slits (groove portions) 9a are provided on the upper surface side of an insulating member 91. The number, length, width, depth, etc. of the slits 9a are not particularly limited. Other configurations of the semiconductor device according to the second embodiment are substantially similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0104] In the semiconductor device according to the second embodiment, the slits 9a are provided on the upper surface side of the insulating member 91, so that the insulation distance between the negative electrode terminal 2a and the positive electrode terminal 2b can be further ensured.

[0105] Third embodiment FIG. 16 is a plan view of the semiconductor device according to the third embodiment, with the sealing resin 10 omitted. As shown in FIG. 16, the semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment in that a fixing portion (convex portion) 93a for fixing the negative electrode terminal 2a is provided on the insulating member 93. The end of the fixing portion 93a is adjusted to a position where it contacts the pad bonding portion 29 of the negative electrode terminal 2a. The position and shape of the fixing portion for fixing the negative electrode terminal 2a are not limited to this, and it is sufficient to provide it at a position and shape that allows the negative electrode terminal 2a to be fixed. Other configurations of the semiconductor device according to the third embodiment are substantially similar to those of the semiconductor device according to the first embodiment, so that repeated explanations will be omitted.

[0106] According to the semiconductor device of the third embodiment, by providing a fixing portion 93a on the insulating member 93, the negative electrode terminal 2a can be fixed (positioned) even at the end opposite to the end of the negative electrode terminal 2a that is arranged in close proximity to the positive electrode terminal 2b.

[0107] (Other embodiments) As described above, the present disclosure has been described by the first to third embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0108] For example, in the first to third embodiments, the positive electrode terminal 2b is covered with the insulating member 91, and the negative electrode terminal 2a is disposed adjacent to the upper surface side of the positive electrode terminal 2b with the insulating member 91 interposed therebetween, but the arrangement relationship between the positive electrode terminal 2b and the negative electrode terminal 2a may be reversed. That is, the negative electrode terminal 2a may be covered with the insulating member 91, and the positive electrode terminal 2b may be disposed on the upper surface side of the negative electrode terminal 2a with the insulating member 91 interposed therebetween.

[0109] In addition, the configurations disclosed in the embodiments can be appropriately combined within a range that does not cause contradictions. In this way, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is determined only by the invention-specifying matters related to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0110] 1a, 1b...Insulated circuit board 2a...External terminal (negative terminal) 2b…External terminal (positive terminal) 2c...External terminal (output terminal) 2x, 2y...Tie bar wiring 3a to 3l: Power semiconductor elements (semiconductor chips) 4a~4g...External terminals (control terminals) 5. Temperature detection chip 5a~5g…Support part (sleeve) 6...Conductive material 7a, 7b...insulating plate 8...Insulating material 9a…Slit (groove) 10…Sealing resin 10a to 10e: Conductive plate 11...Insulating layer 12a~12d...conductive layer 13...Insulating layer 14a, 14b...conductive layer 15, 16, 17a, 17b, 18...Pad section 21a~21f…Chip joint 22a~22c, 23, 24a~24c...Connections 25a, 25b...locking part 27...Terminal section 28…Connection 29…Pad joint 31a~31l…Source electrodes 41, 42...Insulating member 60...Insulating material (insulating sheet) 61…Pad joint 61a~61f…Chip joint 62…Connection 63a~63f…Chip joint 64a~64c…Connections 71a~71l, 72a~72l, 73a, 73b...Bonding wire 81, 82a to 82c... Covering section 91~93...Insulating materials 92a~92g…opening 93a…Fixed part (protruding part) 94…Covering part 95…Frame 96a, 96b...locking part 101a to 101c...Semiconductor device 102a to 102c: Resin layer (resin sheet) 103…Cooler (base) D1, D2: Body diode G1, G2: Gate control terminals N...Negative terminal P...Positive terminal S1, S2: Auxiliary source terminals T1, T2: Transistor U: Output terminal

Claims

1. an insulating circuit board having an insulating plate and a conductive plate provided on an upper surface side of the insulating plate; a semiconductor chip provided on an upper surface side of the conductive plate; a first external terminal electrically connected to the semiconductor chip; a first insulating member including a covering portion that covers a part of the first external terminal and a first locking portion provided on an upper surface side of the covering portion; a second external terminal electrically connected to the semiconductor chip, the second external terminal being provided on an upper surface side of the first external terminal via the covering portion, the second external terminal having a second locking portion that locks to the first locking portion; a sealing resin that seals the semiconductor chip and also seals parts of the first external terminal, the first insulating member, and the second external terminal; A semiconductor device comprising:

2. The first engaging portion is a protrusion, The second locking portion is a recess. The semiconductor device according to claim 1 .

3. The first and second locking portions are covered with the sealing resin. The semiconductor device according to claim 1 .

4. The first insulating member has a frame portion surrounding a part of a side surface of the second external terminal. The semiconductor device according to claim 1 .

5. a third external terminal electrically connected to the semiconductor chip and spaced apart from the first external terminal and the second external terminal; a second insulating member covering a portion of the third external terminal; Further comprising The semiconductor device according to claim 1 .

6. The insulating member further includes a third insulating member provided between the first insulating member and the second insulating member and integrally with the first insulating member and the second insulating member. The semiconductor device according to claim 5 .

7. A control terminal electrically connected to the semiconductor chip is further provided. The third insulating member has an opening for positioning the control terminal. The semiconductor device according to claim 6.

8. A slit is provided on the upper surface side of the covering portion. The semiconductor device according to claim 1 .

9. The second insulating member has a fixing portion for fixing the second external terminal. The semiconductor device according to claim 1 .

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