Compilation program and compilation method

Abstract

To shorten time required for execution of one instruction and to reduce restriction on use to perform an SIMD operation.SOLUTION: There is provided a compilation method in which computer executes processing of: securing a data area of at least one array to which a data element satisfying an escape condition of an arithmetic loop belongs to have equal to or more than SIMD width as data length which can be processed in parallel at once in memory data to be loaded from a memory; acquiring a data position in the array in which the data element exists; setting an arithmetic mask to each data element of the array on the basis of the data position; and executing an SIMD operation to the memory data by using the arithmetic mask.SELECTED DRAWING: Figure 23

Description

[Technical field]

[0001] The present invention relates to a compilation program and a compilation method. [Background technology]

[0002] In computers, SIMD (Single Instruction Multiple Data) instructions, which execute operations on multiple pieces of data in parallel using the same arithmetic unit, are increasingly being used to improve computing performance. SIMD instructions are provided particularly in computing devices that operate in supercomputers or servers, where high computing performance is expected. Computing devices are also sometimes called processors.

[0003] When a processor that supports SIMD instructions executes a SIMD instruction, it reads memory data from memory into a register and uses the register to perform operations in parallel on multiple data elements included in a given SIMD element unit (SIMD processing unit). The processor then stores the operation results in memory as a SIMD element unit that includes the multiple SIMD elements. For example, a SIMD element unit may consist of eight 8-byte data elements. When the same operation is performed simultaneously on eight elements, the number of SIMD elements (number of elements) is eight.

[0004] In addition, in order to speed up program logic written in software, particularly loop processing (i.e., repetitive processing), it is desirable for a compiler to perform optimal instruction expansion. Various methods have been devised as techniques for speeding up loop processing, such as loop unrolling, software pipelining, and loop merging.

[0005] A method of using a first fault load instruction to perform SIMD operations in a program involving loop processing is known. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Special Publication No. 2018-534672 Summary of the Invention [Problem to be solved by the invention]

[0007] The technique of using the first-fault load instruction to perform SIMD operations can make it difficult to improve performance because the time required to execute one instruction, i.e., instruction latency, is longer than that of a technique that uses normal SIMD instructions without the first-fault load instruction.

[0008] In addition, the first-fault load instruction has limitations in addressing and few types of instructions. Therefore, the first-fault load instruction may be a constraint in object expansion and optimization by a compiler. In addition, the first-fault load instruction can be used only in CPUs that support the first-fault load instruction.

[0009] In one aspect, an object of the present invention is to reduce the time required to execute one instruction for SIMD calculations and to alleviate restrictions on use. [Means for solving the problem]

[0010] In one aspect, the compilation program causes a computer to execute the following processes: for memory data loaded from a memory, a data area for at least one array to which a data element that satisfies an exit condition of an operation loop belongs, the data area being equal to or larger than a SIMD width, which is a data length that can be processed in parallel at one time; obtaining a data position within the array in which the data element exists; setting an operation mask for each of the data elements of the array based on the data position; and executing a SIMD operation on the memory data using the operation mask. Effect of the Invention

[0011] According to one aspect, the present invention can reduce the time required to execute one instruction for SIMD calculations and ease restrictions on use. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a diagram showing the relationship between the SIMD width, data elements, and the number of elements of a SIMD register. [Diagram 2] FIG. 1 is a diagram illustrating an example of an application of a SIMD instruction. [Diagram 3] FIG. 1 is a diagram illustrating an example of SIMD object expansion using loop division. [Figure 4] FIG. 13 is a diagram illustrating an example of a comparison between a case where a SIMD instruction is applied and a case where a SIMD instruction is not applied. [Diagram 5] FIG. 13 is a diagram showing a first example of a source program in which an exit process is included in a loop. [Figure 6] FIG. 13 is a diagram showing a second example of a source program including an exit process in a loop. [Figure 7] FIG. 13 is a diagram illustrating an example of the relationship between a do while statement and an if exit statement. [Figure 8] FIG. 13 is a diagram illustrating an example of a process for invalidating the remaining loop process that was scheduled after an if exit statement. [Figure 9] FIG. 13 illustrates a technique using a fast fault load process. [Figure 10] FIG. 13 is a diagram illustrating a mask register in a first fault load process. [Figure 11] FIG. 13 is a diagram illustrating an example of an operation in a first fault load process. [Figure 12] FIG. 13 is a diagram illustrating an example of a first fault load process in a SIMD process including an exit process in a loop. [Figure 13]FIG. 13 is a diagram showing an example of an intermediate program obtained by analyzing a source program and performing SIMD processing using a first fault load process. [Figure 14] FIG. 13 is a diagram showing object development and an excerpt of main instructions in a first fault load process. [Figure 15] FIG. 13 is a diagram illustrating an example of a first fault load process. [Figure 16] This is an example of the process subsequent to FIG. [Figure 17] FIG. 2 is a diagram illustrating an example of a hardware (HW) configuration of the compiling device according to the present embodiment. [Figure 18] 2 is a block diagram showing an example of a functional configuration of a compiling device according to the present embodiment. FIG. [Figure 19] 19 is a block diagram showing an example of a functional configuration of an analysis unit shown in FIG. 18. [Figure 20] FIG. 13 is a diagram illustrating classification of loop processes. [Figure 21] FIG. 13 illustrates an example of a DO management table. [Figure 22] 19 is a block diagram showing an example of a functional configuration of a code generating unit shown in FIG. 18. [Figure 23] FIG. 11 is a diagram illustrating a first example of a compilation process in the present embodiment. [Figure 24] FIG. 11 is a diagram illustrating a second example of a compilation process in the present embodiment. [Diagram 25] 11 is a diagram illustrating an example of instruction expansion of a Do while statement in the compilation process according to the present embodiment. FIG. [Figure 26] FIG. 4 is a diagram illustrating an example of control in a compilation process according to the present embodiment. [Figure 27] This is an example of the control following FIG. [Figure 28] FIG. 11 is a diagram illustrating a third example of a compilation process in the present embodiment. [Figure 29] FIG. 11 is a diagram illustrating a fourth example of a compilation process in the present embodiment. [Diagram 30]10 is a flowchart showing an example of a process of SIMD object development of a SIMD instruction in this embodiment. [Diagram 31] 9 is a flowchart showing an example of a process of SIMD object development of a SIMD instruction in the comparative example of FIGS. 3 to 8; [Diagram 32] 11 is a flowchart showing an example of an escape loop development process in the present embodiment. [Diagram 33] 11 is a flowchart showing an example of a process of expanding a SIMD instruction into a SIMD object based on an ocl specification in this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] [A] Explanation of related methods [A-1] Overview of SIMD processing

[0014] FIG. 1 is a diagram showing the relationship between the SIMD width, data elements, and the number of elements of a SIMD register. A SIMD (Single Instruction Multiple Data) instruction is an instruction that executes operations on multiple data elements in parallel in the same arithmetic unit in order to improve arithmetic performance. A compiler expands the SIMD instruction into objects. The object expansion of a SIMD instruction is called "SIMD operation expansion." In addition, a vector register used for SIMD operations by a SIMD instruction may be called a "SIMD register." A SIMD register is also called a register for SIMD operations.

[0015] SIMD instructions operate on memory data in units of SIMD elements with a given number of elements. The SIMD width is the data length that can be processed in parallel at one time. The SIMD width is sometimes called the SIMD boundary. For example, in FIG. 1, the SIMD width is eight data elements, each of which is eight bytes (real 8) in size, in the memory data. The number of data elements included in the SIMD element unit is the number of elements.

[0016] The number of data elements to be parallelized (i.e., the number of instructions) is arbitrary and is not limited to eight. Also, the source program does not depend on the description language, such as FORTRAN or C. In the following, for the sake of convenience, the number of data elements that can be processed simultaneously by a SIMD instruction is set to eight, and the language used is either FORTRAN or C.

[0017] Fig. 2 is a diagram showing an example of an application of a SIMD instruction. Fig. 2 shows an example of data definition for array A, array B, and array X. The elements of each array are double-precision real numbers, and the number of elements in each array is n (n is an integer equal to or greater than 2).

[0018] In code T3, Ai (i = 1 to n) represents the i-th element A(i) of array A, and Bi represents the i-th element B(i) of array B. The array X(i) of the calculation result shown in code T2 represents the i-th element X(i) of array X. The memory data of A1 to An may be stored consecutively in the memory area for array A. The memory data of B1 to Bn may be stored consecutively in the memory area for array B. And the calculation result of array X(i) = A(i) + B(i) may be stored consecutively in the memory area for array X.

[0019] Code T2-1 is an example of source code written in FORTRAN that includes an operation loop for arrays A and B. In this example, n=1024, and the do loop includes an operation X(i)=A(i)+B(i).

[0020] Reference symbol T2-2 indicates an example of SIMD arithmetic expansion for the loop indicated by T2-1 above. Reference symbol T3 indicates a schematic representation of the SIMD arithmetic processing in T2-2.

[0021] In this example, the number of elements that can be processed simultaneously by a SIMD instruction is eight. Arrays A, B, and X are the targets of consecutive memory data access. Therefore, using each memory area, each data stream is accessed in groups of eight elements, and addition is performed in parallel on the eight elements of array A and the eight elements of array B. The eight addition results are then stored in parallel in the memory area.

[0022] In this way, multiple elements of each array are stored in consecutive areas in memory. On the other hand, when data to be used for SIMD operations is read from memory to a SIMD register, multiple elements stored consecutively are read consecutively to the SIMD register.

[0023] [A-2] Dividing into SIMD loops and remainder loops (non-SIMD loops) Figure 3 is a diagram showing an example of SIMD object expansion using loop division. Code T2-3 is an example of source code written in FORTRAN. "do i=1,x" is written, where x is the loop rotation, and the number of rotations is not fixed. In this respect, code T2-3 differs from code T2-1 in Figure 2, where the number of rotations is fixed.

[0024] As a method of SIMD arithmetic expansion when the number of loop rotations cannot be determined at the time of translation in SIMD arithmetic expansion, there is a method using loop division as shown by reference symbol T4 in Fig. 3. Loop division is a method of object expansion by dividing a loop into a SIMD loop process (SIMD instruction loop process) such as reference symbol T4-1 and a remainder loop process (non-SIMD loop process) that cannot be expanded by SIMD arithmetic, such as reference symbol T4-2.

[0025] For example, when the loop rotation count x is 111, the processor executes 13 rotations of a SIMD loop process with a SIMD width of 8 bytes (the quotient of x / 8 and the remainder are truncated) and executes the remainder loop process 7 times (the remainder of x / 8), as shown in code T4-1.

[0026] 4 is a diagram showing an example of a comparison between the case where a SIMD instruction is applied and the case where a SIMD instruction is not applied. Reference symbol T5 shows the case where a SIMD instruction is not applied, and reference symbol T6 shows the case where a SIMD instruction is applied. In reference symbol T5, the processor adds each element of array A and each element of array B individually to calculate an array X which is the addition result. In reference symbol T6, the processor performs addition (i.e., calculation) in parallel for each SIMD element unit (in FIG. 4, the number of elements is 4) by the loop division explained in FIG. 3, and adds each element of array A and each element of array B individually for the remainder part.

[0027] As described in FIG. 3 and FIG. 4, when the technique of dividing a loop into a SIMD loop process and a remainder loop process is adopted, performance degradation occurs in cases where the number of loop rotations is small and the execution ratio of the remainder loop process to the entire process is high.

[0028] Furthermore, in the loop division technique, the loop process is divided into two loop processes, which increases branch overhead. Also, if the number of loop rotations is equal to or less than the SIMD width, the processor does not execute the SIMD loop process, but executes the remainder loop process. Therefore, the benefits of SIMD processing cannot be obtained, and performance deteriorates.

[0029] 5 is a diagram showing a first example of a source program in which an exit process is included in a loop. There are cases in which a loop includes an exit process that aborts the loop process when a loop end condition is satisfied, such as a "while loop", a "do while loop", "if goto", "if exit (Fortran)", and "if break (C language)".

[0030] A loop that includes an escape process is sometimes called an "exit loop." The escape process uses a predetermined number of loop rotations as the loop termination condition, but terminates the loop by satisfying the escape condition (i.e., the loop stop condition) even on the way to reaching the predetermined number of loop rotations. The escape loop also includes cases where the loop is terminated by satisfying the escape condition without using the number of loop rotations as the loop termination condition.

[0031] Code T7 in Fig. 5 includes an arithmetic loop that includes an "if break statement" as an escape condition. Code T7 in Fig. 5 is source code written in C language. In the case of code T7, the number of loop iterations is fixed. And, the processor immediately aborts the loop processing when the condition is satisfied midway through the loop. In code T7 in Fig. 5, the number of loop iterations is fixed as the loop termination condition.

[0032] When the SIMD operation is expanded, if the defined size of array A becomes 1024 bits or less due to the existence of an exit condition, the processor accesses a non-existent area. Therefore, in a normal load instruction, an exception (i.e., an exceptional condition) is detected and a response action is executed, causing the normal processing to be interrupted.

[0033] In addition, when SIMD arithmetic is expanded, if a comparison operation is performed on a SIMD element basis to determine whether an exit condition (for example, an if statement) is satisfied, there is no instruction that can determine at which SIMD element the condition is satisfied.Furthermore, when SIMD arithmetic is expanded, if a comparison operation is performed on a SIMD element basis to determine whether an exit condition (for example, an if statement) is satisfied, there is no instruction that can count the SIMD elements up to the satisfied element.

[0034] 5, the number of loop rotations is fixed, but SIMD arithmetic expansion is not possible and scalar expansion is executed. In scalar expansion, object expansion is performed so that one element of array A and one element of array B are individually arithmetically processed.

[0035] Figure 6 is a diagram showing a second example of a source program in which an exit process is included in a loop. Code T8 in Figure 6 includes an arithmetic loop that includes a "do while statement" as an exit condition. Code T8 in Figure 6 is source code written in Fortran. In the case of code T8, the number of loop rotations is not defined as the loop termination condition. The processor terminates the loop processing when the exit condition is satisfied.

[0036] When the number of loop rotations is not determined as the loop termination condition as shown in FIG. 6, this corresponds to the case where the number of loop rotations is set to infinity as the loop termination condition in the source program shown in FIG.

[0037] Fig. 7 is a diagram showing an example of the relationship between a do while statement and an if exit statement. In Fig. 7, a computation loop including a "do while statement" shown at reference symbol T9 is equivalent to a computation loop in which the loop rotation count is set to infinity as a loop termination condition shown at reference symbol T10 and an if exit statement is provided at the beginning of the loop processing.

[0038] An escape loop such as that shown in FIGS. 5 and 6, that is, a loop in which processing is terminated midway through the loop, cannot be expanded into SIMD operations.

[0039] 8 is a diagram showing an example of processing for invalidating the remaining loop processing scheduled after the if exit statement. Reference character T11 in FIG. 8 indicates processing before scalar expansion, and reference character T12 indicates processing after scalar expansion.

[0040] In the process of dividing a loop, the processor aborts the process scheduled in the SIMD loop and invalidates the remaining process of the loop. Then, after the invalidation process, scalar expansion is executed. Reference symbol T12 in FIG. 8 shows an example of a process of invalidating the remaining process of the loop scheduled after an if exit statement. The escape process, for example, an if exit process, is a process of aborting and exiting the loop midway when a predetermined condition is satisfied or not satisfied (i.e., when the escape condition is satisfied). In scalar expansion, the remaining process of the loop scheduled after the escape condition, for example, an if exit statement, is invalidated. To invalidate, in scalar expansion, a goto statement is provided immediately after the if exit statement, and a process that branches immediately after the loop is executed.

[0041] [A-3] Technique using the first fault load instruction FIG. 9 is a diagram showing a method using a first fault load process. Reference code T13 in FIG. 9 is an example of source code written in FORTRAN. "do i=1,x" is written, where x is a loop loop and the number of loops is not determined. Reference code T13 is the same as T2-3 in FIG. 3. However, in FIG. 3, the length of the arrays is 1024 in arrays A(i) and B(i). In contrast, in this example, for simplicity, the length of the memory data areas of A and B is set to 11 elements (0 to 10).

[0042] In the example of Figure 9, the SIMD element unit is 8. That is, the processor performs SIMD processing on 8 elements in parallel. Fast-fault load processing is processing that expands a loop with an unknown loop turn count into a SIMD loop and a remainder loop (non-SIMD loop) and performs SIMD operations on the loop as a loop containing one masked SIMD instruction.

[0043] As explained in Fig. 3, the loop rotation count is not limited to a multiple of the number of elements. In the first fault load process, since a remainder loop is not used, the final SIMD operation expansion executes SIMD processing including non-existent area memory data.

[0044] In the first loop, the processor loads a total of eight elements of array A, from element #1-0 (A(0)) to element #1-7 (A(7)), into the SIMD register. A similar process is performed for array B. The processor then executes a SIMD addition process. In the second loop, the processor also attempts to load eight elements (i.e., element #2-0 (A(8)) to element #2-7 (A(15)) in succession to the memory data loaded in the first loop in array A. However, in the second loop, as shown by reference T14, there are no memory data elements for the second element #2-4 (A(12)), element #2-5 (A(13)), element #2-6 (A(14)), and element #2-7 (A(15)), and no memory area exists. The same is true for array B, shown by reference T15. Therefore, the processor If the processor attempts to load the memory data as is, an exception condition such as an address translation fault or a memory permission fault occurs. A corresponding action is initiated to handle the exception condition. In one example, the corresponding action is to generate a trap instruction to abnormally terminate the program, which interrupts normal processing. To avoid interrupting processing, the processor has difficulty loading the memory data into the SIMD operation register. Therefore, the processor uses a fast-fault load instruction to perform SIMD operation expansion.

[0045] 10 is a diagram showing the mask register in the first fault load process. In the first SIMD load instruction, the processor fetches memory data into the SIMD operation register (z1), as shown by reference symbol T16. The processor then executes the SIMD process. In the second SIMD load instruction, the processor reads a non-existent memory area, as shown by reference symbol T17. In a normal SIMD load instruction, if the memory does not actually exist, the processor generates a trap instruction to abnormally terminate the program as a response action in the event of an exception condition occurring.

[0046] However, in this method, the corresponding action is suppressed because the load instruction has the following functions: In one example, the generation of a trap instruction is suppressed, and the occurrence of an abnormal termination is suppressed. Then, the processor can process only valid elements in parallel at SIMD width.

[0047] The processor records (i.e., marks) access information about an access to a memory region in a mask register. The mask register is also referred to as a First Fault Register (ffr). In one example, if there is a memory region and the memory access to the element is successful (i.e., valid), the mask value for the element is set to 1 in the mask register ffr. The mask value may be referred to as a mask flag or a mask bit.

[0048] On the other hand, if the memory area does not exist and the memory access for the element is unsuccessful (invalid), 0 is set as the mask value for the element in the mask register ffr. For example, in the second load of this method, the memory area from data element #4 onwards is undefined data elements that do not exist, so 0 (failure) is set in the mask register ffr for data elements #4 onwards. The mask value in the mask register indicates whether the corresponding data element is a valid data element or not. In this example, when the mask value is 1, the corresponding data element is valid. Conversely, when the mask value is 0, the corresponding data element may be valid.

[0049] If not even one data element exists as a memory area, an exception condition is met and a trap must be generated to terminate the program abnormally, just like with a normal SIMD load instruction. If a trap is not generated to terminate the program abnormally, the execution behavior when using a normal SIMD load instruction that is not SIMD compatible will differ from the behavior when using scalar compatible instructions.

[0050] Then, if an exception condition occurs for the first data element #1, the processor will determine that an exception condition has indeed occurred and will trigger a response action, but will not trigger a response action when an exception condition occurs for another data element, as shown in Figure 10. Because the first SIMD element raises the exception condition, this is called first-fault processing.

[0051] 11 is a diagram showing an example of an operation in the first fault load process. In the SIMD add instruction, the mask register ffr obtained in the first fault load process is used. A mask value in which only valid data is masked (1 in FIG. 11) is set as the mask value of the masked SIMD operation instruction and the masked store instruction, and then the instruction is executed. Even in a loop with an unknown number of loop rotations, the instruction can be processed as one SIMD operation expansion loop.

[0052] In the first process indicated by reference symbol T18 in FIG. 11, the value of mask (p0) is valid for all data elements, so the mask value is 1. In the second process indicated by reference symbol T19 in FIG. 11, the value of mask (p0) is 1 up to the third element, and the value of mask (p0) is 0 for the fourth to eighth elements. Therefore, the processor performs a SIMD addition on SIMD register z1 and SIMD register z2 by a masked SIMD operation instruction, and stores the addition result in SIMD register z3. Then, the processor stores the data in SIMD register z3 in memory.

[0053] 12 is a diagram showing an example of a first fault load process in a SIMD process including an exit process in a loop. When an exit process is included, the process is terminated in the middle of the loop when the exit condition is satisfied. Since the loop is exited when the exit condition is satisfied, the SIMD process including an exit process in a loop is an example of a case where the number of loop rotations is unknown.

[0054] In the code T7 in Fig. 5, the number of loop rotations is fixed, but SIMD operation expansion is not possible and scalar expansion is performed. In Fig. 5, when comparing each SIMD element in an exit condition such as an if condition expression, there is no instruction that can determine at which SIMD element the condition is satisfied. When comparing each SIMD element in an exit condition such as an if condition expression, there is no instruction that can count the number of SIMD elements that are satisfied.

[0055] In order to solve the above two problems, the first fault load process executes a process as shown in the sample program of reference symbol T20 in FIG. 12. The process shown in FIG. 12 corresponds to both (1) a loop with an unknown number of rotations, and (2) a loop including an exit process within the loop. Therefore, hereinafter, an explanation will be given using the sample program shown in FIG. 12 as an example of solving the two problems. In this sample program, the processing unit of SIMD processing is 16 elements. One element unit is, for example, 4 bytes.

[0056] Reference symbol T21 in Fig. 12 indicates a specific memory configuration example. In reference symbol T21, memory data exists up to data element #19 (address #18). Data element #20 (address #19) and onwards are assumed to be a non-existent area (U).

[0057] The processor utilizes the mask value (i.e., the mask flag) described in Fig. 11. This allows the processor to truncate the fraction that cannot be processed in the last SIMD unit of the loop. This allows the processor to consolidate the loop into one loop that processes in SIMD units. Furthermore, the processor executes a SIMD fraction determination process.

[0058] In the SIMD fraction determination process, in order for the processor to escape from a loop using a SIMD instruction, the processor must be able to perform a condition determination for each element in a SIMD unit using a single SIMD instruction.

[0059] <First function> When multiple elements are compared in parallel, in order to perform SIMD processing on multiple elements, there is a possibility that a load in the SIMD fractional area may access an area where no memory data elements exist. Therefore, it is necessary to suppress the occurrence of the example condition that accompanies an access to an area where no memory data elements exist. This is the function of the first-fault load instruction described above.

[0060] <Second function> A function is provided to check that the exit condition is not satisfied in the final element of SIMD processing when SIMD processing is performed. This function determines whether to continue loop processing in units of SIMD elements. If the exit condition is not satisfied in the final SIMD element, the loop processing continues in the next SIMD unit. If the exit condition is satisfied in the final SIMD element, processing exits from the loop processing in units of SIMD elements.

[0061] <Third function> The processor detects at which element in the SIMD fraction the exit condition is satisfied. The processor then counts the number of elements until the exit condition is satisfied. During SIMD processing that is not a SIMD fraction, the number of elements processed is accumulated as the number of SIMD elements x the number of rotations. When the SIMD fraction is included, the number of elements processed until the condition is satisfied is as follows: Number of processed elements = Number of SIMD elements x number of rotations + Number of processed elements in SIMD fraction

[0062] Note that the present technology is not limited to the case where the first to third functions are realized by SIMD instructions. The first to third functions may be realized by other instructions. The first to third functions may be realized by a plurality of instructions. The first to third functions may be realized by microinstructions consisting of a plurality of instructions having the same functions, or may be realized in combination with other instructions and software.

[0063] When loading memory data, the data must be fetched into a register in units of the SIMD element length. However, the length of the data to be accessed is not limited to an integer multiple of the SIMD element length, so the final access in SIMD element units (SIMD fractional processing) may result in accessing a non-existent area.

[0064] Normally, a memory access exception occurs when an area that does not exist is accessed. Therefore, the processor executes a memory access to a memory area where no memory data element exists, using SIMD fractional operations including a first-fault load operation. Whether or not a memory area has a data element is determined by a mask value (i.e., a mask bit). A masked SIMD operation is executed on data elements limited by the mask value among multiple data elements, and a masked SIMD store instruction is used. This allows SIMD processing even for loop processing with an unknown number of rotations (number of data elements). Furthermore, SIMD operation can be expanded even when an exit operation is included in the loop.

[0065] FIG. 13 is a diagram showing an example of an intermediate program obtained by analyzing a source program and performing SIMD processing using the first fault load processing.

[0066] 13, a source program indicated by reference symbol T22 is converted into an intermediate language indicated by reference symbol T23. Since the parts indicated by reference symbols T22-1 and T23-1 are processes that can be conventionally expanded into SIMD arithmetic, detailed explanation of the expansion process will be omitted hereafter, and only the loop processing part will be explained.

[0067] The processor analyzes the source program T22 and performs SIMD processing to generate an intermediate program T23. In the case shown by reference symbol T21 in Figures 12 and 13, the number of SIMD elements is determined to be 16. Thereafter, the processor executes SIM processing on 16 elements at a time.

[0068] (1) The processor sets the number of SIMD elements to the SIMD width. In the case of code T21 in FIG.

[0069] (2) The processor loads memory data including 16 data elements from the memory to a SIMD register by a first-fault load instruction. The processor sets a first mask flag (m1) of the corresponding data element. The processor may set the first mask value to 1 if the area exists in the memory, and may set the first mask value to 0 if the area does not exist.

[0070] (3) In the process of determining whether to exit the loop, the processor calculates the number of processing elements by SIMD processing. The following process is performed for elements present in the memory by the SIMD load instruction, that is, comparatively valid elements that are elements whose corresponding first mask value of the first mask flag (m1) is 1.

[0071] (4) The data elements stored in the SIMD register are compared in parallel with the comparison value (0x00) corresponding to the element by the SIMD compare instruction. The SIMD comparison result is set as the second mask value in the second mask flag (m2) for each element.

[0072] If it is true, the exit condition is met and the second mask value is 1. If it is false, the exit condition is not met and the second mask value is 0.

[0073] (5) The processor calculates the position (x) where the exit condition is first satisfied (i.e., the second mask value is 1) for the second mask value obtained by the SIMD compare instruction, with the top of the data elements being the starting point 0. If no exit condition is satisfied, the position (x) may be a value equal to the number of first mask values ​​of the first mask flag (m1) that are 1 (the number of comparison valid elements).

[0074] (6) The processor executes the operation (a(i)=a(i)+10) to be executed when the comparison effective element calculated in (3) above is "1", that is, when the first mask value is 1. Therefore, the processor sets the first mask value obtained in (3) as the mask value of the operation. In the case of a SIMD fraction, the processor performs the operation up to the element immediately before the element where the condition is satisfied.

[0075] (7) The number of elements processed (S) is calculated using the following formula. This value is equal to the number of elements processed in scalar fashion for each data element. S = S + x (where the initial value of S is 0.)

[0076] (8) The processor executes a second determination process for exiting the loop (loop Taken / Nottaken). The processor calculates the second mask value of the second mask flag (m2) for an element present in memory by a SIMD load instruction, that is, the final element for which the corresponding first mask value of the first mask flag (m1) is 1. Based on the calculation result, the processor determines whether to continue the loop processing (Taken) or exit the loop processing (NotTaken).

[0077] If the second mask value of the second mask flag for the final element whose first mask value is 1 is 1, the loop exit condition is satisfied (i.e., the comparison condition is satisfied), so the processor exits the loop and executes subsequent processing of the loop. On the other hand, if the second mask value is 0, the loop exit condition is not satisfied for any data element, so the processor executes the processing of (2) above, i.e., processing of the top of the loop.

[0078] Fig. 14 is a diagram showing object expansion and an excerpt of a main instruction in the first fault load process. Fig. 15 is a diagram showing an example of the first fault load process. Fig. 16 is an example of the process subsequent to Fig. 15. In reference numeral T25 in Fig. 15 and reference numeral T26 in Fig. 16, only the part related to the loop control is illustrated. As for the parts such as reference numerals T22-1 and T23-1 in Fig. 13, the illustration is omitted because the process in the loop is a process that can be expanded by SIMD arithmetic conventionally.

[0079] Fig. 15 shows the process for the first rotation. The instructions shown in Fig. 14 will be described with reference to Fig. 15. In the code shown by reference T24 in Fig. 14, the part indicated by reference T24-1 corresponds to the first fault load process.

[0080] (1) Setffr is an instruction that sets the initial values ​​of the mask values ​​of each element in ffr (first fault register) to all 1.

[0081] (2) Ldff1w is an instruction to execute the first-fault load instruction. Specifically, memory data is fetched into the SIMD operation register (z1). This first SIMD load instruction loads all data in the existing data area. Therefore, all elements are successfully loaded, and the mask register (p7) is set to all "1".

[0082] (3) Rdffr is an instruction to store the mask value of p7 in p0 for the subsequent mask specification of Cmpeq.

[0083] (4) Cmpeq is an instruction that uses a SIMD compare instruction to compare each of 16 data elements to see if they match the value (0x00). The comparison targets are all data elements because the first mask values ​​are all 1, as specified by p0. The SIMD comparison result is stored in p1. If the comparison condition is satisfied, the exit condition is satisfied, and the second mask value is 1. On the other hand, if the comparison condition is not satisfied, the exit condition is not satisfied, and the second mask value is 0. The value of the second mask value is stored in p1 as the comparison result.

[0084] (5) In Brkbs, specifically, it may be an instruction to determine whether the exit condition is not satisfied for a valid SIMD final element, i.e., whether the second mask value is a value (e.g., 0) indicating that the condition is not satisfied. If the first mask flags are all successful by the first fault load instruction, i.e., for a data element whose first mask value is 1, the second mask values ​​of the second mask flags whose exit condition is not satisfied are all 0, it is not a SIMD fraction.

[0085] (6) Incp is an instruction to calculate the number of processed elements and store the calculation result in register x2. In FIG. 15, since it is not a SIMD fraction, the number of processed elements is calculated as number of SIMD elements (16) × number of loop rotations (1 time) = 16. Therefore, 16 is stored in register x2.

[0086] (7) In the first SIMD instruction, as explained in (5) above, the operation to be executed is not a SIMD fraction operation. Therefore, the operation to be executed (a(i)=a(i)+10) is executed in SIMD units for all SIMD elements. In other words, the processor executes a(1:16)=a(1:16)+10 using a SIMD add instruction.

[0087] (8)b.Last loop is an instruction that judges whether the process should be continued (taken) because the exit condition is not satisfied, or not taken because the exit condition is satisfied. In Fig. 15, the output result (p1) by Compeq (comparison process), i.e., the second mask value, is all 0, so the exit condition is not satisfied. Therefore, it is judged that the process should be continued (taken).

[0088] Fig. 16 shows the process for the second rotation. The commands shown in Fig. 14 will be explained with reference to Fig. 16.

[0089] (1) Setffr sets the initial values ​​of the mask values ​​of all elements in ffr to 1.

[0090] (2) Ldff1w is an instruction to execute a first-fault load instruction. Memory data is fetched into the SIMD operation register (z1). In this second SIMD load instruction, the accessed elements #4 (fourth from the right in FIG. 16) and onwards do not exist in memory. Therefore, the first mask value in bits #0, 1, 2 corresponding to data elements #0, 1, 2 (a, 0, c) of the mask register (p7) is set to 1, and the first mask value in bits #3 and onwards is set to 0.

[0091] (3) Rdffr is the same as in FIG.

[0092] (4) Cmpeq is an instruction that uses a SIMD compare instruction to compare each of 16 data elements to see if they match the value (0x00). The objects of comparison are data elements #0, 1, 2 (a, 0, c) with the first mask value specified as 1 in p0. The SIMD comparison result is stored in p1. If the comparison condition is met, the exit condition is established and the second mask value becomes 1.

[0093] (5) In accordance with the Brkbs instruction, the element position in the SIMD fraction of the data element for which the first mask value is 1 and for which the exit condition is satisfied, i.e., the data element for which the second mask value is 1, is calculated. If the first element position in the SIMD fraction is 0, then in FIG. 16, the exit condition is satisfied in the first data element. In p1, the second mask value of the second from the right (the first data element) is 1. From the second data element onwards, up to the third data element, which is the final element, the second mask value is 0. As a result, in FIG. 16, the exit condition is satisfied in the middle of the SIMD element.

[0094] (6) From (5) above, it is determined that the second SIMD instruction is a SIMD fraction. The processor also performs operations up to the data element (data element #0) immediately before the data element (data element #1) for which the exit condition was met. In the table of FIG. 16, since the exit condition is met in the second data element from the right (data element #1), the position of the second mask value of p1 is shifted so that operations up to the first data element from the right (data element #0) immediately before that data element are performed. The processor then performs SIMD addition processing only for data element #0. That is, in FIG. 16, only one addition processing of a(17) is performed.

[0095] (7)Incp is an instruction to calculate the number of processed elements and store the calculation result in register x2. In Fig. 16, the number of processed elements is calculated as 17 by adding 1 to the number of SIMD elements (16) x number of loop rotations (1 time) = 16 as the element executed in (5) above. The calculation result, 17, is stored in register x2.

[0096] (8)b.Last loop is an instruction to judge whether the process is taken because the exit condition is not satisfied, or not taken because the exit condition is satisfied. In Fig. 16, the output result (p1) by Compeq (comparison process), i.e., the second mask value, contains 1, so the exit condition is satisfied. Therefore, the process is judged to be not taken.

[0097] In the above description of the first fault load process, an example of direct instruction expansion was shown. However, the process is not limited to the direct instruction expansion. The processor may expand the source code into intermediate text and then expand it into an object. The process can be executed in the compiler processing phase. The process may be executed either during the process of replacing with SIMD instructions or during the process of directly outputting. In the above description, an example was presented in which the SIMD element length was fixed, but it may be variable. In this example, a case in which there is one loop hierarchy was shown, but the same can be done in the case in which the loop structure has a multiple hierarchical structure.

[0098] The process using the first-fault load instruction described with reference to Figures 9 to 16 has the following problems. The first-fault load instruction (i.e., ldff) may have a longer instruction latency and may not improve performance compared to the conventional load instructions shown in Figures 3 to 8. Instruction latency is the time it takes to execute one instruction.

[0099] The first-fault load instruction is a special instruction that applies SIMD to a memory area that does not exist, so it is used infrequently. Therefore, the first-fault load instruction has few types, such as limitations on addressing, and may restrict the compiler's machine code expansion and optimization, hindering performance improvement.

[0100] Furthermore, in a processor that does not support fast-fault load processing, it is difficult to apply SIMD to the exit loop of the fast-fault load instruction.

[0101] Therefore, there are problems in achieving high speed by using SIMD processing using the first fault load instruction explained in Fig. 9 to Fig. 16. A code conversion method for solving these problems will be explained.

[0102] [B] Embodiment [B-1] Hardware configuration example 17 is a block diagram showing an example of a hardware (HW) configuration of a computer that realizes the functions of the compiling device 10 according to the embodiment. The compiling device 10 is an example of a computer.

[0103] As shown in FIG. 17, the compiling device 10 includes a processor 101, a memory unit 102, a display control unit 103, a storage device 104, an input IF 105, an external recording medium processing unit 106, and a communication IF 107.

[0104] The memory unit 102 is an example of a storage unit, and is illustratively a Read Only Memory (ROM) and a Random Access Memory (RAM). A program such as a Basic Input / Output System (BIOS) may be written in the ROM of the memory unit 102. The software program in the memory unit 102 may be appropriately read and executed by the processor 101. The RAM of the memory unit 102 may be used as a temporary storage memory or a working memory. The software program may be a compiled program.

[0105] The display control unit 103 is connected to a display device 1030 and controls the display device 1030. The display device 1030 is a liquid crystal display, an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), an electronic paper display, or the like, and displays various information to an operator, etc. The display device 1030 may be combined with an input device, for example, a touch panel.

[0106] The storage device 104 is a storage device with high IO performance, and may be, for example, a dynamic random access memory (DRAM), an SSD, a storage class memory (SCM), or an HDD.

[0107] The input IF 105 may be connected to input devices such as a mouse 1051 and a keyboard 1052, and may control the input devices such as the mouse 1051 and the keyboard 1052. The mouse 1051 and the keyboard 1052 are examples of input devices, and an operator performs various input operations via these input devices.

[0108] The external recording medium processing unit 106 is configured so that the recording medium 1060 can be attached. The external recording medium processing unit 106 is configured so that, when the recording medium 1060 is attached, the information recorded on the recording medium 1060 can be read. In this example, the recording medium 1060 is portable. For example, the recording medium 1060 is a flexible disk, an optical disk, a magnetic disk, a magneto-optical disk, a semiconductor memory, or the like.

[0109] The communication IF 107 is an interface for enabling communication with an external device.

[0110] The processor 101 is an example of a computer, and is a processing device that performs various controls and calculations. The processor 101 realizes various functions by executing an Operating System (OS) and a compilation program loaded into the memory unit 102. The processor 101 may be a CPU, a multiprocessor including multiple CPUs, a multicore processor having multiple CPU cores, or a configuration having multiple multicore processors.

[0111] The device for controlling the overall operation of the compiling device 10 is not limited to a CPU, and may be, for example, any one of a GPU, an MPU, a DSP, an ASIC, a PLD, and an FPGA. The device for controlling the overall operation of the compiling device 10 may be a combination of two or more of a CPU, a GPU, an MPU, a DSP, an ASIC, a PLD, and an FPGA. Note that GPU is an abbreviation for Graphics Processing Unit, MPU is an abbreviation for Micro Processing Unit, DSP is an abbreviation for Digital Signal Processor, and ASIC is an abbreviation for Application Specific Integrated Circuit. Also, PLD is an abbreviation for Programmable Logic Device, and FPGA is an abbreviation for Field Programmable Gate Array.

[0112] The above-described HW configuration of the compiling device 10 is an example. Therefore, the HW in the compiling device 10 may be increased or decreased (for example, adding or deleting any block), divided, integrated in any combination, or the bus may be added or deleted, as appropriate.

[0113] [B-2] Functional configuration example 18 is a block diagram showing an example of a functional configuration of the compiling device 10 according to the first embodiment. The compiling device 10 is an information processing device and functions as a compiler. The compiling device 10 is an example of a code conversion device.

[0114] A compiling device 10 reads and analyzes a source program 2 (source code) written in a programming language, and converts it into a computer-executable machine language program 4. Code conversion is called compiling.

[0115] In response to a SIMD load instruction, the compiling device 10 performs object expansion so as to read memory data including a plurality of data elements from a storage unit into at least one SIMD register with a SIMD width. The compiling device 10 performs object expansion so as to store a result obtained by an operation with the SIMD width in memory.

[0116] The compiling device 10 includes an analysis unit 210, an intermediate code conversion unit 220, and a code generation unit 230.

[0117] The analysis unit 210 analyzes a source program 2 (source code). The intermediate code conversion unit 220 converts the source program into intermediate code. The code generation unit 230 generates object code based on the intermediate code. The object code may be a machine language program 4.

[0118] The code generation unit 230 includes an expansion unit 231 and an output unit 232. The expansion unit 231 executes object expansion. In particular, the expansion unit 231 executes object expansion of a SIMD instruction. A SIMD instruction is an instruction that executes operations on multiple data in parallel by the same computing unit in order to improve computing performance. The output unit 232 outputs the code obtained by the object expansion.

[0119] Fig. 19 is a block diagram showing an example of a functional configuration of the analysis unit 210 shown in Fig. 18. The analysis unit 210 includes a loop structure analysis unit 211, an array analysis unit 212, a dependency analysis unit 213, a loop structure management unit 214, and a variable data storage unit 215.

[0120] The loop structure management unit 214 has a DO management table 216. The variable data storage unit 215 has an array management table 217.

[0121] The loop structure analysis unit 211 analyzes the structure of an operational loop included in the source program 2. The loop structure management unit 214 may store the analysis result by the loop structure analysis unit 211 as a DO management table 216.

[0122] In one example, the loop structure analysis unit 211 analyzes whether the source program 2 can be expanded into SIMD arithmetic. The loop structure analysis unit 211 determines whether an escape statement, i.e., a construct indicating an escape condition, is present in the middle of the arithmetic loop.

[0123] The loop structure analysis unit 211 also judges whether the source program falls under a reason why it cannot be converted to SIMD due to an escape statement indicating an escape condition. Furthermore, the loop structure analysis unit 211 judges whether the source program falls under a reason why it cannot be converted to SIMD due to processing of an arithmetic loop excluding an escape condition.

[0124] 20 is a diagram showing classification of loop processes. In one example, the loop structure analysis unit 211 executes classification of operation loops as shown in FIG.

[0125] 20, loop #1 is a case where a syntax indicating an escape condition is not included in the middle of the computation loop. Also, the processing of the loop in the computation loop can be expanded to SIMD computation by using existing techniques.

[0126] The loop #2 shown by the code T28 in FIG. 20 is a case where a syntax indicating an escape condition exists in the middle of the computation loop, as shown by the code T28-1. In the code T28, there is no reason why SIMD conversion cannot be performed due to the escape statement indicating the escape condition. In addition, in the code T28, there is no reason why SIMD conversion cannot be performed due to the processing of the computation loop excluding the escape condition. The escape condition does not include a SIMD comparison involving different elements of the same array a. This is an example of a case where there is no reason why SIMD conversion cannot be performed due to the escape statement indicating the escape condition. In addition, the processing of the computation loop excluding the escape condition does not include a SIMD computation process including an operation between different elements of the same array a. This is an example of a case where there is no reason why SIMD conversion cannot be performed due to the processing of the computation loop excluding the escape condition.

[0127] Loop #3 shown by code T29 in Fig. 20 includes array a(i) = a(i) + a(i + 1) as the processing of the arithmetic loop excluding the exit condition, as shown by code T29-1. The processing of code T29-1 is an operation between different elements of the same array a. In this case, as shown in the explanation of code T29-2, even if there is no if exit statement, which is an exit condition statement, it is difficult to SIMDize the processing of the arithmetic loop using existing SIMD technology.

[0128] Loop #4 indicated by reference symbol T30 in FIG. 20 includes "if (b(a(i+1)).ne.a(i)) exit" as an exit statement T30-1 indicating an exit condition. The exit condition indicated by reference symbol T30-1 includes a comparison between different elements of the same array a. In this case, as indicated in the description of reference symbol T30-2, it is difficult to convert the conditional expression indicating the exit condition into SIMD using existing SIMD conversion technology.

[0129] Fig. 21 is a diagram showing an example of the DO management table 216. The loop structure management unit 214 may manage the analysis results by the loop structure analysis unit 211 as the DO management table 216. The DO management table 216 shown in Fig. 21 describes information about the loops #1 to #4 shown in Fig. 20.

[0130] The DO management table 216 has an mid-escape statement existence flag. The mid-escape statement existence flag is information indicating whether or not an escape statement, i.e., a syntax indicating an escape condition, exists in the middle of the computation loop. When an escape condition exists in the middle of the computation loop, the processor 101 sets the value of the mid-escape statement existence flag to a first value, and when an escape condition does not exist, the processor 101 sets the value of the mid-escape statement existence flag to a second value different from the first value. In the case shown in FIG. 21, the first value is 1 and the second value is 0.

[0131] As described in FIG. 20, the value of the mid-escape statement presence flag for loop #1 is 0 (i.e., the second value), and the value of the mid-escape statement presence flag for loops #2 to #4 is 1 (i.e., the first value).

[0132] The DO management table 216 has a first SIMD expansion availability flag indicating whether SIMD expansion is possible due to the midway exit condition expression. If the content of the midway exit condition expression indicates that SIMD arithmetic expansion is possible, the value of the first SIMD expansion availability flag is set to a first value, and if the content of the midway exit condition expression indicates that SIMD arithmetic expansion is not possible, the value of the first SIMD expansion availability flag is set to a second value.

[0133] As described in FIG. 20, in loops #2 and #3, the value of the first SIMD deployment availability flag is 1 (i.e., the first value), and in loop #4, the value of the first SIMD deployment availability flag is 0 (i.e., the second value).

[0134] The DO management table 216 has a second SIMD expansion availability flag indicating whether SIMD expansion is possible due to the processing of the computation loop excluding the exit condition expression. If the processing content of the computation loop is SIMD expansion available, the value of the second SIMD expansion availability flag is set to a first value, and if the processing content of the computation loop is not SIMD expansion available, the value of the second SIMD expansion availability flag is set to a second value.

[0135] As described in FIG. 20, in loops #2 and #4, the value of the second SIMD deployment availability flag is 1 (i.e., the first value), and in loop #3, the value of the second SIMD deployment availability flag is 0 (i.e., the second value).

[0136] The DO management table 216 may have a loop SIMD flag indicating whether or not the loop can be expanded into SIMD operations. If the loop can be expanded into SIMD operations, the value of the loop SIMD flag may be set to a first value (1), and if the loop cannot be expanded into SIMD operations, the value of the loop SIMD flag may be set to a second value (0).

[0137] 21, when the mid-execution escape statement presence flag is the second value (0), the loop SIMD flag is the first value (1). When the mid-execution escape statement presence flag is the first value (1), when both the first and second SIMD deployment availability flags are the first value (1), the loop SIMD flag is the first value (1). When at least one of the first and second SIMD deployment availability flags is the second value (0), the loop SIMD flag is the second value (0).

[0138] The DO management table 216 may include information such as control variables, initial values, final values, and increment values ​​of the control variables, and address information of array syntax information, in addition to the values ​​of the above flags.

[0139] 19, an array analysis unit 212 analyzes a data area of ​​an array in memory data. A dependency analysis unit 213 analyzes the relationship between the satisfaction of an escape condition, a processing unit in a SIMD register, and a data area of ​​an array in memory data.

[0140] In one example, the dependency analysis unit 213 has a second function in the process using the first fault load process described in FIG. 9 to FIG. 16. That is, the dependency analysis unit 213 checks whether or not an exit condition is satisfied in the SIMD-processed final element when SIMD processing is performed with the SIMD width. This function is a function for determining whether or not to continue loop processing with the SIMD width. When SIMD processing is performed with the SIMD width, if the exit condition is not satisfied in the SIMD-processed final element, all of the multiple data elements included in the SIMD width are SIMD-processed. Therefore, the SIMD-processed data is not a SIMD fraction. On the other hand, when SIMD processing is performed with the SIMD width, if the exit condition is satisfied in the SIMD-processed final element, the SIMD-processed data may be a SIMD fraction in which a part is SIMD-processed and the other part is not SIMD-processed.

[0141] The dependency analysis unit 213 has a third function in the process using the first fault load process described in FIG. 9 to FIG. 16. The dependency analysis unit 213 detects at which element in the SIMD fraction the exit condition is satisfied. Then, the dependency analysis unit 213 counts the number of elements processed until the exit condition is satisfied. During SIMD processing that is not a SIMD fraction, the dependency analysis unit 213 accumulates the number of elements processed as the number of SIMD elements x the number of rotations. When the SIMD fraction is included, the number of elements processed until the condition is satisfied is as follows: Number of processed elements = Number of SIMD elements x number of rotations + Number of processed elements in SIMD fraction

[0142] In addition, the present technology is not limited to the case where the second and third functions are realized by SIMD instructions. The second and third functions may be realized by other instructions. The second and third functions may be realized by multiple instructions. The second and third functions may be realized by microinstructions consisting of multiple instructions having the same functions, or may be realized in combination with other instructions and software.

[0143] The variable data storage unit 215 stores the analysis results from the sequence analysis unit 212 and the dependency relationship analysis unit 213 as a sequence management table 217 .

[0144] Fig. 22 is a block diagram showing an example of a functional configuration of the code generation unit 230 shown in Fig. 18. In the code generation unit 230, an expansion unit 231 executes object expansion based on the analysis result by the analysis unit 210.

[0145] The expansion unit 231 may include a SIMD instruction expansion unit 234, a scalar instruction expansion unit 235, and an exit loop SIMD expansion unit 236. In one example, the SIMD instruction expansion unit 234 expands the SIMD instruction into an object when the loop SIMD flag in the DO management table 216 of the loop structure management unit 214 is a first value (for example, 1).

[0146] The scalar instruction expansion unit 235 executes scalar expansion when the loop SIMD flag in the DO management table 216 of the loop structure management unit 214 is a second value (for example, 0). As described in FIG. 5, scalar expansion is object expansion such that one element of array A and one element of array B are individually operated on.

[0147] The exit loop SIMD expansion unit 236 secures a data area of ​​at least one array to which an end element that satisfies the exit condition of the loop processing belongs, with a width equal to or larger than the SIMD width, in the memory data. The exit loop SIMD expansion unit 236 performs object expansion so that the memory data including the end element that satisfies the exit condition is processed with the SIMD width. The exit loop SIMD expansion unit 236 may use the analysis results by the array analysis unit 212 and the dependency analysis unit 213. The SIMD fraction is processed using the second and third functions of the dependency analysis unit 213.

[0148] 23 is a diagram showing a first example of the compilation process in this embodiment. Code T31 is a source program portion that defines array a. Code T32 is a source program portion that includes an arithmetic loop with an exit condition.

[0149] 23, the compiling device 10 executes a process of accepting option settings for compilation as indicated by reference symbol T31-1. The option settings include a pre-setting as to whether or not to expand and secure the data area to the SIMD width when the compiling device 10 compiles. The process of reserving the data area of ​​the array to be equal to or larger than the SIMD width is executed based on the option settings.

[0150] Reference symbol T33 indicates a process in which the compiling device 10 executing the compiled program secures and expands the data area so that the size of array a becomes the SIMD width. In the source program of reference symbol T31, the size of array a is defined as 48 bytes, that is, a data area of ​​384 bits, since the number of 4-byte data elements is 12. In contrast, as shown in reference symbol T33, after compilation, the size of array a is defined as 64 bytes, that is, a data area of ​​512 bits, since the number of 4-byte data elements is 16. In other words, after compilation, the data area of ​​array a is secured to be equal to or larger than the SIMD width. The data area of ​​the SIMD width is called a SIMD boundary.

[0151] As described in the description of reference symbol T34, the compiling device 10 secures and expands the data area so that the size of array a becomes 512-bit SIMD width (i.e., SIMD width, SIMD byte boundary). However, as described later, when loop unrolling is performed, a data area larger than the area obtained by multiplying the SIMD width by the number of unrolls may be secured. The secured and expanded data area may be called an overrun area or a dummy area.

[0152] As described in the description of reference symbol T35, the compiling device 10 uses an existing SIMD load instruction that does not include a first-fault load process, on the assumption that the data area of ​​the memory data of array a has been expanded to the SIMD width.

[0153] 24 is a diagram showing a second example of the compilation process in this embodiment. Code T31 is a source program portion that defines array a. Code T36 is a source program portion that includes an arithmetic loop with an exit condition.

[0154] In Fig. 24, the source program indicated by reference symbol T36 includes a user instruction indicated by reference symbol T36-1. As described in the description of reference symbol T37 in Fig. 24, the user describes the user instruction in the source program using OCL (Object Constraint Language). In the user instruction indicated by reference symbol T36-1, the size of array a is secured such that the data area of ​​array a after compilation is equal to or larger than the SIMD width.

[0155] As described in the description of reference symbol T38, the compiling device 10 secures and expands the data area so that the size of array a becomes 512-bit SIMD width (i.e., SIMD width, SIMD byte boundary) based on an instruction in the user's source program. However, as described later, if loop unrolling is performed, a data area larger than the area obtained by multiplying the SIMD width by the number of unrolls may be secured.

[0156] Fig. 25 is a diagram showing an example of instruction expansion of a Do while statement in the compilation process in this embodiment. Compared with the instruction expansion in Fig. 14 when the first fault load process is used, in the code shown by reference symbol T39 in Fig. 25, the part T24-1 related to the first fault load process in Fig. 14 is omitted. On the other hand, the code shown in Fig. 25 includes a SIMD load instruction that does not include the first fault load process, as shown by reference symbol T39-1.

[0157] The compilation program executed by the compiling device 10 in this embodiment, that is, the outline of the compiler, will be described.

[0158] (1) The processor 101 determines the number of SIMD elements according to the SIMD width, which is the data length that can be processed in parallel at one time. In the case of FIGS. 23 and 24, the processor 101 determines the number of SIMD elements to be 16.

[0159] (2) The processor 101 reads memory data of 16 data elements from memory using a normal SIMD load name instruction (ld) that is not a first-fault load instruction. In the method using the first-fault load instruction shown in FIG. 9 to FIG. 16, since there may be cases where the memory area does not exist, the result of whether the memory access was successful or not is reflected in ffr (first fault register). However, in this embodiment, it is assumed that all data areas in the memory exist by expanding and reserving the data area. Therefore, in this embodiment, the use of the first-fault load instruction can be omitted. Also, in the first mask flag (m1) used in the calculation, the first mask value is specified as 1 for all data elements.

[0160] (3) The processor 101 executes a first determination process for a loop exit by SIMD processing. The first determination process includes a calculation process for the number of processed data elements. The processor 101 executes the following process for elements present in the memory by a SIMD load instruction, that is, elements (comparatively valid elements) whose first mask value of the mask flag (m1) is 1.

[0161] (4) For each data element stored in the SIMD register, a SIMD compare instruction is used to compare whether the data element matches the comparison value (0x00) corresponding to the element. The SIMD comparison result is stored as the second mask value of the second mask flag (m2) for each data element. If the comparison condition is satisfied, the exit condition is satisfied and the second mask value is set to true (e.g., 1). If the comparison condition is not satisfied, the exit condition is not satisfied and the second mask value is set to false (e.g., 0).

[0162] (5) The processor 101 calculates the position (x) where the exit condition is first satisfied (i.e., the second mask value is 1) for the second mask value obtained by the SIMD compare instruction, with the head of the data elements being the starting point 0. The processor 101 may mark the position (x). If no exit condition is satisfied, the position (x) becomes a value equal to the number of first mask values ​​of the first mask flag (m1) that are 1 (the number of comparison valid elements).

[0163] (6) The processor 101 calculates the position (x) where the exit condition is first satisfied (i.e., the second mask value is 1) for the second mask value obtained by the SIMD compare instruction, with the head of the data element as the starting point 0. If no exit condition is satisfied, the position (x) may be a value equal to the number of first mask values ​​of the first mask flag (m1) that are 1 (the number of comparison valid elements).

[0164] (7) The processor 101 executes the operation (a(i)=a(i)+10) to be executed when the comparison effective element calculated in (3) above is "1", that is, when the first mask value is 1. Therefore, the processor 101 sets the first mask value obtained in (3) as the mask value of the operation. In the case of a SIMD fraction, the processor 101 performs the operation up to the element immediately before the element where the condition is satisfied.

[0165] (8) The number of elements processed (S) is calculated using the following formula. This value is equal to the number of elements processed scalarly for each data element. S = S + x (where the initial value of S is 0.)

[0166] (9) The processor 101 executes a second determination process for exiting the loop (loop Taken / Nottaken). The SIMD load instruction calculates a second mask value of the second mask flag (m2) for an element present in memory, that is, a final element for which the corresponding first mask value of the first mask flag (m1) is 1. The final element exists as a memory area and is a data element at a high address that has been loaded into a SIMD register. The processor 101 determines whether to continue the loop processing (Taken) or exit the loop processing (NotTaken) based on the calculation result of the second mask value for the final element.

[0167] If the second mask value of the second mask flag for the final element whose first mask value is 1 is 1, the loop exit condition is satisfied (i.e., the comparison condition is satisfied), so the processor 101 exits the loop and executes subsequent processing of the loop. On the other hand, if the second mask value is 0, the loop exit condition is not satisfied for any data element, so the processor 101 executes the processing of (2) above, i.e., processing of the top of the loop.

[0168] The compilation program executed by the compiling device 10 in this embodiment, i.e., the compiler, reserves a data area of ​​at least one array to which an end element that satisfies an exit condition of a loop belongs, the data area being equal to or larger than the SIMD width in memory data, and uses a general SIMD load instruction instead of a first-fault load instruction.

[0169] Fig. 26 is a diagram showing an example of control in the compilation process in this embodiment. Fig. 27 is an example of control following Fig. 26. At reference numeral T40 in Fig. 26 and reference numeral T41 in Fig. 27, only the portion related to loop control is illustrated.

[0170] Fig. 26 shows the process for the first rotation. The commands shown in Fig. 25 will be explained with reference to Fig. 26.

[0171] (1) ld1w is a normal SIMD load instruction that is not a first-fault load instruction. Specifically, memory data is fetched for SIMD operation (z1). The processor 101 of the compiling device 10 secures a data area of ​​at least one array to which an end element that satisfies an escape condition of a loop process belongs, in the memory data, with a width equal to or larger than the SIMD width. This assumes that a data area exists for all of the data elements to be loaded. Therefore, since the loading of all data elements is successful, the mask values ​​of each element in the first mask register (p0) are all set to 1. The processing related to ffr (first-fault register) in the first-fault load instruction is also omitted. The processing of (1) is different from the processing shown in FIG. 15 and FIG. 16.

[0172] (2) Cmpeq is an instruction that uses a SIMD compare instruction to compare each of 16 data elements to see if they match the value (0x00). The comparison targets are all data elements because the first mask values ​​are all 1, as specified in p0. The SIMD comparison result is stored in p1. If the comparison condition is satisfied, the exit condition is satisfied, and the second mask value is 1. On the other hand, if the comparison condition is not satisfied, the exit condition is not satisfied, and the second mask value is 0. The value of the second mask value is stored in p1 as the comparison result.

[0173] (3) In Brkbs, specifically, an instruction may be provided to determine whether the exit condition is not satisfied for a valid SIMD final element, i.e., whether the second mask value is a value indicating that the condition is not satisfied (false, for example, 0). When all first mask flags are successful, i.e., when all second mask values ​​of second mask flags for which the exit condition is not satisfied for data elements for which the first mask value is 1, are 0, the processor 101 sets a flag to continue the loop processing. In FIG. 26, the condition is not satisfied in the middle of the SIMD element.

[0174] (4) Incp is an instruction that calculates the number of processed elements and stores the calculation result in register x2. In FIG. 26, since it is not a SIMD fraction, the number of processed elements is calculated as number of SIMD elements (16) x number of loop rotations (1 time) = 16. Therefore, 16 is stored in register x2.

[0175] (5) As explained in (3) above, in the first SIMD instruction, the loaded memory data does not include a SIMD fraction. Therefore, in Dup add st1w, the operation to be executed (a(i)=a(i)+10) is executed in SIMD units for all SIMD elements. That is, the processor 101 executes a(1:16)=a(1:16)+10 by the SIMD addition instruction.

[0176] (6)b.Last loop is an instruction that judges whether the process should be continued (taken) because the escape condition is not satisfied, or not taken because the escape condition is satisfied. In Fig. 26, the output result (p1) by Compeq (comparison process), i.e., the second mask value, is all 0, so the escape condition is not satisfied. Therefore, it is judged that the process should be continued (taken).

[0177] Fig. 27 shows the process for the second rotation. The commands shown in Fig. 25 will be explained with reference to Fig. 27.

[0178] (1) ld1w is a SIMD load instruction (ld) that fetches memory data for SIMD operation (z1). ld1w is a normal SIMD load instruction that is not a first-fault load instruction. In the memory data, a data area of ​​at least one array to which an end element that satisfies the condition for escaping the loop processing belongs is secured to be equal to or larger than the SIMD width. This makes it possible to consider that a data area exists for all the data elements to be loaded. In FIG. 27, if the leading element (the rightmost column in FIG. 27) is #0, data elements #3 to #15 correspond to an area (U) in which no data exists in the array T21 in FIG. 12 and FIG. 13. In this case, the data element corresponding to the area in which no memory data exists may be any value, not a true value. FIG. 27 shows a case in which the data elements #3 to #6 and #8 to #15 are 0x0, and the data element #7 is x. However, the value of the data element when it is considered that a data area exists for an area in which no data exists is not limited to the case in FIG. 27.

[0179] (2) Cmpeq is an instruction that uses a SIMD compare instruction to compare whether each of 16 data elements matches the value (0x00). The comparison targets are all data elements because the first mask values ​​are all 1 as specified by p0. The SIMD comparison result is stored in p1. If the comparison condition is met, the exit condition is met and the second mask value is 1. On the other hand, if the comparison condition is not met, the exit condition is not met and the second mask value is 0. The value of the second mask value is stored in p1 as the comparison result. In the case of Figure 27, data elements #1, #3 to #6, and #8 to #15 match the comparison targets. Therefore, the second mask value for these is 1.

[0180] (3) In Brkbs, the position where the second mask value corresponding to the comparison result for each data element obtained by the SIMD comparison first becomes 1, that is, the position of the data element where the escape condition is first satisfied is detected. For example, the data position of the data element where the escape condition is first satisfied when the head of the data elements of the SIMD-compared array is set as the starting point 0 is detected. Based on the detection result of the data position of the data element in the array, mask information for the mask used in the operation is set. In one example, the processor 101 may set the operation mask value of the data element where the escape condition is first satisfied to a first value (e.g., 1), and set the data elements thereafter to 0 to indicate invalidity. Also, the processor 101 may set the operation mask value of the data element immediately before the data element where the escape condition is first satisfied to a first value (e.g., 1), and set the operation mask values ​​of the data elements thereafter to a second value (e.g., 0). In FIG. 27, as shown by the reference symbol T41-1, when the head (right end) of the data elements is set to the 0th data element, the escape condition is first satisfied in the first data element. Then, as shown in T41-2, the mask value of the 0th data element, which is the data element immediately preceding the 1st data element for which the exit condition was first satisfied, is set to a first value (1) (see p1a in FIG. 27). On the other hand, the mask values ​​of the subsequent data elements are set to a second value (0). In the case shown in FIG. 27, the exit condition is satisfied midway (the first) among multiple data elements to be SIMD processed. Therefore, FIG. 27 corresponds to the case of a SIMD fraction.

[0181] (4) In the second SIMD instruction of Dup add st1w, if element #0 is the first element, this corresponds to the case where the exit condition is satisfied in element #1. Therefore, for element #0 (a(17)), a SIMD addition operation is performed. In one example, based on the second mask value obtained by the comparison operation, a SIMD addition operation is performed up to the data element immediately before the data element whose second mask value first became the first value, and the addition operation result is stored in memory.

[0182] (5) Incp is an instruction to calculate the number of processed elements and store the calculation result in register x2. In Fig. 27, the number of processed elements is calculated as 17 by adding 1 to the number of SIMD elements (16) x number of loop rotations (1 time) = 16 as the element executed in (4) above. The calculation result, 17, is stored in register x2.

[0183] (6)b.Last loop is an instruction that judges whether the loop is taken because the escape condition is not satisfied, or not taken because the escape condition is satisfied. In Fig. 27, the output result (p1) by Compeq (comparison process), i.e., the second mask value, contains 1, so the escape condition is satisfied. Therefore, it is judged that the loop process is not taken.

[0184] The above explanation of the compilation process is not limited to the case of direct instruction expansion. The processor 101 may expand the source code into intermediate text and then expand it into objects. The process can be executed in the compiler processing phase. The process may be executed either during the process of replacing with SIMD instructions or during the process of directly outputting. In the above explanation, an example was presented in which the SIMD element length is fixed, but it may be variable. In this example, the case where there is one loop hierarchy is shown, but the case where the loop structure has a multiple hierarchical structure can also be handled in the same way.

[0185] Fig. 28 is a diagram showing a third example of the compilation process in this embodiment. The part indicated by reference symbol T42 in Fig. 28 is similar to the first and second examples shown in Fig. 23 and Fig. 24. In the source code indicated by reference symbol T43 in Fig. 28, loop unrolling is instructed.

[0186] Reference symbol T44 indicates a process in which the compiling device 10 executing the compiled program expands and secures a data area so that the size of array a becomes the loop unroll count times the SIMD width. In FIG. 28, in the process of securing the data area of ​​array a to be equal to or larger than the SIMD width, the compiling device 10 secures a data area equal to or larger than the area obtained by multiplying the SIMD width by the loop unroll count. As described in the description of reference symbol T44-1, in this example, the SIMD width (i.e., the SIMD width) is 64 bytes, and the loop unroll count is 3. Therefore, the compiling device 10 secures an extra overrun area (i.e., a dummy area) that is a 192-byte boundary as a memory area. When the size of one data element is 8 bytes, a memory area for 24 elements is secured.

[0187] As shown in the explanatory text T45-1, in the compiled code T45, the array a has a SIMD width of 512 bits (64 bytes), and the loop body is unrolled three times. Then, SIMD processing is performed using a normal SIMD instruction that does not use the first-fault load instruction.

[0188] In code T46 which is the process of loop unrolling, as explained in the explanation of code T46-1, the array can be accessed up to the unroll count times the SIMD width.

[0189] Fig. 29 is a diagram showing a fourth example of the compilation process in this embodiment. In the first, second, and third examples shown in Fig. 23, Fig. 24, and Fig. 28, a continuous data area equal to or larger than the SIMD width is reserved as a dummy area. However, at least one array that is the subject of SIMD processing may have multiple discrete data areas.

[0190] In Fig. 29, reference symbols T47 and T49 are source codes. As in the second example in Fig. 24, user instructions are shown in the source code of reference symbol T49. However, as in the first example in Fig. 23, instead of user instructions in the source code, option settings for compilation may be made.

[0191] As explained with reference symbol T48-1, reference symbol T48 indicates a process in which the compiling device 10 executing the compiled program expands and secures data areas so that the sizes of array a, array b, and array idx each become SIMD width.

[0192] As described in the explanations of the codes T50-1 and T50-2, in the process of the code T50, the array idx has multiple discrete data areas. In FIG. 29, an indirect reference may be adopted in which the value of i in the array a(i) is indirectly pointed to by referring to the array idx. The array idx for indirect reference is initialized within a range of 16, which is the number of elements of the array a. In FIG. 29, a discrete SIMD load instruction is used that accesses multiple discrete data areas in parallel (for example, simultaneously). In one example, the indirect reference of the array a is executed by a normal discrete SIMD load instruction that does not use the first-fault load instruction.

[0193] [B-3] Example of operation FIG. 30 is a flowchart showing an example of a process of SIMD object development of a SIMD instruction in this embodiment.

[0194] 30, the analysis unit 210 analyzes a source program. The intermediate code conversion unit 220 generates an intermediate program from the source program 2 based on the analysis result of the analysis unit 210. The loop structure analysis unit 211 extracts one loop from the intermediate program (step S10).

[0195] The loop structure management unit 214 checks whether there is a mid-loop abort process in the computation loop by referring to the DO management table 216 shown in Fig. 21. In other words, it is checked whether the computation loop includes an escape condition. In one example, the loop structure management unit 214 judges whether there is an mid-loop escape statement presence flag (for example, a value of 1) (step S11).

[0196] If the mid-escape statement existence flag determines that the loop includes mid-escape processing (see the Yes route of step S11), the process proceeds to step S12. If the mid-escape statement existence flag determines that the loop does not include mid-escape processing (see the No route of step S11), the process proceeds to step S13.

[0197] In step S12, even if it is determined that the loop includes an escape condition based on the mid-escape statement existence flag, it is not immediately determined that SIMD expansion is impossible. The loop structure management unit 214 refers to the value of the loop SIMD flag in the DO management table 216 to determine whether SIMD arithmetic expansion is possible. If SIMD arithmetic expansion is possible, the SIMD instruction expansion unit 234 and the escape loop SIMD expansion unit 236 execute SIMD arithmetic expansion. If SIMD arithmetic expansion is impossible, the scalar instruction expansion unit 235 scalar expands the DO statement (step S14).

[0198] Also in step S13, the loop structure management unit 214 refers to the value of the loop SIMD flag in the DO management table 216 to determine whether SIMD arithmetic expansion is possible. If SIMD arithmetic expansion is possible (see the Yes route in step S13), the SIMD instruction expansion unit 234 and the exit loop SIMD expansion unit 236 execute SIMD arithmetic expansion for the DO statement (step S15). If SIMD arithmetic expansion is not possible (see the No route in step S13), the scalar instruction expansion unit 235 scalar expands the DO statement (step S14). Then, the process of SIMD object expansion of the SIMD instruction in this embodiment ends.

[0199] Fig. 31 is a flowchart showing an example of a process of SIMD object expansion of a SIMD instruction in the comparative example of Fig. 3 to Fig. 8. The process of the comparative example of Fig. 31 is similar to the process of this embodiment shown in Fig. 30 except that it does not include step S12 in Fig. 30. Therefore, if there is a process of aborting the loop midway, it is not possible to expand the loop into a SIMD operation.

[0200] FIG. 32 is a flowchart showing an example of the process of unfolding an escape loop in this embodiment.

[0201] The loop structure management unit 214 checks the loop numbers k=0 to the last number (step S20).

[0202] The loop structure management unit 214 checks the value of the "intermediate escape statement existence flag" in the computation loop by referring to the DO management table 216 (step S21). If the intermediate escape statement existence flag indicating that an intermediate escape statement exists in the computation loop exists (see the Yes route of step S21), the process proceeds to step S22. On the other hand, if the intermediate escape statement existence flag indicating that an intermediate escape statement exists in the computation loop does not exist (see the No route of step S21), the same processes as steps S13 and S15 in Fig. 30 are performed. Therefore, detailed explanation will be omitted.

[0203] The loop structure management unit 214 refers to a first SIMD expansion possibility flag in the DO management table 216 indicating whether SIMD is possible due to the mid-way exit condition expression, and a second SIMD expansion possibility flag indicating whether SIMD is possible due to the processing of the arithmetic loop excluding the exit condition expression.

[0204] When the loop structure management unit 214 confirms that the first SIMD expansion enable / disable flag, the second SIMD expansion enable / disable flag, and the mid-exit statement existence flag are all the first value (for example, 1) (see the Yes route of step S22), the processing of step S23 and the following steps is executed. When either the first SIMD expansion enable / disable flag or the second SIMD expansion enable / disable flag is not the first value (for example, 1) (see the No route of step S22), the same processing as step S14 in Fig. 30 is performed. Therefore, a detailed description will be omitted.

[0205] In step S23, the code generation unit 230 loads the memory data to be subjected to the SIMD arithmetic processing into the SIMD register by a SIMD load instruction. At this time, the number of loop rotations converted into SIMD is SIMD expanded as the number of loop rotations (l) / SIMD element length (s)+1.

[0206] In step S24, the exit loop SIMD expansion unit 236 executes SIMD expansion of the exit condition expression such as an if exit statement. Since the first SIMD expansion availability flag in the DO management table 216 is a first value (for example, 1), it is possible to execute SIMD expansion of the exit condition expression such as an if exit statement. The processor 101 expands a masked CMP instruction (compare instruction) that compares the exit condition for SIMD elements. The exit loop SIMD expansion unit 236 may specify all mask values ​​of the first mask flag in the masked SIMD compare instruction as 1 and execute the process assuming that the data area exists. The result of the masked SIMD compare instruction (true, false) is stored in the second mask flag (m2) as the second mask value. If true (i.e., if the exit condition is satisfied), the second mask value may be 1, and if false (i.e., if the exit condition is not satisfied), the second mask value may be 0.

[0207] In step S25, the Brkbs instruction is executed. With respect to the second mask value for each element obtained by the SIMD comparison instruction, the processor 101 detects the data element for which the escape condition is first satisfied (i.e., the second mask value is 1) with the head of the data element being the starting point of 0 as the corresponding mask information. The processor 101 may mark the position of the detected data element with a flag or the like. The processor 101 sets the operation mask value to 1 for the data element for which the escape condition is first satisfied or the data element immediately preceding it. With respect to the subsequent data elements, the processor 101 sets the operation mask value to 0 and information indicating that the subsequent data elements are invalid, i.e., are not subject to SIMD processing, as mask information.

[0208] In step S26, the exit loop SIMD development unit 236 sets the operation mask value obtained in step S25 as the operation mask value for the masked SIMD operation instruction. In the case of a SIMD fraction, the exit loop SIMD development unit 236 performs SIMD operation processing up to the data element immediately before the data element for which the exit condition is first satisfied.

[0209] In step S27, the exit loop SIMD development unit 236 develops an instruction incp that calculates the number of processed data elements (S). The incp instruction may calculate the number of processed data elements S by the following formula. The result of this calculation is equal to the number of elements processed by scalar processing for each data element. S=S+x (the initial value of S is 0).

[0210] In step S28, the B.loop instruction is expanded by the exit loop SIMD expansion unit 236 to determine whether to continue the loop processing (Taken) or to exit the loop processing (NotTaken). If information (invalid) that is not subject to SIMD processing is set in the mask information corresponding to the SIMD processing, it may be determined that the SIMD fraction has been reached and the operation loop may be exited. If the flags of p1a in Figs. 26 and 27 are all 1, none of the comparison conditions are met, and therefore the exit condition is not satisfied. In this case, the process proceeds to the loop head process in step S24. On the other hand, if the flag of p1a in Figs. 26 and 27 is 0, the comparison condition is not met, and therefore the process proceeds to step S29.

[0211] In step S29, the processor 101 executes subsequent processing of the loop, and the process of unrolling the exit loop in this embodiment is then terminated.

[0212] FIG. 33 is a flowchart showing an example of a process for expanding an SIMD instruction into a SIMD object based on an ocl specification in this embodiment.

[0213] The analysis unit 210 identifies an arithmetic loop instructed by a user using OCL or the like in the source program 2 (step S30). If an instruction for an array specified in the arithmetic loop described in OCL or the like is determined to be an instruction for allocating a data area by a compiler, the area start address is placed on a SIMD boundary (step S31).

[0214] The data area size is set to the SIMD boundary (step S33). If the specified array is an area that cannot be managed by the compiler during translation, it may be assumed that the user has reserved the area as a SIMD boundary. SIMD processing is performed using a normal SIMD load instruction that does not include a first-fault load instruction. Then, the process of expanding the SIMD object of the SIMD instruction based on the ocl specification in this embodiment ends.

[0215] [C] Effects of one embodiment According to a compilation program and a compilation method according to an embodiment, in memory data loaded from a memory, a data area of ​​at least one array to which a data element that satisfies an escape condition of an operation loop belongs is reserved to be equal to or larger than a SIMD width, which is a data length that can be processed in parallel at one time. A data position in the array in which the data element exists is obtained. An operation mask is set for each data element of the array based on the data position. A SIMD operation is performed on the memory data using the operation mask.

[0216] This ensures that a large data area is reserved for the fractional part where an element that satisfies the loop exit condition exists in SIMD expansion, making it possible to suppress the occurrence of exception conditions.Since a first fault load instruction is not required to suppress the occurrence of exception conditions, the time required to execute one instruction for SIMD calculations can be shortened and restrictions on use can be alleviated.

[0217] Furthermore, the computer is caused to execute a process for accepting option settings for compilation, and the process for reserving a data area for an array that is equal to or larger than the SIMD width is executed based on the option settings.

[0218] This makes it possible to secure a data area by setting options in advance.

[0219] Furthermore, the computer is caused to execute a process for recognizing a user instruction in a source program, and the process for reserving a data area for the array that is equal to or larger than the SIMD width is executed based on the user instruction in the source program.

[0220] This makes it possible to instruct the allocation of a data area by description in the source program.

[0221] Furthermore, loop unrolling is performed to increase the number of codes that can be executed in parallel by expanding loop instructions, and the process of reserving a data area for the array that is equal to or larger than the SIMD width reserves a data area that is equal to or larger than the SIMD width multiplied by the number of loop unrolls.

[0222] This makes it possible to secure a data area of ​​an appropriate length according to the number of times loop unrolling is performed.

[0223] At least one of the arrays has a plurality of discrete data regions.

[0224] This makes it possible to reduce the time required to execute a single instruction and ease restrictions on use, even in an array that has multiple discrete data areas.

[0225] Furthermore, the compiling program and the compiling method cause the computer to execute the process of analyzing a source program, converting the source program into intermediate code based on the analysis result, and converting the intermediate code into a machine language program.

[0226] This enables appropriate compilation depending on the results of the source program analysis.

[0227] [D] Notes The following supplementary notes are further disclosed regarding the above embodiment.

[0228] (Appendix 1) In the memory data loaded from the memory, a data area of ​​at least one array to which a data element that satisfies an exit condition of the arithmetic loop belongs is secured to be equal to or larger than a SIMD (Single Instruction Multiple Data) width, which is a data length that can be processed in parallel at one time; Obtaining a data position in the array where the data element resides; setting an operational mask for each of the data elements of the array based on the data position; performing a SIMD operation on the memory data using the operation mask; A compiled program that causes a computer to carry out a process.

[0229] (Appendix 2) Furthermore, the method causes the computer to execute a process of accepting option settings for compilation, The process of reserving a data area for the array that is equal to or larger than the SIMD width is performed based on the option setting. 2. The compiled program according to claim 1.

[0230] (Appendix 3) and causing the computer to execute a process of recognizing a user instruction in a source program; the process of reserving a data area for the array that is equal to or larger than the SIMD width is executed based on the user's instruction in the source program. 2. The compiled program according to claim 1.

[0231] (Appendix 4) and causing the computer to execute a loop unrolling process to increase the number of codes that can be executed in parallel by unrolling loop instructions. The process of reserving a data area for the array that is equal to or larger than the SIMD width reserves a data area that is equal to or larger than the SIMD width multiplied by a loop unroll count. 2. The compilation program according to claim 1.

[0232] (Appendix 5) At least one of the arrays has a plurality of discrete data regions. 2. The compilation program according to claim 1.

[0233] (Appendix 6) In addition, the source program is analyzed, converting the source program into an intermediate code based on the analysis result; converting the intermediate code into a machine language program; causing the computer to execute a process; 2. The compilation program according to claim 1.

[0234] (Appendix 7) In the memory data loaded from the memory, a data area of ​​at least one array to which a data element that satisfies an exit condition of the arithmetic loop belongs is secured to be equal to or larger than a SIMD (Single Instruction Multiple Data) width, which is a data length that can be processed in parallel at one time; Obtaining a data position in the array where the data element resides; setting an operational mask for each of the data elements of the array based on the data position; performing a SIMD operation on the memory data using the operation mask; A compilation method in which processing is carried out by a computer.

[0235] (Appendix 8) Furthermore, the computer executes a process of accepting option settings for compilation, The process of reserving a data area for the array that is equal to or larger than the SIMD width is performed based on the option setting. 8. The compilation method according to claim 7.

[0236] (Appendix 9) Furthermore, the computer executes a process for recognizing a user instruction in a source program, the process of reserving a data area for the array that is equal to or larger than the SIMD width is executed based on the user's instruction in the source program. 8. The compilation method according to claim 7.

[0237] (Appendix 10) Furthermore, the computer executes a loop unrolling process to increase the number of codes that can be executed in parallel by unrolling loop instructions; The process of reserving a data area for the array that is equal to or larger than the SIMD width reserves a data area that is equal to or larger than the SIMD width multiplied by a loop unroll count. 8. The compilation method according to claim 7.

[0238] (Appendix 11) At least one of the arrays has a plurality of discrete data regions. 8. The compilation method according to claim 7.

[0239] (Appendix 12) In addition, the source program is analyzed, converting the source program into an intermediate code based on the analysis result; converting the intermediate code into a machine language program; The process is executed by the computer. 8. The compilation method according to claim 7. [Explanation of symbols]

[0240] 2. Source Program 4 Machine language programs 10 Compilation device 101 Processor 102 Memory section 103 Display control unit 104 Storage device 105 Input IF 106 External storage media processing unit 107 Communication Interface 1030 Display device 1051 Mouse 1052 Keyboard 210 Analysis Department 211 Loop Structure Analysis Section 212 Sequence Analysis Department 213 Dependency Analysis Unit 214 Loop Structure Management Section 215 Variable data storage unit 216 DO Management Table 217 Array Management Table 220 Intermediate Code Conversion Unit 230 Code Generation Unit 231 Development Section 232 Output section 234 SIMD instruction conversion unit 235 Scalar instruction expansion section 236 Exit Loop SIMD Expansion Part

Claims

1. In the memory data loaded from the memory, a data area of ​​at least one array to which a data element that satisfies an exit condition of the arithmetic loop belongs is secured to have a width equal to or larger than a SIMD (Single Instruction Multiple Data) width, which is a data length that can be processed in parallel at one time; Obtaining a data position in the array where the data element resides; setting an operational mask for each of the data elements of the array based on the data position; performing a SIMD operation on the memory data using the operation mask; A compiled program that causes a computer to carry out a process.

2. Furthermore, the method causes the computer to execute a process of accepting option settings for compilation, The process of reserving a data area for the array that is equal to or larger than the SIMD width is performed based on the option setting. The compilation program according to claim 1 .

3. and causing the computer to execute a process of recognizing a user instruction in a source program; the process of reserving a data area for the array with a width equal to or larger than the SIMD width is executed based on a user instruction in the source program. The compilation program according to claim 1 .

4. and causing the computer to execute a loop unrolling process to increase the number of codes that can be executed in parallel by unrolling loop instructions. The process of reserving a data area for the array that is equal to or larger than the SIMD width reserves a data area that is equal to or larger than the SIMD width multiplied by a loop unroll count. The compilation program according to claim 1 .

5. At least one of the arrays has a plurality of discrete data regions. The compilation program according to claim 1 .

6. In addition, the source program is analyzed, converting the source program into an intermediate code based on the analysis result; converting the intermediate code into a machine language program; causing the computer to execute a process; The compilation program according to claim 1 .

7. In the memory data loaded from the memory, a data area of ​​at least one array to which a data element that satisfies an exit condition of the arithmetic loop belongs is secured to have a width equal to or larger than a SIMD (Single Instruction Multiple Data) width, which is a data length that can be processed in parallel at one time; Obtaining a data position in the array where the data element resides; setting an operational mask for each of the data elements of the array based on the data position; performing a SIMD operation on the memory data using the operation mask; A compilation method in which processing is carried out by a computer.

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