Memory system and method

Abstract

To provide a memory system and a method, capable of effectively using a storage region.SOLUTION: A memory system comprises: a non-volatile memory device; and a controller which writes a first error correction frame (ECC frame 0) and a second error correction frame (ECC frame 1) into the memory device. The first error correction frame and the second error correction frame include duplicate regions (R4 and R5). Regions other than the duplicate region of the first error correction frame include first data and first error correction data (P0). Regions other than the duplicate region of the second error correction frame include second data and second error correction data (P1). The duplicate regions include a part of the first data (D0) and a part of the second data (D1).SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE 1. Field of the Invention Embodiments of the present invention relate to memory systems and methods. [Background technology]

[0002] The memory system calculates parity for error correction from the data, forms an Error Correction Code (ECC) frame of a certain size including the data and the parity, and writes the ECC frame to a memory device.

[0003] The memory system may write variable length data to the memory device. One example of variable length data is compressed data. When writing variable length data, depending on the size of the variable length data, the ECC frame may contain invalid data. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2011 / 131346 [Patent Document 2] US Patent Application Publication No. 2008 / 46608 [Patent Document 3] US Patent Application Publication No. 2022 / 46114 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a memory system and method that efficiently utilizes storage space. [Means for solving the problem]

[0006] A memory system according to an embodiment includes a non-volatile memory device and a controller configured to write a first error correction frame and a second error correction frame to the memory device. The first error correction frame and the second error correction frame include an overlapping area. An area of ​​the first error correction frame other than the overlapping area includes first data and first error correction data. An area of ​​the second error correction frame other than the overlapping area includes second data and second error correction data. The overlapping area includes a portion of the first data and a portion of the second data. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram for explaining an example of the outline of a memory system according to an embodiment; [Diagram 2] 1A and 1B are diagrams for explaining a comparative example of an ECC frame configuration when the memory system according to the embodiment compresses data and writes it to a memory device. [Diagram 3] 11A and 11B are diagrams for explaining another comparative example of the configuration of an ECC frame when the memory system according to the embodiment compresses data and writes it to a memory device. [Figure 4] 2 is a diagram for explaining an example of the configuration of an ECC frame in the memory system according to the embodiment. [Diagram 5] 11 is a diagram for explaining another example of the configuration of an ECC frame in the memory system according to the embodiment. [Figure 6] 1 is a diagram for explaining an example of a specific size of an ECC frame configuration in a memory system according to an embodiment. [Figure 7] FIG. 1 is a diagram for explaining an example of an information processing system according to an embodiment. [Figure 8] FIG. 4 is a diagram for explaining an example of an address conversion table according to the embodiment. [Figure 9] 11 is a flowchart illustrating an example of a write process according to the embodiment. [Figure 10] 11 is a flowchart illustrating an example of a write process according to the embodiment. [Figure 11]4A and 4B are diagrams for explaining an example of creating an ECC frame according to the embodiment. [Figure 12] 11 is a flowchart illustrating an example of a read process according to the embodiment. [Figure 13] FIG. 4 is a diagram for explaining an example of data decompression processing according to the first embodiment. [Figure 14] 11 is a diagram for explaining a specific example of the configuration of an ECC frame in a memory system according to the second embodiment. FIG. [Figure 15] 13 is a diagram for explaining a specific example of the configuration of an ECC frame in a memory system according to a third embodiment. FIG. [Figure 16] FIG. 13 is a diagram for explaining an example of an operation of sequentially reading four consecutive ECC frames in the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described with reference to the drawings. The following description is an example of an apparatus and method for embodying the technical idea of ​​the embodiment, and the technical idea of ​​the embodiment is not limited to the structure, shape, arrangement, material, etc. of the components described below. Modifications that a person skilled in the art can easily conceive are naturally included in the scope of the disclosure. In order to make the description clearer, the size, thickness, planar dimensions, or shape of each element may be changed from the actual embodiment and shown diagrammatically. Elements having different dimensional relationships or ratios may be included in multiple drawings. In multiple drawings, corresponding elements may be given the same reference numerals and duplicated descriptions may be omitted. Some elements may be given multiple names, but these examples of names are merely examples and do not deny the use of other names for these elements. In addition, it is not denied that elements not given multiple names may be given other names. In the following description, "connection" may include not only direct connection but also connection via other elements.

[0009] 1 is a diagram for explaining an example of a schematic of a memory system 10 according to a first embodiment. The memory system 10 includes a nonvolatile memory device 12. An example of a nonvolatile memory is a NAND type flash memory. An interface 14 is defined in the memory system 10 for transferring commands and data between the memory system 10 and a host (not shown in FIG. 1).

[0010] The memory device 12 stores multiple pages. A page includes multiple ECC frames. FIG. 1 shows an example where one page includes four ECC frames. The ECC frames store data and parity. An example of sizes is as follows: the data size is 1024 bytes, the parity size is 118 bytes, the ECC frame size is 1142 bytes, and the page size is 4568 bytes.

[0011] A page may consist of a single ECC frame instead of multiple ECC frames.

[0012] When writing, the memory system 10 calculates 118 bytes of parity from multiple (e.g., eight) 128-byte units of data (total of 1024 bytes). The memory system 10 generates a 1142-byte ECC frame from the data and parity, and writes the ECC frame to the memory device 12.

[0013] During a read, the memory system 10 reads the ECC frame from the memory device 12 and extracts the parity and data from the ECC frame. The memory system 10 performs error correction on the data based on the parity.

[0014] The memory system 10 may compress data before writing it to the memory device 12 in order to reduce memory usage and increase data transfer speed.

[0015] FIG. 2 is a diagram for explaining a comparative example of the configuration of an ECC frame when the memory system 10 according to the first embodiment compresses data and writes the data to the memory device 12. In FIG.

[0016] The ECC frame includes a data area 24, an invalid area 26, and a parity area 28. The data area 24 includes a data stream D. The data stream D corresponds to the data in FIG. 1. The invalid area 26 includes invalid data. An example of the size of each area 24, 26, 28 is shown below. The total size of the data area 24 and the invalid area 26 is 1024 bytes. The size of the parity area 28 is 118 bytes. The size of each of the data area 24 and the invalid area 26 is variable.

[0017] The memory system 10 compresses unit data of a fixed size, for example, 128 bytes, and writes at least one compressed data as a data stream D to the data area 24 of the ECC frame 0. An example of a compression method is a lossless compression method. In the lossless compression method, the compressed data has a variable length size.

[0018] When the size of the data stream D exceeds 1024 bytes, that is, when there is no free space in the data area 24, the memory system 10 stops writing compressed data to the data area 24. Since the compressed data has a variable length, in most cases, there will be no free space in the data area 24 when a portion of the compressed data has been written to the data area 24.

[0019] For example, if the data area 24 becomes full after a portion of the compressed data of the unit data 22 has been written as a data stream D0 into the data area 24 of ECC frame 0, the memory system 10 stops writing the compressed data. After stopping the writing, the memory system 10 writes all of the compressed data of the unit data 22 as a data stream D1 into the head portion of the data area 24 of ECC frame 1. Thereafter, the memory system 10 writes the compressed data sequentially into the data area 24 of ECC frame 1.

[0020] A portion of the compressed data of the unit data 22 stored in the data area 24 of ECC frame 0 is invalid data that cannot be used even if it is read later. When writing of a portion of the compressed data is stopped, the data area 24 containing the invalid data is changed to an invalid area 26. The average size of the invalid area 26 varies depending on the conditions, but is, for example, about several tens of bytes per ECC frame. For this reason, there is a possibility that several percent of the storage area of ​​the memory device will become the invalid area 26.

[0021] The memory system 10 calculates the parity P0 based on the data stream D0 contained in the data area 24. The memory system 10 writes the parity P0 to the parity area .

[0022] 3 is a diagram for explaining another comparative example of the configuration of an ECC frame when the memory system 10 according to the first embodiment compresses data and writes it to the memory device 12. The data compression method, data, and size of each area are the same as those in the comparative example of FIG.

[0023] Each ECC frame other than the last ECC frame of the page includes a 1024-byte data area 34 and a 118-byte parity area 38, and does not include an invalid area. The last ECC frame of the page includes a 1024-byte data area, a parity area, and an invalid area.

[0024] The memory system 10 compresses data in units of 128 bytes and writes at least one variable-length compressed data as a data stream D to the data area 34 .

[0025] When the size of the data stream D exceeds 1024 bytes, that is, when the data area 34 has no free space, the memory system 10 stops writing compressed data to the data area 34.

[0026] For example, if the data area 34 becomes full after a portion of the compressed data of data 32 has been written to the data area 34 of ECC frame 0, the memory system 10 stops writing compressed data to the data area 34 of ECC frame 0. After stopping the writing, the memory system 10 writes the remaining portion of the compressed data of data 32 as data stream D0 to the beginning of the data area 34 of ECC frame 1. Thereafter, the memory system 10 writes compressed data sequentially to the data area 34 of ECC frame 1.

[0027] The memory system 10 calculates parity P0 based on the data stream D0 included in the data area 34 of ECC frame 0 and the data area 34 of ECC frame 1. The memory system 10 writes parity P0 to the parity area 38.

[0028] In the example of FIG. 2, the data area 24 of ECC frame 1 includes all of the compressed data of the 128-byte unit data 22 as a data stream D1. Therefore, each ECC frame includes an invalid area 26. In the example of FIG. 3, one piece of compressed data of 128 bytes of data 32 is divided into two sub-compressed data. Two ECC frames 0 and 1 each include two sub-compressed data as a data stream D0. The last ECC frame of a page may include an invalid area, but the other ECC frames do not include an invalid area. Therefore, the size of the invalid area in the example of FIG. 3 is smaller than the size of the invalid area in the example of FIG. 2.

[0029] 3, however, it is necessary to read two ECC frames to read one unit data 32. This increases the number of data communications with the host 32 when reading data, consuming more interface bandwidth and possibly degrading performance.

[0030] FIG. 4 is a diagram for explaining an example of the configuration of an ECC frame in the memory system 10 according to the first embodiment.

[0031] Each page includes four ECC frames. Two adjacent ECC frames have an overlapping area. Figure 4(a) shows an example of the configuration of ECC frames 0 and 1. Figure 4(b) shows an example of the configuration of ECC frames 2 and 3.

[0032] ECC frame 0 includes six regions R0-R5. The size of each of regions R0, R1, R2, and R3 is constant. The total size of regions R4 and R5 is constant. The size of each of regions R4 and R5 is variable. The size of region R0 is equal to the total size of regions R4 and R5.

[0033] Region R0 includes the beginning of data stream D0. Region R1 includes a header H0. The header H0 indicates the address of memory device 12 corresponding to the beginning of data stream D0. Region R2 includes parity P0 of data stream D0. Regions R3 and R4 include data stream D0. Region R5 includes the beginning of data stream D1.

[0034] Areas R4 and R5 are also included in ECC frame 1 and are overlapping areas between ECC frame 0 and ECC frame 1. The end of data stream D0 is written up to the middle of the overlapping area (area R4). Data stream D1 is written from the middle of the overlapping area (area R5).

[0035] ECC frame 1 includes seven regions R4-R10. The size of each of regions R6, R7, and R8 is constant. The total size of regions R9 and R10 is constant. The size of each of regions R9 and R10 is variable. The total size of regions R9 and R10 is equal to the total size of regions R4 and R5.

[0036] Region R6 contains a header H1. The header H1 indicates the address in memory device 12 where the beginning of data stream D1 is stored. Region R7 contains parity P1 for data stream D1. Regions R8 and R9 contain data stream D1. Region R10 contains the beginning of data stream D2.

[0037] Areas R9 and R10 are also included in ECC frame 2 and are overlapping areas between ECC frame 1 and ECC frame 2. The end of data stream D1 is written up to the middle of the overlapping area (area R9). Data stream D2 is written from the middle of the overlapping area (area R10).

[0038] ECC frame 2 includes seven regions R9-R15. The sizes of regions R11, R12, and R13 are constant. The total size of regions R14 and R15 is constant. The sizes of regions R9 and R10 are variable. The total size of regions R9 and R10 is equal to the total size of regions R4 and R5.

[0039] Region R11 includes a header H2. Header H1 indicates the address in memory device 12 corresponding to the beginning of data stream D2. Region R12 includes parity P2 of data stream D2. Regions R13 and R14 include data stream D2. Region R15 includes the beginning portion of data stream D3.

[0040] Areas R14 and R15 are also included in ECC frame 3 and are overlapping areas between ECC frame 2 and ECC frame 3. The end of data stream D2 is written up to the middle of the overlapping area (area R14). Data stream D3 is written from the middle of the overlapping area (area R10).

[0041] The ECC frame 3 includes six regions R14 to R19. The sizes of the regions R16 and R17 are constant.

[0042] Region R16 includes a header H3. The header H3 indicates an address in memory device 12 corresponding to the beginning of data stream D3. Region R17 includes parity P3 of data stream D3. Region R18 includes data stream D3. Region R19 is an invalid region that includes invalid data. The invalid region R19 corresponds to invalid region 26 (FIG. 2).

[0043] The sizes of the regions R1, R6, R11, and R16 including headers are equal to each other. The sizes of the regions R2, R7, R12, and R17 including parity are equal to each other. The total size of the overlap regions R4 and R5, the total size of the overlap regions R9 and R10, and the total size of the overlap regions R14 and R15 are equal to each other.

[0044] The memory system 10 according to the first embodiment generates ECC frames such that adjacent ECC frames partially overlap each other. The ECC frames do not include the invalid area R19 and include one entire data stream. The boundary between the first data stream and the second data stream is located in the overlapping area. This makes it possible to reduce the invalid area of ​​the memory device without increasing the number of data transfers during reading.

[0045] It is not essential that all of the boundaries between the two data streams are located in the overlapping area. At least one of the boundaries between the two data streams does not have to be located in the overlapping area. Figure 5 is a diagram for explaining another example of the configuration of an ECC frame in the memory system 10 according to the first embodiment.

[0046] Each page includes four ECC frames. Two adjacent ECC frames have an overlapping area. Figure 5(a) shows an example of the configuration of ECC frames 0 and 1. Figure 5(b) shows an example of the configuration of ECC frames 2 and 3.

[0047] ECC frame 0 includes six regions R30-R35. The sizes of regions R30, R31, R32, and R35 are constant. The sizes of regions R33 and R34 are variable. The size of region R30 is equal to the size of region R35.

[0048] Region R30 includes the beginning of data stream D0. Region R31 includes a header H0. The header H0 indicates an address in memory device 12 corresponding to the beginning of data stream D0. Region R32 includes parity P0 of data stream D0. Region R33 includes data stream D0. Region R34 includes invalid data. The invalid region R34 corresponds to invalid region 26 (FIG. 2).

[0049] Region R35 is also included in ECC frame 1, and is an overlap region between ECC frame 0 and ECC frame 1. Overlap region R35 does not include data stream D0 of ECC frame 0, but includes the beginning portion of data stream D1 of ECC frame 1.

[0050] ECC frame 1 includes six regions R35-R40. The total size of regions R36 and R37 is constant. The size of region R38 is variable. The total size of regions R39 and R40 is constant. The total size of regions R36 and R37 is equal to the size of region R35.

[0051] Region R36 includes a header H1. The header H1 indicates the address in the memory device 12 corresponding to the beginning of the data stream D1. Region R37 includes a parity P1 for the data stream D1. Region R38 includes the data stream D1.

[0052] Areas R39 and R40 are also included in ECC frame 2 and are overlapping areas between ECC frame 1 and ECC frame 2. The end of data stream D1 is written up to the middle of the overlapping area (area R39). Data stream D2 is written from the middle of the overlapping area (area R40).

[0053] ECC frame 2 includes seven regions R39-R45. The size of each of regions R41, R42, and R43 is constant. The total size of regions R44 and R45 is constant. The size of each of regions R44 and R450 is variable. The total size of regions R39 and R40 is equal to the total size of regions R44 and R45.

[0054] Region R41 includes a header H2. Header H1 indicates the address in memory device 12 that stores the beginning of data stream D2. Region R42 includes parity P2 of data stream D2. Regions R43 and R44 include data stream D2. Region R45 includes the beginning of data stream D3.

[0055] Areas R44 and R45 are also included in ECC frame 3 and are overlapping areas between ECC frame 2 and ECC frame 3. The end of data stream D2 is written up to the middle of the overlapping area (area R44). Data stream D3 is written from the middle of the overlapping area (area R45).

[0056] ECC frame 3 includes six regions R44-R49. The size of each of regions R46 and R47 is constant. The total size of regions R48 and R49 is constant. The size of each of regions R48 and R49 is variable.

[0057] Region R46 includes a header H3. The header H3 indicates an address in memory device 12 corresponding to the beginning of data stream D3. Region R47 includes parity P3 of data stream D3. Region R48 includes data stream D3. Region R49 is an invalid region that includes invalid data. The invalid region R49 corresponds to the invalid region 26 (FIG. 2).

[0058] The sizes of the regions R31, R36, R41, and R46 including headers are equal to each other. The sizes of the regions R32, R37, R42, and R47 including parity are equal to each other. The size of overlap region R35, the total size of overlap regions R39 and R40, and the total size of overlap regions R44 and R45 are equal to each other.

[0059] 5, an overlapping area R35 between ECC frame 0 and ECC frame 1 does not include the data stream D0 of ECC frame 0, but only includes the data stream D1 of ECC frame 1. Therefore, an invalid area R34 occurs in ECC frame 0.

[0060] If there is a high probability that the boundary between the two data streams is located in the overlapping area, the size of the invalid area will be small. If all of the boundaries between the two data streams are always located in the overlapping area, the size of the invalid area will be the smallest. To realize the ECC frame of FIG. 4, it is sufficient that the increase in the size of the data stream when one piece of compressed data is added (in other words, the amount of decrease in the free space in the data area) is equal to or less than the size of the overlapping area. When the data before compression is in units of 128 bytes, the maximum size of the compressed data is 128 bytes. The maximum increase in the size of the data stream when one piece of compressed data is added is 128 bytes. Therefore, if the size of the overlapping area of ​​the ECC frame is set to 128 bytes, the ECC frame of FIG. 4 can be realized.

[0061] As the size of the overlap area increases, the size of the parity area also increases, so the size of the data area decreases. If the size of the overlap area is smaller than 128 bytes, the ECC frame in Figure 4 may not be realized, but the ECC frame in Figure 5 may be realized.

[0062] In the examples of Figures 4 and 5, the areas other than the overlap area, such as areas R1, R6, R11, and R16, include a header, but the overlap area may include a header depending on the performance and cost required for the memory system. For example, the beginning or end of the overlap area may include a header. Furthermore, a memory device other than the memory device that stores data may include a header.

[0063] The formats of the four ECC frames that partially overlap with adjacent ECC frames (size / storage location of data stream, size / storage location of parity, etc.) may all be the same or different. If the formats are uniform, multiple types of parity generation processing and error correction processing are not required, and only one type of parity generation processing and error correction processing is required.

[0064] According to the memory system 10 of the first embodiment, when variable-length data such as compressed data is stored, the number of invalid areas can be reduced. In the comparative example shown in Fig. 2, each ECC frame includes one invalid area, but in the first embodiment shown in Fig. 4, one invalid area is included in four frames (pages), so that the number of invalid areas can be reduced to about 1 / 4, and the area for storing the data stream can be increased.

[0065] Furthermore, in the first embodiment shown in FIG. 4 and FIG. 5, the number of ECC frames that need to be read is one when any unit data (128 bytes) is read. In the comparative example shown in FIG. 3, multiple (usually two, but when the size of the unit data is large, it may be three or more) ECC frames contain compressed data of one unit data. In order to read one unit data, multiple ECC frames may be read. Therefore, in the first embodiment shown in FIG. 4 and FIG. 5, in order to read one unit data, it is sufficient to read a single ECC frame. In the first embodiment shown in FIG. 4 and FIG. 5, the number of data communications with the host 32 during data reading is reduced, the amount of interface bandwidth consumed is reduced, and performance is improved, compared to the comparative example shown in FIG. 3.

[0066] The effects of the first embodiment will be described using specific values. Fig. 6 is a diagram for explaining an example of a specific size of the configuration of an ECC frame in the memory system 10 according to the first embodiment. Fig. 6 shows the size (unit: bytes) entered in each area of ​​Fig. 4.

[0067] The storage area of ​​the memory device 12 shown in FIG. 1 includes a page (4568 bytes) including four ECC frames. The size of the data area of ​​the ECC frame is 1024 bytes. The memory system 10 compresses one unit (128 bytes) of data and generates a data stream from multiple compressed data. The error correction capability required for the memory system 10 is 60 bits per ECC frame. When a BCH code is used as the ECC, a code that satisfies the following relationship can be realized (m is an integer) where the size of the parity is p (bits), the size of the compressed data is k (bits), and the number of correctable bits per ECC frame is t.

[0068] p=mt Equation 1 k<2 m -p expression 2 Here, t=60 and k=8192 (=1024×8). The minimum value of m for which Equation 1 and Equation 2 hold is 14. From Equation 1, the minimum value of the parity bit length p is 840 bits (105 bytes). The minimum value of the size required for four ECC frames is 4516 (=(1024+105)×4) bytes. The size of four ECC frames is 52 bytes more than the page size (4568 bytes). According to the comparative example shown in FIG. 2, it is possible to improve the storage capacity by about 52 bytes per page by simply increasing the size of the ECC frame.

[0069] Next, the improvement of the storage capacity according to the first embodiment will be described. Compared with the ECC frame shown in Fig. 3, the ECC frame according to the first embodiment has an increased overlap area (128 bytes, the same as the data unit) and a header (2 bytes), and the size of the ECC frame becomes larger. Therefore, it is necessary to increase the correction capability accordingly. Fig. 6 shows an example of the configuration of an ECC frame in which the total data size per page remains at 4096 bytes, and the parity is increased as much as possible to improve the correction capability.

[0070] Assume that the size of the ECC frame is 1238 bytes (data: 1120 bytes + header: 2 bytes + parity: 116 bytes). The number of correctable bits is 66 bits (=p / m=116×8 / 14). The number of correctable bits (66 bits) is 1.1 (=6.6 / 6.0) times larger than the original 60 bits. The increase in the number of correctable bits corresponds to the increase in the size of the ECC frame, 1.097 (=1238 / 1129).

[0071] Assume that the average size of each invalid area is 40 bytes. In the comparative example shown in FIG. 2, the invalid area per page is 160 bytes. According to the first embodiment shown in FIG. 6, the invalid area per page is 40 bytes. The invalid area of ​​the first embodiment shown in FIG. 6 is reduced by 120 bytes compared to the comparative example shown in FIG. 2. In other words, it can be said that the storage capacity is improved by 120 bytes. Since the improvement in storage capacity in the comparative example shown in FIG. 2 was 52 bytes, it can be said that according to the first embodiment, the storage capacity per page (4096 bytes of data) is improved by 68 bytes (=120-52) compared to the comparative example.

[0072] 7 is a diagram illustrating an example of an information processing system 1 according to the first embodiment. The information processing system 1 includes a memory system 10 and a host 32.

[0073] The host 32 is an information processing device that accesses the memory system 10. The memory system 10 can be used as a main storage of the host 32. The memory system 10 may be built into the host 32, or may be provided outside the host 32 and connected to the host 32 via a cable or a network. The host 32 may be a server (storage server) that stores a large amount of various data in the memory system 10. The host 32 may be a personal computer. The memory system 10 may be a system for business use that is incorporated into a server such as a data center. The memory system 10 may be a system for personal use that is incorporated into a personal computer. Examples of the memory system 10 are an SSD (Solid State Drive) and an HDD (Hard Disk Drive). In the following description, the memory device 12 is referred to as a NAND type flash memory 12.

[0074] The memory system 10 includes a NAND flash memory 12, a dynamic random access memory (DRAM) 44, and a controller 44. Instead of the NAND flash memory 12, a NOR flash memory, a magneto-resistive random access memory (MRAM), a phase change random access memory (PRAM), a resistive random access memory (ReRAM), or a ferroelectric random access memory (FeRAM) may be used. The NAND flash memory 12 includes a memory cell array including a plurality of memory cells arranged in a matrix. The memory cell array may have a two-dimensional structure or a three-dimensional structure.

[0075] The DRAM 44 is an example of a volatile memory. The DRAM 44 is, for example, a DRAM conforming to the DDR3L (Double Data Rate 3 Low voltage) standard. The DRAM 44 includes a write buffer 46, a read buffer 48, an address conversion table 50, and the like. Data that is supplied from the host 32 to the memory system 10 and is being written to the NAND flash memory 12 or has not yet been written is stored in the write buffer 46. Data that is read from the NAND flash memory 12 and is being transferred to the host 32 or has not yet been transferred is stored in the read buffer 48. The DRAM 44 also functions as a temporary buffer for data used during the operation of the memory system 10 and software executed in the controller 44. The DRAM 44 may be provided inside the controller 44 instead of outside the controller 44. Note that, as the volatile memory, a static random access memory (SRAM) capable of faster access may be used instead of the DRAM 44.

[0076] The controller 44 compresses data transmitted from the host 32 and writes the compressed data to the NAND flash memory 12 in accordance with a command transmitted from the host 32, or reads the compressed data from the NAND flash memory 12 and decompresses the read data. The controller 44 may be configured by a circuit such as a System on a Chip (SoC). The controller 44 controls the operation of the memory system 10. The controller 44 includes a host interface (referred to as a host I / F circuit) 52, a CPU 54, a NAND interface (referred to as a NAND I / F circuit) 56, a DRAM interface (referred to as a DRAM I / F circuit) 58, a compression circuit 60, an expansion circuit 62, an ECC encoder 64, and an ECC decoder 66.

[0077] The host I / F circuit 52 communicates with the host 32. The communication with the host 32 is performed using, for example, a PCI Express TM The host I / F circuit 52 receives commands from the host 32 in accordance with the standard.

[0078] The NAND I / F circuit 56 is a memory control circuit that controls the NAND flash memory 12 under the control of the CPU 54. The NAND I / F circuit 56 and the NAND flash memory 12 are connected by multiple channels Ch. The NAND flash memory 12 is made up of multiple memory chips. Multiple memory chips are connected to each channel.

[0079] The DRAM I / F circuit 58 is a DRAM control circuit that controls the DRAM 44 under the control of the CPU 54 .

[0080] The compression circuit 60 compresses the data transmitted from the host 32 using a lossless compression method. The compressed data is variable-length data. The ECC encoder 64 generates an ECC frame from the compressed data. The NAND I / F circuit 56 writes the ECC frame to the NAND flash memory 12.

[0081] The NAND I / F circuit 56 reads the ECC frame from the NAND flash memory 12. The ECC decoder 66 performs error correction processing on the compressed data extracted from the ECC frame. The decompression circuit 62 decompresses the compressed data after the error correction processing by a lossless decompression method. The host I / F circuit 52 transmits the decompressed data to the host 32.

[0082] Some or all of the compression circuit 60, the decompression circuit 62, the ECC encoder 64, and the ECC decoder 66 may be realized by the CPU 54 executing firmware. Some or all of the compression circuit 60, the decompression circuit 62, the ECC encoder 64, and the ECC decoder 66 may be provided outside the memory system 10. The outside of the memory system 10 is, for example, the host 32 or a server to which the host 32 is further connected.

[0083] 8 is a diagram illustrating an example of the address conversion table 50 according to the first embodiment. The address conversion table 50 stores an ECC frame ID corresponding to a host address and information on the start position of a data area in the ECC frame (called an offset).

[0084] 9 is a flowchart illustrating an example of a write process according to the first embodiment. The write process shown in FIG.

[0085] The CPU 54 receives a write command sent from the host 32 (S102).

[0086] The CPU 54 writes the write data to the write buffer 46 according to the contents of the write command, and also writes the host address specified in the write command to the write buffer 46 (S104). The write data is data in units of a predetermined size. The predetermined size is, for example, 128 bytes.

[0087] The CPU 54 notifies the host 32 of the completion of the write (S106), and ends the process. Note that this notification may be omitted.

[0088] Fig. 10 is a flowchart for explaining an example of a write process according to the first embodiment. The write process shown in Fig. 10 is executed once when data for four ECC frames is stored in the write buffer 46. Fig. 11 is a diagram for explaining an example of creating an ECC frame according to the first embodiment.

[0089] The CPU 54 reads the unit data stored in the write buffer 46, compresses the unit data using the compression circuit 60, and concatenates the compressed data to generate the first data stream D0 for the first ECC frame (S108). Figure 11(a) shows an example of the unit data read from the write buffer 46.

[0090] When reading the first unit data, the CPU 54 treats the compressed data as a data stream D0. When reading the second or subsequent unit data, the CPU 54 adds the compressed data to the data stream D0 and treats the result of the addition as a new data stream D0.

[0091] The CPU 54 generates a data stream so that compressed data of a 128-byte unit data is not divided into two data streams but always enters one data stream. If the size of a certain data stream exceeds an upper limit size as a result of adding certain compressed data to the certain data stream, the CPU 54 does not add the certain compressed data to the certain data stream, but adds the certain compressed data to the data stream next to the certain data stream.

[0092] ECC frames have a fixed size. Because compressed data is variable-length data, the data stream size must be less than or equal to the upper limit size. The upper limit size varies depending on the data stream. The upper limit size of the first data stream D0 is 1120 bytes. The upper limit size of the second data stream D1 is 992 bytes + α0. α0 is the remainder of the difference between the upper limit size of the first data stream D0 and the actual size of the first data stream D0. The upper limit size of the third data stream D2 is 992 bytes + α1. α1 is the remainder of the difference between the upper limit size of the second data stream D1 and the actual size of the second data stream D1. The upper limit size of the fourth data stream D3 is 992 bytes + α2. α2 is the remainder of the difference between the upper limit size of the third data stream D2 and the actual size of the third data stream D2.

[0093] For example, if the first data stream D0 is 1110 bytes and there are 10 bytes remaining, the CPU 54 generates the second data stream D1 which is 992+10=1002 bytes or less.

[0094] The CPU 54 reads the unit data stored in the write buffer 46, compresses the unit data using the compression circuit 60, and concatenates the compressed data to generate the second to fourth data streams D1-D3 for the second to fourth ECC frames (S110). Figure 11(b) shows an example of the data streams D1-D3.

[0095] The CPU 54 writes the ID of the ECC frame in which the data stream D0-D3 is recorded and the data position (offset) within the ECC frame in the address conversion table 50 (FIG. 8) (S112).

[0096] The CPU 54 calculates the headers H0-H3 to be inserted into the data streams D0-D3 (S114). Since the start position of the first data stream D0 is the start position of the ECC frame, the header H0 is always 0. Therefore, the header H0 is not necessary, but adding a header makes it possible to unify the format of the four ECC frames. Therefore, the decoding process of the ECC decoder 64 can be standardized.

[0097] If the first data stream D0 is 1110 bytes, the second data stream D1 is placed in the latter half (10 bytes) of the overlapping area (128 bytes) of ECC frames 0 and 1. The start position of the second data stream D1 is 118 (=128-10) bytes from the start of ECC frame 1, so the header H1 is 118. The remaining headers H2 and H3 are generated in a similar manner. Figure 11(c) shows an example of the arrangement of data streams and headers in an ECC frame.

[0098] The CPU 54 generates ECC parities P0-P3 for the data streams D0-D3 and headers H0-H3, respectively, and inserts them into the ECC frames 0-3 (S116). Two adjacent ECC frames partially overlap, and the data in the overlapping area is used to generate the parity for the two adjacent ECC frames.

[0099] The CPU 54 writes the four ECC frames thus generated as one page of data to the NAND flash memory 12 via the NAND I / F circuit 56 (S118). The data is written to the NAND flash memory 12 (S118). An example of a page written to the NAND flash memory 12 is the same as that shown in FIGS. 6(a) and 6(b).

[0100] Fig. 12 is a flowchart for explaining an example of a read process according to the first embodiment. Fig. 13 is a diagram for explaining an example of a data decompression process according to the first embodiment.

[0101] The CPU 54 receives the read command sent from the host 32 (S202).

[0102] The CPU 54 determines whether or not data at the host address specified by the read command is stored in the write buffer 46 (S204).

[0103] When the CPU 54 determines that the data at the host address is stored in the write buffer 46 (S204; YES), it transfers the data to the host 32 (S206).

[0104] When the CPU 54 determines that the data of the host address is not stored in the write buffer 46 (S204; NO), it reads the ECC frame ID and offset corresponding to the host address from the address conversion table 50 (S208). Figure 13(a) shows an example of a page written to the NAND flash memory 12. Figure 13(a) is the same as that shown in Figures 6(a) and (b).

[0105] The CPU 54 reads the ECC frame indicated by the ECC frame ID from the NAND flash memory 12 via the NAND I / F circuit 56 (S210). Figure 13(b) shows an example of the read ECC frame. Each ECC frame also includes data of the adjacent ECC frame.

[0106] The CPU 54 performs error correction processing on the ECC frame based on the parity included in the ECC frame by the ECC decoder 66 (S212). Fig. 13(c) shows an example of the ECC frame after the error correction processing.

[0107] The CPU 54 reads the header from the ECC frame (S214). The CPU 54 reads the data stream from the ECC frame based on the header (S216). Figure 13(d) shows an example of the data streams D1 and D2.

[0108] The CPU 54 decompresses the data stream using the decompression circuit 62 to obtain multiple pieces of data (uncompressed data) (S218). FIG. 13(e) shows an example of multiple pieces of uncompressed data. Since the decompression circuit 62 cannot recognize the end of the data stream, it uses an algorithm that allows decompression even if the exact data size is unknown. In the case of a method that compresses 8 bytes of 0 to 1 bit, decompression processing is possible even if the size of the compressed data is unknown. When using a decompression method that requires the exact size of the compressed data, the data can be arranged so that the header is included in the overlapping area.

[0109] The CPU 54 refers to the address conversion table 50, selects the data indicated by the offset from the acquired data, and transfers it to the host 32 (S220).

[0110] The CPU 54 notifies the host 32 of the completion of the read (S222). This notification may be omitted.

[0111] Even if the memory system 10 of the first embodiment decompresses compressed data without recognizing the end of the compressed data and obtains excess uncompressed data, the excess uncompressed data is not selected because an offset pointing to valid data is written in the address conversion table 50 at the write process stage. Therefore, the memory system 10 can transfer only correct data to the host 32 (S220).

[0112] According to the first embodiment, the ECC frame includes an overlap area, and the overlap area includes data streams of two ECC frames, so that the ECC frame does not include an invalid area, and the storage area can be used efficiently.

[0113] Second embodiment FIG. 14 is a diagram for explaining a specific example of the configuration of an ECC frame in the memory system 10 according to the second embodiment. In the first embodiment, the ECC frame other than the overlap area includes parity. In the second embodiment, two types of parity p, P are calculated. The overlap area includes a second type of parity p. The ECC frame other than the overlap area includes a first type of parity P and a second type of parity p. An example of the first type of parity p is horizontal parity. An example of the second type of parity P is vertical parity.

[0114] As in FIG. 1 and FIG. 6, one page includes four ECC frames, and two adjacent ECC frames among the four ECC frames are stored in an overlapping manner. In each ECC frame, the data stream D is divided into a predetermined size. The area of ​​the ECC frame other than the overlap area includes data of a plurality of divided areas. The memory system 10 calculates horizontal parity p for each divided area. The horizontal parity p is adjacent to the data of the divided area. The overlap area of ​​ECC frame 0 includes the end part of data stream 0 and the start part of data stream 1. The size of the first data D0 of ECC frame 0 is equal to the size of the data included in the overlap area. The memory system 10 calculates vertical parity P for data streams 0 and 1 in the ECC frame. The vertical parity P is adjacent to the parity p of the first data D0 in ECC frame 0. In ECC frames 1-3, the vertical parity P is adjacent to the first overlap area.

[0115] In the second embodiment, the overlapping area includes horizontal parity p that is shared by two ECC frames. Therefore, it is not necessary to store the parity used in one ECC frame and the parity used in the other ECC frame separately, and the size of the parity can be reduced.

[0116] Third embodiment 15 is a diagram for explaining a specific example of the configuration of an ECC frame in the memory system 10 according to the third embodiment. In the first and second embodiments, four ECC frames are linked to each other using an overlapping area, but in the third embodiment, two ECC frames are linked to each other using an overlapping area. FIG. 15 shows a specific example of the configuration of ECC frames 0 and 1.

[0117] ECC frame 0 includes data streams D0 and D1, and parity P0. Parity P0 is calculated from data streams D0 and D1, and the size of parity P0 is constant. The beginning of ECC frame 0 includes parity P0. The overlapping area includes the end of data stream D0 and the beginning of data stream D1. Parity P0, data streams D0, and D1 are arranged in ascending address order. As a result, parity P0 and data streams D0 and D1 are written and read in this order.

[0118] ECC frame 1 includes data streams D0, D1, and parity P1. Parity P1 is calculated from data streams D0, D1, and the size of parity P1 is constant. The end of ECC frame 0 includes parity P1. The overlapping area includes the end of data stream D0 and the beginning of data stream D1. Parity P1, data streams D1, D0 are arranged in descending address order. As a result, parity P1, data streams D1, D0 are written and read in this order. Alternatively, the write and read order may be in ascending address order, and the data order may be changed, for example, at the ECC processing stage.

[0119] In the third embodiment, the start position of the data stream D is shifted from the end of the ECC frame by the amount of the parity, which eliminates the need for a header and increases storage capacity.

[0120] In the example of FIG. 15, the end position and size of the data stream cannot be determined, but as explained in the first embodiment, this does not pose a problem if a decompression algorithm that can perform decompression without using the exact data size is used.

[0121] Fourth embodiment In the above embodiment, when an ECC frame is read, a part of the data stream of the adjacent ECC frame is also read. Therefore, the amount of data transferred from the NAND flash memory 12 to the controller 42 when reading one ECC frame increases slightly. However, when ECC frames having overlapping parts are read continuously, the amount of data transferred from the NAND flash memory 12 to the controller 42 can be reduced by reading the overlapping area only once.

[0122] 16 is a diagram for explaining an example of an operation of sequentially reading four consecutive ECC frames 0-3 in the fourth embodiment. After reading to the end of ECC frame 0, the memory system 10 reads from header H1 adjacent to the overlapping area of ​​ECC frame 1. After reading to the end of ECC frame 1, the memory system 10 reads from header H2 adjacent to the overlapping area of ​​ECC frame 2. After reading to the end of ECC frame 2, the memory system 10 reads from header H3 adjacent to the overlapping area of ​​ECC frame 3.

[0123] In this way, in each ECC frame, the overlapping area located at the beginning is read only once, not twice, and the amount of data transferred three times for the overlapping area can be reduced.

[0124] Two or more of the first to fourth embodiments may be combined.

[0125] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0126] 12...NAND type flash memory, 42...controller, 44...DRAM, 46...write buffer, 48...read buffer, 50...address conversion table, 54...CPU, 60...compression circuit, 62...expansion circuit, 64...ECC encoder, 66...ECC decoder

Claims

1. a non-volatile memory device; a controller for writing the first error correction frame and the second error correction frame to the memory device; the first error correction frame and the second error correction frame include an overlapping area, an area of ​​the first error correction frame other than the overlap area includes first data and first error correction data; an area of ​​the second error correction frame other than the overlap area includes second data and second error correction data; The overlap region includes a portion of the first data and a portion of the second data.

2. the first error correction frame and the second error correction frame have a fixed length; the size of the first data is a first variable-length size; 2. The memory system according to claim 1, wherein the size of said second data is a second variable length size.

3. 2. The memory system according to claim 1, wherein said second error correction frame further includes a header indicating a leading position of a portion of said second data.

4. 2. The memory system according to claim 1, wherein said overlapping area further includes a header indicating a beginning position of a portion of said second data.

5. the size of the first data is variable length; 2. The memory system according to claim 1, wherein the maximum value of the variable length size is equal to or smaller than the size of the overlapping area.

6. the controller includes a compression circuit, and compresses one or more unit data by the compression circuit to generate one or more variable-length compressed data; the first data includes the one or more variable length compressed data; 2. The memory system according to claim 1, wherein a maximum value of a size of each of said one or more variable-length compressed data is equal to or smaller than a size of said overlap region.

7. the maximum value of the size of the first data is a first size; the maximum value of the size of the second data is the sum of the second size and the third size; 2. The memory system according to claim 1, wherein the second size is the smaller of a difference between a size of the first data and the first size and a size of the overlapping area.

8. The memory system of claim 1 , wherein the controller generates the first error correction data based on the first data and a portion of the second data.

9. 2. The memory system according to claim 1, wherein said controller performs error correction processing on said first data based on said first error correction data, said first data, and a portion of said second data.

10. the controller determines third error correction data based on the first data and a portion of the second data; The memory system of claim 1 , wherein the overlapping area stores the third error correction data.

11. the controller performs an error correction process on the first data based on the third error correction data and the first data; 11. The memory system according to claim 10, wherein an error correction process is performed on the second data based on the third error correction data and the second data.

12. The order of the storage position of the first error correction data and the storage position of the first data in the first error correction frame is as follows:

2. The memory system according to claim 1, wherein an order of a storage location of the second error correction data in the second error correction frame is different from an order of a storage location of the second data.

13. The memory system according to claim 1 , wherein the controller reads the overlapping area only once when reading the first error correction frame and the second error correction frame consecutively.

14. Generate first data and second data; generating a first error correction frame and a second error correction frame that partially overlap each other; calculating first error correction data from the first data and the data in the overlapping area; calculating second error correction data from the second data and the data in the overlapping area; an area other than the overlap area of ​​the first error correction frame includes the first data and the first error correction data; an area other than the overlap area of ​​the second error correction frame includes the second data and the second error correction data; the overlapping region includes a portion of the first data and a portion of the second data, A method of writing the first error correction frame and the second error correction frame to a non-volatile memory device.

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