Semiconductor device and imaging device

Abstract

To suppress facets.SOLUTION: A semiconductor device includes: an MIM structure that includes a lower electrode and an upper electrode; an upper wiring layer; and a via that connects the upper electrode and the upper wiring layer. The upper wiring layer includes: a first wiring pattern that extends so as not to cover the via; and a second wiring pattern that has a width narrower than a width of the first wiring pattern and protrudes and extends from the first wiring pattern, so as to cover the via. The via connects the upper electrode and the second wiring pattern.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and an imaging device. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor device including an MIM capacitor including a lower electrode and an upper electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-48340 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide electrical contact to a MIM structure, such as a MIM capacitor, vias are provided connecting the wiring pattern of the upper wiring layer to the top electrode of the MIM structure, which can result in widening facets as the vias extend upward, thereby degrading the electrical performance of the MIM structure.

[0005] One aspect of the present disclosure suppresses faceting. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure comprises an MIM structure including a lower electrode and an upper electrode, an upper wiring layer, and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes a first wiring pattern extending so as not to cover the via, and a second wiring pattern having a width narrower than that of the first wiring pattern and extending protruding from the first wiring pattern so as to cover the via, and the via connects the upper electrode and the second wiring pattern.

[0007] An imaging device according to one aspect of the present disclosure comprises an MIM structure including a lower electrode and an upper electrode, an upper wiring layer, and a via connecting the upper electrode and the upper wiring layer, wherein the upper wiring layer includes a first wiring pattern extending so as not to cover the via, and a second wiring pattern having a width narrower than that of the first wiring pattern and extending protruding from the first wiring pattern so as to cover the via, and the via connects the upper electrode and the second wiring pattern. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing an example of a schematic configuration of a semiconductor device 1 according to an embodiment. [Diagram 2] 1 is a diagram showing an example of a schematic configuration of a semiconductor device 1 according to an embodiment. [Diagram 3] 1 is a diagram showing an example of a schematic configuration of a semiconductor device 1 according to an embodiment. [Figure 4] 2A to 2C are diagrams illustrating an example of a manufacturing method for the semiconductor device 1. [Diagram 5] 2A to 2C are diagrams illustrating an example of a manufacturing method for the semiconductor device 1. [Figure 6] 2A to 2C are diagrams illustrating an example of a manufacturing method for the semiconductor device 1. [Figure 7] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 8] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 9] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 10] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 11] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 12] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 13] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 14] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 15]13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 16] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 17] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 18] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 19] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 20] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 21] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Figure 22] 13A and 13B are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. [Diagram 23] 1 is a diagram showing an example of a schematic configuration of a semiconductor device 1 having a stack structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same elements are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0010] The present disclosure will be described in the following order. 1. Embodiment 2. Variations 3. Summary

[0011] 1. Embodiment 1 to 3 are diagrams showing an example of a schematic configuration of a semiconductor device 1 according to an embodiment. The semiconductor device 1 includes a lower wiring layer 2, a metal-insulator-metal (MIM) layer 3, an upper wiring layer 4, vias 5, vias 6, and an insulating material 7.

[0012] An XYZ coordinate system is also shown. The X-axis and Y-axis directions (XY plane directions) correspond to the surface directions of the lower wiring layer 2, MIM layer 3, and upper wiring layer 4. The Z-axis direction corresponds to the thickness direction (height direction) of the layers. The Z-axis direction is also referred to as the up-down direction. The positive direction of the Z-axis corresponds to the upward direction, and the negative direction of the Z-axis corresponds to the downward direction. The lower wiring layer 2, MIM layer 3, and upper wiring layer 4 are located in this order in the positive direction of the Z-axis.

[0013] Fig. 1 shows a schematic planar layout of several elements when the semiconductor device 1 is viewed in a plan view (when viewed in the negative direction of the Z axis). Fig. 2 and Fig. 3 show schematic cross sections when viewed along lines II-II and III-III in Fig. 1. For ease of understanding, wiring patterns 41, 42 and insulating material 7 (all of which will be described later) are shown hatched in Fig. 1 as well.

[0014] The lower wiring layer 2 is a wiring layer located below (on the negative side of the Z-axis) the MIM layer 3, and in this example, is provided on the opposite side of the upper wiring layer 4 across the MIM layer 3. Examples of wiring patterns included in the lower wiring layer 2 include a wiring pattern 21 and a wiring pattern 22. The material (metal material) of the wiring pattern of the lower wiring layer 2 is copper (Cu), aluminum (Al), tungsten (W), or the like.

[0015] The MIM layer 3 is provided between the lower wiring layer 2 and the upper wiring layer 4. The MIM layer 3 includes an MIM structure 30.

[0016] The MIM structure 30 includes a lower electrode 31, a dielectric 32, and an upper electrode 33. The lower electrode 31, the dielectric 32, and the upper electrode 33 are laminated in this order in the positive direction of the Z axis. The dielectric 32 is provided between the lower electrode 31 and the upper electrode 33 so that the lower electrode 31 and the upper electrode 33 are capacitively coupled to each other while electrically isolating them. The MIM structure 30 can also be called an MIM capacitor or the like.

[0017] The MIM structure 30 includes a trench portion 300. The trench portion 300 is configured to bring the lower electrode 31 close to the lower wiring layer 2. The lower electrode 31 is connected to the wiring pattern 21 of the lower wiring layer 2 at the trench portion 300. To the extent not inconsistent, the connection may be interpreted to include an electrical connection.

[0018] The MIM layer 3 may include several films. One example of the film is a metal diffusion prevention film. As such films, films 34, 35, and 36 are illustrated with reference numerals. The film 34 is provided so as to cover a portion of the upper surface (the surface on the Z-axis positive direction side) of the lower wiring layer 2 other than the wiring pattern 21. The film 34 may be an insulating film such as a TEOS film. The film 35 is provided so as to cover the lower electrode 31. The film 35 may be a conductive film (e.g., SiC) and electrically connects the lower electrode 31 to the wiring pattern 21 of the lower wiring layer 2. The film 36 is provided so as to cover a portion of the upper electrode 33 other than the via 5. The film 36 may be an insulating film such as P-Sin, SiO2, SiN, SiCN, etc.

[0019] At the end of the MIM structure 30 (end in the XY plane direction), the end of the lower electrode 31 and the end of the upper electrode 33 are misaligned. Specifically, the lower electrode 31 extends further outward than the upper electrode 33. When the semiconductor device 1 is viewed in a plan view (when viewed in the negative Z-axis direction), the upper electrode 33 is located inside the lower electrode 31. By misaligning the end of the lower electrode 31 and the end of the upper electrode 33, it becomes easier to ensure electrical isolation between the lower electrode 31 and the upper electrode 33 than when they are aligned. However, for this reason, the MIM structure 30 has a step portion 30s at its end. At the step portion 30s, the lower electrode 31 extends further outward than the upper electrode 33.

[0020] The upper wiring layer 4 is a wiring layer located above (on the positive side of the Z-axis) the MIM layer 3. The upper wiring layer 4 includes a wiring pattern 41, a wiring pattern 42, and a wiring pattern 43. When there is no particular distinction between these, they will be simply referred to as the wiring patterns of the upper wiring layer 4. The material of the wiring pattern of the upper wiring layer 4 may be the same as the material of the wiring pattern of the lower wiring layer 2.

[0021] The wiring pattern 41 is a first wiring pattern that extends so as not to cover the vias 5. The wiring pattern 42 is a second wiring pattern that extends so as to cover the vias 5. The wiring pattern 42 has a width narrower than the width of the wiring pattern 41 (the length in the X-axis direction in this example) and extends, protruding from the wiring pattern 41 (in this example, in the negative Y-axis direction). When viewed in a plan view, the wiring pattern 41 and the wiring pattern 42 may have a convex layout that protrudes toward the vias 5 as a whole.

[0022] The wiring pattern 42 includes an extending portion 421 and a tip portion 422. Of the extending portion 421 and the tip portion 422, the tip portion 422 covers the via 5. The extending portion 421 is connected between the wiring pattern 41 and the tip portion 422.

[0023] Both end faces of the tip portion 422 are referred to as side face 422a and side face 422b and are illustrated. Side face 422a and side face 422b are a pair of side faces facing each other. The end face at the tip of the tip portion 422 is referred to as tip face 422c and is illustrated. Tip face 422c connects side face 422a and side face 422b at the tip of the tip portion 422. Further details of the wiring pattern 42 will be described later.

[0024] The wiring pattern 43 is a third wiring pattern provided separately from the wiring patterns 41 and .

[0025] The via 5 connects the upper electrode 33 of the MIM structure 30 and the wiring pattern 42 of the upper wiring layer 4. More specifically, the via 5 connects the upper electrode 33 and the tip portion 422 of the wiring pattern 42. The material of the via 5 may be the same as the material of the wiring patterns of the lower wiring layer 2 and the upper wiring layer 4.

[0026] The via 5 is connected to a portion of the upper electrode 33 of the MIM structure 30 other than the trench portion 300 (for example, a portion somewhat distant from the trench portion 300). In this example, the via 5 is connected to the upper electrode 33 near the end of the MIM structure 30.

[0027] The side surfaces of the via 5 are referred to as side surface 5a, side surface 5b, side surface 5c, and side surface 5d and are illustrated. The side surface 5a is the side surface of the via 5 on the trench portion 300 side (located on the trench portion 300 side). The side surfaces 5b and 5c are the side surfaces of the via 5 on the step portion 30s side.

[0028] In the semiconductor device 1, the wiring patterns 41 and 42 of the upper wiring layer 4 are provided so as to suppress the facet of the via 5. The facet indicates that the via 5 widens as it goes upward, and more specifically, may be understood to indicate the widened portion. The length of the facet (length in the XY plane direction) is also referred to as the "facet width." The facet width may be the length of the facet at the upper end of the via 5.

[0029] The principle will be described later, but the facets of the via 5 are suppressed at three side surfaces, the side surface 5a, the side surface 5b, and the side surface 5c of the via 5. The facets of the via 5 are not suppressed at the side surface 5d of the via 5. The facet widths of the side surfaces 5a, 5b, and 5c of the via 5 are smaller than the facet width of the side surface 5d, and are substantially zero in the example shown in FIG. 2 and FIG. 3. The side surfaces 5a, 5b, and 5c extend in the same direction as the Z-axis direction. The side surface 5d extends at an angle with respect to the Z-axis direction.

[0030] The via 6 is a via different from the via 5, and connects the wiring pattern 43 of the upper wiring layer 4 to the lower wiring layer 2. More specifically, the via 6 connects the wiring pattern 43 of the upper wiring layer 4 to the wiring pattern 22 of the lower wiring layer 2. The material of the via 6 may be the same as the materials of the lower wiring layer 2, the upper wiring layer 4, and the via 5.

[0031] The via 6 has a height different from the height (length in the Z-axis direction) of the via 5, and more specifically, has a height greater than the height of the via 5. A portion of the via 6 that is located at the same height as the via 5 is referred to as a via 61. A portion of the via 6 other than the via 61 is referred to and illustrated as a via 62. Of the vias 61 and 62, the via 61 is connected to the wiring pattern 43 of the upper wiring layer 4. The via 62 is connected to the wiring pattern 22 of the lower wiring layer 2.

[0032] The insulating material 7 is provided so as to fill the spaces between the elements of the semiconductor device 1 described above. For example, the insulating material 7 is provided so as to fill the spaces between the wiring patterns of the lower wiring layer 2. The insulating material 7 is provided so as to fill the portions of the MIM layer 3 other than the MIM structure 30, the film 34, the film 35, and the film 36. The insulating material 7 is provided so as to fill the spaces between the wiring patterns of the upper wiring layer 4.

[0033] Further description will be given of the wiring pattern 42 of the upper wiring layer 4. When the semiconductor device 1 is viewed in plan, a tip surface 422c of a tip portion 422 of the wiring pattern 42 is adjacent to a corresponding side surface of the via 5, in this example, a side surface 5c (a side surface on the step portion 30s side).

[0034] The above-mentioned "adjacent" may mean that the distance between the tip surface 422c and the side surface 5c is smaller than the facet width of the side surface 5d described above. "Adjacent" may be interpreted to include the meaning that the distance between the tip surface 422c and the side surface 5c is substantially zero. For example, even if the design value of the distance between the tip surface 422c and the side surface 5c is zero, but the actual distance is not zero due to variation, the distance may be interpreted as being substantially zero.

[0035] In addition, a side surface 422a of the tip portion 422 of the wiring pattern 42 is adjacent to a corresponding side surface of the via 5, which is the side surface 5a (the side surface on the trench portion 300 side) in this example. A side surface 422b of the tip portion 422 of the wiring pattern 42 is adjacent to a corresponding side surface of the via 5, which is the side surface 5b (the side surface on the step portion 30s side) in this example.

[0036] It can be said that the tip 422 of the wiring pattern 42 has a rectangular shape in which the side surface 422a, the side surface 422b and the tip surface 422c are in contact with the insulating material 7. Such tip 422 of the wiring pattern 42 covers the via 5, thereby suppressing facets of the side surface 5a, the side surface 5b and the side surface 5c of the via 5. The reason for this will be explained together with the manufacturing method of the semiconductor device 1.

[0037] 4 to 6 are diagrams showing an example of a method for manufacturing the semiconductor device 1. (A) and (B) in each diagram correspond to the portions of FIG. 2 and FIG.

[0038] It is assumed that the process of preparing the lower wiring layer 2 and the MIM layer 3 and providing (e.g., depositing) the insulating material 7 so as to cover them has already been completed. As will be described next, dry etching is performed to obtain the shape of the wiring pattern of the vias 6, the vias 5, and the upper wiring layer 4. Hereinafter, the dry etching process may also be simply referred to as processing.

[0039] 4, the insulating material 7 is processed to obtain the shape of the via 62 of the via 6. The void portion obtained by this processing is referred to as the void portion 62r and is illustrated.

[0040] As shown by the white arrows in FIG. 5, the insulating material 7 is further processed to obtain the shape of the via 5 and the shape of the via 61 of the via 6. The voids obtained by this processing are referred to as voids 5r and 61r and are illustrated. The voids 61r are connected to the void 62r, and are collectively referred to as voids 6r and are illustrated. The voids 6r may correspond to the shape of the via 6.

[0041] As shown by the white arrows in FIG. 6, the insulating material 7 is further processed and the film 36 is processed to obtain the shapes of the wiring pattern 41, the wiring pattern 42, and the wiring pattern 43. The voids obtained by this processing are called and illustrated as voids 41r, 42r, and 43r. The voids 41r and 42r are connected to each other. More specifically, the void 42r includes voids 421r and 422r corresponding to the shapes of the extension portion 421 and the tip portion 422 of the wiring pattern 42. The voids 421r and 422r are connected to each other. The void 422r is connected to the void 5r. Moreover, the void 43r is connected to the void 61r of the void 6r.

[0042] During the processing shown in Fig. 6, the insulating material 7 may be scraped off from the upper edge periphery of the gap 5r and the gap 61r. In particular, regarding the gap 5r, the portion of the upper edge periphery of the gap 5r in the insulating material 7 that is susceptible to the effect of dry etching for obtaining the gap 421r and the gap 41r that are connected to the gap 422r is scraped off. In this example, the portion of the upper edge periphery of the gap 5r in the insulating material 7 that is located below the gap 421r is scraped off. In that portion, the gap 5r has a shape that widens as it goes upward.

[0043] In other parts, the gap 5r does not have a shape that widens toward the top. This is because, as described above with reference to Figs. 1 to 3, the wiring pattern 42 (extension 421 and tip 422) extends from the wiring pattern 41 with a width narrower than that of the wiring pattern 41. This reduces the influence of the dry etching process for obtaining the shape of the wiring pattern 42 on the upper edge periphery of the gap 5r compared to when the wiring pattern 42 has the same width as the wiring pattern 41. More specifically, as described above, when the semiconductor device 1 is viewed in plan, the side 422a, side 422b, and tip surface 422c of the tip 422 of the wiring pattern 42 are adjacent to the side 5a, side 5b, and side 5c of the via 5. The dry etching process for obtaining such a shape of the wiring pattern 42 does not remove the portion of the upper edge periphery of the gap 5r that corresponds to the side 5a, side 5b, and side 5c of the via 5.

[0044] As described above, dry etching is performed to obtain the voids 6r, 5r, 41r, 42r, and 43r. In other words, dry etching is performed to obtain the overall shapes of the vias 6, 5, the wiring patterns 41, 42, and 43 of the upper wiring layer 4, which have been described above with reference to Figs. 1 to 3. Thereafter, a metal material is provided (deposited as a film, etc.) so as to fill the voids 6r, 5r, 41r, 42r, and 43r, thereby forming the vias 6, 5, the wiring patterns 41, 42, and 43. Since the shape of the vias 5 is the same as the shape of the voids 5r, the vias 5 with suppressed facets on the side surfaces 5a, 5b, and 5c are obtained as described above.

[0045] The technical significance of suppressing facets of the via 5 will be described. If the facets are large (if the facet width is large), the upper electrode 33 and the lower electrode 31 of the MIM structure 30 may become conductive, and the electrical performance of the MIM structure 30 may deteriorate. For example, if facets are generated such that the via 5 spreads toward the step portion 30s of the MIM structure 30, the electrical separation between the upper electrode 33 and the lower electrode 31 of the MIM structure 30 may be weakened due to interference of the via 5 with the step portion 30s, and leakage or the like may occur. If facets are generated such that the via 5 spreads toward the trench portion 300 of the MIM structure 30, a similar problem may occur.

[0046] By suppressing the facets of the via 5, it is possible to suppress the deterioration of the electrical performance of the MIM structure 30 as described above. That is, by suppressing the facets of the side surface 5a of the via 5, it is possible to suppress the facets of the via 5 that spread toward the trench portion 300. By suppressing the facets of the side surface 5b of the via 5, it is possible to suppress the facets of the via 5 that spread toward the step portion 30s. By suppressing the facets of the side surface 5c of the via 5, it is possible to suppress the facets of the via 5 that spread toward the step portion 30s.

[0047] 2. Variations The disclosed technology is not limited to the above-described embodiment, and some modified examples will be described.

[0048] The wiring pattern of the upper wiring layer 4 may be designed in various layouts within a range that can obtain the effect of suppressing facets of the vias 5. Some examples will be described with reference to FIGS.

[0049] 7 to 22 are diagrams showing modified examples of the wiring pattern of the upper wiring layer 4. The area of ​​the wiring pattern 41 may be larger or smaller than the area of ​​the wiring pattern 41 shown in FIG. 1 described in the previous embodiment. The area of ​​the wiring pattern 41 is determined by, for example, the length in the X-axis direction and the length in the Y-axis direction. FIGS. 7 to 21 show various wiring patterns 41 having different lengths, particularly in the Y-axis direction. FIG. 22 shows a wiring pattern 41 having different lengths in the X-axis direction.

[0050] The extending portion 421 of the wiring pattern 42 may be longer or shorter than the extending portion 421 shown in Fig. 1 described in the previous embodiment. For example, Fig. 8, Fig. 12 to Fig. 14, Fig. 17 and Fig. 18 show a wiring pattern 42 having a relatively long extending portion 421. The length of the extending portion 421 may be zero, and in that case, the wiring pattern 42 may include only a tip portion 422, as shown in Fig. 10, for example.

[0051] The extending direction of the extending portion 421 of the wiring pattern 42 is not limited, and the extending portion 421 may include a bent portion, a curved portion, etc. For example, as shown in Fig. 11 to Fig. 18, the extending portion 421 of the wiring pattern 42 may protrude and extend from the wiring pattern 41, bend, and further extend.

[0052] The wiring pattern 42 may protrude in any direction from any portion of the wiring pattern 41. For example, as shown in Figures 15 to 18 and 21, the wiring pattern 42 may protrude in the positive direction of the Y axis from an edge of the wiring pattern 41 on the positive side of the Y axis. As shown in Figure 22, the wiring pattern 42 may protrude in the positive direction of the X axis from an edge of the wiring pattern 41 on the positive side of the X axis.

[0053] 19 and 20, the wiring pattern 42 may be connected to two different portions of the wiring pattern 41. Even with the wiring pattern 42 as shown in the drawings, facets on the two side surfaces of the via 5 are suppressed.

[0054] In the above embodiment, a case has been described as an example in which the side surface 422a of the tip portion 422 of the wiring pattern 42 is adjacent to the side surface 5c of the via 5 on the stepped portion 30s side when the semiconductor device 1 is viewed in plan. However, the side surface 422a of the tip portion 422 may be adjacent to the side surface of the via 5 on the trench portion 300 side.

[0055] In one embodiment, the semiconductor device 1 may be an imaging device. In the following, the imaging device is assumed to be a solid-state imaging device such as an image sensor. For example, the semiconductor device 1 includes a pixel array section including a plurality of pixel circuits, and peripheral circuits that drive the pixel array section and read out pixel signals.

[0056] The pixel circuit includes one or more photoelectric conversion units, one or more transistors, one or more capacitors, etc. The photoelectric conversion unit includes a photoelectric conversion element such as a photodiode. The transistor discharges (resets) the charge accumulated in the photoelectric conversion unit, converts the charge accumulated in the photoelectric conversion unit into a pixel signal, and outputs the pixel signal. The capacitor, for example, converts the charge of the photoelectric conversion unit into a voltage, and accumulates the charge in cooperation with the photoelectric conversion unit. The MIM structure 30 described above is used as at least some of the capacitors.

[0057] In one embodiment, the semiconductor device 1 may have a stack structure in which two semiconductor chips are stacked. The two semiconductor chips are attached to each other so as to be electrically connected. The description will be made with reference to FIG. 23 as well.

[0058] 23 is a diagram showing an example of a schematic configuration of a semiconductor device 1 having a stack structure. The semiconductor device 1 includes a semiconductor chip 100 and a semiconductor chip 200. The semiconductor chip 100 and the semiconductor chip 200 are stacked in the Z-axis direction.

[0059] The semiconductor chip 100 includes, for example, the pixel array section described above. The MIM structure 30 described above is used as a capacitor therein.

[0060] The semiconductor chip 200 includes, for example, the peripheral circuits described above. Among the components of the semiconductor chip 200, the wiring layer 8 is illustrated with a reference symbol. Several wiring patterns included in the wiring layer 8 are illustrated and referred to as wiring pattern 81, wiring pattern 82, and wiring pattern 83. The material of the wiring pattern of the wiring layer 8 may be the same as the material of the wiring pattern of the lower wiring layer 2, the wiring pattern of the upper wiring layer 4, the vias 5, and the vias 6.

[0061] The semiconductor chips 100 and 200 are bonded so that the wiring pattern of the upper wiring layer 4 of the semiconductor chip 100 and the wiring pattern of the wiring layer 8 of the semiconductor chip 200 are in surface contact with each other. In this example, the semiconductor chips 100 and 200 are bonded so that the wiring patterns 41, 42, and 43 of the upper wiring layer 4 are in surface contact with the wiring patterns 81, 82, and 83 of the wiring layer 8.

[0062] The operating voltage of the semiconductor chip 100 and the operating voltage of the semiconductor chip 200 may be different from each other. For example, the operating voltage of the semiconductor chip 200 may be higher than the operating voltage of the semiconductor chip 100. The operation of the semiconductor chip 200 may affect the semiconductor chip 100. For example, an electromagnetic field generated in the semiconductor chip 200 may cause hot carriers or noise to be generated in the semiconductor chip 100.

[0063] In order to suppress the occurrence of the above-mentioned hot carriers, noise, and the like, the semiconductor chip 100 is designed so that the wiring pattern of the upper wiring layer 4 covers as much area as possible (so that the area is large). In addition, only the wiring pattern 42 may be designed to have a narrower width than the wiring pattern 41 so that the facet of the via 5 can be suppressed.

[0064] 3. Summary The above-described techniques are specified, for example, as follows. One of the techniques disclosed is a semiconductor device 1 (for example, a solid-state imaging device). As described with reference to Figs. 1 to 23 and the like, the semiconductor device 1 includes an MIM structure 30 including a lower electrode 31 and an upper electrode 33, an upper wiring layer 4, and a via 5 connecting the upper electrode 33 and the upper wiring layer 4. The upper wiring layer 4 includes a wiring pattern 41 (first wiring pattern) extending so as not to cover the via 5, and a wiring pattern 42 (second wiring pattern) having a width narrower than the wiring pattern 41 and extending protruding from the wiring pattern 41 so as to cover the via 5, and the via 5 connects the upper electrode 33 and the wiring pattern 42. For example, as described with reference to Figs. 1, 2, and 7 to 22 and the like, the wiring pattern 42 includes a tip portion 422 covering the via 5, and the via 5 may connect the upper electrode 33 and the tip portion 422 of the wiring pattern 42. As described with reference to FIGS. 1, 2, 8, 9, and 11 to 22, the wiring pattern 42 may include an extension portion 421 connected between the wiring pattern 41 and the tip portion 422.

[0065] According to the semiconductor device 1 described above, faceting of the via 5 can be suppressed more effectively than in the case where the wiring pattern 42 has the same width as the wiring pattern 41, for example.

[0066] 1 and 2, when viewed in a plan view, the tip surface 422c of the tip portion 422 of the wiring pattern 42 may be adjacent to the corresponding side surface 5c of the via 5. This makes it possible to suppress faceting of the side surface 5c of the via 5.

[0067] 1 and 2, the MIM structure 30 includes a step portion 30s at its edge where the lower electrode 31 extends further outward than the upper electrode 33, and in a plan view, a tip surface 422c of the tip portion 422 of the wiring pattern 42 may be adjacent to a side surface 5c of the via 5 on the step portion 30s side. This makes it possible to suppress facets in which the via 5 spreads toward the step portion 30s, and to suppress deterioration of the electrical performance of the MIM structure 30 that may occur due to interference of the via 5 with the step portion 30s, etc.

[0068] 1 and 3, etc., in plan view, the side surface 422a of the tip portion 422 of the wiring pattern 42 may be adjacent to the corresponding side surface 5a of the via 5, and the side surface 422b may be adjacent to the corresponding side surface 5b of the via 5. This makes it possible to suppress facets of the side surface 5a of the via 5 and to suppress facets of the side surface 5b.

[0069] 1 to 3, the MIM structure 30 includes the trench portion 300, and in plan view, the side surface 422a (one of a pair of side surfaces) of the tip portion 422 of the wiring pattern 42 may be adjacent to the side surface 5a of the via 5 on the trench portion 300 side. This makes it possible to suppress facets in which the via 5 spreads toward the trench portion 300 of the MIM structure 30, and to suppress deterioration of the electrical performance of the MIM structure 30 that may occur due to interference of the via 5 with the trench portion 300, etc.

[0070] 1 and 3, etc., in plan view, the side surface 42b (the other side surface of the pair of side surfaces) of the tip portion 422 of the wiring pattern 42 may be adjacent to the side surface 5b on the stepped portion 30s side of the via 5. This makes it possible to suppress faceting of the via 5 expanding toward the stepped portion 30s of the MIM structure 30, and to suppress deterioration of the electrical performance of the MIM structure 30 that may occur due to interference of the via 5 with the stepped portion 30s, etc.

[0071] 1 to 3, the semiconductor device 1 includes an insulating material 7 provided so as to fill the gaps between the wiring patterns (e.g., the wiring pattern 41 and the wiring pattern 42) of the upper wiring layer 4, and the tip portion 422 of the wiring pattern 42 may have a rectangular shape in which the side surfaces 422a and 422b (a pair of side surfaces) and the tip surface 422c are in contact with the insulating material 7. For example, by covering the via 5 with such a wiring pattern 42, facets on the side surfaces of the via 5 corresponding to the three sides of the side surfaces 422a, 422b, and the tip portion 422 can be suppressed.

[0072] As described with reference to Figs. 1 to 6, the semiconductor device 1 includes a lower wiring layer 2 provided on the opposite side of the upper wiring layer 4 across the MIM structure 30, and the upper wiring layer 4 includes a wiring pattern 43 (a third wiring pattern). The semiconductor device 1 may include a via 6 (another via) connecting the wiring pattern 43 of the upper wiring layer 4 to the lower wiring layer 2. The via 6, the via 5, the wiring pattern 41, the wiring pattern 42, and the wiring pattern 43 of the upper wiring layer 4 may be formed by providing a metal material after performing a dry etching process to obtain their overall shape. For example, it is possible to suppress faceting of the via 5 that may occur when the via 6, the via 5, the wiring pattern 41, the wiring pattern 42, and the wiring pattern 43 of the upper wiring layer 4 are formed at the same time in this manner.

[0073] Note that the effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0074] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0075] The present technology can also be configured as follows. (1) a MIM structure including a bottom electrode and a top electrode; An upper wiring layer; a via connecting the upper electrode and the upper wiring layer; Equipped with The upper wiring layer is a first wiring pattern extending so as not to cover the via; a second wiring pattern having a width narrower than that of the first wiring pattern and extending from the first wiring pattern so as to cover the via; Including, the via connects the upper electrode and the second wiring pattern; Semiconductor device. (2) the second wiring pattern includes a tip portion covering the via, the via connects the upper electrode and the tip of the second wiring pattern; The semiconductor device according to (1). (3) the second wiring pattern includes an extension portion connected between the first wiring pattern and the tip portion; The semiconductor device according to (2). (4) When viewed in a plan view, a tip surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via. The semiconductor device according to (2) or (3). (5) the MIM structure includes a step portion at an edge of the lower electrode extending outward beyond the upper electrode, When viewed in a plan view, the tip surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the step portion side. The semiconductor device according to (4). (6) When viewed in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via. The semiconductor device according to any one of (2) to (5). (7) The MIM structure includes a trench portion, When viewed in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the trench portion side. The semiconductor device according to (6). (8) the MIM structure includes a step portion at an edge of the lower electrode extending outward beyond the upper electrode, When viewed in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the step portion side. The semiconductor device according to (6) or (7). (9) the MIM structure includes a step portion at an edge of the lower electrode extending outward beyond the upper electrode, The MIM structure includes a trench portion, the side surfaces of the tip portion of the second wiring pattern are a pair of side surfaces, one of the pair of side surfaces is adjacent to a side surface of the via on the trench portion side, the other side of the pair of side surfaces is adjacent to the side surface of the via on the step portion side; The semiconductor device according to any one of (6) to (8). (10) an insulating material provided so as to fill spaces between the wiring patterns of the upper wiring layer; the tip portion of the second wiring pattern has a rectangular shape with a pair of side surfaces and a tip surface in contact with the insulating material; The semiconductor device according to any one of (2) to (9). (11) a lower wiring layer provided on the opposite side of the upper wiring layer with the MIM structure interposed therebetween; the upper wiring layer includes a third wiring pattern; the semiconductor device further includes another via that connects a third wiring pattern of the upper wiring layer and the lower wiring layer; The semiconductor device according to any one of (1) to (10). (12) the another via, the via, and the wiring pattern of the upper wiring layer are formed by providing a metal material after performing a dry etching process for obtaining their overall shapes; The semiconductor device according to (11). (13) a MIM structure including a bottom electrode and a top electrode; An upper wiring layer; a via connecting the upper electrode and the upper wiring layer; Equipped with The upper wiring layer is a first wiring pattern extending so as not to cover the via; a second wiring pattern having a width narrower than that of the first wiring pattern and extending from the first wiring pattern so as to cover the via; Including, the via connects the upper electrode and the second wiring pattern; Imaging device. [Explanation of symbols]

[0076] 1 Semiconductor device (imaging device) 2. Bottom wiring layer 21 Wiring Pattern 22 Wiring Pattern 3 MIM layer 30 MIM structures 30s step part 300 Trench Section 31 Lower electrode 32 Dielectrics 33 Upper electrode 34 membrane 35 membrane 36 membrane 4 Upper wiring layer 41 Wiring pattern (first wiring pattern) 41r void area 42 Wiring pattern (second wiring pattern) 42r void 421 Extension 421r void area 422 Tip 422a side 422b Side 422c Tip surface 422r void area 43 Wiring pattern (third wiring pattern) 43r void 5 Via 5a side 5b side 5c side 5d side 5r void area 6 via (another via) 6r void area 61 Via 61r void 62 Via 62r void 7. Insulation Materials 8 wiring layer 81 Wiring Pattern 82 Wiring Pattern 83 Wiring Pattern 100 Semiconductor Chips 200 Semiconductor Chips

Claims

1. a MIM structure including a bottom electrode and a top electrode; An upper wiring layer; a via connecting the upper electrode and the upper wiring layer; Equipped with The upper wiring layer is a first wiring pattern extending so as not to cover the via; a second wiring pattern having a width narrower than a width of the first wiring pattern and extending from the first wiring pattern so as to cover the via; Including, the via connects the upper electrode and the second wiring pattern; Semiconductor device.

2. the second wiring pattern includes a tip portion covering the via, the via connects the upper electrode and the tip of the second wiring pattern; The semiconductor device according to claim 1 .

3. the second wiring pattern includes an extension portion connected between the first wiring pattern and the tip portion; The semiconductor device according to claim 2 .

4. When viewed in a plan view, a tip surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via. The semiconductor device according to claim 2 .

5. the MIM structure includes a step portion at an edge of the MIM structure, the step portion being such that the lower electrode extends outward beyond the upper electrode; When viewed in a plan view, the tip surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the step portion side. The semiconductor device according to claim 4.

6. When viewed in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a corresponding side surface of the via. The semiconductor device according to claim 2 .

7. the MIM structure includes a trench portion, When viewed in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the trench portion side. The semiconductor device according to claim 6.

8. the MIM structure includes a step portion at an edge of the MIM structure, the step portion being such that the lower electrode extends outward beyond the upper electrode; When viewed in a plan view, a side surface of the tip portion of the second wiring pattern is adjacent to a side surface of the via on the step portion side. The semiconductor device according to claim 6.

9. the MIM structure includes a step portion at an edge of the MIM structure, the step portion being such that the lower electrode extends outward beyond the upper electrode; the MIM structure includes a trench portion, the side surfaces of the tip portion of the second wiring pattern are a pair of side surfaces, one of the pair of side surfaces is adjacent to a side surface of the via on the trench portion side, the other side of the pair of side surfaces is adjacent to the side surface of the via on the step portion side; The semiconductor device according to claim 6.

10. an insulating material provided so as to fill spaces between the wiring patterns of the upper wiring layer; the tip portion of the second wiring pattern has a rectangular shape with a pair of side surfaces and a tip surface in contact with the insulating material; The semiconductor device according to claim 2 .

11. a lower wiring layer provided on the opposite side of the MIM structure from the upper wiring layer; the upper wiring layer includes a third wiring pattern, the semiconductor device further includes another via connecting a third wiring pattern of the upper wiring layer and the lower wiring layer; The semiconductor device according to claim 1 .

12. the another via, the via, and the wiring pattern of the upper wiring layer are formed by providing a metal material after performing a dry etching process for obtaining their overall shapes; The semiconductor device according to claim 11.

13. a MIM structure including a bottom electrode and a top electrode; An upper wiring layer; a via connecting the upper electrode and the upper wiring layer; Equipped with The upper wiring layer is a first wiring pattern extending so as not to cover the via; a second wiring pattern having a width narrower than a width of the first wiring pattern and extending from the first wiring pattern so as to cover the via; Including, the via connects the upper electrode and the second wiring pattern; Imaging device.

Images