Semiconductor device

Abstract

To improve a protection function of a switching element by detecting consecutive occurrences of a minute short-circuit pulse.SOLUTION: A semiconductor device 1 includes a switching element 1a and a protection control circuit 1b. The switching element 1a operates a load by performing switching on the basis of an input signal Vin. The protection control circuit 1b protects the switching element 1a according to an operation state of the switching element 1a. The protection control circuit 1b detects a minute short-circuit pulse p2 having a pulse width w2 which is shorter than a pulse width w1 of a short circuit pulse p1 at the time when a voltage level of the short circuit pulse p1 exceeds a predetermined level Vth consecutively for a predetermined time, in the case where the switching element 1a is in a short-circuited state. Then, the protection control circuit 1b counts the number of times of consecutive occurrences of the minute short-circuit pulses p2, and protects the switching element 1a when having detected that the number of times of the consecutive occurrences has reached a predetermined number of times.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In recent years, there has been progress in the development of semiconductor devices called IPMs (Intelligent Power Modules), which incorporate switching elements, which are power semiconductors such as IGBTs (Insulated Gate Bipolar Transistors), and driving circuits for driving the switching elements. IPMs are provided with a protection function for protecting the switching elements.

[0003] Related techniques include, for example, a technique for changing the response time of an overcurrent protection circuit by utilizing an overcurrent detection signal from the overcurrent protection circuit (Patent Document 1). Also, a technique for determining an overheated state of a semiconductor device by the sum of a voltage according to the temperature of the semiconductor device and a voltage according to the current flowing through the semiconductor device (Patent Document 2). Furthermore, a technique for lowering the temperature protection level of a switching element according to an increase in the output current of a power conversion device has been proposed (Patent Document 3). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2002-280886 A [Patent Document 2] Patent Publication No. 2022-19128 [Patent Document 3] JP 2007-174832 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to improve the protection function of a switching element by detecting the successive occurrence of minute short-circuit pulses. [Means for solving the problem]

[0006] In order to solve the above problems, a semiconductor device is provided, which includes a switch element that operates a load by switching based on an input signal, and a protection control circuit that protects the switch element when it detects continuous occurrence of minute short-circuit pulses having a second pulse width shorter than a first pulse width of a short-circuit pulse that is output when the switch element is short-circuited. Effect of the Invention

[0007] According to one aspect, it is possible to improve the protection function of a switch element by detecting the successive occurrence of micro short-circuit pulses. [Brief description of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Diagram 2] 11 is a diagram showing an example of a state in which the number of consecutive occurrences of micro short-circuit pulses has reached a predetermined number. FIG. [Diagram 3] FIG. 13 is a diagram showing an example of a state in which a micro short-circuit pulse has not yet occurred. [Figure 4] 11 is a diagram showing an example of a state in which the number of consecutive occurrences of a micro short-circuit pulse does not reach a predetermined number. FIG. [Diagram 5] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device. [Figure 6] 11 is a diagram for explaining protection when the number of consecutive occurrences of micro short-circuit pulses reaches a predetermined number. FIG. [Figure 7] 1 is a diagram for explaining an example of a state in which an IGBT is destroyed by overheating when small short-circuit pulses are generated successively. FIG. [Figure 8] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device. [Figure 9] 13A and 13B are diagrams for explaining operation when the time until protection is activated when continuous occurrence of micro short-circuit pulses and detection of an overheating state are shortened. [Figure 10] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device. [Figure 11] FIG. 2 is a diagram illustrating an example of a configuration of a counter circuit. [Figure 12] FIG. 4 is a diagram illustrating an example of a configuration of a detection delay circuit. [Figure 13] FIG. 11 is a diagram for explaining a detection delay time. [Figure 14] FIG. 13 is a diagram illustrating an example of a configuration of a hysteresis circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the present embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same configuration are denoted by the same reference numerals, and duplicated description may be omitted.

[0010] 1 is a diagram for explaining an example of a semiconductor device. The semiconductor device 1 has a switch element 1a and a protection control circuit 1b. The switch element 1a operates a load by switching based on an input signal Vin. The switch element 1a is a power semiconductor that is a voltage-driven power control element such as an IGBT or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0011] The protection control circuit 1b protects the switch element 1a according to the voltage level and duration of the operation state signal Vst output from the switch element 1a. When the switch element 1a is short-circuited, the voltage level of the operation state signal Vst exceeds a predetermined level Vth for a predetermined time w1 or more.

[0012] In this way, the waveform of the operating state signal Vst having a pulse width larger than the pulse width w1 (first pulse width) in the short-circuit state is called a short-circuit pulse p1. That is, the protection control circuit 1b protects the switch element 1 when it detects the short-circuit pulse p1.

[0013] Here, the waveform of the operating state signal Vst having a pulse width w2 (second pulse width) shorter than the pulse width w1 (first pulse width) is called a micro short-circuit pulse p2. The occurrence of the micro short-circuit pulse p2 multiple times within a predetermined time is called continuous occurrence, and the protection control circuit 1b also protects the switch element 1a when it detects continuous occurrence of the micro short-circuit pulse p2.

[0014] The operation of the protection control circuit 1b is, for example, to detect a minute short-circuit pulse p2 having a pulse width w2 (second pulse width) shorter than the pulse width w1 (first pulse width) of the short-circuit pulse p1 when the voltage level of the short-circuit pulse p1 exceeds a predetermined level Vth for a predetermined period of time when the switch element 1a is in a short-circuit state.

[0015] The protection control circuit 1b counts the number of consecutive occurrences of the micro short-circuit pulse p2, and when it detects that the number of consecutive occurrences has reached a predetermined number, it protects the switch element 1a. For example, if the predetermined number is set to three, the switch element 1a is protected when the number of consecutive occurrences of the micro short-circuit pulse p2 has reached three.

[0016] In this way, the semiconductor device 1 is configured to protect the switch element when it detects the continuous occurrence of a small short-circuit pulse having a second pulse width shorter than the first pulse width of the short-circuit pulse. This makes it possible to improve the protection function of the switch element by detecting the continuous occurrence of a small short-circuit pulse that would not be detected by a conventional short-circuit detection circuit.

[0017] Next, the continuous generation of the micro short-circuit pulse will be described with reference to Fig. 2 to Fig. 4. Fig. 2 is a diagram showing an example of a state in which the number of continuous occurrences of the micro short-circuit pulse reaches a predetermined number. The switch element 1a is driven by switching on / off the input signal Vin for driving the switch element 1a. When the switch element 1a is driven, a collector current Ic flows through the switch element 1a.

[0018] When the voltage level proportional to the collector current Ic exceeds the short-circuit protection level (corresponding to the predetermined level Vth in FIG. 1) for a predetermined time, the switch element 1a is detected to be in a short-circuit state. The predetermined time is, for example, 1 ms.

[0019] On the other hand, if the time during which the short circuit protection level is exceeded is less than the specified time, that is, if a micro-short circuit pulse occurs, which is a short circuit pulse with a width shorter than the short circuit pulse width detected as a normal short circuit state, the switch element 1a is in a micro-short circuit state.

[0020] A counter included in the protection control circuit 1b counts the number of consecutive occurrences of the micro short-circuit pulse. When the number of consecutive occurrences reaches a predetermined number, the protection control circuit 1b outputs a signal for protecting the switch element 1a (in this example, a protection function is turned on at an H level and a protection function is turned off at an L level).

[0021] Here, it is assumed that the switch element 1a is protected when the number of consecutive occurrences of the micro short-circuit pulse reaches three. In Fig. 2, the counter counts the number of consecutive occurrences of the micro short-circuit pulse to three. Therefore, since the number of consecutive occurrences of the micro short-circuit pulse reaches three, an H-level signal is output to protect the switch element 1a.

[0022] 3 is a diagram showing an example of a state in which a micro short-circuit pulse has not yet occurred. When a micro short-circuit pulse has not yet occurred, that is, a short-circuit pulse has not yet occurred in the switch element 1a, in this case, since there is no counting operation by the counter, an L-level signal is output to turn off the protection function based on the continuous occurrence of micro short-circuit pulses.

[0023] 4 is a diagram showing an example of a state in which the number of consecutive occurrences of a micro short-circuit pulse does not reach a predetermined number. A micro short-circuit pulse occurs once, but thereafter, no micro short-circuit pulses are generated. Therefore, the counter counts one micro short-circuit pulse, but is reset because the number does not reach the predetermined number, and an L-level signal is output to turn off the protection function based on the consecutive occurrence of a micro short-circuit pulse.

[0024] Next, the configuration and operation of the semiconductor device 1 will be described in detail. Fig. 5 is a diagram showing an example of the configuration of the semiconductor device. The semiconductor device 10a includes an IGBT with a current sensing function and a temperature detection diode Dth for detecting the operating temperature of the IGBT, and the IGBT and the temperature detection diode Dth are integrated into one chip.

[0025] The semiconductor device 10a further includes, as constituent elements, constant current sources IR1-IR3, logic elements IC1-IC10, PMOS transistors mp1, mp2, NMOS transistors mn1, mn2, a counter circuit c1, an SR flip-flop f1, detection delay circuits dt1-dt6, hysteresis circuits hy1, hy2, comparators cmp1-cmp4, resistors R1-R5, and a plurality of reference voltage sources that output reference voltages Voh, Vsc, Voc, and VLv.

[0026] The detection delay circuits can set the detection delay time individually, and output when a predetermined time has elapsed (when the detection delay time has elapsed) after detecting the received signal. The counter circuit c1 and the detection delay circuit dt5 enclosed by dotted lines in the figure correspond to the protection control circuit.

[0027] The connections of the components are as follows. The input terminal V1, to which the input signal Vin is input, is connected to the output terminal of the constant current source IR1, the input terminal of the Schmitt trigger inverter IC1, and the cathode of the Zener diode D1. The input terminal of the constant current source IR1 is connected to the power supply voltage Vcc, and the anode of the Zener diode D1 is connected to GND.

[0028] The alarm output terminal ALM is connected to one end of a resistor R5, and the other end of the resistor R5 is connected to the output end of a constant current source IR2, the input end of a Schmitt trigger inverter IC2, and the drain of an NMOS transistor mn2. The input end of the constant current source IR2 is connected to a power supply voltage Vcc, and the source of the NMOS transistor mn2 is connected to GND.

[0029] The output terminal of the Schmitt trigger inverter IC1 is connected to a first input terminal of a 3-input 1-output logic element IC3, one input terminal of a counter circuit c1, and a first input terminal of a 3-input 1-output logic element IC10.

[0030] The output terminal of the Schmitt trigger inverter IC2 is connected to the second input terminal of the logic element IC3 and one input terminal of the two-input, one-output logical OR element IC4. The third input terminal of the logic element IC3 is connected to the other input terminal of the logical OR element IC4, the gate of the NMOS transistor mn2, the output terminal Q of the SR flip-flop f1, and the input terminal of the detection delay circuit dt6.

[0031] The output terminal of logic element IC3 is connected to the input terminal of inverter element IC5 and one input terminal of 2-input 1-output logic element IC6. The output terminal of OR element IC4 is connected to the other input terminal of logic element IC6 and the input terminal of inverter element IC7.

[0032] The output terminal of the inverter element IC5 is connected to the gate of the PMOS transistor mp1, the output terminal of the logic element IC6 is connected to the gate of the NMOS transistor mn1, and the output terminal of the inverter element IC7 is connected to the gate of the PMOS transistor mp2.

[0033] The source of the PMOS transistor mp1 is connected to the power supply voltage Vcc, the drain of the PMOS transistor mp1 is connected to the drain of the NMOS transistor mn1, the source of the PMOS transistor mp2, and the gate of the IGBT, and the source of the NMOS transistor mn1 is connected to the drain of the PMOS transistor mp2, the emitter of the IGBT, and the N terminal.

[0034] The anode of the temperature detection diode Dth is connected to the output terminal of the constant current source IR3 and the inverting input terminal (-) of the comparator cmp1. The input terminal of the constant current source IR3 is connected to the power supply voltage Vcc. The cathode of the temperature detection diode Dth is connected to GND.

[0035] The collector of the IGBT is connected to the U terminal, and the sense emitter of the IGBT is connected to the non-inverting input terminal (+) of the comparator cmp2 and one end of the resistor R1. The other end of the resistor R1 is connected to one end of the resistor R2 and the non-inverting input terminal (+) of the comparator cmp3. The other end of the resistor R2 is connected to GND.

[0036] One end of resistor R3 is connected to a power supply terminal Vcc that supplies a power supply voltage Vcc to the device, and the other end of resistor R3 is connected to one end of resistor R4 and the inverting input terminal (-) of comparator cmp4. The other end of resistor R4 is connected to GND. The GND terminal is a terminal that supplies GND to the device.

[0037] The non-inverting input terminal (+) of the comparator cmp1 is connected to the positive terminal of a reference voltage source that outputs a reference voltage Voh for overheat detection, and the negative terminal of the reference voltage source is connected to GND. The inverting input terminal (-) of the comparator cmp2 is connected to the positive terminal of a reference voltage source that outputs a reference voltage Vsc for short circuit detection, and the negative terminal of the reference voltage source is connected to GND.

[0038] The inverting input terminal (-) of the comparator cmp3 is connected to the positive terminal of a reference voltage source that outputs a reference voltage Voc for detecting an overcurrent, and the negative terminal of the reference voltage source is connected to GND. The non-inverting input terminal (+) of the comparator cmp4 is connected to the positive terminal of a reference voltage source that outputs a reference voltage VLv for detecting a drop in the control voltage, and the negative terminal of the reference voltage source is connected to GND.

[0039] The output terminal of the counter circuit c1 is connected to the input terminal of the detection delay circuit dt5, and the output terminal of the detection delay circuit dt5 is connected to the first input terminal of a 4-input 1-output logical sum element IC9. The output terminal of the comparator cmp1 is connected to the input terminal of the detection delay circuit dt1, and the output terminal of the detection delay circuit dt1 is connected to the input terminal of the hysteresis circuit hy1, and the output terminal of the hysteresis circuit hy1 is connected to the second input terminal of the logical sum element IC9.

[0040] The output terminal of the comparator cmp2 is connected to the input terminal of the detection delay circuit dt2 and the other input terminal of the counter circuit c1, and the output terminal of the detection delay circuit dt2 is connected to one input terminal of a two-input one-output logical OR element IC8.

[0041] The output terminal of the comparator cmp3 is connected to the input terminal of the detection delay circuit dt3, and the output terminal of the detection delay circuit dt3 is connected to the other input terminal of the OR gate IC8. The output terminal of the OR gate IC8 is connected to the third input terminal of the OR gate IC9.

[0042] The output terminal of the comparator cmp4 is connected to the input terminal of the detection delay circuit dt4, the output terminal of the detection delay circuit dt4 is connected to the input terminal of the hysteresis circuit hy2, and the output terminal of the hysteresis circuit hy2 is connected to the fourth input terminal of the logical sum element IC9.

[0043] The output terminal of the OR element IC9 is connected to the input terminal S (set terminal) of the SR flip-flop f1 and the second input terminal of the logic element IC10. The third input terminal of the logic element IC10 is connected to the output terminal of the detection delay circuit dt6. The output terminal of the logic element IC10 is connected to the input terminal R (reset terminal) of the SR flip-flop f1.

[0044] Next, the operation will be described. The comparator cmp1, the detection delay circuit dt1, and the hysteresis circuit hy1 provide an overheat detection function corresponding to the overheat detection circuit. When the voltage corresponding to the temperature characteristic (negative temperature characteristic) of the IGBT monitored by the temperature detection diode Dth falls below the reference voltage Voh, the comparator cmp1 determines that the IGBT is in an overheated state and outputs an H-level signal.

[0045] When the detection delay circuit dt1 receives the H-level signal output from the comparator cmp1 continuously for the set detection delay time, it outputs an H-level signal when the detection delay time has elapsed since receiving the H-level signal. The hysteresis circuit hy1 is a circuit with a hysteresis setting so that the output level does not switch frequently even if the H-level signal output from the detection delay circuit dt1 is affected by short-term temperature fluctuations, and outputs a stable H-level signal when an overheating state is detected.

[0046] The comparator cmp2 and the detection delay circuit dt2 have a short circuit detection function corresponding to the short circuit detection circuit. When the voltage corresponding to the sense current of the IGBT becomes equal to or higher than the reference voltage Vsc, the comparator cmp2 judges that the IGBT is in a short circuit state and outputs an H level. When the detection delay circuit dt2 receives an H level signal output from the comparator cmp2 continuously for a set detection delay time, it outputs an H level signal when the detection delay time has elapsed since receiving the H level signal.

[0047] The comparator cmp3 and the detection delay circuit dt3 have an overcurrent detection function corresponding to the overcurrent detection circuit. The comparator cmp3 compares the divided voltage, which is the voltage corresponding to the sense current of the IGBT divided by resistors R1 and R2, with a reference voltage Voc, and when the divided voltage becomes equal to or higher than the reference voltage Voc, it determines that the IGBT is in an overcurrent state and outputs an H level. When the detection delay circuit dt3 receives an H level signal output from the comparator cmp3 continuously for a set detection delay time, it outputs an H level signal when the detection delay time has elapsed since receiving the H level signal.

[0048] The comparator cmp4, the detection delay circuit dt4, and the hysteresis circuit hy2 have a control voltage drop detection function corresponding to the control voltage drop detection circuit. The comparator cmp4 compares the divided voltage when the power supply voltage Vcc is divided by the resistors R3 and R4 with the reference voltage VLv, and when the divided voltage becomes equal to or lower than the reference voltage VLv, it determines that the control voltage is in a drop state and outputs an H level.

[0049] When the detection delay circuit dt4 receives the H-level signal output from the comparator cmp4 continuously for the set detection delay time, it outputs an H-level signal when the detection delay time has elapsed since receiving the H-level signal. The hysteresis circuit hy2 is a circuit in which hysteresis is set so that the output level does not switch frequently even if the H-level signal output from the detection delay circuit dt4 is affected by a short-term control voltage fluctuation, and outputs a stable H-level signal when a control voltage drop state is detected.

[0050] Here, when a short circuit occurs in the IGBT and an H level signal (detection signal) is output from the comparator cmp2 (short circuit detection comparator), the detection delay circuit dt2 (detection delay circuit for short circuit detection) outputs an H level signal (short circuit detection signal) indicating a short circuit state after 1 ms has elapsed if the detection delay circuit dt2 continues to receive the H level signal for 1 ms. Therefore, a minute short circuit pulse of less than 1 ms can be detected from the output of the comparator cmp2 before it is input to the detection delay circuit dt2.

[0051] The counter circuit c1 counts the number of consecutive occurrences of minute short-circuit pulses by counting the pulses of the H-level signal (detection signal) output from the comparator cmp2 in synchronization with the input signal Vin output from the Schmitt trigger inverter IC1.

[0052] In the above embodiment, the counter circuit c1 performs counting operations in synchronization with the input signal Vin output from the Schmitt trigger inverter IC1. However, instead of the output of the Schmitt trigger inverter IC1, the gate voltage of the IGBT may be input to the counter circuit c1, and the counter circuit c1 may perform counting operations in synchronization with the gate voltage of the IGBT.

[0053] The counter circuit c1 outputs an H-level signal (protection signal) when the number of consecutive occurrences of the micro short-circuit pulse reaches a predetermined number, and the detection delay circuit dt5 outputs an H-level signal when a set detection delay time has elapsed.

[0054] Furthermore, the OR element IC9 outputs an H level signal when at least one of the following abnormal states is detected: an overheat state, a short circuit state, an overcurrent state, a control voltage drop state, and a state in which the number of consecutive occurrences of minute short circuit pulses has reached a predetermined number.If no abnormal state is detected and the device is operating normally, an L level signal is output.

[0055] Here, when an H-level signal is output from the logical sum element IC9, the logical element IC10 outputs an L-level signal. At this time, the levels of the input terminals S and R of the SR flip-flop f1 are (S, R)=(1, 0), so an H-level signal is output from the output terminal Q.

[0056] When the output terminal Q of the SR flip-flop f1 is at an H level, at least one of the following abnormal states has occurred: an overheating state, a short circuit state, an overcurrent state, a control voltage drop state, or a state in which the number of consecutive occurrences of minute short circuit pulses has reached a predetermined number.

[0057] Furthermore, when the abnormal state is released, an L-level signal is output from the logical sum element IC9, and the output from the Schmitt trigger inverter IC1 is at L level (when the input signal Vin is at H level indicating a turn-off command), the logic element IC10 outputs an H-level signal and the SR flip-flop f1 is reset.

[0058] At this time, the levels of the input terminals S and R of the SR flip-flop f1 are (S, R) = (0, 1), so an L level signal is output from the output terminal Q. When the output terminal Q of the SR flip-flop f1 is at the L level, no abnormal state has occurred and the device is in a normal state.

[0059] When the device is in an abnormal state, the output terminal Q of the SR flip-flop f1 goes to H level, turning on the NMOS transistor mn2 and outputting an L level alarm signal from the alarm output terminal ALM to notify the outside world that the device is in an abnormal state. When the device is in an abnormal state, the output of the Schmitt trigger inverter IC2 goes to H level.

[0060] Also, when the device is in a normal state, the output terminal Q of the SR flip-flop f1 goes to L level, so the NMOS transistor mn2 turns off and an H level signal is output from the alarm output terminal ALM, disabling alarm notification. Note that when the device is in a normal state, the output of the Schmitt trigger inverter IC2 goes to L level.

[0061] On the other hand, when the device is in a normal state, when an L-level input signal Vin (an instruction to turn on the IGBT) is input to the input terminal V1, the output of the logic element IC3 becomes H level, the output of the inverter element IC5 becomes L level, and the PMOS transistor mp1 turns on.

[0062] In addition, the output of the OR element IC4 becomes L level, so the output of the logic element IC6 becomes L level and the NMOS transistor mn1 turns off. In addition, the output of the inverter element IC7 becomes H level and the PMOS transistor mp2 turns off. Therefore, a signal equivalent to the drive level is input to the gate of the IGBT, so the IGBT turns on.

[0063] Furthermore, when an H-level input signal Vin (IGBT turn-off command) is input to input terminal V1 in the device's normal state, the output of logic element IC3 goes to L level, the output of inverter element IC5 goes to H level, and PMOS transistor mp1 turns off. Also, since the output of OR element IC4 goes to L level, the output of logic element IC6 goes to H level, turning NMOS transistor mn1 on. Also, since the output of inverter element IC7 goes to H level, PMOS transistor mp2 turns off. Therefore, the gate of the IGBT goes to a level equivalent to a turn-off command, and the IGBT turns off.

[0064] Furthermore, when the device is in an abnormal state, the output of the OR element IC4 becomes H level, and the output of the inverter element IC7 becomes L level, turning on the PMOS transistor mp2. This causes the charge to be drawn from the gate of the IGBT, forcing the IGBT to turn off, thereby protecting the IGBT when an abnormal state occurs.

[0065] FIG. 6 is a diagram for explaining protection when the number of consecutive occurrences of a micro short circuit pulse reaches a predetermined number. The IGBT is protected when the number of consecutive occurrences of a micro short circuit pulse reaches three. In the example shown in the figure, the operating temperature Tvj of the IGBT does not exceed the overheat protection level, but when the number of consecutive occurrences of a micro short circuit pulse reaches three, an L-level alarm ALM is output to notify of an abnormality. Also, when the number of consecutive occurrences of a micro short circuit pulse reaches three, the gate voltage Vge becomes L level, turning off the IGBT and protecting the IGBT.

[0066] Next, a case where the IGBT is protected by detecting the continuous generation of minute short-circuit pulses and the overheating state will be described. Figure 7 is a diagram for explaining an example of a state where the IGBT is destroyed by overheating when minute short-circuit pulses are continuously generated.

[0067] Overheat protection is performed when the overheat protection level is exceeded for 1 ms or more. If micro-short circuit pulses occur continuously at this time, the operating temperature of the IGBT may rise due to the micro-short circuit pulses before the overheat protection function can activate the overheat protection, and the IGBT may be destroyed before protection is activated. In other words, if it takes 1 ms from the detection of an overheat state until protection is activated, there is a risk that the IGBT may be destroyed by the temperature rise caused by the micro-short circuit pulses before 1 ms is reached.

[0068] 8 is a diagram showing an example of the configuration of a semiconductor device. The semiconductor device 10b is a circuit that prevents the destruction of an IGBT by shortening the operating time until overheat protection is activated when small short-circuit pulses are generated continuously.

[0069] The semiconductor device 10b includes, as a protection control circuit, a counter circuit c1, a two-input, one-output AND element IC12, a detection delay circuit dt7 (a detection delay circuit for reducing time), and a two-input, one-output OR element IC13, as shown in the dotted line frame in the figure. Also, the OR element IC9 shown in Figure 5 is replaced with a three-input, one-output OR element IC11. The other circuit configurations are the same as those in Figure 5.

[0070] Here, as described above, the counter circuit c1 counts the number of consecutive occurrences of micro short-circuit pulses by counting the pulses of the H-level signal (first detection signal) output from the comparator cmp2 in synchronization with the input signal Vin output from the Schmitt trigger inverter IC1.

[0071] The counter circuit c1 outputs an H level signal (counter signal) when the number of consecutive occurrences of the micro short-circuit pulses reaches a predetermined number. Also, the comparator cmp1 (overheat detection comparator) outputs an H level signal (second detection signal) when the voltage corresponding to the IGBT operating temperature becomes equal to or lower than the reference voltage Voh, indicating an overheat state.

[0072] Therefore, when the number of consecutive occurrences of the minute short-circuit pulse reaches a predetermined number and the IGBT is in an overheated state, the AND element IC12 outputs an H-level signal (AND signal) to the detection delay circuit dt7.

[0073] When the detection delay circuit dt7 (time-saving detection delay circuit) receives the H-level signal output from AND element IC12 continuously for the set detection delay time, it outputs an H-level signal when the detection delay time has elapsed.

[0074] In this case, the detection delay circuit dt7 is set to a detection delay time (second time) that is shorter than the detection delay time (first time) of the detection delay circuit dt1 (detection delay circuit for overheating detection). For example, if the detection delay time (first time) of the detection delay circuit dt1 is 1 ms, the detection delay time (second time) of 10 μs is set in the detection delay circuit dt7.

[0075] Therefore, the detection delay circuit dt1 outputs an H-level signal (overheat detection signal) when a detection delay time of 1 ms has elapsed since the overheating state was detected, and the detection delay circuit dt7 outputs an H-level signal (time-shortened detection signal) when 10 μs has elapsed since the overheating detection when the number of consecutive occurrences of micro short-circuit pulses reaches a predetermined number and it is detected that the IGBT is in an overheating state.

[0076] When the logical sum element IC13 receives at least one of the H-level signal (overheating detection signal) output from the detection delay circuit dt1 or the H-level signal (time-shortening detection signal) output from the detection delay circuit dt7, it outputs an H-level signal (protection signal) to the hysteresis circuit hy1.

[0077] Figure 9 is a diagram for explaining the operation when the time until protection is activated when continuous occurrence of micro-short pulses and an overheating state are detected is shortened. The number of detections of continuous occurrence of micro-short pulses is set to three. When the number of continuous occurrences of micro-short pulses reaches three and the operating temperature Tvj of the IGBT exceeds the overheating protection level, the time until overheating protection is activated is shortened to 10 μs.

[0078] For this reason, an L-level alarm ALM is output to notify of an abnormality 10 μs after the overheating state is detected. Also, the gate voltage Vge becomes L level, forcing the IGBT to turn off, thereby protecting the IGBT.

[0079] In this way, when continuous micro-shorting pulses are generated and an overheating state is detected, the time until a protection signal is output that was set before normal overheating protection was activated is shortened (for example, from 1 ms to 10 μs), so protection can be performed before the IGBT reaches an overheating state that would lead to its destruction, thereby preventing destruction of the IGBT.

[0080] FIG. 10 is a diagram showing an example of the configuration of a semiconductor device. The semiconductor device 10c is a modified example of the semiconductor device 10b shown in FIG. 8. The semiconductor device 10c includes a counter circuit c1, an inverter element IC14, a PMOS transistor mp3, a detection delay circuit dt7 (a detection delay circuit for reducing time), and an OR element IC13, which are shown in a dotted line frame in the diagram as a protection control circuit. In the semiconductor device 10c, the AND element IC12 shown in FIG. 8 is replaced with a PMOS transistor mp3, and an inverter element IC14 is added. The other configurations are the same as those in FIG. 8.

[0081] The counter circuit c1 outputs an H level signal when the number of consecutive occurrences of the micro short-circuit pulses reaches a predetermined number, and the inverter element IC14 inverts the H level signal to output an L level signal (inverted counter signal). The comparator cmp1 outputs an H level signal (second detection signal) when the voltage corresponding to the IGBT operating temperature becomes equal to or lower than the reference voltage Voh, indicating an overheated state.

[0082] Also, since an L level signal is output from the inverter element IC14, the PMOS transistor mp3 turns on and the H level signal of the comparator cmp1 is input to the detection delay circuit dt7. The subsequent operations are the same as those in FIG.

[0083] Even with this configuration, when continuous micro-shorting pulses are generated or an overheating state is detected, the time until a protection signal is output that was set before normal overheating protection was activated can be shortened (for example, from 1 ms to 10 μs), making it possible to protect the IGBT before it reaches an overheating state that would lead to its destruction, thereby preventing destruction of the IGBT.

[0084] Next, configuration examples of the counter circuit, detection delay circuit, and hysteresis circuit will be described. Fig. 11 is a diagram showing an example of the configuration of the counter circuit. The counter circuit c1 is a circuit that counts pulses (micro short-circuit pulses) whose level exceeds the reference voltage Vr0, and includes a comparator cmp10, a reference voltage source that outputs the reference voltage Vr0, logic elements IC21-IC24, and D-type flip-flops f11, f12, f13, f20-1, ..., f20-n.

[0085] The input terminal of inverter element IC21 is connected to the output terminal of Schmitt trigger inverter IC1, and the output terminal of inverter element IC21 is connected to one input terminal of 2-input 1-output AND element IC22 and one input terminal of 2-input 1-output AND element IC24.

[0086] The non-inverting input terminal (+) of the comparator cmp10 is connected to the output terminal of the comparator cmp2, ​​and the inverting input terminal (-) of the comparator cmp10 is connected to the positive terminal of a reference voltage source that outputs a reference voltage Vr0. The negative terminal of the reference voltage source is connected to GND.

[0087] The output terminal of the comparator cmp10 is connected to the other input terminal of the AND gate IC22. The output terminal of the AND gate IC22 is connected to the input terminal of the inverter gate IC23 and the clock input terminal CLK of the flip-flop f11. The output terminal of the inverter gate IC23 is connected to the other input terminal of the AND gate IC24.

[0088] The input terminal D of flip-flop f11 is connected to the inverting output terminal QB of flip-flop f11, the input terminal D of flip-flop f12 is connected to the inverting output terminal QB of flip-flop f12, and the input terminal D of flip-flop f13 is connected to the inverting output terminal QB of flip-flop f13.

[0089] The output terminal Q of the flip-flop f11 is connected to the clock input terminal CLK of the flip-flop f12, and the output terminal Q of the flip-flop f12 is connected to the clock input terminal CLK of the flip-flop f13.

[0090] The input terminal D of the flip-flop f20-1 is connected to the inverting output terminal QB of the flip-flop f20-1, and the input terminal D of the flip-flop f20-n is connected to the inverting output terminal QB of the flip-flop f20-n. The output terminal Q of the flip-flop f20-1 is connected to the clock input terminal CLK of the flip-flop located after the flip-flop f20-1, and the clock input terminal CLK of the flip-flop f20-n is connected to the output terminal Q of the flip-flop located before the flip-flop f20-n.

[0091] The output terminal of AND gate IC24 is connected to the reset input terminal RST of each of flip-flops f11, f12, and f13, and is further connected to the reset input terminal RST of each of flip-flops f20-1, . . . , f20-n.

[0092] 12 is a diagram showing an example of the configuration of the detection delay circuit dt0. The detection delay circuit dt0 includes an inverter element IC31, a constant current source IR10, PMOS transistors mp11, mp12, mp13, an NMOS transistor mn11, a capacitor C0, a reference voltage source that outputs a reference voltage Vr2, and a comparator cmp20.

[0093] The input terminal IN1 is connected to the input terminal of the inverter element IC31, and the output terminal of the inverter element IC31 is connected to the gate of the PMOS transistor mp13 and the gate of the NMOS transistor mn11.

[0094] The power supply terminal Vcc is connected to the source of the PMOS transistor mp11 and the source of the PMOS transistor mp12. The gate of the PMOS transistor mp11 is connected to the drain of the PMOS transistor mp11, the gate of the PMOS transistor mp12, and the input terminal of the constant current source IR10.

[0095] The drain of the PMOS transistor mp12 is connected to the source of the PMOS transistor mp13. The drain of the PMOS transistor mp13 is connected to the drain of the NMOS transistor mn11, one end of the capacitor C0, and the non-inverting input terminal (+) of the comparator cmp20. The inverting input terminal (-) of the comparator cmp20 is connected to the positive terminal of the reference voltage source that outputs the reference voltage Vr2.

[0096] The GND terminal is connected to the output terminal of the constant current source IR10, the source of the NMOS transistor mn11, the other terminal of the capacitor C0, and the negative terminal of the reference voltage source that outputs the reference voltage Vr2. The output terminal of the comparator cmp20 is connected to the output terminal OUT1.

[0097] 13 is a diagram for explaining the detection delay time. Let us assume that an H-level voltage is input to the input terminal IN1 of the detection delay circuit dt0. At this time, if the H-level voltage is continuously received for the time period of the detection delay time Td, an H-level voltage is output from the output terminal OUT1 of the detection delay circuit dt0 when the detection delay time Td has elapsed.

[0098] 14 is a diagram showing an example of the configuration of a hysteresis circuit. The hysteresis circuit hy0 includes a constant current source IR20, a diode D10, a reference voltage source that outputs a reference voltage Vr3, resistors R10 and R11, and a comparator cmp30.

[0099] The input terminal IN2 is connected to the anode of the diode D10, the output terminal of the constant current source IR20, and the inverting input terminal (-) of the comparator cmp30. The input terminal of the constant current source IR20 is connected to the power supply voltage Vcc.

[0100] The cathode of the diode D10 is connected to the negative terminal of a reference voltage source that outputs a reference voltage Vr3 and to GND. The positive terminal of the reference voltage source that outputs the reference voltage Vr3 is connected to one terminal of a resistor R10, and the other terminal of the resistor R10 is connected to the non-inverting input terminal (+) of a comparator cmp30 and one terminal of a resistor R11. The output terminal of the comparator cmp30 is connected to the other terminal of the resistor R11 and the output terminal OUT2.

[0101] Although the embodiments have been described above, the configurations of the parts shown in the embodiments can be replaced with other parts having similar functions. Any other components or steps may be added. Furthermore, any two or more configurations (features) of the above-mentioned embodiments may be combined. [Explanation of symbols]

[0102] 1 Semiconductor device 1a Switch element 1b Protection control circuit p1 Short circuit pulse p2 Micro short circuit pulse w1 Short circuit pulse width w2 Pulse width of the micro short circuit pulse Vin Input signal Vth Predetermined level Vst Operation Status Signal

Claims

1. a switch element that switches on and off based on an input signal to operate a load; a protection control circuit that protects the switch element when detecting continuous generation of minute short-circuit pulses having a second pulse width shorter than a first pulse width of a short-circuit pulse that is output when the switch element is in a short-circuit state; A semiconductor device having the above structure.

2. a short circuit detection circuit that detects the short circuit state of the switch element and outputs a short circuit detection signal, The protection control circuit detects the micro short circuit pulse. The semiconductor device according to claim 1.

3. the short circuit detection circuit includes a short circuit detection comparator that outputs a detection signal when the short circuit state of the switch element is detected, and a short circuit detection delay circuit that receives the detection signal continuously for a predetermined time and outputs the short circuit detection signal when the predetermined time has elapsed; The protection control circuit includes a counter circuit, which detects the micro short-circuit pulse from the detection signal, counts the number of consecutive occurrences of the micro short-circuit pulse in synchronization with the input signal, and outputs a protection signal when the number of consecutive occurrences reaches a predetermined number.

3. The semiconductor device according to claim 2.

4. 4. The semiconductor device according to claim 3, wherein when said protection signal is output from said protection control circuit, driving of said switch element is stopped and an alarm notification is output to the outside.

5. 4. The semiconductor device according to claim 3, wherein said predetermined time is 1 ms, and said second pulse width of said micro short-circuit pulse is less than 1 ms.

6. the short circuit detection circuit detecting the short circuit state of the switch element and outputting the short circuit detection signal when the first pulse width of the short circuit pulse continues to exceed a predetermined time, and an overheat detection circuit detecting an operating temperature of the switch element and outputting an overheat detection signal when the overheat state of the switch element continues for a first time, the protection control circuit detects the micro short-circuit pulse having the second pulse width shorter than the predetermined time, which is not detected by the short-circuit detection circuit, and when the number of consecutive occurrences of the micro short-circuit pulse reaches a predetermined number and the overheating state is detected, outputs a protection signal for a second time that is a shortened version of the first time.

3. The semiconductor device according to claim 2.

7. the short circuit detection circuit includes a short circuit detection comparator that outputs a first detection signal when the short circuit state of the switch element is detected, and a short circuit detection delay circuit that receives the first detection signal continuously for the predetermined time and outputs the short circuit detection signal when the predetermined time has elapsed; the overheat detection circuit includes an overheat detection comparator that outputs a second detection signal when it detects the overheated state of the switch element, and an overheat detection delay circuit that receives the second detection signal continuously for the first time period and outputs the overheat detection signal when the first time period has elapsed.

7. The semiconductor device according to claim 6.

8. the protection control circuit includes a counter circuit, a logical AND element, a time-saving detection delay circuit, and a logical OR element; the counter circuit detects the micro short-circuit pulse from the first detection signal, counts the number of consecutive occurrences of the micro short-circuit pulse in synchronization with the input signal, and outputs a counter signal when the number of consecutive occurrences reaches a predetermined number; the AND element outputs a logical AND signal when receiving the counter signal and the second detection signal; the time-shortening detection delay circuit outputs a time-shortening detection signal when the second time has elapsed since receiving the logical AND signal; the logical sum element outputs the protection signal when at least one of the overheating detection signal and the time reduction detection signal is received.

8. The semiconductor device according to claim 7.

9. the protection control circuit includes a counter circuit, an inverter element, a PMOS transistor, a time-saving detection delay circuit, and a logical OR element; the counter circuit detects the micro short-circuit pulse from the first detection signal, counts the number of consecutive occurrences of the micro short-circuit pulse in synchronization with the input signal, and outputs a counter signal when the number of consecutive occurrences reaches a predetermined number; The inverter element outputs an inverted counter signal obtained by inverting a level of the counter signal, the PMOS transistor is turned on by the inverted counter signal and inputs the second detection signal to the time-shortening detection delay circuit; the time-shortening detection delay circuit outputs a time-shortening detection signal when the second time has elapsed since receiving the second detection signal; the logical sum element outputs the protection signal when at least one of the overheating detection signal and the time reduction detection signal is received.

8. The semiconductor device according to claim 7.

10. 7. The semiconductor device according to claim 6, wherein, when said protection signal is output from said protection control circuit, driving of said switch element is stopped and an alarm notification is output to the outside.

11. The predetermined time is 1 ms, and the second pulse width of the micro short-circuit pulse is less than 1 ms; The first time period is 1 ms and the second time period is 10 μs.

7. The semiconductor device according to claim 6.

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