Wiring board

Abstract

To improve adhesiveness between a first seed layer and a third insulation layer and effectively prevent occurrence of inter-wire short-circuiting.SOLUTION: A wiring board comprises a core substrate CS, a first build-up part BU1, a second build-up part BU2, a third build-up part BU3, and a fourth build-up part BU4. A third insulation layer includes a top face, a via opening from the top face to a third conductor layer being a lower layer, and a via conductor formed in the via opening and connecting the third conductor layer with the third conductor layer being the lower layer. The third conductor layer is formed of a seed layer and an electrolytic plating layer which is formed on the seed layer. The seed layer includes a first layer and a second layer which is formed on the first layer, and is composed of the first layer, the second layer, and the electrolytic plating layer successively from a side closer to the third insulation layer. On a cross section of the third conductor layer, a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board having a plurality of build-up portions. [Background technology]

[0002] 4, Patent Document 1 discloses a printed wiring board 51 in which a conductor circuit 53 is formed on an insulating layer 52 having a roughened surface. The conductor circuit 53 is formed by an electroless plating film (seed layer) 54 formed in conformity with the roughened surface of the insulating layer 52, and an electrolytic plating film 55 formed on the electroless plating film 54. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-214828 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, as shown in Fig. 4, width D4 of electroless plating film 54 is the same in the height direction. In order to improve adhesion between electroless plating film 54 and insulating layer 52, width D4 of electroless plating film 54 needs to be increased. However, if width D4 of electroless plating film 54 is made too large, short circuits between adjacent conductor circuits are likely to occur. For this reason, it has been difficult to design electroless plating film 54 that has high adhesion to insulating layer 52 and does not cause short circuits between adjacent conductor circuits. [Means for solving the problem]

[0005] A wiring board according to the present invention has a core substrate having a first surface and a second surface opposite to the first surface, a first buildup section formed on the first surface and including a plurality of first insulating layers and a plurality of first conductor layers which are alternately stacked, a second buildup section formed on the second surface and including a plurality of second insulating layers and a plurality of second conductor layers which are alternately stacked, a third buildup section formed on the first buildup section and including a plurality of third insulating layers and a plurality of third conductor layers which are alternately stacked, and a fourth buildup section formed on the second buildup section and including at least one fourth insulating layer and at least one fourth conductor layer which are alternately stacked, wherein an outermost surface of the wiring board is constituted by an outermost surface of the third buildup section and an outermost surface of the fourth buildup section, and a minimum value of a wiring width of wiring included in the third conductor layer is a minimum value of a wiring width of wiring included in the first conductor layer, the second conductor layer, and the fourth conductor layer. the third insulating layer has an upper surface, a via opening extending from the upper surface to a third conductor layer below, and a via conductor formed in the via opening and connecting the third conductor layer to the third conductor layer below, the third conductor layer being formed of a seed layer and an electrolytic plating layer formed on the seed layer, the seed layer having a first layer and a second layer formed on the first layer, the seed layer being composed of the first layer, the second layer, and the electrolytic plating layer in that order from closest to the third insulating layer, and in a cross section of the third conductor layer, the width of the first layer is greater than the width of the second layer, and the width of the electrolytic plating layer is greater than the width of the first layer. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a schematic diagram of an embodiment of a build-up portion in a wiring board according to the present invention. [Diagram 2]5A to 5C are cross-sectional views each showing a typical characteristic portion of each layer of a third buildup portion in a wiring board according to the present invention according to one embodiment of the present invention. [Figure 3A] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3B] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3C] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3D] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3E] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3F] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3G] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3H] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 3I] 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. [Figure 4] FIG. 1 is a diagram showing an example of a conventional printed wiring board. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] <About the wiring board of the present invention> An embodiment of a wiring board of the present invention will be described with reference to the drawings. In the example shown in Figures 1 to 4, the dimensions of each member, particularly the height dimension, are shown in dimensions different from the actual dimensions in order to make the features of the present invention easier to understand.

[0008] FIG. 1 is a cross-sectional view for explaining an embodiment of a build-up section in a wiring board according to the present invention. In FIG. 1, CS is a core substrate having, for example, a first surface CS1 on the upper side in the figure and a second surface CS2 on the lower side. BU1 is a first build-up section formed on the first surface CS1 of the core substrate CS and including a plurality of first insulating layers 12 and a plurality of first conductor layers 11 that are alternately stacked. BU2 is a second build-up section formed on the second surface CS2 of the core substrate CS and including a plurality of second insulating layers 22 and a plurality of second conductor layers 21 that are alternately stacked. BU3 is a third build-up section formed on the first build-up section BU1 and including a plurality of third insulating layers 32 and a plurality of third conductor layers 31 that are alternately stacked. BU4 is a fourth build-up section formed on the second build-up section BU2 and including at least one fourth insulating layer 42 and at least one fourth conductor layer 41 that are alternately stacked. In this embodiment, chip 1 and chip 2 are mounted on third buildup section BU3 of wiring board 1 having the above-described configuration.

[0009] In the wiring board according to the present invention shown in Fig. 1, it is preferable to use a glass core as the core substrate CS. When a glass core is used as the core substrate, high density wiring can be easily formed compared to wiring boards using core substrates of other materials. Any conventionally known material can be used as the glass core. For example, borosilicate glass, which has excellent heat resistance and impact resistance and a thermal expansion coefficient close to that of silicon, can be used.

[0010] The wiring board according to this embodiment is characterized by the structure of the third buildup section BU3. That is, in the wiring board according to this embodiment, the minimum value of the wiring width of the wiring included in the third conductor layer is smaller than the minimum value of the wiring width of the wiring included in the first conductor layer, the second conductor layer, and the fourth conductor layer, the minimum value of the distance between the wiring included in the third conductor layer is smaller than the minimum value of the distance between the wiring included in the first conductor layer, the second conductor layer, and the fourth conductor layer, the minimum wiring width of the wiring included in the third conductor layer is 3 μm or less, the minimum wiring interval is 3 μm or less, and the third insulating layer has an upper surface and an upper a via opening extending from the surface to a third conductor layer below, and a via conductor formed in the via opening and connecting the third conductor layer to the third conductor layer below, the third conductor layer being formed of a seed layer and an electrolytic plating layer formed on the seed layer, the seed layer having a first layer and a second layer formed on the first layer, and being composed of the first layer, second layer, and electrolytic plating layer in that order from closest to the third insulating layer, and in a cross section of the third conductor layer, the width of the first layer is greater than the width of the second layer, and the width of the electrolytic plating layer is greater than the width of the first layer.

[0011] In the wiring board of this embodiment, the third build-up section BU3 has the above-mentioned configuration, so that a seed layer can be formed in the third build-up section BU3 that has high adhesion to the third insulating layer and does not cause inter-line shorts with the adjacent third conductor layer.

[0012] 2 is a schematic diagram for explaining characteristic parts of each layer of the third buildup section BU3 in the wiring board according to the present embodiment. In FIG. 2, the configuration of the layer L1 to be explained is the same as the layers other than the layer L1. The layers other than the layer L1 are formed continuously above and below the layer L1 to be explained.

[0013] In the wiring board according to this embodiment, each layer in the third build-up section BU3 includes the configuration shown in FIG. 2. In FIG. 2, the third conductor layer 31 is formed by a seed layer 38 and an electrolytic plating layer 31d formed on the seed layer 38. The seed layer 38 has a first layer 38-1 and a second layer 38-2 formed on the first layer 38-1. In order from the side closer to the third insulating layer 32, the first layer 38-1, the second layer 38-2, and the electrolytic plating layer 31d are included. In a cross section of the third conductor layer 31, the width D2 of the first layer 38-1 is larger than the width D3 of the second layer 38-2. The width D1 of the electrolytic plating layer 31d is larger than the width D2 of the first layer 38-2.

[0014] 2, the width D2 of the first layer 38-1 is larger than the width D3 of the second layer 38-2, thereby improving the adhesion between the first seed layer 38-1 and the third insulating layer 32. In addition, the width D1 of the electrolytic plating layer 31d is larger than the width D2 of the first layer 38-2, thereby increasing the distance between the adjacent seed layer of the third conductor layer 31 and the target seed layer 38 in FIG. 2, thereby effectively preventing the occurrence of short circuits between lines.

[0015] In the embodiment of FIG. 2, the third insulating layer 32 is made of resin. As a preferred embodiment, the third insulating layer 32 may contain resin and inorganic particles. As a preferred embodiment, each of the first insulating layer, the second insulating layer, and the third insulating layer contains inorganic particles, and the maximum particle size of the inorganic particles contained in the third insulating layer is smaller than the maximum particle size of the inorganic particles contained in the first insulating layer and the second insulating layer. Furthermore, in the description based on FIG. 2, the relationship between the sizes of D1-D3 in the cross section of the third conductor layer 31 is specified, but the relationship between the via conductor and the seed layer may be the same.

[0016] <Regarding the manufacturing method of the third build-up section BU3, which is a feature of the wiring board of the present invention> For the first buildup section BU1, the second buildup section BU2, and the fourth buildup section BU4, the formation of the alternating first insulating layers 12 and the alternating first conductor layers 11, the formation of the alternating second insulating layers 22 and the alternating second conductor layers 21, and the formation of at least one alternating fourth insulating layer 42 and at least one alternating fourth conductor layer 41 can be performed by a conventionally known method. Detailed descriptions thereof will not be given here.

[0017] A method for manufacturing the third buildup section BU3, which is a feature of the wiring board of the present invention, will be described with reference to FIGS. 3A to 3I.

[0018] First, as shown in Fig. 3A, a third insulating layer 32 made of the resin of the target layer L1 is formed on the lower layer L2, and a protective film 36 is formed on the upper surface 32a of the third insulating layer 32. The resin is preferably a thermosetting resin, a thermoplastic resin, or a composite resin thereof. The protective film 36 is preferably a film made of polyethylene terephthalate (PET), or the like.

[0019] Next, as shown in FIG. 3B, a laser beam is irradiated from above the protective film 36. The laser beam penetrates the protective film 36 and the third insulating layer 32 at the same time. As a result, a via opening 37 for forming a via conductor is formed on the third conductor layer 31 of the lower layer L2. The laser beam is, for example, a UV laser beam or a CO2 laser beam. The third conductor layer 31 of the lower layer is exposed by the via opening 37. When the via opening 37 is formed, the upper surface 32a of the third insulating layer 32 is covered with the protective film 36. Therefore, even if the resin is scattered when the via opening 37 is formed, the adhesion of the resin to the upper surface 32a of the third insulating layer 32 is suppressed.

[0020] 3C, with the upper surface 32a of the third insulating layer 32 covered with the protective film 36, a desmear process is performed on the inside of the via opening 37 by a dry process (plasma). As a result, the inner wall surface 37a of the via opening 37 is roughened, but the upper surface 32a of the third insulating layer 32 is not roughened. The desmear process can be performed by reactive ion etching (RIE) including, for example, a fluorocarbon gas.

[0021] 3D, the protective film 36 is removed from the upper surface 32a of the third insulating layer 32. After the protective film 36 is removed, the upper surface 32a of the third insulating layer 32 is not roughened. After the protective film 36 is removed, the upper surface 32a of the third insulating layer 32 is cleaned by dry etching using Ar sputtering.

[0022] Next, as shown in FIG. 3E, a seed layer 38 is formed on the upper surface 32a of the third insulating layer 32. The seed layer 38 is formed by sputtering. The seed layer 38 is formed by a dry process. The seed layer 38 is also formed on the upper surface of the lower third conductor layer 31 exposed from the via opening 37 and on the inner wall surface 37a of the via opening 37. In this embodiment, the seed layer 38 is composed of a first layer 38-1 formed by sputtering an alloy containing copper, silicon, and aluminum, and a second layer 38-2 formed by sputtering copper thereon.

[0023] 3F, a plating resist 40 is formed on the seed layer 38. The plating resist 40 has openings for forming the third conductor layer 31 including the conductor pads 31a and the wiring 31b.

[0024] Next, as shown in Fig. 3G, an electrolytic plating layer 31d is formed on the seed layer 38 exposed from the plating resist 40. The electrolytic plating layer 31d fills the via opening 37. The electrolytic plating layer 31d is formed to be higher than the height of the plating resist 40. That is, for example, as shown in Fig. 3G, the electrolytic plating layer 31d is formed outside the upper surface of the plating resist 40 so that the upper surface has a convex spherical shape.

[0025] 3H, the electrolytic plating layer 31d and a portion of the upper side of the plating resist 40 are removed by polishing. Polishing is performed until the electrolytic plating layer 31d has a desired thickness. The polishing is performed by, for example, chemical mechanical polishing (CMP).

[0026] Thereafter, the plating resist 40 and the seed layer 38 thereunder are removed. As a result, as shown in Fig. 3I, wiring 31b is formed by the seed layer 38 and the electrolytic plating layer 31d on the upper surface 32a of the third insulating layer 32. The seed layer 38 and the electrolytic plating layer 31d in the via opening 37 form a via conductor 39 in the via opening 37 and a conductor pad 31a thereon. In this manner, as shown in Fig. 3I, a wiring board according to one embodiment of the present invention is obtained.

[0027] As shown in FIG. 2 described above, the first layer 38-1 having the width D2 and the second layer 38-2 having the width D3 can be formed by controlling the etching conditions, such as the temperature and concentration of the etching solution, when etching and removing the seed layer 38 after deposition by sputtering.

[0028] In a wiring board according to one embodiment of the present invention, when forming seed layer 38 and electrolytic plated layer 31d in third buildup section BU3, electrolytic plated layer 31d having width D1, first layer 38-1 having width D2, and second layer 38-2 having width D3 are formed as shown in Fig. 2. This makes it possible to improve adhesion between first seed layer 38-1 and third insulating layer 32 and effectively prevent the occurrence of short circuits between lines.

[0029] Hereinafter, preferred embodiments of the wiring board according to the present invention will be described.

[0030] In the wiring board according to one embodiment of the present invention, as a suitable example of the third buildup section BU3, the wiring 31b included in the third conductor layer 31 is preferably formed so as to have an aspect ratio of 2 or more and 4 or less. In this way, the third buildup section BU3 has wiring 31b with a relatively high aspect ratio, so that a wiring board having wiring 31b with a relatively high density in the surface layer portion can be realized. More appropriate wiring corresponding to the electrical signals carried in the surface layer portion of the wiring board is provided.

[0031] In the wiring board according to one embodiment of the present invention, as a suitable example of the third buildup section BU3, it is preferable that the upper surfaces of the wiring included in the third conductor layer 31 are polished surfaces. By polishing the upper surfaces of the wiring included in the third conductor layer 31, the upper surface of the third conductor layer 31 has a relatively small roughness and is flat, and therefore the third conductor layer 31 has a relatively uniform thickness.

[0032] In the wiring board according to one embodiment of the present invention, as a preferred example of the third build-up section BU3, when the third insulating layer 32 is composed of resin and inorganic particles, it is preferable that the maximum particle size of the inorganic particles contained in the third insulating layer 32 is smaller than the maximum particle size of the inorganic particles contained in the first insulating layer 12 and the second insulating layer 22. When inorganic particles are contained in the third insulating layer 32 that contacts the wiring 31b formed at a relatively high density, if inorganic particles with a relatively large particle size are located between the adjacent wirings 31b, 31b, a short circuit may occur between the wirings 31b, 31b due to migration through the surfaces of the inorganic particles. Therefore, by making the maximum particle size of the inorganic particles that can be contained in the third insulating layer 32 relatively small, the risk of a short circuit in the wirings 31b, 31b can be reduced.

[0033] In a wiring board according to one embodiment of the present invention, as a suitable example in third buildup section BU3, it is preferable that the volume of third insulating layer 32 constituting third buildup section BU3 and the volume of fourth insulating layer 42 constituting fourth buildup section BU4 are substantially equal. It is also preferable that the volume occupied by the conductors in third buildup section BU3 and the volume occupied by the conductors in fourth buildup section BU4 are substantially equal. By satisfying these conditions, warping of wiring board 1 can be reduced. [Explanation of symbols]

[0034] 1. Wiring board 11 First conductor layer 12 First insulating layer 21 Second conductor layer 22 Second insulating layer 31 Third conductor layer 31a Contact pad 31b Wiring 31d Electrolytic plating layer 32 Third insulating layer 32a top surface 36 Protective film 37 Via opening 37a Inner wall surface 38 Seed Layer 38-1 1st layer 38-2 2nd layer 39 Via conductor 40 Plating resist 41 4th conductor layer 42 Fourth insulating layer BU1 First build-up section BU2 Second build-up section BU3 Third build-up section BU4 4th Buildup Section CS Core Board CS1 1st page CS2 2nd page L1 Target layer L2 lower layer

Claims

1. a first buildup section formed on the first surface and including a plurality of first insulating layers and a plurality of first conductor layers that are alternately stacked; a second buildup section formed on the second surface and including a plurality of second insulating layers and a plurality of second conductor layers that are alternately stacked; a third buildup section formed on the first buildup section and including a plurality of third insulating layers and a plurality of third conductor layers that are alternately stacked; and a fourth buildup section formed on the second buildup section and including at least one fourth insulating layer and at least one fourth conductor layer that are alternately stacked, an outermost surface of the wiring board is constituted by an outermost surface of the third buildup section and an outermost surface of the fourth buildup section; a minimum value of a wiring width of the wiring included in the third conductor layer is smaller than a minimum value of a wiring width of the wiring included in the first conductor layer, the second conductor layer, and the fourth conductor layer; a minimum value of a distance between wirings included in the third conductor layer is smaller than a minimum value of a distance between wirings included in the first conductor layer, the second conductor layer, and the fourth conductor layer; The minimum wiring width of the wiring included in the third conductor layer is 3 μm or less, and the minimum wiring interval is 3 μm or less; the third insulating layer has an upper surface, a via opening extending from the upper surface to a third conductor layer in a lower layer, and a via conductor formed in the via opening and connecting the third conductor layer and the third conductor layer in the lower layer; the third conductor layer is formed by a seed layer and an electrolytic plating layer formed on the seed layer, the seed layer has a first layer and a second layer formed on the first layer, and is configured in the order from the side closest to the third insulating layer, that is, the first layer, the second layer, and the electrolytic plating layer; In a cross section of the third conductor layer, the width of the first layer is larger than the width of the second layer, and the width of the electrolytic plating layer is larger than the width of the first layer.

2. 2. The wiring board according to claim 1, wherein the core substrate is a glass core.

3. 2. The wiring board according to claim 1, wherein the aspect ratio of the wiring included in the third conductor layer is 2 or more and 4 or less.

4. 2. The wiring board according to claim 1, wherein an upper surface of the wiring included in the third conductor layer is a polished surface.

5. In the wiring board of claim 1, each of the first insulating layer, the second insulating layer, and the third insulating layer contains inorganic particles, and the maximum particle size of the inorganic particles contained in the third insulating layer is smaller than the maximum particle size of the inorganic particles contained in the first insulating layer and the second insulating layer.

6. 2. The wiring board according to claim 1, wherein a volume of the third insulating layer constituting the third buildup section and a volume of the fourth insulating layer constituting the fourth buildup section are substantially equal to each other.

7. 2. The wiring board according to claim 1, wherein a volume occupied by the third conductor in the third buildup portion is substantially equal to a volume occupied by the fourth conductor in the fourth buildup portion.

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