Semiconductor device

Abstract

To provide a semiconductor device which improves a forward voltage Vf of a diode part and reduces a reverse recovery loss Err.SOLUTION: A semiconductor device comprising a diode part 80 includes: a plurality of trench parts 30 provided on a front face of a semiconductor substrate 10; a drift region of a first conductivity type provided on the semiconductor substrate; an anode region 19 of a second conductivity type provided at an upper side of the drift region; a first plug region 83 of the second conductivity type which is provided at the upper side of the drift region in the diode part and of which the doping concentration is higher than that of the anode region; a front face side electrode provided at an upper side of the semiconductor substrate; and an inter-layer insulation film 38 provided at an upper side of a mesa part 81 which is provided between the plurality of trench parts. The anode region is connected with the front face side electrode on side faces of the plurality of trench parts.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 describes a semiconductor device having a configuration in which "the barrier metal 5 is in ohmic contact with the diode trench electrode 21a and the p-type contact layer 24, and is electrically connected to the diode trench electrode and the p-type contact layer 24." [Prior art document] [Patent documents] [Patent Document 1] JP 2022-056498 A [Patent Document 2] JP 2022-059487 A Summary of the Invention [Problem to be solved by the invention]

[0003] In a semiconductor device, it is desirable to improve the forward voltage Vf of the diode portion and reduce the reverse recovery loss Err. [Means for solving the problem]

[0004] In a first aspect of the present invention, there is provided a semiconductor device having a diode portion, the semiconductor device comprising: a plurality of trench portions provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; an anode region of a second conductivity type provided above the drift region in the diode portion; a first plug region of the second conductivity type provided above the drift region in the diode portion and having a doping concentration higher than that of the anode region; a front surface side electrode provided above the semiconductor substrate; and an interlayer insulating film provided above a mesa portion provided between the plurality of trench portions, wherein the anode region is connected to the front surface side electrode at a side surface of the plurality of trench portions.

[0005] The above semiconductor device may further include a first contact portion above the mesa portion, extending in a trench extension direction of the plurality of trench portions and connected to the anode region and the first plug region.

[0006] In any of the above semiconductor devices, a second contact portion may be provided on the front surface of the semiconductor substrate, extending in a trench arrangement direction of the multiple trench portions from a sidewall of one of the multiple trench portions to a sidewall of the other trench portion, and connected to the mesa portion.

[0007] In any of the above semiconductor devices, the second contact portion may extend beyond at least one of the plurality of trench portions in a trench arrangement direction of the plurality of trench portions and be connected to the at least one trench portion.

[0008] In any of the semiconductor devices described above, a width of the first contact portion in the trench arrangement direction may be larger than a width of the second contact portion in the trench extension direction.

[0009] In any of the semiconductor devices described above, the second contact portion may be provided above the anode region and the plurality of trench portions that are alternately provided in the trench arrangement direction.

[0010] In any of the above semiconductor devices, a plurality of the second contact portions may be provided above the anode regions and the plurality of trench portions that are alternately provided in the trench arrangement direction.

[0011] In any of the above semiconductor devices, the interlayer insulating film may have a first interlayer insulating portion provided between the first plug region and the plurality of trench portions in the trench arrangement direction in a top view.

[0012] In any of the above semiconductor devices, the interlayer insulating film may have a second interlayer insulating portion provided between the anode region and the plurality of trench portions in the trench arrangement direction in a top view.

[0013] In any of the above semiconductor devices, a width of the first interlayer insulating portion in the trench extension direction may be larger than a width of the second interlayer insulating portion in the trench extension direction.

[0014] In any of the above semiconductor devices, the first interlayer insulation portion may be sandwiched in the trench arrangement direction between a plurality of first contact portions extending in the trench extension direction, and the first interlayer insulation portion may be sandwiched in the trench extension direction between a plurality of second contact portions extending in the trench arrangement direction.

[0015] In any of the above semiconductor devices, the second interlayer insulating portion may be sandwiched in the trench arrangement direction between a plurality of the first contact portions extending in the trench extension direction, and the second interlayer insulating portion may be sandwiched in the trench extension direction between a plurality of the second contact portions extending in the trench arrangement direction.

[0016] In any of the semiconductor devices described above, the front surface side electrode may have a barrier metal layer provided inside the first contact portion and the second contact portion.

[0017] Any of the above semiconductor devices may further comprise a transistor portion having a base region of a second conductivity type provided above the drift region, and the doping concentration of the anode region may be lower than the doping concentration of the base region.

[0018] In any of the above semiconductor devices, the transistor portion may include a contact region of a second conductivity type provided above the drift region, and the doping concentration of the first plug region may be higher than the doping concentration of the contact region.

[0019] In any of the above semiconductor devices, the transistor portion may further include a second plug region of a second conductivity type that is provided above the drift region and has a doping concentration higher than that of the base region.

[0020] In any one of the above semiconductor devices, the doping concentration of the anode region is 4E16 cm -3 Above, 1E17cm -3 It may be the following:

[0021] In any one of the above semiconductor devices, the doping concentration of the first plug region is 2E19 cm -3 More than 2E20cm -3 It may be the following:

[0022] In any of the above semiconductor devices, the first plug region may be provided spaced apart from trench sidewalls of the multiple trench portions in a trench arrangement direction of the multiple trench portions, the anode region may be provided extending from one trench sidewall to the other trench sidewall of the multiple trench portions in the trench arrangement direction, and the first plug region and the anode region may be provided alternately in the mesa portion in the trench extension direction of the multiple trench portions.

[0023] In any of the above semiconductor devices, in the mesa portion, an area of ​​the anode region on the front surface of the semiconductor substrate may be larger than an area of ​​the first plug region on the front surface of the semiconductor substrate.

[0024] In any of the above semiconductor devices, the front surface side electrode may have a plug layer made of tungsten.

[0025] In any of the above semiconductor devices, the diode section may further include a cathode region of the first conductivity type provided on a rear surface of the semiconductor substrate, and the doping concentration of the cathode region may be 5E19 cm -3 More than 2E20cm -3 It may be the following:

[0026] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0027] [Figure 1] 2 is a diagram showing an example of the top surface of the semiconductor device 100 of the present embodiment. [Figure 2A] 2 is a diagram showing an example of the top surface of the semiconductor device 100 of the present embodiment. [Figure 2B] 2 is a diagram showing an example of a-a' cross section of the semiconductor device 100 of the present embodiment. FIG. [Figure 2C] 2 is a diagram showing an example of the bb' cross section of the semiconductor device 100 of the present embodiment. FIG. [Figure 2D] 2 is a diagram showing an example of a cc' cross section of the semiconductor device 100 of the present embodiment. FIG. [Figure 2E] 2 is a diagram showing an example of a dd' cross section of the semiconductor device 100 of the present embodiment. FIG. [Figure 2F] 2 is a diagram showing an example of an ee' cross section of the semiconductor device 100 of the present embodiment. FIG. [Diagram 3] FIG. 2 is a diagram showing an example of an enlarged view of the top surface of the semiconductor device 100 of the present embodiment. [Figure 4] 1 is a diagram showing a modified example of an enlarged view of the top surface of the semiconductor device 100 of the present embodiment. [Diagram 5] 1 is a diagram showing an example of the upper surface of a semiconductor device 500 of a comparative example. [Figure 6A] 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100 of the present embodiment. [Figure 6B] 2 is a diagram showing an example of an ff' cross section of the semiconductor device 100 of the present embodiment. FIG. [Figure 6C] 2 is a diagram showing an example of the g-g' cross section of the semiconductor device 100 of the present embodiment. FIG. [Figure 6D] 2 is a diagram showing an example of an hh' cross section of the semiconductor device 100 of the present embodiment. FIG. [Figure 7A] FIG. 2 is a diagram showing a modification of the top view of the semiconductor device 100 of the present embodiment. [Figure 7B]FIG. 2 is a diagram showing a modification of the top view of the semiconductor device 100 of the present embodiment. [Figure 8] 1 is a diagram showing the relationship between the forward voltage Vf and the reverse recovery loss Err of the semiconductor device 100 of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0029] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0030] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0031] In this specification, a plane parallel to the upper surface of the semiconductor substrate is defined as the XY plane, and orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and Y-axis. An axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis. The depth direction of the semiconductor substrate may be referred to as the Z-axis. Note that in this specification, the case where the semiconductor substrate is viewed in the Z-axis direction is referred to as a planar view. Note that in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as a horizontal direction.

[0032] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.

[0033] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0034] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0035] In this specification, doping concentration refers to the concentration of donors or the concentration of acceptors at thermal equilibrium.

[0036] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type.

[0037] FIG. 1 shows an example of the top surface of the semiconductor device 100 of this example. The semiconductor device 100 may include a diode section 80 having an anode region 19 and a first plug region 83 on a front surface 21 of the semiconductor substrate 10, which will be described later. The semiconductor device 100 includes an interlayer insulating film 38, a first contact section 154, and a second contact section 254 above the front surface 21 of the semiconductor substrate 10, but these are omitted in FIG. 1. The interlayer insulating film 38, the first contact section 154, and the second contact section 254 will be described later. The semiconductor device 100 of this example also includes a front surface side electrode 52 provided above the front surface 21 of the semiconductor substrate 10.

[0038] A plurality of trench portions extending in a predetermined direction (in this example, the Y-axis direction) and arranged in a predetermined direction (in this example, the X-axis direction) are provided on the front surface 21 of the semiconductor substrate 10. The plurality of trench portions have dummy trench portions 30 to which a floating potential or an anode potential is applied. The diode portion 80 in this example has the dummy trench portion 30. When a transistor portion is provided in the semiconductor device 100, the diode portion 80 may have a gate trench portion to which a gate potential is applied.

[0039] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is an N+ type, for example. The details of the cathode region 82 will be described later.

[0040] FIG. 1 shows a region around the chip end, which is the edge (end) side of the semiconductor device 100, and omits other regions. For example, an edge termination structure may be provided in a region on the negative side in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, in this example, the edge on the negative side in the Y-axis direction will be described, but the same applies to the other edges of the semiconductor device 100. The edge termination structure may be provided to surround an active region through which a main current flows when the semiconductor device 100 is in operation.

[0041] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0042] The front surface electrode 52 is provided above the dummy trench portion 30, the well region 17, and the anode region 19. The front surface electrode 52 is formed of a material containing a metal. At least a portion of the front surface electrode 52 may be formed of a metal such as aluminum (Al) or an alloy containing aluminum, for example, a metal alloy such as an aluminum-silicon alloy (Al-Si) or an aluminum-silicon-copper alloy (Al-Si-Cu).

[0043] The front surface electrode 52 may have a barrier metal layer 61 made of titanium, a titanium compound, or the like under a region made of aluminum or an alloy containing aluminum. That is, the front surface electrode may have the barrier metal layer 61 provided inside a first contact portion 154 and a second contact portion 254, which will be described later. The barrier metal layer 61 will be described later.

[0044] The front surface side electrode 52 is provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. The interlayer insulating film 38 is omitted in Fig. 1. A contact hole 56 is provided penetrating the interlayer insulating film 38.

[0045] The contact hole 56 connects the front surface electrode 52 and the dummy conductive portion in the dummy trench portion 30. A plug layer 62 made of tungsten or the like may be formed inside the contact hole 56 via a barrier metal layer 61. That is, the front surface electrode 52 may have the plug layer 62 made of tungsten. The plug layer 62 will be described later.

[0046] The connection portion 25 electrically connects the front surface electrode 52 and the semiconductor substrate 10. In one example, the connection portion 25 is provided between the front surface electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0047] The dummy trench portions 30 are trench portions electrically connected to the front surface side electrodes 52. The dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The dummy trench portions 30 in this example may have two extension portions 31 extending along an extension direction (the Y-axis direction in this example) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 33 connecting the two extension portions 31.

[0048] At least a portion of the connection portion 33 may be formed in a curved shape. By connecting the ends of the two extension portions 31 of the dummy trench portion 30, it is possible to alleviate electric field concentration at the ends of the extension portions 31. At the connection portion 33 of the dummy trench portion 30, the front surface side electrode 52 may be connected to the dummy conductive portion.

[0049] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion is a portion of the semiconductor substrate 10 that is sandwiched between two adjacent trench portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. An extension portion of each trench portion may be regarded as one trench portion. In other words, the region sandwiched between the two extension portions may be regarded as a mesa portion.

[0050] The mesa portion 81 has an anode region 19 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has an anode region 19 and a well region 17 on the negative side in the Y-axis direction.

[0051] Well region 17 is a region of a second conductivity type provided on the surface on the front surface 21 side of semiconductor substrate 10. Well region 17 is an example of a well region provided on the edge side of semiconductor device 100. Well region 17 is, as an example, a P+ type.

[0052] Well region 17 is formed in a predetermined range from the end of the active region on the side where front surface electrode 52 is provided. Well region 17 may be provided in a predetermined range from the active region on the side closer to the edge termination structure to the edge termination structure. The diffusion depth of well region 17 may be deeper than the depth of dummy trench portion 30. A portion of dummy trench portion 30 is formed in well region 17. The bottom of the end of dummy trench portion 30 in the extension direction may be covered by well region 17.

[0053] The anode region 19 is a region of a second conductivity type provided above the drift region 18. The drift region 18 will be described later. In this example, the anode region 19 is, for example, a P-type. The doping concentration of the anode region 19 is 4E16 cm -3 It may be 1E17cm or more. -3 E is a power of 10, for example, 1E18 cm -3 is 1×10 18 cm -3 means.

[0054] The anode region 19 in this example is provided on the front surface 21 of the mesa portion 81. The anode region 19 may be provided in the X-axis direction from one of the two dummy trench portions 30 that sandwich the mesa portion 81 to the other. That is, the anode region 19 may be provided extending from one trench sidewall to the other trench sidewall of the multiple trench portions in the trench arrangement direction of the multiple trench portions. The anode region 19 is electrically connected to the front surface electrode 52 on the side surfaces of the multiple trench portions.

[0055] The first plug region 83 is a region of a second conductivity type having a higher doping concentration than the anode region 19. In this example, the first plug region 83 is, for example, a P++ type. The doping concentration of the first plug region 83 is 2E19 cm -3 More than 2E20cm -3 It may be the following:

[0056] In this example, the first plug region 83 is provided spaced apart from the trench sidewalls of the multiple trench portions in the trench arrangement direction of the multiple trench portions. An anode region 19 may be provided between the first plug region 83 and the trench sidewall on the front surface 21 of the semiconductor substrate 10. This reduces the amount of dopant implanted into the first plug region 83, and improves the forward voltage Vf of the diode portion 80.

[0057] In the mesa portion 81, the first plug region 83 and the anode region 19 may be provided alternately in the trench extension direction of the multiple trench portions. In the mesa portion 81, the area of ​​the anode region 19 on the front surface 21 of the semiconductor substrate 10 may be larger than the area of ​​the first plug region 83 on the front surface 21 of the semiconductor substrate 10. By adjusting the amount of the second conductivity type dopant in the diode portion 80, the values ​​of the forward voltage Vf and reverse recovery loss Err of the diode portion 80 can be adjusted.

[0058] Fig. 2A is a diagram showing an example of the upper surface of the semiconductor device 100 of this embodiment. Fig. 2A shows the interlayer insulating film 38, the first contact portion 154, and the second contact portion 254, which are omitted in Fig. 1.

[0059] The first contact portion 154 and the second contact portion 254 are provided inside contact holes extending from the upper surface of the interlayer insulating film 38 in the depth direction of the semiconductor substrate 10. The first contact portion 154 and the second contact portion 254 are provided extending in different directions. The first contact portion 154 and the second contact portion 254 may be provided so as to intersect. The first contact portion 154 and the second contact portion 254 may be formed integrally.

[0060] The first contact portion 154 and the second contact portion 254 are one example of the front surface side electrode 52. The first contact portion 154 and the second contact portion 254 include a barrier metal layer 61 and a plug layer 62 inside the interlayer insulating film .

[0061] The first contact portion 154 may be provided above the mesa portion 81, extending in the trench extension direction of the multiple trench portions. The first contact portion 154 may be connected to the anode region 19, may be connected to the first plug region 83, or may be connected to both the anode region 19 and the first plug region 83.

[0062] The semiconductor device 100 may be provided with a plurality of first contact portions 154. In this example, the first contact portions 154 are arranged in a stripe pattern along the dummy trench portion 30. By injecting a dopant through a contact hole for providing the first contact portion 154 and forming a first plug region 83, the amount of the second conductivity type dopant in the diode portion 80 can be adjusted, and the values ​​of the forward voltage Vf and reverse recovery loss Err of the diode portion 80 can be adjusted.

[0063] The second contact portion 254 may be provided on the front surface 21 of the semiconductor substrate 10, extending from one trench sidewall to the other trench sidewall in the trench arrangement direction of the multiple trench portions, and connected to the mesa portion 81. The second contact portion 254 may be provided on the front surface 21 of the semiconductor substrate 10, extending beyond at least one of the multiple trench portions in the trench arrangement direction of the multiple trench portions, and connected to at least one of the trench portions. The second contact portion 254 of this example is provided extending in the trench arrangement direction of the multiple trench portions, and is connected to the multiple trench portions and the mesa portion 81.

[0064] The second contact portion 254 may be provided above the anode region 19 and the multiple trench portions that are alternately provided in the trench arrangement direction. The second contact portion 254 may be provided in common to the multiple mesa portions 81 in the trench arrangement direction of the multiple trench portions, or may be provided in a single mesa portion 81.

[0065] By providing the second contact portion 254, the area of ​​the connection portion between the front surface side electrode 52 and the semiconductor substrate 10 in the anode region 19 can be made larger than the case where the second contact portion 254 is not provided. As a result, holes injected from the first plug region 83 can be extracted via the second contact portion 254, thereby improving the forward voltage Vf of the diode portion.

[0066] The semiconductor device 100 may be provided with a plurality of second contact portions 254. The plurality of second contact portions 254 may be provided above the anode regions 19 and the plurality of trench portions that are provided alternately in the trench arrangement direction. In this example, the second contact portions 254 are arranged in a stripe pattern along a direction perpendicular to the dummy trench portions 30. By providing the second contact portions 254, peeling of the plug layer 62 formed of tungsten or the like can be prevented.

[0067] The interlayer insulating film 38 is provided above a mesa portion 81 provided between the plurality of trench portions. The interlayer insulating film 38 may be provided above the plurality of trench portions.

[0068] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, or a phosphosilicate glass (PSG) film. The interlayer insulating film 38 may include a high temperature silicon oxide (HTO) film.

[0069] The interlayer insulating film 38 of this example includes a first interlayer insulating portion 381 and a second interlayer insulating portion 382. The first interlayer insulating portion 381 and the second interlayer insulating portion 382 may be made of the same material or different materials.

[0070] The first interlayer insulating portion 381 is provided between the first plug region 83 and the plurality of trench portions in the trench arrangement direction in a top view. By providing the first interlayer insulating portion 381, the amount of dopant implanted when forming the first plug region 83 can be adjusted.

[0071] The first interlayer insulating portion 381 is provided in the trench arrangement direction so as to be sandwiched between a plurality of first contact portions 154 extending in the trench extension direction. The first interlayer insulating portion 381 is provided in the trench extension direction so as to be sandwiched between a plurality of second contact portions 254 extending in the trench arrangement direction. That is, the first interlayer insulating portion 381 is provided in an island shape above the upper surface of the semiconductor substrate 10. This reduces the area of ​​the plug layer 62 of the front surface side electrode 52 and suppresses film peeling of the plug layer 62.

[0072] The second interlayer insulating portion 382 is provided between the anode region 19 and the plurality of trench portions in the trench arrangement direction when viewed from above. By providing the second interlayer insulating portion 382, ​​the area of ​​the portion where the second contact portion 254 and the anode region 19 are connected can be adjusted, and the characteristics of the semiconductor device 100 can be adjusted.

[0073] The second interlayer insulating portion 382 is provided in the trench arrangement direction so as to be sandwiched between a plurality of first contact portions 154 extending in the trench extension direction. The second interlayer insulating portion 382 is provided in the trench extension direction so as to be sandwiched between a plurality of second contact portions 254 extending in the trench arrangement direction. That is, the second interlayer insulating portion 382 is provided in an island shape above the upper surface of the semiconductor substrate 10. This reduces the area of ​​the plug layer 62 of the front surface side electrode 52 and suppresses film peeling of the plug layer 62.

[0074] Fig. 2B is a diagram showing an example of the a-a' cross section in Fig. 2A. The a-a' cross section is an XZ cross section passing through the second contact portion 254. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10 provided with a drift region 18, an anode region 19, a cathode region 82, and a buffer region 20, a front surface side electrode 52, and a back surface side electrode 24.

[0075] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0076] A first conductivity type buffer region 20 may be provided below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the anode region 19 from reaching the cathode region 82.

[0077] The back surface electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The back surface electrode 24 is formed of a conductive material such as a metal. The material of the back surface electrode 24 may be the same as or different from the material of the front surface electrode 52. The back surface electrode 24 may also be formed by laminating multiple metal layers made of different materials. The back surface electrode 24 is, for example, a cathode electrode.

[0078] One or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In the region where the anode region 19 is provided, each trench portion penetrates the anode region 19 to reach the drift region 18. The trench portion penetrating the doped region is not limited to being manufactured in the order of forming the doped region and then the trench portion. The trench portion penetrating the doped region also includes a trench portion formed after the trench portion is formed.

[0079] The dummy trench portion 30 has a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.

[0080] The cathode region 82 is provided on the rear surface 23 of the semiconductor substrate 10 in the diode section 80. The cathode region 82 is a region of the first conductivity type having a higher doping concentration than the drift region 18. The doping concentration of the cathode region is 5E19 cm -3 It may be 2E20cm or more. -3 It may be the following:

[0081] 2B, no interlayer insulating film 38 is provided on the front surface 21. This makes it easier to extract holes from the anode region 19 compared to when the interlayer insulating film 38 is provided, and the forward voltage Vf of the diode portion can be improved. A barrier metal layer 61 made of titanium, a titanium compound, or the like may be provided between the front surface 21 and the front surface electrode 52. In addition, a plug layer 62 made of tungsten or the like may be provided on the upper surface of the barrier metal layer 61.

[0082] Fig. 2C is a diagram showing an example of the bb' cross section in Fig. 2A. The bb' cross section is an XZ cross section that passes through the second interlayer insulating part 382 but does not pass through the first plug region 83. Differences from Fig. 2B will be described using Fig. 2C.

[0083] The front surface side electrode 52 has a first contact portion 154. The first contact portion 154 is provided so as to be sandwiched between the second interlayer insulating portions 382 in the trench arrangement direction of the multiple trench portions. That is, the first contact portion 154 is provided so as to be embedded inside a contact hole provided in the interlayer insulating film 38.

[0084] The first contact portion 154 may have a barrier metal layer 61 formed of titanium, a titanium compound, or the like inside. A plug layer 62 formed of tungsten or the like may be formed inside the barrier metal layer 61. The semiconductor substrate 10 is connected to the front surface electrode 52 via the first contact portion 154. The barrier metal layer 61 may be provided on the upper surface of the second interlayer insulating portion 382.

[0085] 2C, a second interlayer insulating portion 382 is provided on the front surface 21 of the semiconductor substrate 10. The second interlayer insulating portion 382 may be provided so as to be sandwiched between two first contact portions 154 in the trench arrangement direction of the multiple trench portions. In addition, the dummy trench portion 30 is covered by the second interlayer insulating portion 382 on the front surface 21.

[0086] Fig. 2D is a diagram showing an example of the c-c' cross section in Fig. 2A. The c-c' cross section is an XZ cross section passing through the first interlayer insulating portion 381 and the first plug region 83. Differences from Fig. 2B and Fig. 2C will be described using Fig. 2D.

[0087] The first contact portion 154 is provided so as to be sandwiched between the first interlayer insulating portions 381 in the trench arrangement direction of the multiple trench portions. That is, the first contact portion 154 is provided so as to be embedded inside a contact hole provided in the interlayer insulating film 38.

[0088] The first contact portion 154 may have a barrier metal layer 61 formed of titanium, a titanium compound, or the like inside. A plug layer 62 formed of tungsten or the like may be formed inside the barrier metal layer 61. The semiconductor substrate 10 is connected to the front surface electrode 52 via the first contact portion 154. The barrier metal layer 61 may be provided on the upper surface of the first interlayer insulating portion 381.

[0089] The first plug region 83 is provided below the first contact portion 154. The first plug region 83 may be formed by injecting a dopant through a contact hole for providing the first contact portion 154. By providing the first plug region 83, it is possible to make ohmic contact between the semiconductor substrate 10 and the front surface side electrode 52.

[0090] 2D, a first interlayer insulating portion 381 is provided on the front surface 21 of the semiconductor substrate 10. The first interlayer insulating portion 381 may be provided so as to be sandwiched between two first contact portions 154 in the trench array of a plurality of trench portions. In addition, the dummy trench portion 30 is covered by the first interlayer insulating portion 381 on the front surface 21. By providing the first interlayer insulating portion 381, the amount of dopant implanted when forming the first plug region 83 can be adjusted.

[0091] 2E is a diagram showing an example of the dd' cross section in Fig. 2A. The dd' cross section is a YZ cross section passing through the first interlayer insulating portion 381, the second interlayer insulating portion 382, ​​the second contact portion 254, and the dummy trench portion 30.

[0092] 2E, in an area above the dummy trench portion 30 where the first interlayer insulating portion 381 and the second interlayer insulating portion 382 are not provided, the front surface side electrode 52 and the dummy conductive portion 34 are connected. Even if the dummy conductive portion 34 is connected to the front surface side electrode 52, this does not affect the value of the forward voltage Vf of the diode portion 80. Therefore, by designing in this manner, it is possible to adjust the characteristics of the semiconductor device 100 without additional manufacturing costs.

[0093] The second contact portion 254 is provided between the first interlayer insulating portion 381 and the second interlayer insulating portion 382 in the trench extension direction of the multiple trench portions. That is, the second contact portion 254 is provided in a contact hole formed in the interlayer insulating film 38 in the trench arrangement direction of the multiple trench portions.

[0094] Similar to the first contact portion 154, the second contact portion 254 may have a barrier metal layer 61 formed of titanium, a titanium compound, or the like inside. A plug layer 62 formed of tungsten or the like may be provided inside the barrier metal layer 61. The semiconductor substrate 10 is connected to the front surface side electrode 52 via the second contact portion 254. The barrier metal layer 61 may be provided on the upper surfaces of the first interlayer insulating portion 381 and the second interlayer insulating portion 382.

[0095] The first interlayer insulating portion 381 may be provided so as to be sandwiched between two second contact portions 254 in the trench extension direction of the multiple trench portions. The second interlayer insulating portion 382 may be provided so as to be sandwiched between two second contact portions 254 in the trench extension direction of the multiple trench portions. By arranging the first interlayer insulating portion 381 and the second interlayer insulating portion 382 in an island shape in this manner, the area of ​​the front surface side electrode 52 can be reduced and film peeling of the front surface side electrode 52 can be suppressed.

[0096] 2F is a diagram showing an example of the ee' cross section in FIG. 2A. The ee' cross section is a YZ cross section passing through the first contact portion 154, the anode region 19, and the first plug region 83.

[0097] The first contact portion 154 is provided extending in the trench extension direction of the multiple trench portions, and is connected to the semiconductor substrate 10. The first contact portion 154 is connected to the anode region 19 and the first plug region 83. Some of the holes injected from the first plug region 83 are extracted from the first contact portion 154 via the anode region 19, thereby improving the forward voltage of the diode portion 80 and reducing the reverse recovery loss Err.

[0098] Fig. 3 is a diagram showing an example of an enlarged view of the upper surface of the semiconductor device 100 of this example. Fig. 3 shows an enlarged view of one mesa portion 81 provided between two dummy trench portions 30. In Fig. 3, the first contact portion 154 and the second contact portion 254 are indicated by hatching from the upper right to the lower left, and the position of the first plug region 83 provided below these contact portions is indicated by hatching from the upper left to the lower right.

[0099] The hatched portion may have a barrier metal layer 61 (not shown) made of titanium, a titanium compound, or the like. A plug layer 62 (not shown) made of tungsten or the like may be provided inside the barrier metal layer 61. Furthermore, the barrier metal layer 61 may be provided on the upper surface of the interlayer insulating film 38 (first interlayer insulating portion 381, second interlayer insulating portion 382) (not shown).

[0100] The first contact portion 154 has a predetermined width W154 in the trench arrangement direction of the multiple trench portions. The width W154 of the first contact portion 154 in the trench arrangement direction may be greater than the width W254 of the second contact portion 254 in the trench extension direction. In one example, W154 may be 0.1 μm or more and 1.0 μm or less.

[0101] The second contact portion 254 has a predetermined width W254 in the trench extension direction of the multiple trench portions. The width W254 of the second contact portion 254 in the trench extension direction may be smaller than the width W154 of the first contact portion 154 in the trench arrangement direction. In one example, W254 may be 0.1 μm or more and 1.0 μm or less.

[0102] The first interlayer insulating portion 381 has a predetermined width W381 in the trench extension direction of the multiple trench portions. The width W381 in the trench extension direction of the first interlayer insulating portion 381 is greater than the width W382 in the trench extension direction of the second interlayer insulating portion 382. This increases the amount of dopant in the diode portion 80, thereby improving the breakdown voltage of the semiconductor device 100. In one example, W381 may be 0.1 μm or more and 1.0 μm or less.

[0103] The second interlayer insulating portion 382 has a predetermined width W382 in the trench extension direction of the multiple trench portions. The width W382 in the trench extension direction of the second interlayer insulating portion 382 is smaller than the width W381 in the trench extension direction of the first interlayer insulating portion 381. In one example, W382 may be 0 μm or more and 0.8 μm or less.

[0104] 4 is a diagram showing a modified example of an enlarged view of the upper surface of the semiconductor device 100 of this embodiment. Differences from FIG. 3 will be described with reference to FIG.

[0105] The interlayer insulating film 38 includes a third interlayer insulating portion 383 provided above the dummy trench portion 30. The third interlayer insulating portion 383 may be provided between the first interlayer insulating portion 381 and the second interlayer insulating portion 382 in the trench extension direction of the multiple trench portions. The third interlayer insulating portion 383 may extend from above the dummy trench portion 30 in the trench arrangement direction of the multiple trench portions and be provided above the anode region 19.

[0106] The material of third interlayer insulating portion 383 may be the same as or different from the material of first interlayer insulating portion 381 and second interlayer insulating portion 382. When first interlayer insulating portion 381, second interlayer insulating portion 382, ​​and third interlayer insulating portion 383 are all made of the same material, these three interlayer insulating portions do not need to be distinguished.

[0107] That is, the interlayer insulating film 38 may be provided so as to extend in the trench extension direction of the multiple trench portions and cover the upper surfaces of the dummy trench portions 30. The interlayer insulating film 38 may extend from above the dummy trench portions 30 in the trench arrangement direction of the multiple trench portions at a predetermined interval W254 so as to have predetermined widths W381 and W382. In this case, the interlayer insulating film 38 may be formed in a comb-like shape.

[0108] The hatched portion may have a barrier metal layer 61 (not shown) made of titanium, a titanium compound, or the like. A plug layer 62 (not shown) made of tungsten or the like may be provided inside the barrier metal layer 61. Furthermore, the barrier metal layer 61 may be provided on the upper surface of the interlayer insulating film 38 (first interlayer insulating portion 381, second interlayer insulating portion 382, ​​third interlayer insulating portion 383) (not shown).

[0109] The second contact portion 254 is provided, in a top view, extending in the trench arrangement direction of the multiple trench portions from an end of one third interlayer insulating portion 383 to an end of the other third interlayer insulating portion 383, and is connected to the mesa portion 81. This allows holes injected from the first plug region 83 to be extracted from the second contact portion 254 via the anode region 19, thereby improving the forward voltage Vf of the diode portion 80.

[0110] Fig. 5 is a diagram showing an example of the upper surface of a semiconductor device 500 of a comparative example. Using Fig. 5, differences from Fig. 2A showing an example of the upper surface of the semiconductor device 100 of this example will be described.

[0111] In the semiconductor device 500 of the comparative example, the second contact portion 254 is not provided, and only the contact portion 554 is provided. The contact portion 554 may have a configuration similar to that of the first contact portion 154 in the semiconductor device 100 of the present example. That is, the contact portion 554 may be provided inside a contact hole formed in an interlayer insulating film.

[0112] In the semiconductor device 500 of the comparative example, the second contact portion 254 is not provided, and therefore the amount of holes drawn from the front surface side electrode 52 is smaller than that in the semiconductor device 100 of the present example. Therefore, the semiconductor device 500 of the comparative example has a smaller forward voltage Vf and an increased reverse recovery loss Err than the semiconductor device 100 of the present example.

[0113] 6A is a diagram showing a modified example of the upper surface of the semiconductor device 100 of this example. The semiconductor device 100 may be a semiconductor chip further including a transistor section 70. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 may include a boundary region in a portion adjacent to the diode section 80. The transistor section 70 of this example does not include a boundary region.

[0114] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. In this example, the collector region 22 is, for example, a P+ type. The transistor section 70 includes a transistor such as an IGBT.

[0115] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a well region 17, and an anode region 19 on a front surface 21 of a semiconductor substrate 10. The semiconductor device 100 of this example includes a second plug region 73 provided in a mesa portion 71 of a transistor portion 70 and a first plug region 83 provided in a mesa portion 81 of a diode portion 80. The semiconductor device 100 of this example also includes a front surface side electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0116] The interlayer insulating film 38 of this example includes a first interlayer insulating portion 381 and a second interlayer insulating portion 382. The first interlayer insulating portion 381 and the second interlayer insulating portion 382 may be made of the same material or different materials. The second interlayer insulating portion 382 is provided in the trench arrangement direction so as to be sandwiched between a plurality of first contact portions 154 extending in the trench extension direction. The second interlayer insulating portion 382 is provided in the trench extension direction so as to be sandwiched between a plurality of second contact portions 254 extending in the trench arrangement direction. That is, the second interlayer insulating portion 382 is provided in an island shape above the upper surface of the semiconductor substrate 10. This reduces the area of ​​the plug layer 62 of the front surface side electrode 52, and prevents the plug layer 62 from peeling off.

[0117] The gate metal layer 50 is formed of a material containing a metal. At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al) or an alloy containing aluminum, for example, an aluminum-silicon alloy (Al-Si) or an aluminum-silicon-copper alloy (Al-Si-Cu). The gate metal layer 50 is provided separately from the front surface electrode 52.

[0118] The front surface side electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. The interlayer insulating film 38 is omitted in Fig. 6A. A contact hole 55 is provided so as to penetrate the interlayer insulating film 38.

[0119] The contact hole 55 connects the gate metal layer 50 and a gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed via a barrier metal.

[0120] In the modification shown in FIG. 6A, a contact portion 54 is provided in the transistor portion 70. The contact portion 54 is formed on the upper surface of each of the emitter region 12 and the contact region 15. The width of the contact portion 54 in the trench arrangement direction of the multiple trench portions may be the same as the width of the first contact portion 154 in the trench arrangement direction, and may have the same configuration as the first contact portion 154. The width of the contact portion 54 in the trench arrangement direction may be different from the width of the first contact portion 154 in the trench arrangement direction.

[0121] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (the Y-axis direction in this example) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0122] At least a portion of the connection portion 43 may be formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to reduce electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0123] The transistor section 70 of this example has a structure in which one gate trench section 40 and one dummy trench section 30 are repeatedly arranged. That is, the transistor section 70 of this example has the gate trench section 40 and the dummy trench section 30 in a 1:1 ratio. For example, the transistor section 70 has one extension section 31 between two extension sections 41. The transistor section 70 also has one extension section 41 between two extension sections 31.

[0124] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all the trench portions as the gate trench portions 40 and may not have the dummy trench portions 30.

[0125] The mesa portion 71 is provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction of the trench portion (the Y-axis direction in this example) on the front surface 21 of the semiconductor substrate 10.

[0126] The base region 14 is a region of the second conductivity type provided above the drift region 18. The doping concentration of the base region 14 may be higher than the doping concentration of the anode region 19. That is, in this example, the doping concentration of the anode region 19 is lower than the doping concentration of the base region 14. The base region 14 is, for example, a P type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. FIG. 6A shows only one end of the base region 14 in the Y-axis direction.

[0127] The emitter region 12 is a first conductivity type region provided above the base region 14 and has a higher doping concentration than the drift region 18. In this example, the emitter region 12 is an N+ type, for example. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided in contact with the gate trench portion 40 on the front surface 21 of the mesa portion 71. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other.

[0128] Moreover, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0129] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the contact region 15 is of P+ type, for example. In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40.

[0130] The doping concentration of the contact region 15 is lower than the doping concentration of the first plug region 83 provided in the diode section 80. That is, the doping concentration of the first plug region 83 is higher than the doping concentration of the contact region 15. The doping concentration of the contact region 15 is 2E19 cm -3 It may be 2E20cm or more. -3 It may be the following:

[0131] The second plug region 73 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the second plug region 73 is, for example, a P++ type. The doping concentration of the second plug region 73 may be the same as or different from the doping concentration of the first plug region 83. The second plug region 73 may be formed by injecting a dopant through a contact hole for providing the contact portion 54.

[0132] The second plug region 73 is provided in the contact region 15, and does not have to be provided in the emitter region 12. In this example, the second plug region 73 is provided at the same position as the first plug region 83 in the trench arrangement direction of the multiple trench portions. This allows the first plug region 83 and the second plug region 73 to be formed in the same ion implantation step, thereby reducing manufacturing costs.

[0133] 6B is a diagram showing an example of the f-f' cross section in FIG. 6A. The f-f' cross section is an XZ cross section passing through the second contact portion 254. In the f-f' cross section, the semiconductor device 100 of this example has the emitter region 12, the base region 14, the accumulation region 16, the drift region 18, the buffer region 20, the semiconductor substrate 10 in which the first plug region 83 and the second plug region 73 are provided, the interlayer insulating film 38, the front surface side electrode 52, and the back surface side electrode 24. The cathode region 82 of this example may include a first cathode portion 181 and a second cathode portion 182 in the trench extension direction (Y-axis direction). The first cathode portion 181 and the second cathode portion 182 will be described later.

[0134] The accumulation region 16 is a first conductivity type region that is provided below the base region 14 in the depth direction of the semiconductor substrate 10 and has a higher doping concentration than the drift region 18. The accumulation region 16 in this example is an N+ type, for example. The accumulation region 16 is provided in the transistor section 70, and is not provided in the diode section 80. By providing the first accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0135] One or more gate trench portions 40 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In a region where at least one of the emitter region 12, the base region 14, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the trench portion is formed and then the doped region is formed between the trench portions is also included in the case where the trench portion penetrates the doped region.

[0136] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0137] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0138] Fig. 6C is a diagram showing an example of the g-g' cross section in Fig. 6A. The g-g' cross section is an XZ cross section passing through the first plug region 83 and the second plug region 73. Using Fig. 6C, differences from Fig. 6B will be described.

[0139] 6C, a contact region 15 and a second plug region 73 are provided in the transistor section 70. The position of the lower end of the second plug region 73 in the depth direction of the semiconductor substrate 10 may be deeper than the position of the lower end of the contact region 15. This improves extraction of holes via the second plug region 73, thereby improving the latch-up resistance of the semiconductor device 100.

[0140] 6D is a diagram showing an example of the h-h' cross section in FIG. 6A. The h-h' cross section is a YZ cross section passing through the first interlayer insulating portion 381, the second interlayer insulating portion 382, ​​the second contact portion 254, and the dummy trench portion 30. The cathode region 82 may have a first cathode portion 181 and a second cathode portion 182. The first cathode portion 181 is a region of a first conductivity type having a doping concentration higher than that of the drift region 18. In one example, the first cathode portion 181 is an N+ type.

[0141] The second cathode portion 182 is a second conductive type region provided adjacent to the first cathode portion 181 on the rear surface 23 of the semiconductor substrate 10. That is, the second cathode portion 182 may be in direct contact with the first cathode portion 181. In one example, the second cathode portion 182 is P+ type. The first cathode portion 181 and the second cathode portion 182 may be alternately arranged in the trench extension direction (Y-axis direction). Furthermore, the widths of the first cathode portion 181 and the second cathode portion 182 in the trench extension direction (Y-axis direction) are not limited by the structure on the front surface 21 side of the semiconductor substrate 10 and can be set arbitrarily.

[0142] The first cathode portion 181 may be formed by ion implanting an N-type dopant after a P-type dopant has been ion implanted in an ion implantation process for forming the second cathode portion 182. Conversely, the second cathode portion 182 may be formed by ion implanting a P-type dopant after an N-type dopant has been ion implanted in an ion implantation process for forming the first cathode portion 181.

[0143] The first cathode portion 181 and the second cathode portion 182 may be arranged alternately in any direction. In this example, the first cathode portion 181 and the second cathode portion 182 are arranged alternately in the trench extension direction (for example, the Y-axis direction), but may be arranged alternately in the trench arrangement direction (for example, the X-axis direction). The first cathode portion 181 and the second cathode portion 182 may be arranged in a stripe pattern when viewed from above. One of the first cathode portion 181 and the second cathode portion 182 may be formed in a dot pattern.

[0144] In the cathode region 82 in the diode section 80 of the present example, a second cathode section 182 may be provided. In the cathode region 82 in the diode section 80 of the present example, the first cathode section 181 and the second cathode section 182 may be provided alternately. In the cathode region 82 in the diode section 80 of the present example, the first cathode section 181 and the second cathode section 182 may be provided so as to be in contact with each other. This reduces the concentration of the first conductive type dopant in the cathode region 82, and the forward voltage Vf of the diode section 80 can be improved.

[0145] Fig. 7A is a diagram showing a modification of the upper surface of the semiconductor device 100 of this embodiment. Differences from Fig. 2A will be described with reference to Fig. 7A.

[0146] In the modification shown in Fig. 7A, there is no second interlayer insulating portion 382. In this example, in the region between two first interlayer insulating portions 381 adjacent to each other in the trench extension direction, the second interlayer insulating portion 382 is not provided, and the second contact portion 254 is provided instead. This makes it possible to obtain the same effect as in Fig. 2A, and also to increase the extraction of holes from the anode region 19, thereby improving the forward voltage Vf of the diode portion.

[0147] Fig. 7B is a diagram showing a modified example of the upper surface of the semiconductor device 100 of this example. The semiconductor device 100 may be a semiconductor chip further including a transistor section 70. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 may include a boundary region in a portion adjacent to the diode section 80. The transistor section 70 of this example does not include a boundary region. Differences from Fig. 6A will be described with reference to Fig. 7B.

[0148] In the modification shown in Fig. 7B, there is no second interlayer insulating portion 382. In this example, in the region between two first interlayer insulating portions 381 adjacent to each other in the trench extension direction, the second interlayer insulating portion 382 is not provided, and the second contact portion 254 is provided instead. This makes it possible to obtain the same effect as in Fig. 6A, and also to increase the extraction of holes from the anode region 19, thereby improving the forward voltage Vf of the diode portion.

[0149] Fig. 8 is a graph showing the relationship between the forward voltage Vf of the diode section 80 and the reverse recovery loss Err in the semiconductor device 500 of the comparative example and the semiconductor device 100 of the present example. In Fig. 8, the forward voltage Vf of the diode section 80 is plotted on the horizontal axis, and the reverse recovery loss Err is plotted on the vertical axis. In the figure, the black circles correspond to the semiconductor device 500 of the comparative example, and the white circles correspond to the semiconductor device 100 of the embodiment.

[0150] In the semiconductor device 100 of the present embodiment, by providing the second contact portion 254, the hole current flowing through the front surface side electrode 52 is larger than that of the semiconductor device 500 of the comparative example. This allows the forward voltage Vf of the semiconductor device 100 to be higher than the forward voltage Vf of the semiconductor device 500 of the comparative example. In addition, since the forward voltage Vf is higher, the reverse recovery loss Err of the semiconductor device 100 can be lower than the reverse recovery loss Err of the semiconductor device 500 of the comparative example.

[0151] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0152] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0153] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 19 anode region, 20 buffer region, 21 front surface, 22 collector region, 23 rear surface, 24 rear surface electrode, 25 connection portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 50 gate metal layer, DESCRIPTION OF THE PREFERRED EMBODIMENTS 52 front surface electrode, 54 contact portion, 55 contact hole, 56 contact hole, 61 barrier metal layer, 62 plug layer, 70 transistor portion, 71 mesa portion, 73 second plug region, 80 diode portion, 81 mesa portion, 82 cathode region, 83 first plug region, 100 semiconductor device, 154 first contact portion, 254 second contact portion, 181 first cathode portion, 182 second cathode portion, 381 first interlayer insulating portion, 382 second interlayer insulating portion, 383 third interlayer insulating portion, 500 semiconductor device, 554 contact portion

Claims

1. A semiconductor device including a diode portion, A plurality of trenches provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; a second conductivity type anode region provided above the drift region in the diode portion; a first plug region of a second conductivity type provided above the drift region in the diode portion and having a doping concentration higher than that of the anode region; a front surface electrode provided above the semiconductor substrate; an interlayer insulating film provided above a mesa portion provided between the plurality of trench portions; Equipped with The anode region is connected to the front surface electrode on the side surfaces of the plurality of trench portions. Semiconductor device.

2. a first contact portion extending in a trench extension direction of the trench portions above the mesa portion and connected to the anode region and the first plug region; The semiconductor device according to claim 1 .

3. a second contact portion extending from a sidewall of one of the plurality of trench portions to a sidewall of the other of the plurality of trench portions in a trench arrangement direction of the plurality of trench portions on the front surface of the semiconductor substrate and connected to the mesa portion; The semiconductor device according to claim 2 .

4. The second contact portion extends beyond at least one of the trench portions in a trench arrangement direction of the trench portions and is connected to the at least one trench portion. The semiconductor device according to claim 3 .

5. The width of the first contact portion in the trench arrangement direction is larger than the width of the second contact portion in the trench extension direction. The semiconductor device according to claim 4.

6. The second contact portion is provided above the anode region and the plurality of trench portions that are alternately provided in the trench arrangement direction. The semiconductor device according to claim 4.

7. A plurality of the second contact portions are provided above the anode regions and the plurality of trench portions that are alternately provided in the trench arrangement direction. The semiconductor device according to claim 4.

8. The interlayer insulating film has a first interlayer insulating portion provided between the first plug region and the plurality of trench portions in the trench arrangement direction when viewed from above. The semiconductor device according to claim 4.

9. The interlayer insulating film has a second interlayer insulating portion provided between the anode region and the plurality of trench portions in the trench arrangement direction when viewed from above. The semiconductor device according to claim 8.

10. The width of the first interlayer insulating portion in the trench extension direction is larger than the width of the second interlayer insulating portion in the trench extension direction. The semiconductor device according to claim 9.

11. the first interlayer insulating portion is sandwiched between a plurality of the first contact portions extending in the trench extension direction in the trench arrangement direction, The first interlayer insulating portion is sandwiched between a plurality of the second contact portions extending in the trench arrangement direction in the trench extension direction. The semiconductor device according to claim 8.

12. the second interlayer insulating portion is sandwiched between a plurality of the first contact portions extending in the trench extension direction in the trench arrangement direction, The second interlayer insulating portion is sandwiched between a plurality of the second contact portions extending in the trench arrangement direction in the trench extension direction. The semiconductor device according to claim 9.

13. The front surface electrode has a barrier metal layer provided inside the first contact portion and the second contact portion. The semiconductor device according to claim 4.

14. a transistor portion having a base region of a second conductivity type provided above the drift region, The doping concentration of the anode region is lower than the doping concentration of the base region. The semiconductor device according to claim 1 .

15. a contact region of a second conductivity type provided above the drift region in the transistor portion; The doping concentration of the first plug region is higher than the doping concentration of the contact region. The semiconductor device according to claim 14.

16. a second plug region of a second conductivity type provided above the drift region and having a doping concentration higher than that of the base region in the transistor section; The semiconductor device according to claim 14.

17. The doping concentration of the anode region is 4E16 cm －３ Above, 1E17cm －３ is less than or equal to The semiconductor device according to claim 1 .

18. The doping concentration of the first plug region is 2E19 cm －３ Above, 2E20cm －３ is less than or equal to The semiconductor device according to claim 1 .

19. the first plug region is provided spaced apart from trench sidewalls of the trench portions in a trench arrangement direction of the trench portions, the anode region is provided to extend from one trench sidewall to the other trench sidewall of the plurality of trench portions in the trench arrangement direction; The first plug region and the anode region are provided alternately in the mesa portion in a trench extension direction of the plurality of trench portions. The semiconductor device according to claim 1 .

20. In the mesa portion, the area of ​​the anode region on the front surface of the semiconductor substrate is larger than the area of ​​the first plug region on the front surface of the semiconductor substrate. The semiconductor device according to claim 1 .

21. The front surface electrode has a plug layer made of tungsten. The semiconductor device according to claim 1 .

22. the diode portion includes a cathode region of a first conductivity type provided on a rear surface of the semiconductor substrate; The doping concentration of the cathode region is 5E19 cm －３ Above, 2E20cm －３ Is less than or equal to The semiconductor device according to claim 1 .

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