Semiconductor device and method for manufacturing the same

Abstract

To improve the performance of a semiconductor device including an LDMOSFET.SOLUTION: An insulation film 100 in contact with a field plate electrode FP is formed between the field plate electrode FP and a gate electrode GE, and a hollow 200 is formed in the upper surface of the insulation film 100 between a drain region DR and the gate electrode GE.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having a lateral diffused field effect transistor (LDMOSFET) and a manufacturing technique thereof that is effectively applicable thereto. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2018-50048 (Patent Document 1) describes a technique for improving the performance of a semiconductor device including an LDMOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-50048 A Summary of the Invention [Problem to be solved by the invention]

[0004] For example, LDMOSFET is known as a power device that can be integrated with CMOSFET (Complementary MOSFET). Power devices require improved breakdown voltage and reduced on-resistance, which are in a trade-off relationship. For this reason, LDMOSFET, which is one type of power device, also needs to be improved in both terms: improved breakdown voltage and reduced on-resistance. [Means for solving the problem]

[0005] In one embodiment, the semiconductor device has an insulating film between the field plate electrode and the gate electrode in contact with the field plate electrode, and the insulating film has a recess on its upper surface between the drain region and the gate electrode in order to reduce the distance between the field plate electrode and the lower end of the gate electrode, and this recess is filled with a part of the field plate electrode.

[0006] In one embodiment, a method for manufacturing a semiconductor device includes a step of forming an insulating film so as to contact a portion of an upper surface of a gate electrode, a sidewall spacer, and a semiconductor substrate, and in this step, the insulating film is formed by using an atmospheric pressure CVD method or a plasma CVD method. Effect of the Invention

[0007] According to one embodiment, the performance of a semiconductor device including an LDMOSFET can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device including an LDMOSFET. [Diagram 2] FIG. 2 is an enlarged view showing the configuration between a field plate electrode and a lower end of a gate electrode. [Diagram 3] 1A and 1B are diagrams for explaining a schematic diagram of a difference between a depression and the surface roughness of an insulating film. [Figure 4] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Diagram 5] 5 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 4. [Figure 6] 6 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 5. [Figure 7] 7 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 6. [Figure 8] 8 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 7. [Figure 9] 9 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 8. [Figure 10]10 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 9. [Figure 11] 1A is a diagram showing a "sloping region" present in a recess and the "recess amount" of the recess, and FIG. 1B is a graph showing the relationship between the recess amount and the withstand voltage. [Figure 12] FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to a first modified example. [Figure 13] 13 is a cross-sectional view of the semiconductor device taken along line AA in FIG. 12. [Figure 14] 13 is a cross-sectional view of the semiconductor device taken along line BB in FIG. 12. [Figure 15] FIG. 15 is an enlarged view showing a part of FIG. [Figure 16] 13 is an enlarged view showing a configuration between a field plate electrode and a lower end of a gate electrode in Modification 2. FIG. [Figure 17] 13 is an enlarged view showing a configuration between a field plate electrode and a lower end of a gate electrode in Modification 3. FIG. [Figure 18] 13 is an enlarged view showing a configuration between a field plate electrode and a lower end of a gate electrode in Modification 4. FIG. [Figure 19] FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to a fifth modified example. [Figure 20] 13(a) and 13(b) are enlarged views showing the configuration between the field plate electrode and the sidewall spacer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0010] <Usefulness of field plate electrodes> For example, an LDMOSFET has a source region and a drain region formed in a semiconductor substrate, and a gate electrode disposed on the semiconductor substrate via a gate insulating film. Here, a feature of an LDMOSFET is that the distance between the gate electrode and the drain region is greater than the distance between the gate electrode and the source region.

[0011] This makes it possible to increase the width of the depletion layer extending from the drain region when the LDMOSFET is turned off, thereby reducing the electric field in the depletion layer and improving the breakdown voltage of the LDMOSFET.

[0012] On the other hand, LDMOSFETs also require a reduction in on-resistance. For example, one possible way to reduce on-resistance is to increase the impurity concentration in the drift region. However, when the impurity concentration in the drift region increases, it becomes difficult for the depletion layer to extend from the drain region. This reduces the spacing between the equipotential lines in the depletion layer, and the electric field becomes stronger. Therefore, increasing the impurity concentration in the drift region to reduce on-resistance leads to a decrease in the breakdown voltage.

[0013] Therefore, in order to improve the breakdown voltage while reducing the on-resistance, the formation of a field plate electrode in the LDMOSFET has been considered. Specifically, the field plate electrode is formed on the upper surface of the semiconductor substrate so as to cover a part of the gate electrode, and a reference potential (0V) is supplied to the field plate electrode. This field plate electrode can widen the interval between the equipotential lines in the drift region generated by the potential difference between the source region and the drain region, and the electric field in the drift region is alleviated. For this reason, the formation of a field plate electrode in the LDMOSFET can improve the breakdown voltage. In this way, an LDMOSFET having a field plate electrode can ensure the breakdown voltage while reducing the on-resistance.

[0014] <New Findings Discovered by the Inventor> When increasing the impurity concentration in the drift region to reduce the on-resistance, simply forming a field plate electrode may not be sufficient in terms of improving the breakdown voltage. The present inventors have newly discovered that it is necessary to implement some measure to improve the breakdown voltage.

[0015] Specifically, even if a field plate electrode is formed in an LDMOSFET, depending on the distance between the field plate electrode and the lower end of the gate electrode, the breakdown voltage may not be ensured. This is because, when the impurity concentration is increased, the interval between the equipotential lines becomes smaller, and the equipotential lines are more likely to enter between the field plate electrode and the lower end of the gate electrode. The equipotential lines entering between the field plate electrode and the lower end of the gate electrode means that the interval between the equipotential lines between the field plate electrode and the lower end of the gate electrode becomes smaller, and the electric field strength becomes larger. As a result, for example, the electric field concentration occurring at the lower end of the gate electrode leads to a decrease in the breakdown voltage at the lower end of the gate electrode. Thus, the present inventor has found that, when the impurity concentration of the drift region is increased, the effect of improving the breakdown voltage by the field plate electrode (electric field relaxation effect) may not be sufficiently obtained.

[0016] Therefore, in this embodiment, in an LDMOSFET having a field plate electrode, attention is paid to the distance between the field plate electrode and the lower end of the gate electrode, and the breakdown voltage of the LDMOSFET having a field plate electrode is improved. The technical idea of ​​this embodiment will be described below.

[0017] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to reduce the distance between the field plate electrode and the lower end of the gate electrode. Even if the interval between the equipotential lines in the drift region is reduced by increasing the impurity concentration in the drift region, the equipotential lines are less likely to penetrate between the field plate electrode and the lower end of the gate electrode. The fact that the equipotential lines are less likely to penetrate means that the interval between the equipotential lines between the field plate electrode and the lower end of the gate electrode can be prevented from becoming smaller. As a result, according to the basic idea, it is possible to prevent the electric field strength between the field plate electrode and the lower end of the gate electrode from becoming large. Therefore, according to the basic idea, it is possible to prevent, for example, the electric field concentration at the lower end of the gate electrode from causing a decrease in the breakdown voltage. Therefore, according to the basic idea, it is possible to improve the performance of a semiconductor device including an LDMOSFET.

[0018] Here, in order to realize the above-mentioned basic idea, it is necessary to consider the influence on the characteristics of elements such as CMOSFETs that are mounted together with LDMOSFETs. That is, LDMOSFETs have a structure suitable for being mounted together with CMOSFETs. And the basic idea can be realized in a semiconductor device in which an LDMOSFET is mounted together with a CMOSFET, while minimizing the influence on the characteristics of the CMOSFET.

[0019] For example, it is conceivable to reduce the width of the sidewall spacer formed on the side of the gate electrode by adding a manufacturing process. This makes it possible to reduce the distance between the field plate electrode and the bottom end of the gate electrode. However, since the CMOSFET also has a sidewall spacer, the width of the CMOSFET's sidewall spacer is also reduced. The reduction in the width of the CMOSFET's sidewall spacer may cause the characteristics of the CMOSFET to fluctuate.

[0020] Therefore, in this embodiment, in order to realize the basic idea, the influence on the characteristics of the CMOSFET mounted together with the LDMOSFET is reduced as much as possible. In the following, an embodiment that realizes the above-mentioned basic idea while taking into consideration the reduction of the influence on the characteristics of the CMOSFET as much as possible will be described.

[0021] <Embodiment> First, the concept of the embodiment will be described.

[0022] For example, the concept of the embodiment is that when an insulating film in contact with the field plate electrode is present between the field plate electrode and the gate electrode, a recess is formed on the upper surface of the insulating film between the drain region and the gate electrode (between the field plate electrode and the gate electrode). Also, the recess is filled with a part of the field plate electrode. This makes it possible to reduce the distance between the field plate electrode and the lower end of the gate electrode.

[0023] The following describes in detail how the above-mentioned concept is embodied.

[0024] <<Semiconductor Device Structure>> FIG. 1 is a cross-sectional view showing the structure of a semiconductor device including an LDMOSFET 1.

[0025] The LDMOSFET1 has a semiconductor substrate SUB, an epitaxial layer EPI, a p-type well PWL, a gate insulating film GOX, a gate electrode GE, a sidewall spacer SW, a source region SR, a drain region DR, an offset drain region ODR, an insulating film 100, a field plate electrode FP, and a body contact region BC.

[0026] As shown in Fig. 1, an epitaxial layer EPI is formed on a semiconductor substrate SUB. The semiconductor substrate SUB is made of single crystal silicon into which an n-type impurity (donor) such as arsenic (As) is introduced. The epitaxial layer EPI is also made of single crystal silicon into which an n-type impurity is introduced. A stacked body made of the semiconductor substrate SUB and the epitaxial layer EPI may be called a substrate 1S.

[0027] The epitaxial layer EPI functions as a drift region. The epitaxial layer EPI has an impurity concentration lower than the impurity concentration of the semiconductor substrate SUB.

[0028] Next, a p-type well PWL, which is a p-type semiconductor region, is formed in the upper part of the epitaxial layer EPI. This p-type well PWL is also called a p-type body region. The p-type well PWL functions as a punch-through stopper that suppresses "punch-through" when the LDMOSFET1 is turned off. When the depletion layer reaches the source region SR from the drain region DR, "punch-through" occurs.

[0029] Next, a gate electrode GE is formed on the substrate 1S via a gate insulating film GOX. The gate insulating film GOX is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a polysilicon film and a metal silicide SL formed on the upper surface of the polysilicon film. A sidewall spacer SW made of, for example, a silicon oxide film is formed on the side surface of the gate electrode GE.

[0030] A source region SR and an offset drain region ODR are formed in the epitaxial layer EPI. The source region SR and the offset drain region ODR are separated from each other with a channel formation region formed in the upper surface of the p-type well PWL therebetween.

[0031] The channel formation region corresponds to the region directly under the gate electrode GE. When a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode GE, a channel made of an inversion layer is formed in the channel formation region.

[0032] A metal silicide SL is formed on an upper surface of the source region SR. In this specification, the metal silicide SL is also included in the source region SR. A drain region DR is formed in the epitaxial layer EPI so as to be in contact with the offset drain region ODR. A metal silicide SL is formed on an upper surface of the drain region DR. In this specification, the metal silicide SL is also included in the drain region DR. The depth of the drain region DR is shallower than the depth of the offset drain region ODR. In addition, the impurity concentration of the drain region DR is higher than the impurity concentration of the offset drain region ODR.

[0033] In the LDMOSFET 1, an offset drain region ODR is formed between the drain region DR and the gate electrode GE. Therefore, in the LDMOSFET 1, the distance between the gate electrode GE and the drain region DR is larger than the distance between the gate electrode GE and the source region SR. That is, in the LDMOSFET 1, the source region SR and the drain region DR are formed asymmetrically with respect to the gate electrode GE.

[0034] This allows the depletion layer to be sufficiently extended from the drain region DR to the offset drain region ODR when the LDMOSFET 1 is turned off, thereby improving the breakdown voltage between the source region SR and the drain region DR. In other words, the offset drain region ODR is formed in order to ensure a sufficient breakdown voltage.

[0035] 1, an insulating film 100 is formed so as to contact the substrate 1S, the sidewall spacer SW, and a part of the upper surface of the gate electrode GE. The insulating film 100 is made of, for example, a silicon oxide film. A field plate electrode FP is formed on the insulating film 100 so as to contact the insulating film 100. That is, the field plate electrode FP is continuously formed on a part of the gate electrode GE, on the sidewall spacer SW formed on the side surface of the gate electrode GE facing the drain region DR, and on the offset drain region ODR. The field plate electrode FP is made of, for example, a metal silicide film.

[0036] An interlayer insulating film IL is formed so as to cover the LDMOSFET 1. The interlayer insulating film IL is made of, for example, a silicon oxide film. As shown in Fig. 1, the interlayer insulating film IL has, for example, a plug PLG1 reaching the drain region DR and a plug PLG2 reaching the source region SR formed therein.

[0037] Here, in the substrate 1S, a body contact region BC made of a p-type semiconductor region is formed so as to be in contact with the source region SR. The plug PLG2 is electrically connected not only to the source region SR but also to the body contact region BC. Therefore, in the LDMOSFET1, the source region SR and the body contact region BC have the same potential. Since the body contact region BC is connected to the p-type well PWL, the p-type well PWL and the source region SR are connected at the same potential. As a result, according to the LDMOSFET1, a potential difference between the p-type well PWL and the source region SR is unlikely to occur. This makes it possible to suppress the parasitic npn bipolar transistor made of the source region SR, the p-type well region PWL, and the semiconductor substrate SUB (epitaxial layer EPI) from being turned on. In other words, according to the LDMOSFET1, it is possible to suppress "latch-up" caused by the parasitic bipolar transistor.

[0038] The LDMOSFET 1 is configured as described above.

[0039] Next, a detailed configuration between the field plate electrode FP and the lower end of the gate electrode GE will be described. Fig. 2 is an enlarged view showing the configuration between the field plate electrode FP and the lower end of the gate electrode GE. In particular, the insulating film 100 located below the field plate electrode FP will be described below.

[0040] 2, the insulating film 100 has a first portion P1 in contact with the substrate 1S, a second portion P2 in contact with the sidewall spacer SW, and a third portion P3 in contact with a part of the upper surface of the gate electrode GE. A recess 200 is formed at a connection point between the upper surface of the first portion P1 and the upper surface of the second portion P2. This recess 200 is filled with a part of the field plate electrode FP. In the LDMOSFET 1 thus configured, as shown in FIG. 2, the "distance B" (first distance) between the upper surface of the substrate 1S and the recess 200 is larger than the "thickness A" of the gate insulating film GOX. In this case, the "distance B" is the shortest distance between the upper surface of the substrate 1S and the lower end of the recess 200 in a direction perpendicular to the upper surface of the substrate 1S.

[0041] Here, unevenness corresponding to the surface roughness exists on the upper surface of the insulating film 100. In this regard, a depression 200 formed at a connection point between the upper surface of the first portion P1 and the upper surface of the second portion P2 of the insulating film 100 is larger than the above-mentioned unevenness, and the depression 200 is distinguished from the above-mentioned unevenness.

[0042] The difference between the depressions 200 and the irregularities corresponding to the surface roughness will be described below with reference to FIG.

[0043] FIG. 3 is a diagram showing the difference between the recess 200 and the surface roughness of the insulating film 100. In FIG. 3, the recess 200 is formed at the connection point between the first portion P1 and the second portion P2 of the insulating film 100. As shown in FIG. 3, the upper surface of the first portion P1 of the insulating film 100 is formed with unevenness corresponding to the surface roughness. The distance "S" (first difference) between the highest position of the unevenness and the lowest position of the recess 200 is larger than the difference "H1" (second difference) between the highest position of the unevenness and the lowest position of the unevenness. Specifically, the distance "S" is larger than 2 nm. Thus, in the embodiment, the recess 200 is clearly distinguished from the unevenness corresponding to the surface roughness.

[0044] <<Method of manufacturing semiconductor device>> Next, a method for manufacturing a semiconductor device will be described with reference to the drawings.

[0045] First, as shown in Fig. 4, a gate electrode GE is formed via a gate insulating film GOX on the upper surface of a substrate 1S in which a p-type well PWL, an offset drain region ODR, and a drain region DR are formed. Then, a sidewall spacer SW is formed on the side surface of the gate electrode GE. Next, as shown in Fig. 5, an insulating film 100 is formed so as to cover the upper surfaces of the substrate 1S (the offset drain region ODR and the drain region DR), the sidewall spacer SW, and the gate electrode GE.

[0046] The insulating film 100 is formed, for example, by using atmospheric pressure CVD (Chemical Vapor Deposition) or plasma CVD. The film formation conditions when forming the insulating film 100 by using atmospheric pressure CVD are as follows. For example, the film formation temperature is 380 degrees. The raw material gases are silane gas (SiH4) and oxygen gas (O2). The film formation pressure is 760 Torr (1 Torr = 133.32 Pa).

[0047] On the other hand, the deposition conditions when the insulating film 100 is formed by using the plasma CVD method are as follows. For example, the deposition temperature is 400 degrees. The raw material gas is TEOS and oxygen gas. The deposition pressure is 3 Pa.

[0048] 5, the insulating film 100 in the embodiment includes a first portion P1 in contact with the substrate 1S, a second portion P2 in contact with the sidewall spacer SW, and a third portion P3 in contact with the upper surface of the gate electrode GE. By using the atmospheric pressure CVD method or the plasma CVD method, the thickness uniformity of the insulating film 100 is reduced, and a recess 200 is formed at the connection point between the upper surface of the first portion P1 and the upper surface of the second portion P2. That is, in the embodiment, the recess 200 is formed intentionally.

[0049] Next, as shown in FIG. 6, the insulating film 100 is patterned by using photolithography and etching techniques. As a result, the insulating film 100 covers a part of the upper surface of the gate electrode GE and exposes the other part of the upper surface of the gate electrode GE. By patterning the insulating film 100, the insulating film 100 is composed of a first portion P1, a second portion P2, and a third portion P3 that contacts a part of the upper surface of the gate electrode GE. Then, as shown in FIG. 7, a metal silicide SL is formed by using silicide techniques on the upper surface of the substrate 1S exposed from the insulating film 100 and the other part of the upper surface of the gate electrode GE.

[0050] Next, as shown in Fig. 8, for example, a sputtering method is used to form a tungsten silicide film SF so as to cover the insulating film 100 and the gate electrode GE. Then, as shown in Fig. 9, the tungsten silicide film SF is patterned by using photolithography and etching techniques to form a field plate electrode FP. At this time, a part of the field plate electrode FP is filled inside the recess 200. In this manner, the LDMOSFET 1 can be formed.

[0051] Thereafter, as shown in FIG. 10, for example, an interlayer insulating film IL is formed so as to cover the LDMOSFET 1 formed on the substrate 1S. The interlayer insulating film IL is made of, for example, a silicon oxide film. Next, although not shown, a plug penetrating the interlayer insulating film IL and a wiring connected to the plug are formed. This allows the manufacture of a semiconductor device including the LDMOSFET 1 in the embodied embodiment.

[0052] <<Features of the Realization>> Next, features of the embodiment will be described.

[0053] A first feature of the embodiment is that a recess 200 is formed at a connection point between an upper surface of a first portion P1 and an upper surface of a second portion P2 of the insulating film 100 located under the field plate electrode FP, as shown in Fig. 2. As a result, a part of the field plate electrode FP is filled into the recess 200, so that the distance "L" between the field plate electrode FP and the lower end of the gate electrode GE can be made smaller than in a configuration without the recess 200.

[0054] According to the first feature, even if the interval between the equipotential lines in the drift region is reduced by increasing the impurity concentration in the drift region (inside the substrate 1S), the presence of the recess 200 reduces the distance "L" shown in FIG. 2. Therefore, the equipotential lines are less likely to enter between the field plate electrode FP and the lower end of the gate electrode GE. Therefore, the interval between the equipotential lines between the field plate electrode FP and the lower end of the gate electrode GE can be prevented from being reduced. As a result, according to the first feature, even if the impurity concentration in the drift region is increased to reduce the on-resistance of the LDMOSFET1, the electric field intensity between the field plate electrode FP and the lower end of the gate electrode GE can be prevented from being increased. Therefore, according to the first feature, the on-resistance can be reduced while preventing the electric field concentration at the lower end of the gate electrode GE from causing a decrease in the breakdown voltage. That is, according to the first feature, both the reduction in the on-resistance and the improvement in the breakdown voltage, which are in a trade-off relationship, can be improved. Therefore, according to the first feature, the performance of a semiconductor device including the LDMOSFET1 can be improved.

[0055] As described above, by forming the recess 200 in the insulating film 100, the breakdown voltage of the LDMOSFET 1 can be improved. In this regard, the formation of the recess 200 can improve the breakdown voltage, so the shape of the recess 200 is not limited to the shape shown in FIG. 2. This is because the technical significance of forming the recess 200 is to reduce the distance "L" between the field plate electrode FP and the lower end of the gate electrode GE. In other words, if the distance "L" is reduced by the presence of the recess 200, it becomes difficult for an equipotential line to appear between the field plate electrode FP and the lower end of the gate electrode GE.

[0056] On the other hand, the present inventors have clarified that when the size of the recess 200 is changed, a certain difference occurs in the effect of improving the withstand voltage, and this point will be described below.

[0057] 11(a) and 11(b) are diagrams illustrating the size dependency of a dent on the breakdown voltage. Fig. 11(a) is a diagram showing the "inclined region" present in the dent 200 and the "dent amount" of the dent, and Fig. 11(b) is a graph showing the relationship between the dent amount and the breakdown voltage.

[0058] As shown in Fig. 11(a), the "inclined area" and "recess amount" of the recess 200 are defined. The "inclined area" corresponds to the horizontal length of the upper surface of the first portion P1 that is inclined with respect to the upper surface of the substrate 1S. The "recess amount" corresponds to the distance between the highest point of the upper surface of the first portion P1 and the lower end of the recess in the direction perpendicular to the upper surface of the substrate 1S.

[0059] 11B, graph (1) shows the relationship between the depression amount corresponding to the depression 200 having a "gradient region=0.03 μm" and the breakdown voltage. In contrast, graph (2) shows the relationship between the depression amount corresponding to the depression 200 having a "gradient region=0.09 μm" and the breakdown voltage.

[0060] As shown in FIG. 11(b), the same tendency is observed in both graphs (1) and (2). That is, as the "depth of recess" increases, the breakdown voltage improves (first tendency), but as the "depth of recess" exceeds "0.05 μm", the breakdown voltage decreases (second tendency). Here, an increase in the "depth of recess" means that the size of recess 200 increases. Thus, the first tendency indicates that as the size of recess 200 increases, the distance "L" decreases, and the intrusion of equipotential lines is sufficiently suppressed.

[0061] An increase in the "recess amount" means that the distance between the recess 200 and the upper surface of the substrate 1S, in other words, the thickness of the insulating film 100 directly below the recess 200, decreases. When the "recess amount" increases, the thickness of the insulating film 100 directly below the recess 200 becomes smaller than the thickness of the gate insulating film GOX. In this case, it is considered that the thin part of the insulating film 100 directly below the recess 200 acts as a hot spot for a decrease in breakdown voltage. In other words, the second tendency indicates that when the size of the recess 200 increases and the thickness of the insulating film 100 directly below the recess 200 becomes smaller than the thickness of the gate insulating film GOX, the region directly below the recess 200 becomes apparent as a hot spot for a decrease in breakdown voltage.

[0062] From the above, in order to form the recess 200 and improve the breakdown voltage, it is desirable to increase the size of the recess 200 (the "recess amount") so that the thickness of the insulating film 100 directly below the recess 200 is not smaller than the thickness of the gate insulating film GOX.

[0063] A second feature of the embodiment is that the insulating film 100 is formed by using an atmospheric pressure CVD method or a plasma CVD method, for example, as shown in Fig. 5. This makes it possible to form a recess 200 at the connection portion between the upper surface of the first portion P1 and the upper surface of the second portion P2 of the insulating film 100, as shown in Fig. 5, simply by changing the method of forming the insulating film 100 from the low pressure CVD method to the atmospheric pressure CVD method or the plasma CVD method.

[0064] By the atmospheric pressure CVD method or the plasma CVD method, a film having a lower thickness uniformity than a film formed by the low pressure CVD method is formed. As a result, a recess 200 as shown in FIG. 5 can be formed at the connection portion between the upper surface of the first portion P1 and the upper surface of the second portion P2 of the insulating film 100.

[0065] For example, it is generally desirable for the insulating film 100 to be a conformal film with high thickness uniformity, and therefore the insulating film 100 is formed by a low-pressure CVD method.

[0066] In this regard, the present inventor has noted that if an insulating film 100 with low thickness uniformity is formed, rather than forming a conformal insulating film 100 with high thickness uniformity, then recesses 200 will inevitably be formed. In particular, the present inventor has noted that a film formed by atmospheric pressure CVD or plasma CVD has lower thickness uniformity than a film formed by low pressure CVD, and has proactively used atmospheric pressure CVD or plasma CVD, which are not normally used as a method for forming the insulating film 100.

[0067] For example, when using the atmospheric pressure CVD method, it is desirable to lower the film formation temperature (approximately 380° C. to 420° C.) in order to facilitate the formation of the recesses 200 in the insulating film 100. On the other hand, when using the plasma CVD method, it is desirable to (1) lower the film formation temperature (approximately 380° C. to 420° C.), (2) increase the pressure (approximately 3 Pa to 4 Pa), or (3) change the balance between high and low frequencies (high frequency: approximately 13 MHz to 14 MHz, low frequency: approximately 250 kHz to 400 kHz).

[0068] According to the second feature of the above-described embodiment, the recess 200 can be formed in the insulating film 100 while reducing the effect on the characteristics of elements such as a CMOSFET that are mounted together with the LDMOSFET1. This is because the field plate electrode FP and the insulating film 100, which is an underlying film, are components unique to the LDMOSFET1. In other words, since the insulating film 100 is not left in the CMOSFET, a change in the method of forming the insulating film 100 does not affect the structure of the CMOSFET. Therefore, the second feature of the embodiment can improve the breakdown voltage of the LDMOSFET1 without affecting the characteristics of the CMOSFET.

[0069] Furthermore, in the embodiment, the material of the field plate electrode FP is selected so as not to affect the characteristics of the CMOSFET. For example, titanium nitride (TiN) may be used as the material of the field plate electrode FP. This titanium nitride melts in the cleaning process "APM process / SPM process", which may cause a defective formation of the field plate electrode FP. Therefore, if the field plate electrode FP is made of titanium nitride, it is necessary to change the cleaning conditions of the cleaning process used in the process of forming the contact holes that reach the field plate electrode FP. In this regard, not only the contact holes that reach the field plate electrode FP but also the contact holes that reach the CMOSFET (the source region, the drain region, and the gate electrode) are formed. Therefore, a change in the cleaning conditions means that the cleaning conditions of the cleaning process of the contact holes that reach the CMOSFET are also changed. Therefore, a change in the cleaning conditions of the cleaning process of the contact holes may affect the characteristics of the CMOSFET. That is, if the field plate electrode FP is made of titanium nitride, a change in the cleaning conditions of the cleaning process of the contact holes may affect the characteristics of the CMOSFET.

[0070] Therefore, in the embodiment, the field plate electrode FP is made of metal silicide (for example, tungsten silicide), because metal silicide does not melt in the "APM process / SPM process", and therefore there is no need to change the cleaning conditions.

[0071] Moreover, in order to suppress the influence on the characteristics of the CMOSFET, the field plate electrode FP does not have to be made of a polysilicon film, because the deposition temperature of the polysilicon film is higher than the formation temperature of the metal silicide, and there is a concern that the characteristics of the CMOSFET may fluctuate due to heat.

[0072] For the above reasons, in the embodiment, by forming the field plate electrode FP from a metal silicide film rather than a titanium nitride film or a polysilicon film, it is possible to realize the field plate electrode FP without adversely affecting the characteristics of the CMOSFET that is integrated with the LDMOSFET 1.

[0073] <Variation 1> Next, the semiconductor device according to the first modification will be described.

[0074] <<Semiconductor Device Structure>> FIG. 12 is a plan view showing a schematic configuration of a semiconductor device according to the first modification.

[0075] In FIG. 12, a plurality of plugs PLG1 (eight plugs PLG1 in FIG. 12) are arranged so as to be spaced apart in the Y direction. Also, a plurality of plugs PLG1 (two plugs PLG1 in FIG. 12) are arranged so as to be spaced apart in the X direction. That is, in FIG. 12, a "plug row" consisting of eight plugs PLG1 arranged in the Y direction is arranged in two rows in the X direction. Between the two "plug rows" thus arranged, a "plug row" consisting of eight plugs PLG2 arranged in the Y direction is arranged. Here, the plug PLG1 is electrically connected to the drain region. On the other hand, the plug PLG2 is electrically connected to the source region.

[0076] 12, between the left "plug row" and the central "plug row", and between the central "plug row" and the right "plug row", a gate electrode GE extends in the Y direction. The width of the gate electrode GE in the Y direction is the gate width. On the other hand, the width of the gate electrode GE in the X direction is the gate length. A field plate electrode FP that partially overlaps with the gate electrode GE in a plan view extends in the Y direction. That is, as shown in FIG. 12, the field plate electrode FP in this modification 1 has a left extension portion and a right extension portion, and the left extension portion extends in the Y direction while partially overlapping with the gate electrode GE on the left side, and the right extension portion extends in the Y direction while partially overlapping with the gate electrode GE on the right side. The left extension portion and the right extension portion are connected to each other by a plurality of connection portions extending in the X direction. In this way, the field plate electrode FP in this modification 1 is composed of a left extension portion, a right extension portion, and a plurality of connection portions. In FIG. 12, the portion where the gate electrode GE overlaps with the field plate electrode FP is indicated by a dotted line.

[0077] FIG. 13 is a cross-sectional view of the semiconductor device taken along line AA in FIG.

[0078] In FIG. 13, the LDMOSFET 1A has an insulating film 100 formed in contact with a part of the upper surface of the gate electrode GE, the sidewall spacer SW, and the substrate 1S.

[0079] 13, the insulating film 100 is composed of an insulating film 10, an insulating film 20, and an insulating film 30. The insulating film 10 is formed so as to contact a part of the upper surface of the gate electrode GE, the sidewall spacer SW, and the substrate 1S. The insulating film 20 is formed so as to contact the other part (remaining part) of the upper surface of the gate electrode GE and the insulating film 10, and to cover the gate electrode GE. The insulating film 30 is formed so as to contact the insulating film 20 and to cover the gate electrode GE. The field plate electrode FP in this modification 1 is formed so as to contact the insulating film 30.

[0080] The insulating film 10 is formed of, for example, a silicon oxide film. The insulating film 20 is formed of, for example, a silicon nitride film. The insulating film 30 is formed of, for example, a silicon oxide film. The thickness uniformity of the insulating film 20 is higher than the thickness uniformity of each of the insulating film 10 and the insulating film 30.

[0081] 14 is a cross-sectional view of the semiconductor device taken along line BB in FIG.

[0082] In Fig. 14, the field plate electrode FP is in contact with the insulating film 30. Furthermore, the field plate electrode FP covers the gate electrode GE and extends so as to be electrically connected to the plug PLG2. Here, the plug PLG2 shown in Fig. 13 is electrically connected to the source region SR. Moreover, the plug PLG2 shown in Fig. 14 is electrically connected to the field plate electrode FP. Although not shown, the plug PLG2 shown in Fig. 13 and the plug PLG2 shown in Fig. 14 are electrically connected by, for example, a wiring formed on the interlayer insulating film IL. That is, the same potential is applied to the field plate electrode FP and the source region SR.

[0083] FIG. 15 is an enlarged view showing a part of FIG.

[0084] 15, a recess 200 is formed in the insulating film 100. In detail, the recess 200 is formed in each of the insulating films 10, 20, and 30 constituting the insulating film 100. In this manner, the LDMOSFET 1A included in the semiconductor device in the present modified example 1 is configured.

[0085] <<Features of Modification 1>> A feature of the present first modification is that, for example, as shown in Fig. 15, a recess 200 is formed in a region RA of the insulating film 100 located under the field plate electrode FP. In detail, in the region RA, the recess 200 is formed in each of the insulating films 10, 20, and 30. As a result, a part of the field plate electrode FP is filled in the recess 200 formed in the insulating film 30, so that the distance between the field plate electrode FP and the lower end of the gate electrode GE can be made smaller than in a configuration without the recess 200.

[0086] As a result, according to the feature of the present modification 1, it is possible to suppress the electric field concentration at the lower end of the gate electrode GE from causing a decrease in the breakdown voltage while reducing the on-resistance, and therefore, according to the present modification 1, it is possible to improve the performance of the semiconductor device including the LDMOSFET 1A.

[0087] The advantages of the first modified example will be described below.

[0088] In the present first modification, for example, as shown in FIGS. 13 and 14, an insulating film 100 is composed of an insulating film 10, an insulating film 20, and an insulating film 30, and each of the insulating film 20 and the insulating film 30 is formed so as to cover the gate electrode GE.

[0089] As a result, according to the present modification 1, it is possible to suppress a short circuit defect between the field plate electrode FP arranged on the insulating film 30 and the gate electrode GE. In particular, according to the present modification 1, since the gate electrode GE is covered with the insulating films 20 and 30, it is possible to suppress a short circuit defect between the field plate electrode FP and the gate electrode GE even if a "patterning deviation" occurs in the patterning for forming the field plate electrode FP. Therefore, according to the present modification 1, it is possible to improve the reliability of a semiconductor device including the LDMOSFET 1A.

[0090] Furthermore, in the present modification 1, the gate electrode GE is covered with the insulating film 20 and the insulating film 30. Therefore, according to the present modification 1, a part of the field plate electrode FP can be disposed above the gate electrode GE without the risk of short-circuiting. Therefore, according to the present modification 1, the degree of freedom in the layout of the field plate electrode FP can be improved.

[0091] For example, as shown in FIG. 14, a field plate electrode FP can be disposed so as to cover the gate electrode GE. In this case, the same potential "0V" as that of the source region SR is applied to the field plate electrode FP. Therefore, the field plate electrode FP covering the gate electrode GE functions as a shield between the gate electrode GE and the drain region DR. Thus, according to the present modification 1, the field plate electrode FP functions as a shield, and as a result, the "gate-drain capacitance" in the LDMOSFET 1A can be reduced. That is, according to the present modification 1, the parasitic capacitance present in the LDMOSFET 1A can be reduced, and the performance of the semiconductor device including the LDMOSFET 1A can be improved.

[0092] Furthermore, in the present modification 1, a configuration that is unlikely to affect the characteristics of the CMOSFET mounted together with the LDMOSFET 1A will be described.

[0093] For example, as shown in Fig. 15, the insulating film 100 is composed of an insulating film 10, an insulating film 20, and an insulating film 30. Here, in this modification 1, a recess 200 is formed in the insulating film 100 in a region RA shown in Fig. 15. In this case, from the viewpoint of forming the recess 200, it is considered that each of the insulating films 10, 20, and 30 is formed using a film formation method that makes it easy to form the recess 200 in the region RA. For example, it is considered that the insulating films 10, 20, and 30, each having low thickness uniformity, are formed using an atmospheric pressure CVD method or a plasma CVD method, instead of a low pressure CVD method.

[0094] For example, the insulating film 20 is formed of a silicon nitride film. This insulating film 20 functions as a stressor in the so-called "strained silicon technology" that applies stress (distortion) to the LDMOSFET 1A to improve the carrier mobility in the channel. Since it is desirable for the stressor to be able to apply stress uniformly, it is desirable for the stressor to be a film with high thickness uniformity. In this regard, a film with lower thickness uniformity than a film formed by a low-pressure CVD method is formed by the atmospheric pressure CVD method or the plasma CVD method.

[0095] Therefore, it is preferable that the insulating film 20 functioning as a stressor is formed using a low-pressure CVD method, not a normal pressure CVD method or a plasma CVD method. That is, in this modification 1, from the viewpoint of forming the recess 200 and ensuring the function as a stressor, it is preferable that the insulating film 10 and the insulating film 30 are formed using a normal pressure CVD method or a plasma CVD method, while the insulating film 20 is formed using a low-pressure CVD method.

[0096] In this regard, the above-mentioned technique is unlikely to affect the characteristics of the CMOSFET mounted together with the LDMOSFET1A. That is, the insulating film 20 is formed so as to function as a stressor of the "strained silicon technology" not only in the LDMOSFET1A but also in the CMOSFET. If the thickness uniformity of the insulating film 20 is low, the insulating film 20 may not function sufficiently as a good stressor in the CMOSFET. For this reason, if the insulating film 20 with low thickness uniformity is formed using the atmospheric pressure CVD method or the plasma CVD method to form the recess 200, the characteristics of the CMOSFET, such as the carrier mobility in the channel, may be adversely affected. In contrast, according to the above-mentioned technique, the insulating film 20 is formed using the low pressure CVD method. For this reason, according to the present modification 1, the thickness uniformity of the insulating film 20 can be improved. As a result, the recess 200 can be formed in the insulating film 100 of the LDMOSFET1A while being unlikely to affect the characteristics of the CMOSFET mounted together with the LDMOSFET1A. Therefore, according to the present modification 1, the performance of the LDMOSFET1A can be improved without adversely affecting the characteristics of the CMOSFET mounted together with the LDMOSFET1A.

[0097] <Variation 2> Next, the LDMOSFET 1B in the second modification will be described.

[0098] 16 is an enlarged view showing a configuration between a field plate electrode FP and a lower end of a gate electrode GE in an LDMOSFET 1B. In FIG. 16, the present modification 2 is characterized in that a recess portion RC is formed in a lower portion of a sidewall spacer SW.

[0099] 16 can be reduced. That is, according to Modification 2, by forming the recess portion RC in the lower portion of the sidewall spacer SW, the distance between the field plate electrode FP and the lower end portion of the gate electrode GE can be reduced compared to a configuration without the recess portion RC.

[0100] As a result, according to the present modification 2, even if the impurity concentration of the substrate 1S is increased, equipotential lines are unlikely to appear between the field plate electrode FP and the lower end of the gate electrode GE. Therefore, according to the LDMOSFET 1B in the present modification 2, it is possible to suppress a decrease in the breakdown voltage caused by electric field concentration at the lower end of the gate electrode GE while reducing the on-resistance. Therefore, according to the present modification 2, it is possible to improve the performance of a semiconductor device including the LDMOSFET 1B.

[0101] For example, the recessed portion RC can be formed by subjecting the sidewall spacers SW to isotropic etching in addition to the anisotropic etching for forming the sidewall spacers SW.

[0102] In this second modification, a recess RC is formed in the sidewall spacer SW. As a result, even if a conformal insulating film 100 with high thickness uniformity is formed, the presence of the recess RC makes it possible to reduce the "distance L" between the field plate electrode FP and the lower end of the gate electrode GE. In other words, in this second modification, the insulating film 100 can be formed by a low-pressure CVD method that can form a film with high thickness uniformity.

[0103] However, in addition to forming the recessed portion RC in the sidewall spacer SW, a depression may also be formed in the insulating film 100. In this case, the recessed portion RC and the depression can further reduce the "distance L." That is, in this second modification as well, a depression may be formed in the insulating film 100 by using an atmospheric pressure CVD method or a plasma CVD method instead of a low pressure CVD method as a method for forming the insulating film 100.

[0104] <Modification 3> Next, the LDMOSFET 1C according to the third modification will be described.

[0105] 17 is an enlarged view showing a configuration between a field plate electrode FP and a lower end of a gate electrode GE in an LDMOSFET 1C. In FIG. 17, the present modification 3 is characterized in that a recess portion RC2 is formed in the upper surface of a substrate 1S.

[0106] As a result, the upper surface of the substrate 1S in contact with the insulating film 100 is lower than the upper surface of the substrate 1S in contact with the sidewall spacer SW. As a result, according to Modification 3, the "distance L" shown in Fig. 17 can be reduced. That is, according to Modification 3, by forming the recess portion RC2 in the upper surface of the substrate 1S, the "distance L" can be reduced compared to a configuration without the recess portion RC2.

[0107] As a result, according to the present modification 3, even if the impurity concentration of the substrate 1S is increased, equipotential lines are unlikely to appear between the field plate electrode FP and the lower end of the gate electrode GE. Therefore, according to the LDMOSFET 1C in the present modification 3, it is possible to suppress a decrease in the breakdown voltage caused by electric field concentration at the lower end of the gate electrode GE while reducing the on-resistance. Therefore, according to the present modification 3, it is possible to improve the performance of a semiconductor device including the LDMOSFET 1C.

[0108] For example, the recessed portion RC2 can be formed by etching the substrate 1S using the sidewall spacer SW as a mask.

[0109] In the present modified example 3, a recessed portion RC2 is formed in the substrate 1S. As a result, even if a conformal insulating film 100 with high thickness uniformity is formed, the presence of the recessed portion RC2 makes it possible to reduce the "distance L" between the field plate electrode FP and the lower end of the gate electrode GE. In other words, in the present modified example 3, the insulating film 100 can be formed by a low-pressure CVD method that can form a film with high thickness uniformity.

[0110] In addition to forming the recessed portion RC2 in the substrate 1S, a depression may also be formed in the insulating film 100. In this case, the recessed portion RC2 and the depression can further reduce the "distance L." That is, in this third modification, the depression may also be formed in the insulating film 100 by using the normal pressure CVD method or the plasma CVD method instead of the low pressure CVD method as the method for forming the insulating film 100.

[0111] <Modification 4> Next, the LDMOSFET 1D according to the fourth modification will be described.

[0112] Fig. 18 is an enlarged view showing the configuration between the field plate electrode FP and the lower end of the gate electrode GE in the LDMOSFET 1D. In Fig. 18, in the present modification 4, a recess 200 is formed in the insulating film 100 by patterning using photolithography and etching techniques. In this manner, the recess 300 may be formed by patterning. In this case as well, by forming the recess 200 in the insulating film 100, the "distance L" between the field plate electrode FP and the lower end of the gate electrode GE can be reduced.

[0113] <Variation 5> Fig. 19 is a plan view showing a schematic configuration of a semiconductor device including an LDMOSFET 1E in Modification 5. As shown in Fig. 19, a gate electrode GE of the LDMOSFET 1E extends in the Y direction over an active region ACT in plan view.

[0114] The field plate electrode FP extends in the Y direction while partially overlapping the gate electrode GE in a plan view. That is, although not shown in Fig. 19, a part of the field plate electrode FP extends in the Y direction so as to overlap the active region ACT between the drain region DR and the sidewall spacer SW in a plan view.

[0115] Here, the feature of this fifth modification is that, for example, a portion of the field plate electrode FP is electrically connected to a plurality of plugs PLG3 as shown in Fig. 19. That is, wiring (not shown) is formed so as to overlap the field plate electrode FP in a plan view, and the field plate electrode FP and the above-mentioned wiring are connected via the plurality of plugs PLG3 shown in Fig. 19.

[0116] As a result, according to the fifth modification, the electrical connection between the field plate electrode FP and the plug PLG3 can be strengthened. In particular, when a recess is formed in the insulating film located under the field plate electrode FP, it is considered that the thickness uniformity of the field plate electrode FP is reduced. In this case, as a result of a portion having a small thickness being formed in the field plate electrode FP, the resistance value of the field plate electrode FP may be increased due to this portion having a small thickness. Therefore, in the fifth modification, a plurality of plugs PLG3 are connected to the field plate electrode FP. This makes it possible to reduce the resistance value of the field plate electrode FP. That is, according to the fifth modification, the increase in the resistance component caused by the reduction in the thickness uniformity of the field plate electrode FP is reduced by connecting the field plate electrode FP and a plurality of plugs PLG3. As a result, according to the fifth modification, the performance of the semiconductor device including the LDMOSFET1E can be improved.

[0117] <Variation 6> Next, the LDMOSFET 1F in the sixth modification will be described.

[0118] 20(a) and 20(b) are enlarged views showing the configuration between the field plate electrode FP and the sidewall spacer SW. Fig. 20(a) shows an example in which the plug PLG3 connected to the field plate electrode FP is disposed close to the recess 200. In other words, the plug PLG3 is disposed so as to overlap the recess 200.

[0119] As shown in FIG. 20(a), if the plug PLG3 is disposed close to the recess 200, the shape of the recess 200 may cause a connection failure between the field plate electrode FP and the plug PLG3.

[0120] 20(b) shows an LDMOSFET 1F according to Modification 6. Specifically, in FIG. 20(b), the plug PLG3 connected to the field plate electrode FP is disposed away from the recess 200. In other words, the plug PLG3 is disposed so as not to overlap with the recess 200.

[0121] 20(b), by arranging the plug PLG3 away from the recess 200, it is possible to connect the field plate electrode FP and the plug PLG3 without being affected by the shape of the recess 200. As a result, according to the present modification 6, it is possible to improve the reliability of the semiconductor device including the LDMOSFET 1F.

[0122] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0123] In this specification, the epitaxial layer EPI into which n-type impurities are introduced is described, but the epitaxial layer EPI into which p-type impurities are introduced may also be applied. When the epitaxial layer EPI into which p-type impurities are introduced is applied, the epitaxial layer EPI may have, for example, a buried semiconductor layer and a drift layer. The buried semiconductor layer is formed to electrically isolate the LDMOSFET from the semiconductor substrate. The drift layer has a lower impurity concentration than the drain region DR, and is formed from the drain region DR toward the gate electrode GE like the offset drain region ODR. [Explanation of symbols]

[0124] 1 LDMOSFET 1A LDMOSFET 1B LDMOSFET 1C LDMOSFET 1D LDMOSFET 1E LDMOSFET 1F LDMOSFET 1S board 10. Insulating film 20 Insulating film 30 Insulating film 100 Insulating film 200 Depression ACT active region BC Body contact area DR Drain region EPI Epitaxial Layer FP field plate electrode GE gate electrode GOX gate insulating film IL Interlayer insulating film ODR Offset Drain Region PLG1 Plug PLG2 plug PLG3 Plug PWL p-type well P1 Part 1 P2 2nd part P3 3rd part RA area RC recess RC2 Recessed part SF Tungsten silicide film SL Metal silicide SR Source Region SUB Semiconductor Substrate SW Sidewall spacer

Claims

1. A semiconductor substrate; a source region formed in the semiconductor substrate; a drain region spaced from the source region and formed within the semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a sidewall spacer formed on a side surface of the gate electrode; an insulating film formed so as to be in contact with a part of an upper surface of the gate electrode, the sidewall spacer, and the semiconductor substrate; a field plate electrode formed on the insulating film; Equipped with a recess is formed on an upper surface of the insulating film between the drain region and the gate electrode, The recess is filled with a portion of the field plate electrode.

2. 2. The semiconductor device according to claim 1, The insulating film is a first portion in contact with the semiconductor substrate; a second portion in contact with the sidewall spacer; a third portion in contact with a portion of the top surface of the gate electrode; having The semiconductor device, wherein the recess is formed at a connection point between the top surface of the first portion and the top surface of the second portion.

3. 2. The semiconductor device according to claim 1, A semiconductor device, wherein a first distance between the upper surface of the semiconductor substrate and the recess is greater than a thickness of the gate insulating film.

4. 3. The semiconductor device according to claim 2, The upper surface of the first portion is formed with projections and recesses corresponding to the surface roughness, A semiconductor device, wherein a first difference between a highest point of the asperity and a lower end of the depression is greater than a second difference between the highest point of the asperity and a lowest point of the asperity.

5. 5. The semiconductor device according to claim 4, The semiconductor device, wherein the first difference is greater than 2 nm.

6. 2. The semiconductor device according to claim 1, A semiconductor device, wherein a distance between the gate electrode and the drain region is greater than a distance between the gate electrode and the source region.

7. 2. The semiconductor device according to claim 1, The field plate electrode is formed of a metal silicide film.

8. 2. The semiconductor device according to claim 1, The insulating film is a first insulating film formed to contact a portion of the upper surface of the gate electrode, the sidewall spacer, and the semiconductor substrate; a second insulating film formed in contact with the other portion of the upper surface of the gate electrode and the first insulating film and covering the gate electrode; a third insulating film formed so as to be in contact with the second insulating film; The semiconductor device has

9. 9. The semiconductor device according to claim 8, A semiconductor device, wherein the second insulating film has a thickness uniformity higher than the thickness uniformity of each of the first insulating film and the third insulating film.

10. 9. The semiconductor device according to claim 8, the field plate electrode extends to cover the gate electrode and to be electrically connected to the source region.

11. 2. The semiconductor device according to claim 1, A recess is formed in a lower portion of the sidewall spacer.

12. 2. The semiconductor device according to claim 1, a top surface of the semiconductor substrate in contact with the insulating film is lower than a top surface of the semiconductor substrate in contact with the sidewall spacer.

13. 2. The semiconductor device according to claim 1, a portion of the field plate electrode extends in a gate width direction of the gate electrode so as to overlap with an active region between the drain region and the sidewall spacer in a plan view; a portion of the field plate electrode electrically connected to a plurality of plugs.

14. 2. The semiconductor device according to claim 1, the semiconductor device has a plug connected to the field plate electrode, The plug is disposed away from the recess.

15. (a) forming a gate electrode on a semiconductor substrate via a gate insulating film; (b) forming sidewall spacers on side surfaces of the gate electrode; (c) forming an insulating film in contact with a portion of the upper surface of the gate electrode, the sidewall spacer, and the semiconductor substrate; (d) forming a field plate electrode on the insulating film; Equipped with In the step (c), the insulating film is formed by using atmospheric pressure CVD or plasma CVD.

16. 16. The method of manufacturing a semiconductor device according to claim 15, The insulating film is a first portion in contact with the semiconductor substrate; a second portion in contact with the sidewall spacer; a third portion in contact with a portion of the top surface of the gate electrode; having a recess is formed at a connection point between an upper surface of the first portion and an upper surface of the second portion, The recess is filled with a portion of the field plate electrode.

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