Semiconductor device

Abstract

To easily distinguish a shape provided on a surface of a semiconductor device from a portion except for the shape provided on the surface of the semiconductor device.SOLUTION: A semiconductor device 10 includes a semiconductor element 30 and a sealing resin 20 sealing the semiconductor element 30. The semiconductor element 30 includes an exposed surface 33 exposed from the sealing resin 20. A plurality of recessed portions 34 are formed on the exposed surface 33.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art There is known a semiconductor device that includes a semiconductor element and a sealing resin that seals the semiconductor element, and in which a mark is provided on the surface of the sealing resin (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-47112 A

[0004] [overview] When providing a mark on the surface of the sealing resin, the surface condition of the sealing resin may make it difficult to distinguish between a portion with the mark and a portion without the mark. Note that, depending on the surface condition of the sealing resin, it may be difficult to distinguish not only the mark but also the shape provided on the surface of the sealing resin from a portion other than the shape provided on the surface of the sealing resin.

[0005] A semiconductor device according to one embodiment includes a semiconductor element and a sealing resin that seals the semiconductor element. The semiconductor element includes an exposed surface that is exposed from the sealing resin, and a plurality of recesses are formed in the exposed surface. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic perspective view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view of the semiconductor device of FIG. [Diagram 3] FIG. 3 is a schematic plan view of the sealing resin in the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic bottom view of the semiconductor device of FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device manufacturing method subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view illustrating the semiconductor device manufacturing method subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 15] FIG. 15 is a schematic bottom view of the semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the semiconductor device taken along line F16-F16 in FIG. [Figure 17] FIG. 17 is a schematic plan view of the semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of the semiconductor device taken along line F18-F18 in FIG. [Figure 19] 19A to 19C are schematic cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Diagram 23] FIG. 23 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device subsequent to FIG. [Figure 24] FIG. 24 is a schematic side view of a semiconductor device according to a modified example.

[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] First Embodiment [Configuration of semiconductor device] A semiconductor device 10 according to a first embodiment will be described with reference to FIGS.

[0010] FIG. 1 shows a schematic perspective structure of the semiconductor device 10. FIG. 2 shows a schematic planar structure showing the inside of the semiconductor device 10. FIG. 3 shows a schematic planar structure of the semiconductor device 10 of FIG. 1. FIG. 4 shows a schematic bottom structure of the semiconductor device 10 of FIG. 1. FIG. 5 shows a schematic cross-sectional structure of the semiconductor device 10 cut along the line F5-F5 of FIG. 2. In addition, in FIG. 1 and FIG. 2, in order to facilitate understanding of the drawings, a sealing resin 20 described later is shown by a two-dot chain line so as to illustrate the internal structure of the semiconductor device 10. In addition, in FIG. 1 and FIG. 2, in order to facilitate understanding of the drawings, a discrimination groove 27 described later is omitted. In addition, in FIG. 2, an internal conductive layer 48 is omitted. In FIG. 4, an external conductive layer 49 is omitted.

[0011] As shown in FIG. 1, the semiconductor device 10 includes a sealing resin 20, a semiconductor element 30 provided in the sealing resin 20, and a plurality of terminals 40 (four in the first embodiment) provided in the sealing resin 20. The sealing resin 20 seals at least some of the plurality of terminals 40 and at least some of the semiconductor element 30. The sealing resin 20 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. In the following description, the term "planar view" refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal XYZ axes shown in FIG. 1. Also, "planar view" is synonymous with "viewed from the thickness direction of the sealing resin."

[0012] As shown in FIG. 2, the sealing resin 20 is formed in a rectangular shape with the X direction being the longitudinal direction and the Y direction being the lateral direction in a plan view. As shown in FIG. 1, the sealing resin 20 has a sealing surface 21, a sealing back surface 22 facing the opposite side to the sealing surface 21 in the Z direction, and first to fourth sealing side surfaces 23 to 26 connecting the sealing surface 21 and the sealing back surface 22. The sealing back surface 22 is a surface that faces the substrate surface of the wiring board (not shown) when the semiconductor device 10 is mounted on the wiring board. The first sealing side surface 23 and the second sealing side surface 24 constitute both end surfaces of the sealing resin 20 in the X direction, and the third sealing side surface 25 and the fourth sealing side surface 26 constitute both end surfaces of the sealing resin 20 in the Y direction. The shape of the sealing resin 20 in a plan view can be changed arbitrarily. Here, the X direction is an example of the "first direction", and the Y direction is an example of the "second direction".

[0013] As shown in FIG. 3, a discrimination groove 27 for discriminating the polarity of the semiconductor device 10 is formed on the sealing surface 21 of the sealing resin 20. The discrimination groove 27 is formed in a rectangular shape extending in the Y direction in a plan view. In the example shown in FIG. 3, the discrimination groove 27 is located closer to the second sealing side surface 24 than the center in the X direction. The discrimination groove 27 is also disposed in approximately the center of the sealing surface 21 in the Y direction. The discrimination groove 27 is a groove recessed in a rectangular shape from the sealing surface 21 toward the sealing back surface 22. When the semiconductor device 10 is mounted on the wiring board, the polarity of the semiconductor device 10 can be discriminated according to the position of the discrimination groove 27 relative to the sealing surface 21. Furthermore, since the discrimination groove 27 is formed on the sealing surface 21, the polarity of the semiconductor device 10 can be confirmed even after mounting.

[0014] The sealing resin 20 is formed of, for example, an insulating material. The insulating material is formed of, for example, a material including at least one of a silicone resin, an epoxy resin, and an acrylic resin. In one example, the sealing resin 20 is formed of a black epoxy resin.

[0015] 2, the semiconductor element 30 is, for example, a Hall element, and therefore the semiconductor device 10 may be a magnetic sensor (Hall IC). The semiconductor element 30 is disposed at approximately the center of the sealing resin 20 in plan view. The semiconductor element 30 is formed in a rectangular shape in plan view. In one example, the semiconductor element 30 is formed in a square shape in plan view. As shown in FIG. 2 and FIG. 5, the semiconductor element 30 has an element front surface 31 and an element back surface 32 facing opposite sides to each other in the Z direction, and four side surfaces connected to both the element front surface 31 and the element back surface 32. As shown in FIG. 2, the side surfaces of the semiconductor element 30 are inclined with respect to both the X direction and the Y direction in plan view. In the example shown in FIG. 2, the inclination angle of each side surface of the semiconductor element 30 with respect to both the X direction and the Y direction is 45°.

[0016] As shown in FIG. 5, the element back surface 32 of the semiconductor element 30 constitutes an exposed surface 33 exposed from the sealing resin 20. In the first embodiment, the exposed surface 33 is exposed from the sealing back surface 22. In one example, the element back surface 32 may be flush with the sealing back surface 22 of the sealing resin 20, or may be located closer to the sealing front surface 21 than the sealing back surface 22. In the example shown in FIG. 5, the element back surface 32 (exposed surface 33) is located closer to the sealing front surface 21 than the sealing back surface 22. More specifically, a recessed portion 28 recessed from the sealing back surface 22 toward the sealing front surface 21 is formed in the center of the sealing resin 20 in the X direction and the Y direction. As shown in FIG. 4, the recessed portion 28 is formed in a circular shape in a plan view. The element back surface 32 (exposed surface 33) of the semiconductor element 30 is disposed in the recessed portion 28 in a plan view. In one example, the semiconductor element 30 is disposed in the center of the recessed portion 28. In one example, as shown in FIG. 5, exposed surface 33 of semiconductor element 30 is formed to be flush with the bottom surface of recessed portion .

[0017] In one example, the entire element rear surface 32 is exposed from the sealing resin 20. Therefore, the entire element rear surface 32 constitutes the exposed surface 33. As a result, each side of the exposed surface 33 constitutes a side surface of the semiconductor element 30, and is therefore inclined with respect to both the X direction and the Y direction. In addition, the exposed surface 33 is formed in a rectangular shape. Note that a portion of the element rear surface 32 may be exposed from the sealing resin 20. In this case, the exposed surface 33 is constituted by a portion of the element rear surface 32.

[0018] 2, a plurality of electrodes 70 (four in the first embodiment) are provided on the element surface 31. The electrodes 70 are made of, for example, a metal layer in which a gold (Au) layer is laminated on a titanium (Ti) layer. A wire WR is connected to each of the electrodes 70.

[0019] As shown in FIG. 5, the semiconductor device 30 includes a semiconductor substrate 35 and a semiconductor layer 38 formed on the semiconductor substrate 35 . The semiconductor substrate 35 is formed of, for example, gallium arsenide (GaAs). The main material of the semiconductor substrate 35 may be selected from silicon (Si), indium arsenide (InAs), and indium antimonide (InSb). The material of the semiconductor substrate 35 is not limited to these. The semiconductor substrate 35 includes a substrate front surface 36 and a substrate back surface 37 facing the opposite side to the substrate front surface 36. The substrate front surface 36 faces the same side as the element front surface 31. The substrate back surface 37 faces the same side as the element back surface 32. In one example, the substrate back surface 37 constitutes the element back surface 32.

[0020] The semiconductor layer 38 includes a functional section 39 that functions as a Hall element. In addition, a plurality of electrodes 70 are formed in the semiconductor layer 38. The plurality of electrodes 70 are electrically connected to the functional section 39 by a wiring layer (not shown). The thickness of the semiconductor substrate 35 is greater than the thickness of the semiconductor layer 38. In one example, the thickness of the semiconductor substrate 35 is more than twice the thickness of the semiconductor layer 38.

[0021] 1 and 2, a plurality of terminals 40 (four in the first embodiment) form a conductive path between a wiring board on which the semiconductor device 10 is mounted and the semiconductor element 30. The plurality of terminals 40 are arranged at a distance from the semiconductor element 30. Each of the plurality of terminals 40 is electrically connected to the element surface 31 (four electrodes 70) of the semiconductor element 30 via a wire WR. Four terminals 40 are provided, and when distinguishing between them, they are called terminals 40A, 40B, 40C, and 40D.

[0022] Each of the plurality of terminals 40 has a main surface 41, a bottom surface 42, an inner side surface 43, a first outer side surface 44, a second outer side surface 45, and a recessed portion 46. The plurality of terminals 40 further has an inner conductive layer 48 and an outer conductive layer 49. All of the plurality of terminals 40 except for the inner conductive layer 48 and the outer conductive layer 49 are formed from the same metal material. The metal material includes, for example, copper (Cu). Note that the metal material is not limited to Cu, and may be any material that is conductive and non-magnetic.

[0023] As shown in FIGS. 1 and 2, the main surface 41 faces in the same direction as the element surface 31 of the semiconductor element 30. A wire WR is connected to each of the multiple main surfaces 41 via an internal conductive layer 48. In the present disclosure, the main surface 41 of the terminal 40A is referred to as the main surface 41A, the main surface 41 of the terminal 40B is referred to as the main surface 41B, the main surface 41 of the terminal 40C is referred to as the main surface 41C, and the main surface 41 of the terminal 40D is referred to as the main surface 41D. In one example, the shape of the main surface 41C is the same as the main surface 41A. The shape of the main surface 41D is the same as the main surface 41B.

[0024] 1 and 4, the bottom surface 42 faces the opposite side to the main surface 41. The bottom surface 42 is exposed from the sealing resin 20. In one example, the bottom surfaces 42 of the multiple terminals 40 are formed so as to be flush with, for example, the sealing back surface 22 of the sealing resin 20.

[0025] In the present disclosure, the bottom surface 42 of terminal 40A is referred to as bottom surface 42A, the bottom surface 42 of terminal 40B is referred to as bottom surface 42B, the bottom surface 42 of terminal 40C is referred to as bottom surface 42C, and the bottom surface 42 of terminal 40D is referred to as bottom surface 42D. The shape of bottom surface 42C is the same as that of bottom surface 42A. The shape of bottom surface 42D is the same as that of bottom surface 42B.

[0026] 1 and 2, the inner side surface 43 is connected to the main surface 41 and in contact with the sealing resin 20. In the present disclosure, the inner side surface 43 of the terminal 40A is referred to as the inner side surface 43A, the inner side surface 43 of the terminal 40B is referred to as the inner side surface 43B, the inner side surface 43 of the terminal 40C is referred to as the inner side surface 43C, and the inner side surface 43 of the terminal 40D is referred to as the inner side surface 43D. The shape of the inner side surface 43C is the same as the shape of the inner side surface 43A. The shape of the inner side surface 43D is the same as the shape of the inner side surface 43B.

[0027] As shown in FIG. 2, in each of the multiple terminals 40, the inner side surface 43 (inner sides 43A, 43B, 43C, 43D) includes a first region 431, a second region 432, and a third region 433. The first region 431 is disposed along both the X direction and the Z direction. In the X direction, one end of the first region 431 is connected to the first outer side surface 44. The second region 432 is disposed along both the Y direction and the Z direction. In the Y direction, one end of the second region 432 is connected to the second outer side surface 45. The third region 433 is disposed along the Z direction and is inclined with respect to both the X direction and the Y direction. It is most preferable that the inclination angle of the third region 433 with respect to both the X direction and the Y direction is 45°, and the allowable error range of the inclination angle is ±5°. In a plan view, one end of the third region 433 is connected to the first region 431, and the other end of the third region 433 is connected to the second region 432. As shown in Fig. 2, the third region 433 is parallel to the side surface of the semiconductor element 30 in a plan view.

[0028] As shown in FIG. 1 and FIG. 2, the first outer side surface 44 is connected to all of the main surface 41, the bottom surface 42, and the inner side surface 43 (first region 431) and faces the X direction. The first outer side surface 44 is exposed from the sealing resin 20. In the present disclosure, the first outer side surface 44 of the terminal 40A is referred to as the first outer side surface 44A, the first outer side surface 44 of the terminal 40B is referred to as the first outer side surface 44B, the first outer side surface 44 of the terminal 40C is referred to as the first outer side surface 44C, and the first outer side surface 44 of the terminal 40D is referred to as the first outer side surface 44D. The shape of the first outer side surface 44C is the same as that of the first outer side surface 44A. The shape of the first outer side surface 44D is the same as that of the first outer side surface 44B.

[0029] As shown in FIG. 1 and FIG. 2, the second outer side 45 is connected to all of the main surface 41, the bottom surface 42, and the inner side 43 (the second region 432) and faces the Y direction. The second outer side 45 is exposed from the sealing resin 20. The second outer side 45 is connected to the first outer side 44. In a plan view, a portion where a plane including the first outer side 44 and a plane including the second outer side 45 intersect corresponds to a corner of the semiconductor device 10. In the present disclosure, the second outer side 45 of the terminal 40A is the second outer side 45A, the second outer side 45 of the terminal 40B is the second outer side 45B, the second outer side 45 of the terminal 40C is the second outer side 45C, and the second outer side 45 of the terminal 40D is the second outer side 45D. The shape of the second outer side 45C is the same as the second outer side 45A. The shape of the second outer side 45D is the same as the second outer side 45B.

[0030] As shown in FIG. 1, the recessed portion 46 is recessed from both the bottom surface 42 and the inner side surface 43. In a plan view, a portion of the terminal 40 including the area of ​​the main surface 41 overlapping with the recessed portion 46 and the inner side surface 43 forms an eave shape. The recessed portion 46 contacts the sealing resin 20. In the example shown in the semiconductor device 10, the recessed portion 46 is filled with the sealing resin 20. In the present disclosure, the recessed portion 46 of the terminal 40A is referred to as the recessed portion 46A, the recessed portion 46 of the terminal 40B is referred to as the recessed portion 46B, the recessed portion 46 of the terminal 40C is referred to as the recessed portion 46C, and the recessed portion 46 of the terminal 40D is referred to as the recessed portion 46D.

[0031] As shown in Fig. 1 and Fig. 2, the internal conductive layer 48 covers the main surfaces 41 of the multiple terminals 40. The composition of the internal conductive layer 48 is, for example, silver (Ag). The internal conductive layer 48 may be configured such that a nickel (Ni) layer, a palladium (Pd) layer, and an Au layer are laminated in this order, or such that a Pd layer is laminated on a Ni layer. The configuration of the internal conductive layer 48 is not limited to these. The internal conductive layer 48 is covered with a sealing resin 20.

[0032] As shown in FIG. 1 and FIG. 2, the outer conductive layer 49 covers the bottom surfaces 42 of the multiple terminals 40. The composition of the outer conductive layer 49 is an alloy containing tin (Sn). The alloy is, for example, a lead (Pb)-free solder alloy such as an Sn-Sb alloy or an Sn-Ag alloy. The composition of the outer conductive layer 49 may be a configuration in which the alloy layer is laminated on an Ag layer, or a configuration in which an Au layer is laminated on an Ag layer. The configuration of the outer conductive layer 49 is not limited to these. The outer conductive layer 49 is exposed from the sealing resin 20.

[0033] 1 and 2, first outer surfaces 44 of the multiple terminals 40 are exposed from the first sealing side 23 and the second sealing side 24. In one example, each first outer surface 44 is flush with the first sealing side 23 and the second sealing side 24. As shown in FIGS. 1 and 2, second outer surfaces 45 of the multiple terminals 40 are exposed from the third sealing side 25 and the fourth sealing side 26. In one example, each second outer surface 45 is flush with the third sealing side 25 and the fourth sealing side 26.

[0034] As shown in FIG. 1 and FIG. 2, the wires WR mutually connect the electrodes 70 of the semiconductor element 30 and the terminals 40. The wires WR are composed of four wires. The material of the wires WR is, for example, Au. The wires WR are formed by wire bonding. As shown in FIG. 2, each of the wires WR has a first connection portion 61 and a second connection portion 62. The first connection portion 61 is a ball bonding portion formed first in the process of forming the wire WR. The first connection portion 61 is connected to an internal conductive layer 48 (see FIG. 1) covering the main surface 41 of the terminals 40. In this case, the first connection portion 61 is connected to the internal conductive layer 48 located on the region of the main surface 41 that overlaps with the bottom surface 42 in a plan view. The second connection portion 62 is a stitch bonding portion formed last in the process of forming the wire WR. The second connection portion 62 is connected to the electrodes 70 of the semiconductor element 30.

[0035] The connection form of the wires WR can be changed arbitrarily. In the semiconductor device 10, the first connection portions 61 of the wires WR may be connected to the electrodes 70 of the semiconductor element 30. The second connection portions 62 of the wires WR may be connected to the internal conductive layer 48 covering the main surfaces 41 of the terminals 40.

[0036] 4, the sealing resin 20 exposes the exposed surface 33 of the semiconductor element 30, and the bottom surfaces 42, first outer side surface 44 (see FIG. 2), and second outer side surface 45 (see FIG. 2) of the multiple terminals 40. The bottom surfaces 42 of the multiple terminals 40 are exposed from the sealing back surface 22. In the first embodiment, the sealing resin 20 encapsulates the entire parts of the semiconductor element 30 other than the exposed surface 33, the parts of the multiple terminals 40 other than the bottom surfaces 42, the first outer side surface 44, and the second outer side surface 45, and each of the four wires WR (see FIG. 2).

[0037] A plurality of recesses 34 are formed on the exposed surface 33. The plurality of recesses 34 can be said to be formed on the semiconductor substrate 35. In the first embodiment, a pattern is formed by the plurality of recesses 34. The pattern formed by the plurality of recesses 34 is information on the semiconductor device 10 or a mark 34A corresponding to the information. It can be said that the mark 34A is composed of the plurality of recesses 34. It can also be said that the mark 34A includes information on the semiconductor device 10 indicated by the pattern formed by the plurality of recesses 34. Examples of the information on the semiconductor device 10 include a manufacturing lot number, coordinate information of the semiconductor element 30 on a semiconductor wafer on which the semiconductor element 30 is formed, and information on the electrical characteristics of the semiconductor device 10. Such information on the semiconductor device 10 is stored, for example, in a measuring device that measures the semiconductor device 10. The mark 34A can include reference information corresponding to the information stored in the measuring device. For example, the mark 34A is read by an image reader, and the information (information on the semiconductor device 10) stored in the measuring device that measures the semiconductor device 10 can be obtained. That is, since the mark 34A and the information about the semiconductor device 10 stored in the measuring device are linked, the information about the semiconductor device 10 can be acquired based on the mark 34A.

[0038] In one example, each recess 34 is formed in a circular shape in a plan view. The multiple recesses 34 are arranged in a direction along each side of the exposed surface 33. In the first embodiment, the multiple recesses 34 are formed in the exposed surface 33. In other words, the multiple recesses 34 are not formed on the sealing back surface 22 outside the exposed surface 33. In one example, the multiple recesses 34 are formed over almost the entire exposed surface 33. The pattern formed by the multiple recesses 34 may be a two-dimensional code. That is, the mark 34A may be a two-dimensional code. In another example, the depth of the multiple recesses 34 is greater than 20 μm and equal to or less than 50 μm. The depth of the multiple recesses 34 is thinner than the thickness of the semiconductor substrate 35. The multiple recesses 34 are formed, for example, by a laser.

[0039] [Method of manufacturing semiconductor device] An example of a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 6 to 14 are cross-sectional views for explaining a manufacturing method of the semiconductor device 10, and the cross-sectional positions are all the same as the cross-sectional position of FIG.

[0040] First, as shown in FIG. 6, a conductive plate 81 is prepared having a main surface 41 and a bottom surface 42 facing opposite directions in the Z direction. A plurality of terminals 40 (see FIG. 1) of the semiconductor device 10 are formed from the conductive plate 81. The conductive plate 81 is, for example, a thin metal plate containing Cu. The conductive plate 81 has a thickness of, for example, 100 μm. The main surface 41 and the bottom surface 42 are both uniformly flat surfaces. The main surface 41 is entirely covered with an internal conductive layer 48. The internal conductive layer 48 is formed by electrolytic plating.

[0041] Next, as shown in FIG. 7, a mask is formed on both the internal conductive layer 48 and the bottom surface 42 of the conductive plate 81 by photolithography, and then a part of each of the conductive plate 81 and the internal conductive layer 48 is removed by wet etching. The etching solution is, for example, a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). Etching is performed on both the internal conductive layer 48 and the bottom surface 42 of the conductive plate 81. First, a part of the conductive plate 81 is removed by half etching from the bottom surface 42. Then, etching is performed from the internal conductive layer 48, and a part of the conductive plate 81 and the internal conductive layer 48 is penetrated in the Z direction. By this process, the inner surface 43 and the recessed portion 46 are formed in the conductive plate 81.

[0042] 8, a base material 82 is attached to the bottom surface 42 of the conductive plate 81. The base material 82 is an electrically insulating member, such as a tape. 9, after mounting the semiconductor element 30 on the substrate 82, a plurality of wires WR are formed to electrically connect the semiconductor element 30 and the conductive plate 81. More specifically, first, a bonding material 83 is applied to the substrate 82. The bonding material 83 is, for example, a die attach film. Then, the semiconductor element 30 is attracted by a collet or the like and transferred onto the substrate 82, and then placed on the bonding material 83. The bonding material 83 is then thermally cured in a curing oven or the like. Next, a plurality of wires WR are formed by, for example, a wire bonding device so as to individually connect the plurality of electrodes 70 of the semiconductor element 30 to the conductive plate 81.

[0043] 10, a sealing resin 20X is formed to cover the conductive plate 81, the semiconductor element 30, and the wires WR. The sealing resin 20X is formed by transfer molding a thermosetting synthetic resin having electrical insulation properties. The sealing resin 20X contacts the base material 82 and fills the recess 46 formed in the conductive plate 81. Here, the sealing resin 20X is formed so as to cover the bonding material 83, thereby forming a recess 28 in the sealing resin 20X.

[0044] 11, the base material 82 and the bonding material 83 are peeled off from the conductive plate 81 and the sealing resin 20X, and a part of the sealing resin 20X located near the main surface 41 of the conductive plate 81 in the Z direction is uniformly removed in a direction perpendicular to the Z direction by mechanical polishing. Note that the mechanical polishing of the sealing resin 20X may be omitted. In this state, the sealing resin 20X has a sealing front surface 21X and a sealing back surface 22X. Both the bottom surface 42 of the conductive plate 81 and the element back surface 32 of the semiconductor element 30 are exposed from the sealing back surface 22X.

[0045] 12, an outer conductive layer 49 is formed to cover the bottom surface 42 of the conductive plate 81. The outer conductive layer 49 is formed by electrolytic plating. Next, the conductive plate 81 (including the internal conductive layer 48 and the external conductive layer 49) and the sealing resin 20X are cut along both the X direction and the Y direction to separate into individual pieces. For example, a dicing saw is used to cut from the side where the bottom surface 42 of the conductive plate 81 faces. For example, when cutting along the X direction, cutting is performed along the cutting line CL shown in FIG. 13. The individual pieces separated in this process become the semiconductor device 10. At this time, the first outer side surface 44 and the second outer side surface 45 (both see FIG. 2) are formed on the conductive plate 81, and the conductive plate 81 becomes a plurality of terminals 40 (see FIG. 2). In addition, the first to fourth sealing side surfaces 23 to 26 (both see FIG. 2) are formed on the sealing resin 20X, and the sealing resin 20X becomes the sealing resin 20 (see FIG. 2).

[0046] Thereafter, as shown in FIG. 14, a plurality of recesses 34 are formed on the exposed surface 33 formed by the element back surface 32. The plurality of recesses 34 are formed, for example, by irradiating the exposed surface 33 with a laser as indicated by the outline arrow. The pattern formed by the plurality of recesses 34 forms, for example, a two-dimensional code linked to information related to the semiconductor device 10 as a mark 34A. That is, the positions of the plurality of recesses 34 to be irradiated with a laser are set so as to form a two-dimensional code. In addition, a discrimination groove 27 is formed on the sealing surface 21. The discrimination groove 27 is formed, for example, by irradiating the sealing surface 21 with a laser as indicated by the outline arrow. The discrimination groove 27 may be formed by a mold die used when forming the sealing resin 20X. Through the above steps, the semiconductor device 10 is manufactured.

[0047] [Effect] The operation of the semiconductor device 10 of the first embodiment will be described. The element back surface 32 of the semiconductor element 30 of the semiconductor device 10 constitutes an exposed surface 33 exposed from the sealing resin 20. This exposed surface 33 is provided with a plurality of recesses 34. The plurality of recesses 34 form a mark 34A. This makes it easier to read the mark 34A by an image reader regardless of the surface condition of the sealing resin 20, compared to a configuration in which a plurality of recesses 34 are formed on the sealing surface 21 of the sealing resin 20.

[0048] [effect] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a semiconductor element 30 and a sealing resin 20 that seals the semiconductor element 30. The semiconductor element 30 includes an exposed surface 33 that is exposed from the sealing resin 20. A plurality of recesses 34 are formed in the exposed surface 33.

[0049] According to this configuration, a plurality of recesses 34 are provided on exposed surface 33 formed by element back surface 32 of semiconductor element 30, which tends to have a smaller surface roughness than sealing resin 20. Therefore, compared to a configuration in which a plurality of recesses 34 are formed in sealing resin 20, the plurality of recesses 34 can be read more easily by an image reader regardless of the state of surface roughness of sealing resin 20.

[0050] (1-2) A pattern is formed by a plurality of recesses 34. According to this configuration, the plurality of recesses 34 can be used as the mark 34 A. Therefore, by reading the plurality of recesses 34 that form a pattern, information based on the pattern can be obtained.

[0051] (1-3) The pattern formed by the multiple recesses 34 is a mark 34A that includes information about the semiconductor device 10. According to this configuration, by reading the mark 34A, information about the semiconductor device 10 can be obtained. Examples of the information about the semiconductor device 10 include a lot number, coordinate information of the semiconductor element 30 on a semiconductor wafer that constitutes the semiconductor element 30, information about the electrical characteristics of the semiconductor device 10, and the like.

[0052] (1-4) The sealing resin 20 has a sealing surface 21 and a sealing back surface 22 facing the opposite side to the sealing surface 21. The semiconductor element 30 has an element front surface 31 facing the same side as the sealing surface 21 and an element back surface 32 facing the same side as the sealing back surface 22. The element back surface 32 includes an exposed surface 33 exposed from the sealing back surface 22. The semiconductor element 30 includes a semiconductor substrate 35 including a substrate front surface 36 and a substrate back surface 37 facing the opposite side to the substrate front surface 36, and a semiconductor layer 38 formed on the substrate front surface 36. A functional portion 39 of the semiconductor element 30 is formed in the semiconductor layer 38. The substrate back surface 37 constitutes the element back surface 32.

[0053] According to this configuration, the element back surface 32 formed by the substrate back surface 37 is exposed from the sealing back surface 22. In other words, the substrate back surface 37 of the semiconductor substrate 35 not including the functional portion 39 of the semiconductor element 30 constitutes the exposed surface 33. As a result, even if a plurality of recesses 34 are formed on the exposed surface 33, adverse effects on the functional portion 39 can be suppressed.

[0054] (1-5) The exposed surface 33 is formed in a rectangular shape. The sealing resin 20 has a first sealing side surface 23 and a second sealing side surface 24 extending in the Y direction, and a third sealing side surface 25 and a fourth sealing side surface 26 extending in the X direction. Each side of the exposed surface 33 is inclined with respect to both the first sealing side surface 23 and the second sealing side surface 24 (Y direction) and the third sealing side surface 25 and the fourth sealing side surface 26 (X direction) when viewed from the Z direction.

[0055] According to this configuration, since it is necessary to position the semiconductor element 30 so as not to come into contact with the multiple terminals 40 arranged at the four corners of the semiconductor device 10, the area of ​​the exposed surface 33 can be made larger compared to a configuration in which each side of the exposed surface 33 is provided parallel to the first to fourth sealing side surfaces 23-26. As a result, the multiple recesses 34 can be provided in a larger area compared to a configuration in which each side of the exposed surface 33 is provided parallel to the first to fourth sealing side surfaces 23-26.

[0056] (1-6) Since a thin semiconductor device 10 is desired, the thickness of the sealing resin 20 is thin. For this reason, the shortest distance in the Z direction between the sealing surface 21 of the sealing resin 20 and the wire WR is about 30 μm. In such a configuration, if multiple recesses 34 are formed in the sealing surface 21, it is difficult to make the depth of the recesses 34 greater than 20 μm, taking into account the effect on the wire WR. As a result, depending on the surface condition of the sealing surface 21, it becomes difficult to distinguish between a portion where multiple recesses 34 are formed and a portion where multiple recesses 34 are not formed.

[0057] In this regard, in the first embodiment, since the multiple recesses 34 are formed on the element back surface 32 (exposed surface 33) of the semiconductor element 30, the depth of the multiple recesses 34 can be made greater than 20 μm. This makes it easier to distinguish between a portion where the multiple recesses 34 are formed and a portion where the multiple recesses 34 are not formed. In addition, by setting the depth of the multiple recesses 34 to 40 μm or less, it is possible to prevent the time required to form each recess 34 from becoming excessively long.

[0058] (1-7) The pattern formed by the plurality of recesses 34 includes a two-dimensional code. According to this configuration, more information can be added by the plurality of recesses 34 than when the pattern formed by the plurality of recesses 34 is a one-dimensional code (barcode).

[0059] (1-8) The semiconductor device 10 has a main surface 41 facing the same side as the element surface 31, and includes a terminal 40 arranged apart from the semiconductor element 30 in a plan view, and a wire WR connecting the element surface 31 and the main surface 41. The minimum distance between the sealing surface 21 and the wire WR in the Z direction is 50 μm or less.

[0060] According to this configuration, the minimum distance between the sealing surface 21 and the wires WR can be reduced because the multiple recesses 34 are not formed in the sealing surface 21. This allows the semiconductor device 10 to be made thinner.

[0061] (1-9) The terminal 40 is exposed from the back surface 22 of the sealing body. This configuration increases the contact area between the terminals 40 and the wiring board on which the semiconductor device 10 is mounted, compared to a configuration in which the terminals 40 are not exposed from the sealing resin 20 and only the lead wires are exposed. This makes it easier for heat from the semiconductor device 10 to transfer to the wiring board, thereby suppressing a rise in temperature of the semiconductor device 10.

[0062] (1-10) The element back surface 32 is flush with the sealing back surface 22 of the sealing resin 20 or is located closer to the sealing front surface 21 than the sealing back surface 22 . According to this configuration, compared to a configuration in which the element rear surface 32 protrudes from the sealing rear surface 22 to the outside of the sealing resin 20, it is possible to suppress rattling when the semiconductor device 10 is mounted on a wiring board.

[0063] <Second embodiment> A semiconductor device 10 of the second embodiment will be described with reference to Figs. 15 and 16. The semiconductor device 10 of the second embodiment is mainly different from the semiconductor device 10 of the first embodiment in that a support member 84 is added. Below, the differences from the semiconductor device 10 of the first embodiment will be described in detail, and components common to the semiconductor device 10 of the first embodiment will be given the same reference numerals and detailed description thereof will be omitted. Fig. 15 shows a schematic bottom structure of the semiconductor device 10. Fig. 16 shows a schematic cross-sectional structure of the semiconductor device 10 cut along the line F16-F16 in Fig. 15.

[0064] As shown in FIG. 15 and FIG. 16, in the semiconductor device 10 of the second embodiment, the support member 84 is formed so as to contact the entire element back surface 32 of the semiconductor element 30. In one example, the support member 84 is a die attachment film similar to the bonding material 83 of the first embodiment. The method for forming the support member 84 is the same as the method for forming the bonding material 83 of the first embodiment. As shown in FIG. 15, in a plan view, the support member 84 is disposed at approximately the center of the sealing back surface 22. The support member 84 is formed in a circular shape surrounding the entire semiconductor element 30 in a plan view. The support member 84 is exposed from the sealing back surface 22. On the other hand, unlike the first embodiment, the element back surface 32 of the semiconductor element 30 is not exposed from the outside of the semiconductor device 10. In the example shown in FIG. 16, the back surface 85 of the support member 84 and the sealing back surface 22 are flush with each other. Therefore, the back surface 85 of the support member 84 constitutes an exposed surface 86. In other words, it can be said that the support member 84 includes the exposed surface 86. In one example, the entire back surface 85 of the support member 84 is exposed from the sealing back surface 22. Therefore, the exposed surface 86 is constituted by the entire back surface 85 of the support member 84.

[0065] A plurality of recesses 34 are provided on the exposed surface 86. In one example, the shape of the exposed surface 86 matches the shape of the support member 84 in a plan view. In one example, the plurality of recesses 34 are arranged in an area larger than the element back surface 32. The arrangement of the plurality of recesses 34 may be the same as that of the first embodiment.

[0066] In one example, the support member 84 has electrical conductivity by including a base material and metal particles provided in the base material. For example, Ag paste may be used for the support member 84. That is, the support member 84 includes a base material formed of an insulating resin and Ag as metal particles. For example, an epoxy resin may be used as the insulating resin. Note that the support member 84 may include metal particles at a higher rate than the insulating resin. Furthermore, the support member 84 may be formed of an insulating material. For example, an epoxy resin may be used as the insulating material.

[0067] [effect] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) The semiconductor device 10 includes a support member 84, a semiconductor element 30 arranged on the support member 84, and a sealing resin 20 that seals the semiconductor element 30. The support member 84 includes an exposed surface 86 that is exposed from the sealing resin 20. A plurality of recesses 34 are formed in the exposed surface 86. The support member 84 includes a base material and metal particles provided in the base material.

[0068] When forming the support member 84, the support member 84 is formed on the base material 82. Therefore, even when the support member 84 is formed by a mold, for example, the influence of the mold on the surface (rear surface) of the support member 84 that comes into contact with the base material 82 is suppressed. In other words, the influence of the increase in surface roughness of the mold caused by multiple uses of the mold is suppressed on the surface of the support member 84 that comes into contact with the base material 82. Therefore, the surface of the support member 84 that comes into contact with the base material 82 is unlikely to become large in surface roughness. Here, the surface of the support member 84 that comes into contact with the base material 82 corresponds to the exposed surface 86 that is exposed from the sealing resin 20.

[0069] Therefore, in the semiconductor device 10 of the second embodiment, a plurality of recesses 34 are provided on the exposed surface 86 of the support member 84, which is likely to have a smaller surface roughness than the sealing surface 21 of the sealing resin 20. Therefore, compared to a configuration in which a plurality of recesses 34 are formed on the sealing surface 21 of the sealing resin 20, the plurality of recesses 34 can be read more easily by an image reader regardless of the surface condition of the sealing resin 20.

[0070] (2-2) The support member 84 includes a base material and metal particles provided within the base material. According to this configuration, the heat generated by the semiconductor element 30 can be efficiently dissipated to the outside of the semiconductor device 10 by the support member 84 .

[0071] (2-3) The multiple recesses 34 are arranged in an area larger than the rear surface 32 of the element. According to this configuration, in comparison with the first embodiment, the mark 34A made up of a plurality of recesses 34 can be provided over a wider area. Therefore, a large amount of information can be included in the mark 34A.

[0072] (2-4) The support member 84 and the sealing back surface 22 are flush with each other. This configuration can suppress rattling when the semiconductor device 10 is mounted on a wiring board.

[0073] (2-5) The support member 84 is made of a die attach film. As described in the first embodiment, the sealing resin 20 is formed by transfer molding. Therefore, if the surface of the mold for transfer molding becomes rough due to repeated transfer molding many times, the surface roughness of the sealing resin 20 molded by this mold will increase. As a result, if multiple recesses 34 are formed in the sealing resin 20, it will be difficult to distinguish them from the surface of the sealing resin 20. On the other hand, since the support member 84 is made of a die attachment film, that is, a ready-made die attachment film is used, the surface roughness of the die attachment film is prevented from increasing.

[0074] In consideration of these circumstances, in the semiconductor device 10 of the second embodiment, a plurality of recesses 34 are formed in the support member 84 serving as a die attachment film. Therefore, compared to a configuration in which a plurality of recesses 34 are formed in the sealing resin 20, the plurality of recesses 34 can be read more easily by an image reader regardless of the surface condition of the sealing resin 20.

[0075] <Third embodiment> The third embodiment will be described with reference to Figures 17 and 18. In the following description, the semiconductor element and the sealing resin will be described as the semiconductor element 30 and the sealing resin 20, similarly to the first embodiment.

[0076] [Configuration of semiconductor device] As shown in FIG. 18, the semiconductor device 10 of the third embodiment includes a substrate 50 made of an insulating material, a back electrode 91 that forms the mounting surface of the semiconductor device 10, and a wiring layer 92 connected to the back electrode 91.

[0077] The substrate 50 has a substrate front surface 51 and a substrate back surface 52 facing opposite to each other in the Z direction. The substrate front surface 51 faces the same side as the sealing surface 21 of the sealing resin 20. A wiring layer 92 is formed on the substrate front surface 51. A plurality of wiring layers 92 are formed on the substrate front surface 51 at a distance from each other. A back surface electrode 91 is formed on the substrate 50. The back surface electrode 91 is exposed from the substrate back surface 52. The back surface electrode 91 may also be exposed from the substrate side surface. A plurality of back surface electrodes 91 are formed at a distance from each other. In one example, the plurality of back surface electrodes 91 are disposed outward (closer to the substrate side surface) than the semiconductor element 30. The plurality of back surface electrodes 91 are individually connected to the plurality of wiring layers 92.

[0078] The semiconductor element 30 is mounted on the wiring layer 92. Here, the semiconductor element 30 is mounted on the wiring layer 92 such that an element front surface 31 faces the wiring layer 92. In other words, an element back surface 32 of the semiconductor element 30 faces in the same direction as the substrate front surface 51. In the third embodiment, the semiconductor element 30 is, for example, an LSI (Large-Scale Integration).

[0079] The semiconductor element 30 includes a plurality of connection electrodes 93 instead of the electrodes 70 (see FIG. 2) of the first embodiment. The plurality of connection electrodes 93 are formed on the element surface 31. Therefore, the plurality of connection electrodes 93 face the wiring layer 92 in the Z direction.

[0080] A plurality of connection electrodes 93 of the semiconductor element 30 are bonded to the wiring layer 92 by a bonding material 94. As a result, the connection electrodes 93 of the semiconductor element 30 are electrically connected to the back surface electrodes 91 via the bonding material 94 and the wiring layer 92. The bonding material 94 may be a conductive bonding material such as solder paste, Ag paste, or the like.

[0081] 17, the semiconductor element 30 is disposed approximately in the center of the sealing resin 20 in a plan view. The semiconductor element 30 is disposed, for example, such that the side surfaces of the semiconductor element 30 are parallel to the first to fourth sealing side surfaces 23-26 (X direction and Y direction) of the sealing resin 20. The arrangement of the semiconductor element 30 in a plan view may be the same as that of the first embodiment.

[0082] 18, the semiconductor element 30 includes a semiconductor substrate 35 and a semiconductor layer 38, similar to the first embodiment. The semiconductor substrate 35 constitutes the back surface 32 of the element. The semiconductor layer 38 constitutes the front surface 31 of the element. For this reason, a plurality of connection electrodes 93 are formed on the semiconductor layer 38. A functional section (LSI circuit region) (not shown) is formed in the semiconductor layer 38.

[0083] In the third embodiment, the element back surface 32 of the semiconductor element 30 formed by the substrate back surface 37 is exposed from the sealing surface 21 of the sealing resin 20. Therefore, the element back surface 32 constitutes the exposed surface 33. In one example, the element back surface 32 may be flush with the sealing surface 21 of the sealing resin 20, or may be located closer to the sealing back surface 22 than the sealing surface 21. In the example shown in FIG. 18, the element back surface 32 (exposed surface 33) is flush with the sealing surface 21. In one example, the entire surface of the element back surface 32 is exposed from the sealing surface 21. Therefore, the entire surface of the element back surface 32 constitutes the exposed surface 33.

[0084] A plurality of recesses 34 are provided on the exposed surface 33. Therefore, it can be said that a plurality of recesses 34 are formed on the element back surface 32 constituted by the substrate back surface 37. The plurality of recesses 34 form a pattern (mark 34A). In one example, the pattern formed by the plurality of recesses 34 forms a two-dimensional code. The arrangement of the plurality of recesses 34 on the exposed surface 33 may be similar to that of the first embodiment.

[0085] [Method of manufacturing semiconductor device] An example of a method for manufacturing the semiconductor device 10 of the third embodiment will be described with reference to Figures 19 to 23. Figures 19 to 23 are cross-sectional views for explaining the method for manufacturing the semiconductor device 10, and the cross-sectional positions are all the same as the cross-sectional position of Figure 18.

[0086] 19, first, a substrate unit is prepared. The substrate unit includes a substrate 50, a plurality of back electrodes 91 provided on the substrate 50, and a plurality of wiring layers 92 provided on a substrate front surface 51.

[0087] 20, the semiconductor element 30 is mounted on the wiring layers 92. More specifically, first, a bonding material 94 is applied to the wiring layers 92. Then, the semiconductor element 30 is placed on the bonding materials 94 so that the connection electrodes 93 of the semiconductor element 30 are individually connected to the bonding materials 94. Then, the bonding materials 94 are melted by heating, and then the bonding materials 94 are solidified, so that the connection electrodes 93 of the semiconductor element 30 are bonded to the wiring layers 92 by the bonding materials 94.

[0088] 21, the sealing resin 20 that seals the semiconductor element 30 is formed. The sealing resin 20 is formed by transfer molding an electrically insulating thermosetting synthetic resin. The sealing resin 20 is formed on the substrate 50. That is, the sealing resin 20 is in contact with the substrate surface 51 and each wiring layer 92. In this process, the sealing resin 20 is formed so as to cover the entire surface of the element back surface 32 of the semiconductor element 30.

[0089] 22, the sealing resin 20 is ground to reduce the thickness of the sealing resin 20. As a result, the element back surface 32 of the semiconductor element 30 is exposed from the sealing surface 21 of the sealing resin 20. The element back surface 32 constitutes an exposed surface 33 exposed from the sealing surface 21.

[0090] Thereafter, as shown in FIG. 23, a plurality of recesses 34 are formed on the exposed surface 33 formed by the element back surface 32. The plurality of recesses 34 are formed, for example, as indicated by the white arrows, by irradiating the exposed surface 33 with a laser. The plurality of recesses 34 form a two-dimensional code linked to information related to the semiconductor device 10. In other words, the positions of the plurality of recesses 34 to be irradiated with a laser are set so as to form a two-dimensional code. In addition, a discrimination groove 27 is formed on the sealing surface 21. The discrimination groove 27 is formed, for example, by irradiating the sealing surface 21 with a laser, as indicated by the white arrows. Through the above steps, the semiconductor device 10 is manufactured.

[0091] [effect] According to the semiconductor device 10 of the third embodiment, the following effects can be obtained. (3-1) The sealing resin 20 has a sealing surface 21 and a sealing back surface 22 facing the opposite side to the sealing surface 21. The semiconductor element 30 has an element back surface 32 facing the same side as the sealing surface 21, and an element front surface 31 facing the same side as the sealing back surface 22. The element back surface 32 includes an exposed surface 33 exposed from the sealing surface 21. A plurality of recesses 34 are formed in the exposed surface 33.

[0092] According to this configuration, compared to a configuration in which the element surface 31 of the semiconductor element 30 faces the sealing surface 21 and the element surface 31 and the multiple wiring layers 92 are connected by wires, there is no need to seal the wires, and therefore it is possible to reduce the thickness of the sealing resin 20. Furthermore, since the wires are omitted, the inductance caused by the wires can be reduced.

[0093] In addition, since a plurality of recesses 34 are formed on the exposed surface 33 of the semiconductor element 30 exposed from the sealing surface 21, the plurality of recesses 34 can be read by an image reader in a state in which the semiconductor element 30 is mounted on a wiring board.

[0094] <Example of change> The above-described embodiments may be modified as follows: Furthermore, the above-described embodiments and the following modifications may be combined with each other to the extent that no technical contradiction occurs.

[0095] In the third embodiment, the surface of the semiconductor element 30 exposed from the sealing resin 20 is not limited to the element back surface 32, and may be any surface. In one example, as shown in Fig. 24, the semiconductor device 10 of the first modified example has an exposed surface 33 in which a side surface of the semiconductor element 30 is exposed from any one of the first to fourth sealing side surfaces 23 to 26 of the sealing resin 20. A plurality of recesses 34 are formed in the exposed surface 33. The arrangement of the plurality of recesses 34 in the exposed surface 33 may be the same as in the first embodiment.

[0096] 24, a side surface of the semiconductor element 30 is exposed from the third sealing side surface 25. When viewed from the Y direction, the exposed surface 33 is located approximately in the center of the third sealing side surface 25 and is formed in a rectangular shape. In one example, the semiconductor element 30 is arranged with the element front surface 31 facing the sealing back surface 22, similar to the third embodiment.

[0097] In addition, even in a configuration in which the element surface 31 of the semiconductor element 30 faces the sealing surface 21 and the element surface 31 is connected to multiple terminals 40 by wires WR as in the first and second embodiments, the element side surface of the semiconductor element 30 may be exposed from any one of the first to fourth sealing side surfaces 23 to 26 as in the above modified example.

[0098] In the first and third embodiments, the shape of the exposed surface 33 in plan view is not limited to a rectangular shape and can be changed as desired. In one example, the shape of the exposed surface 33 in plan view may be a circle, an ellipse, an oblong hole, or a polygon having pentagons or more sides.

[0099] In the manufacturing method of the semiconductor device 10 of the first embodiment, the bonding material 83 may be omitted. That is, the semiconductor element 30 may be disposed on the surface of the base material 82. In this case, the recessed portion 28 is omitted from the sealing resin 20, and the element back surface 32 of the semiconductor element 30 is flush with the sealing back surface 22 of the sealing resin 20.

[0100] In each embodiment, the shape of each recess 34 in a plan view can be changed as desired. In one example, the shape of each recess 34 in a plan view may be rectangular. In each embodiment, the recesses 34 are disposed apart from each other in a plan view, but this is not limited to the above. For example, some of the recesses 34 may include portions that overlap each other in a plan view.

[0101] In each embodiment, the discrimination groove 27 may be omitted. One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent.

[0102] The terms "first," "second," "third," etc. in this disclosure are used merely to distinguish objects and do not rank the objects. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0103] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0104] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0105] <Additional Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the above embodiment. The reference numbers are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

[0106] [Appendix 1] A semiconductor element (30); a sealing resin (20) for sealing the semiconductor element (30); Including, The semiconductor element (30) includes an exposed surface (33) exposed from the sealing resin (20), The exposed surface (33) has a plurality of recesses (34) formed therein. A semiconductor device (10).

[0107] [Appendix 2] The plurality of recesses (34) form a pattern. 2. The semiconductor device according to claim 1.

[0108] [Appendix 3] The pattern is an indicia (34A) containing information about the semiconductor device (10). 3. The semiconductor device according to claim 2.

[0109] [Appendix 4] The sealing resin (20) has a sealing surface (21) and a sealing back surface (22) facing the opposite side to the sealing surface (21), The semiconductor element (30) has an element front surface (31) facing the same side as the sealing front surface (21) and an element back surface (32) facing the same side as the sealing back surface (22), The element back surface (32) includes the exposed surface (33) exposed from the sealing back surface (22). 4. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0110] [Appendix 5] The exposed surface (33) is flush with the sealing back surface (22) or is located closer to the sealing front surface (21) than the sealing back surface (22). 5. The semiconductor device according to claim 4.

[0111] [Appendix 6] The sealing resin (20) has a sealing surface (21) and a sealing back surface (22) facing the opposite side to the sealing surface (21), The semiconductor element (30) has an element back surface (32) facing the same side as the sealing front surface (21) and an element front surface (31) facing the same side as the sealing back surface (22), The element back surface (32) includes the exposed surface (33) exposed from the sealing surface (21). 4. The semiconductor device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

[0112] [Appendix 7] The exposed surface (33) is flush with the sealing surface (21) or is located closer to the sealing back surface (22) than the sealing surface (21). 7. The semiconductor device according to claim 6.

[0113] [Appendix 8] The exposed surface (33) is formed in a rectangular shape. 8. The semiconductor device according to claim 4, wherein the first and second electrodes are arranged in a first direction.

[0114] [Appendix 9] When viewed from the thickness direction (Z direction) of the semiconductor element (30), directions perpendicular to each other are defined as a first direction (X direction) and a second direction (Y direction), The sealing resin (20) has a first sealing side surface (23) and a second sealing side surface (24) constituting both end surfaces in the first direction (X direction) when viewed from the thickness direction (Z direction), and a third sealing side surface (25) and a fourth sealing side surface (26) constituting both end surfaces in the second direction (Y direction), Each side of the exposed surface (33) is inclined with respect to both the first direction (X direction) and the second direction (Y direction) when viewed from the thickness direction (Z direction). 9. The semiconductor device according to claim 8.

[0115] [Appendix 10] The plurality of recesses (34) are formed in a direction along each side of the exposed surface (33) when viewed from the thickness direction (Z direction) of the semiconductor element (30). 10. The semiconductor device according to claim 8 or 9.

[0116] [Appendix 11] The recess is formed in a circular shape when viewed in the thickness direction (Z direction) of the semiconductor element (30). 11. The semiconductor device according to any one of claims 1 to 10.

[0117] [Appendix 12] The depth of the recess is greater than 20 μm and less than or equal to 50 μm. 12. The semiconductor device according to claim 1.

[0118] [Appendix 13] The pattern formed by the plurality of recesses (34) includes a two-dimensional code. 4. The semiconductor device according to claim 2 or 3.

[0119] [Appendix 14] a terminal (40) having a main surface (41) facing the same side as the element surface (31) and disposed apart from the semiconductor element (30) when viewed in the thickness direction (Z direction) of the semiconductor element (30); a wire (W) connecting the element surface (31) and the main surface (41); Including, The minimum distance between the sealing surface (21) and the wire (W) in the thickness direction (Z direction) is 50 μm or less. 6. The semiconductor device according to claim 4 or 5.

[0120] [Appendix 15] The terminal (40) is exposed from the sealing back surface (22). 15. The semiconductor device according to claim 14.

[0121] [Appendix 16] The semiconductor device (30) includes a semiconductor substrate (35) having a substrate front surface (36) and a substrate back surface (37) opposite the substrate front surface (36); A semiconductor layer (38) including a functional portion is formed on the substrate surface (36), The back surface (38) of the substrate constitutes the exposed surface (33) of the semiconductor element (30). 8. The semiconductor device according to claim 4, wherein the first and second electrodes are arranged in a first direction.

[0122] [Appendix 17] The semiconductor element (30) is a Hall element. 6. The semiconductor device according to claim 1,

[0123] [Appendix 18] The sealing resin (20) has a sealing surface (21), A discrimination groove (27) for discriminating the polarity of the semiconductor device is formed on the sealing surface (21). 18. The semiconductor device according to claim 1,

[0124] [Appendix 19] A support member (84); a semiconductor element (30) disposed on the support member (84); a sealing resin (20) for sealing the semiconductor element (30); Including, The support member (84) includes an exposed surface (33) exposed from the sealing resin (20), The exposed surface (33) has a plurality of recesses (34) formed therein. A semiconductor device (10).

[0125] [Appendix 20] The support member (84) is A substrate; Metal particles provided within the substrate; Includes 20. The semiconductor device according to claim 19.

[0126] [Appendix 21] The support member (84) is made of an insulating material. 20. The semiconductor device according to claim 19. [Explanation of symbols]

[0127] 10...Semiconductor device 20,20X…Sealing resin 21,21X…Sealing surface 22,22X…Sealing back side 23~26...1st~4th sealing side 27…Discrimination groove 28…Recess 30...Semiconductor element 31...Element surface 32…Back side of element 33…Exposed surface 34…Multiple recesses 34A…Marking 35...Semiconductor substrate 36...Substrate surface 37…Back of the board 38...Semiconductor layer 39…Functional part 40, 40A~40D...Multiple terminals 41,41A~41D…Main surface 42, 42A~42D...Bottom 43, 43A~43D…Inner surface 431...First area 432…Second area 433…Third area 44,44A~44D…First outer surface 45,45A~45D…4th outer surface 46, 46A~46D…Indentation 48…Inner conductive layer 49...Outer conductive layer 50…Substrate 51...Substrate surface 52…Back of the board 61…First connection part 62…Second connection part 70...4 electrodes 81...Conductive plate 82...Base material 83...Joining material 84...Support member 85…Back side 86…Exposed surface 91…Back electrode 92...Wiring layer 93...Connection electrode 94...Joining material WR…Wire CL…cutting line

Claims

1. A semiconductor element; a sealing resin for sealing the semiconductor element; Including, the semiconductor element includes an exposed surface exposed from the sealing resin, The exposed surface has a plurality of recesses formed therein. Semiconductor device.

2. The plurality of recesses form a pattern. The semiconductor device according to claim 1 .

3. The pattern is a mark containing information about the semiconductor device. The semiconductor device according to claim 2 .

4. the sealing resin has a sealing surface and a sealing back surface facing the opposite side to the sealing surface, the semiconductor element has an element front surface facing the same side as the sealing front surface and an element back surface facing the same side as the sealing back surface, The element rear surface includes the exposed surface exposed from the sealing rear surface. The semiconductor device according to claim 1 .

5. The exposed surface is flush with the sealing back surface or is located closer to the sealing front surface than the sealing back surface. The semiconductor device according to claim 4.

6. the sealing resin has a sealing surface and a sealing back surface facing the opposite side to the sealing surface, the semiconductor element has an element back surface facing the same side as the sealing front surface and an element front surface facing the same side as the sealing back surface, The back surface of the element includes the exposed surface that is exposed from the sealing surface. The semiconductor device according to claim 1 .

7. The exposed surface is flush with the sealing surface or is located closer to the sealing back surface than the sealing surface. The semiconductor device according to claim 6.

8. The exposed surface is formed in a rectangular shape.

7. The semiconductor device according to claim 4 or 6.

9. When viewed from the thickness direction of the semiconductor element, directions perpendicular to each other are defined as a first direction and a second direction, the sealing resin has a first sealing side surface and a second sealing side surface constituting both end surfaces in the first direction when viewed from the thickness direction, and a third sealing side surface and a fourth sealing side surface constituting both end surfaces in the second direction, Each side of the exposed surface is inclined with respect to both the first direction and the second direction when viewed from the thickness direction. The semiconductor device according to claim 8.

10. The plurality of recesses are formed in a direction along each side of the exposed surface when viewed in a thickness direction of the semiconductor element. The semiconductor device according to claim 8.

11. The recess is formed in a circular shape when viewed in the thickness direction of the semiconductor element. The semiconductor device according to claim 1 .

12. The depth of the recess is greater than 20 μm and less than or equal to 50 μm. The semiconductor device according to claim 1 .

13. The pattern formed by the plurality of recesses includes a two-dimensional code. The semiconductor device according to claim 2 .

14. a terminal having a main surface facing the same side as the element surface and disposed apart from the semiconductor element when viewed in a thickness direction of the semiconductor element; a wire connecting the element surface and the main surface; Including, The minimum distance between the sealing surface and the wire in the thickness direction is 50 μm or less. The semiconductor device according to claim 4.

15. The terminal is exposed from the rear surface of the sealing member. The semiconductor device according to claim 14.

16. The semiconductor device includes a semiconductor substrate having a substrate front surface and a substrate back surface opposite to the substrate front surface; a semiconductor layer including a functional part is formed on the surface of the substrate; The back surface of the substrate constitutes the exposed surface of the semiconductor element.

7. The semiconductor device according to claim 4 or 6.

17. The semiconductor element is a Hall element. The semiconductor device according to claim 1 .

18. The sealing resin has a sealing surface, A discrimination groove for discriminating the polarity of the semiconductor device is formed on the sealing surface. The semiconductor device according to claim 1 .

19. A support member; a semiconductor element disposed on the support member; a sealing resin for sealing the semiconductor element; Including, the support member includes an exposed surface exposed from the sealing resin, The exposed surface has a plurality of recesses formed therein. Semiconductor device.

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