Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A field plate electrode FP is formed in the inside of a trench TR through an insulation film IF1. The insulation film IF1 is moved backward so that the position of the upper surface of the insulation film IF1 becomes lower than the position of the upper surface of the field plate electrode FP. A buried insulation film EF1 is formed to cover the field plate electrode FP and the insulation film IF1. The buried insulation film EF1 is moved backward so that the position of the upper surface of the buried insulation film EF1 becomes lower than the position of the upper surface of the field plate electrode FP. A gate insulation film GI is formed in the inside of the trench TR by performing a dry oxidation processing, and an insulation film IF2 is formed to cover the field plate electrode FP. A gate electrode is formed on the field plate electrode FP through the insulation film IF2.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode and a field plate electrode inside a trench and a manufacturing method thereof. [Background technology]

[0002] In a semiconductor device equipped with a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure in which a gate electrode is embedded inside a trench is applied. One type of trench gate structure is a split gate structure in which a field plate electrode is formed in the lower part of a trench and a gate electrode is formed in the upper part of the trench. A source potential is supplied to the field plate electrode from a source electrode. By expanding a depletion layer in the drift region by this field plate electrode, it becomes possible to increase the concentration of the drift region and to reduce the resistance of the drift region.

[0003] For example, Patent Document 1 discloses a MOSFET with a split gate structure. In Patent Document 1, a polycrystalline silicon film is formed inside a trench and on a semiconductor substrate, and an anisotropic etching process is performed on the polycrystalline silicon film to remove the polycrystalline silicon film outside the trench, and a field plate electrode is formed inside the trench. After that, an insulating film covering the field plate electrode is formed by a thermal oxidation method, and a gate electrode is formed on the insulating film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-199109 A Summary of the Invention [Problem to be solved by the invention]

[0005] When the field plate electrode is formed, the upper corners of the field plate electrode are easily processed into protruding shapes. Therefore, the electric field is easily concentrated at the protruding parts, and leakage current is easily generated between the gate electrode and the field plate electrode. Also, when the insulating film covering the field plate electrode is formed, the thickness of this insulating film may become locally thin depending on the exposed state of the field plate electrode.

[0006] The present invention relates to a semiconductor device having a gate electrode and a field plate electrode, and is directed to a method of manufacturing the semiconductor device, comprising: [Means for solving the problem]

[0007] A brief outline of a representative embodiment of the present invention will be described below.

[0008] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; (c) after the step (b), forming a first insulating film inside the trench and on the upper surface of the semiconductor substrate; (d) after the step (c), forming a field plate electrode on the first insulating film in the inside of the trench; (e) after the step (d), removing the first insulating film located on the upper surface of the semiconductor substrate and receding the first insulating film located inside the trench toward a bottom of the trench so that a position of an upper surface of the first insulating film located inside the trench is lower than a position of an upper surface of the field plate electrode in a cross-sectional view; (f) after the step (e), removing the field plate electrode and (g) after step (f), removing the buried insulating film located on the top surface of the semiconductor substrate and receding the buried insulating film located inside the trench toward the bottom of the trench so that a position of an upper surface of the buried insulating film located inside the trench is lower than a position of the upper surface of the field plate electrode in a cross-sectional view; (h) after step (g), performing a dry oxidation treatment to form a gate insulating film inside the trench located on the upper surface of the buried insulating film and forming a second insulating film so as to cover the field plate electrode exposed from the buried insulating film by step (g); and (i) after step (h), forming a gate electrode on the field plate electrode via the second insulating film in the inside of the trench.

[0009] A semiconductor device according to one embodiment includes a semiconductor substrate having an upper surface and a lower surface, a trench formed in the semiconductor substrate to a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, a field plate electrode formed inside the trench, a gate electrode formed in the trench above the field plate electrode, and an insulating film formed in the trench to be located between the semiconductor substrate, the field plate electrode, and the gate electrode. An upper corner of the field plate electrode is chamfered or rounded, a part of the gate electrode is also formed as a buried portion between the field plate electrode and the semiconductor substrate, and a thickness of the insulating film formed between the buried portion and the field plate electrode is the thickest between the deepest portion of the buried portion and the field plate electrode. Effect of the Invention

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view showing a semiconductor device in a first embodiment. [Diagram 2] 1 is a plan view showing a main part of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a plan view showing a main part of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Diagram 5] 1 is a cross-sectional view showing a main part of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view showing a main part of a semiconductor device according to a first embodiment. [Figure 7] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] 17 is a cross-sectional view showing a manufacturing process following FIG. 16. [Figure 18] 18 is a cross-sectional view showing a manufacturing process following FIG. 17. [Figure 19] 19 is a cross-sectional view showing a manufacturing process following FIG. 18. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process following FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process following FIG. 21. [Figure 23] 23 is a cross-sectional view showing a manufacturing process following FIG. 22. [Figure 24] 1 is a cross-sectional view showing a main part of a semiconductor device in Study Example 1. FIG. [Diagram 25] 1 is a cross-sectional view showing a main part of a semiconductor device in Study Example 1. FIG. [Figure 26] 11 is a cross-sectional view showing a main part of a semiconductor device in Study Example 2. FIG. [Figure 27] 11 is a cross-sectional view showing a main part of a semiconductor device in Study Example 3. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0013] In addition, the X-direction, Y-direction, and Z-direction described in this application intersect with each other and are perpendicular to each other. In this application, the Z-direction is described as the up-down direction, height direction, or thickness direction of a structure. In addition, expressions such as "plan view" or "planar view" used in this application mean that a surface formed by the X-direction and the Y-direction is a "plane" and this "plane" is viewed from the Z-direction.

[0014] (Embodiment 1) <Structure of Semiconductor Device> A semiconductor device 100 according to a first embodiment will be described below with reference to Figures 1 to 6. The semiconductor device 100 includes a MOSFET with a trench gate structure as a semiconductor element. The MOSFET according to the first embodiment has a split gate structure including a gate electrode GE and a field plate electrode FP.

[0015] The main features of the present application are the shape of the upper part of the field plate electrode FP, the shape of the buried insulating film EF1, and the method of forming the insulating film IF2. These features will be described in detail with reference to Figures 5 and 6 after the explanation of "Semiconductor device structure" and "Semiconductor device manufacturing method".

[0016] FIG. 1 is a plan view of a semiconductor chip which is a semiconductor device 100. FIG. 2 and FIG. 3 are plan views of a main part in which a region 1A shown in FIG. 1 is enlarged. FIG. 3 shows the lower structure of FIG. 2, and mainly shows a trench gate structure formed in a semiconductor substrate SUB. The positions of holes CH1, CH2, and CH3 shown by dashed lines in FIG. 2 coincide with the positions of holes CH1, CH2, and CH3 shown in FIG. 3. FIG. 4 is a cross-sectional view taken along lines AA and BB shown in FIG. 2 and FIG. 3.

[0017] 1 shows a wiring pattern formed mainly above a semiconductor substrate SUB. The semiconductor device 100 has a cell region CR and an outer periphery region OR that surrounds the cell region CR in a plan view. In the cell region CR, main semiconductor elements such as multiple MOSFETs are formed. The outer periphery region OR is used to connect a gate wiring GW to a gate electrode GE and to function as a termination region.

[0018] As shown in FIG. 1 and FIG. 2, most of the cell region CR is covered with the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE. Although not shown here, the source electrode SE and the gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the source electrode SE and the gate wiring GW exposed in the opening become the source pad SP and the gate pad GP. By connecting an external connection member to the source pad SP and the gate pad GP, the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring board, or the like. The external connection member is, for example, a wire made of aluminum, gold, or copper, or a clip made of a copper plate.

[0019] 3, a plurality of trenches TR are formed in the semiconductor substrate SUB in the cell region CR. The plurality of trenches TR are formed in stripes, each extending in the Y direction, and adjacent to each other in the X direction.

[0020] 4, inside the trench TR, a field plate electrode FP is formed in the lower part of the trench TR, and a gate electrode GE is formed in the upper part of the trench TR. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR.

[0021] As shown in the cross section BB of Fig. 4, a part of the field plate electrode FP in the cell region CR forms an extension portion FPa. The field plate electrode FP constituting the extension portion FPa is formed inside the trench TR not only in the lower part of the trench TR but also in the upper part of the trench TR.

[0022] In the cell region CR, a hole CH3 is formed on the lead-out portion FPa. The lead-out portion FPa is electrically connected to the source electrode SE via the hole CH3. In the cell region CR, a hole CH1 is formed on the body region PB and the source region NS, which will be described later. The body region PB and the source region NS are electrically connected to the source electrode SE via the hole CH1. In the outer periphery region OR, a hole CH2 is formed on the gate electrode GE. The gate electrode GE is electrically connected to the gate wiring GW via the hole CH2.

[0023] The cross-sectional structure of the semiconductor device 100 will be described below with reference to FIG.

[0024] As shown in FIG. 4, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the first embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In this case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0025] An n-type drain region ND is formed in the semiconductor substrate SUB so as to extend from a lower surface BS of the semiconductor substrate SUB to a predetermined depth toward an upper surface TS of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film, such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film in which these metal films are appropriately laminated. The drain region ND and the drain electrode DE are formed across the cell region CR and the peripheral region OR. A drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0026] In the semiconductor substrate SUB, a plurality of trenches TR are formed, each of which reaches a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The depth of each trench TR is, for example, not less than 5 μm and not more than 7 μm.

[0027] 4, inside the trench TR, a field plate electrode FP is formed via an insulating film IF1 and a buried insulating film EF1 at the bottom of the trench TR. The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP.

[0028] The buried insulating film EF1 is formed inside the trench TR on the insulating film IF1. The gate insulating film GI is formed inside the trench TR on the buried insulating film EF1. An insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the buried insulating film EF1. A gate electrode GE is formed via the insulating film IF2. The field plate electrode FP and the gate electrode GE are each made of, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. The impurity concentration of this polycrystalline silicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0029] A part of the gate electrode GE is also formed in the space between the field plate electrode FP and the semiconductor substrate SUB, and in the space surrounded by the buried insulating film EF1, the gate insulating film GI, and the insulating film IF2. As will be described later with reference to FIG. 6, such a part of the gate electrode GE is called a buried portion GEa.

[0030] The insulating film IF1 and the buried insulating film EF1 are formed between the semiconductor substrate SUB and the field plate electrode FP. The insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. These films electrically insulate the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP from one another.

[0031] Moreover, the insulating film IF3 is formed on the gate electrode GE, but the insulating film IF3 is mainly used as a protective film for protecting the cell region CR when other semiconductor elements such as resistor elements are formed in a region different from the cell region CR. Therefore, when there is no need to form other semiconductor elements, the insulating film IF3 does not have to be formed.

[0032] The insulating film IF1, the buried insulating film EF1, the insulating film IF2, the insulating film IF3, and the gate insulating film GI are made of, for example, a silicon oxide film. The thickness of each of the insulating film IF1 and the buried insulating film EF1 is thicker than the thickness of each of the insulating film IF2 and the gate insulating film GI, and is, for example, 400 nm or more and 600 nm or less. The thickness of each of the insulating film IF2 and the gate insulating film GI is, for example, 50 nm or more and 70 nm or less. Note that these thicknesses are thicknesses inside the trench TR and in the X direction.

[0033] As shown in FIG. 5, the gate insulating film GI and the insulating film IF2 are stacked films including a silicon oxide film OX1 and a silicon oxide film OX2, respectively.

[0034] A p-type body region PB is formed in the semiconductor substrate SUB, extending from an upper surface TS of the semiconductor substrate SUB toward a lower surface BS of the semiconductor substrate SUB to a predetermined depth. The depth of the body region PB from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR from the upper surface TS of the semiconductor substrate SUB. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0035] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 700 nm or more and 900 nm or less.

[0036] A hole CH1 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL and the source region NS and reaches the body region PB. A high-concentration diffusion region PR is formed in the body region PB at the bottom of the hole CH1. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. The high-concentration diffusion region PR is provided mainly to reduce the contact resistance with the plug PG and to prevent latch-up.

[0037] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR through a hole CH1, and supplies a source potential to these impurity regions.

[0038] 4, a part of the field plate electrode FP forms an extension portion FPa of the field plate electrode FP. The positions of the upper surfaces of the insulating film IF1 and the buried insulating film EF1 in contact with the extension portion FPa are higher than the positions of the upper surfaces of the insulating film IF1 and the buried insulating film EF1 in contact with the field plate electrode FP other than the extension portion FPa.

[0039] An insulating film IF2 is formed so as to cover the drawn-out portion FPa exposed from the buried insulating film EF1. An insulating film IF3 is formed on the buried insulating film EF1, but as described above, the insulating film IF3 does not have to be formed. Also, a body region PB is formed in the semiconductor substrate SUB adjacent to the drawn-out portion FPa, but a source region NS is not formed in this body region PB.

[0040] The interlayer insulating film IL has a hole CH3 formed therein, which penetrates the interlayer insulating film IL, the insulating film IF3, and the insulating film IF2 and reaches the lead-out portion FPa. The source electrode SE is electrically connected to the lead-out portion FPa through the hole CH3 and supplies a source potential to the field plate electrode FP.

[0041] Although not shown here, a hole CH2 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL and the insulating film IF3 and reaches the gate electrode GE. The gate wiring GW is electrically connected to the gate electrode GE through the hole CH2 and supplies a gate potential to the gate electrode GE.

[0042] A plug PG is embedded inside each of the holes CH1, CH2, and CH3. The plug PG is made of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is made of a stacked film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0043] The source electrode SE and the gate wiring GW are made of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten film, and the conductive film is, for example, an aluminum alloy film with copper or silicon added thereto.

[0044] <Method of Manufacturing Semiconductor Device> Each manufacturing process included in the method for manufacturing the semiconductor device 100 will be described below with reference to FIGS.

[0045] 7, first, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by epitaxial growth.

[0046] Next, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. Next, the silicon oxide film is patterned by photolithography and anisotropic etching to form a hard mask HM. Next, anisotropic etching is performed using this hard mask HM to form a trench TR in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by, for example, wet etching using a solution containing hydrofluoric acid.

[0047] 8, an insulating film IF1 is formed inside the trench TR and on the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is, for example, a silicon oxide film formed by thermal oxidation. The thickness of the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB is, for example, 400 nm or more and 600 nm or less. The insulating film IF1 may be a stacked film of a first silicon oxide film formed by thermal oxidation and a second silicon oxide film formed on the first silicon oxide film by a film formation process using a CVD method.

[0048] Next, a conductive film CF1 is formed on the insulating film IF1 by a film formation process using, for example, a CVD method so as to fill the inside of the trench TR. The conductive film CF1 is, for example, an n-type polycrystalline silicon film. The impurity concentration of this polycrystalline silicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV). In order to fill the inside of the trench TR well with the conductive film CF1, the deposition of the conductive film CF1 may be performed in multiple steps, such as deposition of a first polycrystalline silicon film and deposition of a second polycrystalline silicon film.

[0049] Next, as shown in FIG. 9, the conductive film CF1 located outside the trench TR is removed, and the conductive film CF1 remaining inside the trench TR is formed as a field plate electrode FP.

[0050] Specifically, first, the conductive film CF1 formed outside the trench TR is removed by polishing using, for example, a chemical mechanical polishing (CMP) method. Next, the position of the upper surface of the conductive film CF1 inside the trench TR is retreated toward the bottom of the trench TR (arrow in FIG. 9) by performing an anisotropic etching process using, for example, SF6 gas. As a result, the conductive film CF1 remaining inside the trench TR is formed as a field plate electrode FP.

[0051] Next, as shown in FIG. 10, a portion of the field plate electrode FP is selectively removed so that the other portion of the field plate electrode FP is left as an extraction portion FPa.

[0052] Specifically, first, as shown in the BB cross section, a resist pattern RP1 is formed to selectively cover a portion of the field plate electrode FP that will become the lead portion FPa. Next, using the resist pattern RP1 as a mask, an anisotropic etching process using, for example, SF6 gas is performed to remove the other portion of the field plate electrode FP that will not become the lead portion FPa. That is, as shown in the AA cross section of FIG. 10, the position of the upper surface of the field plate electrode FP that will not become the lead portion FPa is selectively recessed toward the bottom of the trench TR (arrow in FIG. 10). The portion of the field plate electrode FP that is not recessed becomes the lead portion FPa. Thereafter, the resist pattern RP1 is removed by ashing.

[0053] 11, an isotropic etching process is performed on the insulating film IF1 to reduce the thickness of the insulating film IF1 and expose the upper part of the field plate electrode FP from the insulating film IF1. At this time, the upper part of the lead portion FPa is also exposed from the insulating film IF1. The isotropic etching process is, for example, a wet etching process using a solution containing hydrofluoric acid. The upper part of the field plate electrode FP and the upper part of the lead portion FPa refer to the portions including the upper surface of the field plate electrode FP and the upper surface of the lead portion FPa.

[0054] At this point, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and inside the trench TR has not been completely removed. Moreover, the upper corners CP of each of the field plate electrode FP and the lead portion FPa exposed from the insulating film IF1 have been processed into protrusions by the anisotropic etching process of FIGS.

[0055] 12, an isotropic etching process is performed on the upper portions of the field plate electrode FP and the lead portion FPa exposed from the insulating film IF1. This isotropic etching process is a chemical dry etching process using CF4 gas. As a result, the corners CP of the upper portions of the field plate electrode FP and the lead portion FPa are chamfered or rounded.

[0056] During this isotropic etching process, the thinned insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and inside the trench TR functions as an etching stopper.

[0057] 13, the insulating film IF1 is subjected to an isotropic etching process using a solution containing hydrofluoric acid. As a result, the insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB (i.e., outside the trench TR) is removed, and the insulating film IF1 located inside the trench TR is recessed toward the bottom of the trench TR so that the position of the upper surface of the insulating film IF1 located inside the trench TR in cross-sectional view is lower than the position of the upper surface of the field plate electrode FP (arrow in FIG. 13).

[0058] At this point, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the drawn-out portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the drawn-out portion FPa.

[0059] 14, a buried insulating film EF1 is formed on the upper surface TS of the semiconductor substrate SUB and inside the trench TR by a film formation process using, for example, a CVD method so as to cover the field plate electrode FP and the insulating film IF1. The buried insulating film EF1 is, for example, an insulating film such as a silicon oxide film. The thickness of the buried insulating film EF1 on the upper surface TS of the semiconductor substrate SUB is, for example, 200 nm or more and 300 nm or less.

[0060] 15, an isotropic etching process is performed on the embedded insulating film EF1 using a solution containing hydrofluoric acid. As a result, the embedded insulating film EF1 located on the upper surface TS of the semiconductor substrate SUB is removed, and the embedded insulating film EF1 located inside the trench TR is retreated toward the bottom of the trench TR so that the position of the upper surface of the embedded insulating film EF1 located inside the trench TR in a cross-sectional view is lower than the position of the upper surface of the field plate electrode FP (arrow in FIG. 15). The isotropic etching process is, for example, a wet etching process using a solution containing hydrofluoric acid.

[0061] Here, the isotropic etching process progresses from a starting point 10 shown in Fig. 14. This starting point 10 is located between (near the middle of) the field plate electrode FP and the semiconductor substrate SUB. More specifically, this starting point 10 is located between the field plate electrode FP and a side portion of the semiconductor substrate SUB that is located next to the field plate electrode FP in the X direction shown in Fig. 14. Therefore, at the end of the isotropic etching process, as shown in Fig. 15, the upper surface of the embedded insulating film EF1 forms a curved shape that rises as it approaches the side portion of the semiconductor substrate SUB and also rises as it approaches the field plate electrode FP.

[0062] Next, as shown in FIG. 16, a gate insulating film GI is formed inside the trench TR located on the buried insulating film EF1, and an insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the buried insulating film EF1.

[0063] 5, the gate insulating film GI and the insulating film IF2 are stacked films including the silicon oxide film OX1 and the silicon oxide film OX2, respectively. The manufacturing process thereof will be described in detail below.

[0064] First, a silicon oxide film OX1 is formed inside the trench TR on the buried insulating film EF1, and the silicon oxide film OX1 is also formed so as to cover the field plate electrode FP exposed from the buried insulating film EF1. The silicon oxide film OX1 is formed by a dry oxidation process, which is a type of thermal oxidation process. In other words, it is not a wet oxidation process, which is also a type of thermal oxidation process. The dry oxidation process is performed using oxygen gas under conditions of, for example, 1000° C. or more and 1200° C. or less. The thickness of the silicon oxide film OX1 is, for example, 25 nm or more and 35 nm or less.

[0065] Next, a silicon oxide film OX2 is formed on the silicon oxide film OX1 by a film formation process using a CVD method. The silicon oxide film OX2 is a TEOS (Tetra Ethoxy Silane) film and has a thickness of, for example, 25 nm or more and 35 nm or less. Thereafter, a heat treatment may be performed to densify the film quality of the silicon oxide film OX2. Such a heat treatment is performed in a nitrogen gas atmosphere or an oxygen gas atmosphere at a temperature of, for example, 900° C. or more and 1000° C. or less. The silicon oxide film OX2 is also formed on the buried insulating film EF1.

[0066] Moreover, the insulating film in contact with the field plate electrode FP and the semiconductor substrate SUB is preferably a silicon oxide film OX1 rather than a silicon oxide film OX2. The silicon oxide film OX1 formed by dry oxidation processing can improve the interface state between the gate insulating film GI and the semiconductor substrate SUB, and the interface state between the insulating film IF2 and the field plate electrode FP, more than the silicon oxide film OX2 formed by a film formation processing using a CVD method.

[0067] 17, a conductive film CF2 is formed on the gate insulating film GI, the insulating film IF2, and the buried insulating film EF1 by a film formation process using, for example, a CVD method so as to fill the inside of the trench TR. The conductive film CF2 is, for example, an n-type polycrystalline silicon film. The impurity concentration of this polycrystalline silicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0068] Next, as shown in Fig. 18, the conductive film CF2 is polished using the CMP method. This reduces the thickness of the conductive film CF2, and the upper surface of the conductive film CF2 is flattened. Next, the conductive film CF2 is anisotropically etched to remove the conductive film CF2 located outside the trench TR. As a result, the conductive film CF2 remaining inside the trench TR on the field plate electrode FP is formed as the gate electrode GE.

[0069] In order to completely remove the conductive film CF2 outside the trench TR, the anisotropic etching process is performed by over-etching. Therefore, as shown in the AA cross section of Fig. 18, the position of the upper surface of the gate electrode GE becomes lower than the position of the upper surface TS of the semiconductor substrate SUB. In addition, the conductive film CF2 formed on the embedded insulating film EF1 and the insulating film IF2 in contact with the lead-out portion FPa is removed by this anisotropic etching process.

[0070] Next, as shown in FIG. 19, an insulating film IF3 is formed on the gate insulating film GI, the gate electrode GE, the insulating film IF2, and the buried insulating film EF1 by a film formation process using, for example, a CVD method so as to cover the trench TR.

[0071] 20, an anisotropic etching process is performed on the insulating film IF3. As a result, the insulating film IF3 and the gate insulating film GI on the upper surface TS of the semiconductor substrate SUB are removed. Moreover, as shown in the AA cross section, the insulating film IF3 is left on the gate electrode GE so as to be in contact with the gate insulating film GI. Moreover, as shown in the BB cross section, the insulating film IF3 is left on the insulating film IF2 and the buried insulating film EF1 so as to be in contact with the gate insulating film GI.

[0072] 21, a p-type body region PB is selectively formed in the semiconductor substrate SUB by introducing, for example, boron (B) using photolithography and ion implantation. The body region PB is formed so that its depth from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR.

[0073] Next, by introducing, for example, arsenic (As) using photolithography and ion implantation, an n-type source region NS is selectively formed in the body region PB of the cell region CR as shown in the AA cross section. Note that, as shown in the BB cross section, the source region NS is not formed in the body region PB adjacent to the lead-out portion FPa. Thereafter, the semiconductor substrate SUB is subjected to a heat treatment to diffuse the impurities contained in the source region NS and the body region PB.

[0074] Next, as shown in FIG. 22, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR.

[0075] Then, holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. Specifically, first, a resist pattern having a pattern that opens the semiconductor substrate SUB in which the source region NS is formed is formed on the interlayer insulating film IL. Next, anisotropic etching is performed using the resist pattern as a mask to form a hole CH1 that penetrates the interlayer insulating film IL and the source region NS and reaches the inside of the body region PB. Next, for example, boron (B) is introduced by ion implantation into the body region PB at the bottom of the hole CH1 to form a p-type high concentration diffusion region PR. After that, the resist pattern is removed by ashing.

[0076] Next, a resist pattern having a pattern that opens above the lead-out portion FPa and above the gate electrode GE is formed on the interlayer insulating film IL. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a hole CH3 that penetrates the interlayer insulating film IL, the insulating film IF3, and the insulating film IF2 and reaches the lead-out portion FPa. Although not shown here, in the process of forming the hole CH3, a hole CH2 that penetrates the interlayer insulating film IL and the insulating film IF3 and reaches the gate electrode GE is also formed. After that, the resist pattern is removed by an ashing process.

[0077] It should be noted that the order in which the hole CH1 is formed and the order in which the hole CH2 and the hole CH3 are formed may not matter.

[0078] Next, as shown in FIG. 23, plugs PG are formed inside each of the holes CH1, CH2, and CH3, and a source electrode SE and a gate wiring GW are formed on the interlayer insulating film IL.

[0079] Specifically, first, a first barrier metal film is formed inside the holes CH1, CH2, and CH3 and on the interlayer insulating film IL by a film formation process using a sputtering method or a CVD method. The first barrier metal film is made of, for example, a stacked film of a titanium nitride film and a titanium film. Next, a first conductive film is formed on the first barrier metal film by a film formation process using a CVD method. The first conductive film is made of, for example, a tungsten film. Next, the first barrier metal film and the first conductive film formed outside the holes CH1, CH2, and CH3 are removed by a CMP method or anisotropic etching process. As a result, a plug PG made of the first barrier metal film and the first conductive film is formed so as to fill the inside of the holes CH1, CH2, and CH3.

[0080] Next, a second barrier metal film is formed on the interlayer insulating film IL by a sputtering method. The second barrier metal film is, for example, a titanium tungsten film. Next, a second conductive film is formed on the second barrier metal film by a sputtering method. The second conductive film is, for example, an aluminum alloy film to which copper or silicon is added. Next, the second barrier metal film and the second conductive film are patterned to form a source electrode SE and a gate wiring GW.

[0081] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. Openings are formed in parts of the protective film to expose the areas of the source electrode SE and the gate wiring GW that will become the source pad SP and the gate pad GP.

[0082] Thereafter, the structure shown in FIG. 4 is obtained through the following manufacturing steps. First, the lower surface BS of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface BS of the semiconductor substrate SUB by ion implantation. Note that if the semiconductor substrate SUB is composed of a laminate of an n-type silicon substrate and an n-type semiconductor layer, the high-concentration n-type silicon substrate forms the drain region ND, so that the formation of the drain region ND by the above-mentioned ion implantation can be omitted. Next, a drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB by sputtering.

[0083] <Main features of the first embodiment> 5, 24, 25, 26, and 27, the semiconductor devices of Study Examples 1, 2, and 3 studied by the present inventors and the main features of the embodiment 1 will be described below. Figures 5, 24, 25, 26, and 27 are enlarged cross-sectional views of the essential part of the inside of the trench TR corresponding to the cross section AA in Figure 4.

[0084] In the study example 1, as shown in Fig. 24, an insulating film IF1 and a field plate electrode FP are formed inside the trench TR. Next, as shown in Fig. 25, the insulating film IF1 inside the trench TR is retreated by one isotropic etching process. Here, the isotropic etching process proceeds from the starting point 11 shown in Fig. 24. Next, a dry oxidation process is performed to form a gate insulating film GI and an insulating film IF2 made of a silicon oxide film OX1.

[0085] In the study example 1, unlike the embodiment 1, the chemical dry etching process of FIG. 12 is not performed. Therefore, the upper corner of the field plate electrode FP is left processed into a protruding shape. Therefore, the electric field tends to concentrate at the protruding portion 20 shown in FIG. 25, and the insulation resistance between the gate electrode GE and the field plate electrode FP deteriorates, and a leakage current tends to occur.

[0086] In contrast, in the first embodiment, the chemical dry etching process of FIG. 12 is applied. Therefore, as shown in FIG. 5, the corners of the upper part of the field plate electrode FP are chamfered or rounded. Therefore, the area where the electric field concentration occurs between the gate electrode GE and the field plate electrode FP is made uniform. In other words, the electric field concentration is mitigated, and the occurrence of the above-mentioned leakage current is suppressed. Therefore, the reliability of the semiconductor device 100 can be improved.

[0087] In addition, in the study example 1, the isotropic etching process proceeds from the starting point 11 shown in FIG. 24. Therefore, as shown in FIG. 25, the position of the portion of the upper surface of the insulating film IF1 located inside the trench TR that contacts the field plate electrode FP is set back lower than the position of the portion that contacts the side of the semiconductor substrate SUB. That is, the position of the portion that contacts the field plate electrode FP is set back toward the bottom of the trench TR. If the insulating film IF2 is formed by performing a dry oxidation process in this state, oxygen gas is unlikely to reach the insulating film IF2, and the thickness of the insulating film IF2 near the insulating film IF1 is likely to become locally thin. Therefore, it is difficult to ensure the insulation resistance between the gate electrode GE and the field plate electrode FP. In FIG. 25, such a portion is shown as a thin-film portion 30.

[0088] In the second study example, in order to ensure the thickness of the thin film portion 30, a silicon oxide film OX3 formed by wet oxidation is applied as shown in Fig. 26. The wet oxidation is a thermal oxidation process performed using water vapor under conditions of, for example, 850°C or more and 950°C or less.

[0089] Since the impurity concentration of the polycrystalline silicon film constituting the field plate electrode FP is higher than that of the semiconductor substrate SUB (drift region NV), when wet oxidation is performed, the thickness of the insulating film IF2 is likely to be formed thicker than that of the gate insulating film GI due to the effect of accelerated oxidation. Also, the thickness of the insulating film IF2 is likely to be secured even in the vicinity of the insulating film IF1.

[0090] On the other hand, the wet oxidation process tends to roughen the oxidized surface of the field plate electrode FP. Therefore, the thickness of the insulating film IF2 tends to be locally thin, and electric field concentration tends to occur at the localized locations. In addition, it is difficult to alleviate the electric field concentration at the protruding locations of the field plate electrode FP.

[0091] In contrast, in the dry oxidation process, the effect of accelerated oxidation is small compared to the wet oxidation process, but the roughness of the oxidized surface of the field plate electrode FP is improved. Therefore, a means is required to ensure the insulation resistance in the thin film portion 30 even when the dry oxidation process is applied.

[0092] For this reason, in the first embodiment, the embedded insulating film EF1 is formed in Fig. 14, and the embedded insulating film EF1 is retreated by an isotropic etching process in Fig. 15. As a result, as shown in Fig. 5, the upper surface of the embedded insulating film EF1 rises as it approaches the semiconductor substrate SUB, and also forms a curved shape that rises as it approaches the field plate electrode FP.

[0093] Therefore, even if the thickness of the silicon oxide film OX1 formed by the dry oxidation process is thin in the vicinity of the embedded insulating film EF1, the thickness can be compensated for by the embedded insulating film EF1. Therefore, the insulation resistance can be secured in the thin-film portion 30, and the reliability of the semiconductor device 100 can be improved.

[0094] In addition, the presence of the buried insulating film EF1 reduces the exposed area of ​​the field plate electrode FP during dry oxidation processing, which has the effect of shortening the time required to form the silicon oxide film OX1 of a given thickness. As a result, the manufacturing process can be shortened.

[0095] In the first embodiment, the stacked film of the silicon oxide film OX1 and the silicon oxide film OX2 is applied to the gate insulating film GI and the insulating film IF2, but the silicon oxide film OX2 is provided mainly to adjust the thickness of the gate insulating film GI and the insulating film IF2. The silicon oxide film OX2 formed by the film formation process using the CVD method is more likely to be formed to a uniform thickness than the silicon oxide film formed by the wet oxidation process. Therefore, it is difficult for locally thin portions to occur, and it is easy to suppress the occurrence of electric field concentration.

[0096] Since the silicon oxide film OX2 is easily formed to a uniform thickness, even if the silicon oxide film OX2 is formed on the silicon oxide film OX1 in the study example 1 of Fig. 25, the thin-film portion 30 still remains a locally thin portion. Therefore, it is necessary to compensate for the thickness by the buried insulating film EF1 as in the first embodiment.

[0097] Furthermore, the number of silicon oxide films stacked on the silicon oxide film OX1 by a film formation process using the CVD method is not limited to one silicon oxide film OX2, and may be multiple.

[0098] Incidentally, it is preferable to form the embedded insulating film EF1 after the field plate electrode FP is subjected to a chemical dry etching process. For example, as shown in the study example 3 of Fig. 27, when the upper corners of the field plate electrode FP are processed into a protruding shape, the aspect ratio is high. Therefore, when the embedded insulating film EF1 is formed by a film formation process using a CVD method, there is a risk that a gap 40 will be generated in the embedded insulating film EF1.

[0099] If such a void 40 exists, there is a risk that an etching solution will penetrate into the void 40 when the embedded insulating film EF1 is recessed by the isotropic etching process of Fig. 15. This may accelerate the etching of the embedded insulating film EF1 in the void 40, making the embedded insulating film EF1 extremely thin, or may result in the embedded insulating film EF1 being removed almost entirely. In any case, there is a high possibility that the embedded insulating film EF1 cannot be formed in the desired shape.

[0100] If the upper corners CP of the field plate electrode FP are chamfered or rounded as in the first embodiment, the aspect ratio is reduced, improving the embedding ability of the embedded insulating film EF1 and making it possible to suppress the occurrence of voids 40.

[0101] Fig. 6 is a cross-sectional view of a main part showing that the semiconductor device 100 of the first embodiment does not have a portion such as the thin film portion 30 in Fig. 25 and has improved insulation resistance. In Fig. 6, the boundaries between the insulating film IF1, the insulating film IF2, the gate insulating film GI, and the buried insulating film EF1 are not shown. When these insulating films are the same type of film such as a silicon oxide film, these insulating films can be regarded as one integrated insulating film IF inside the trench TR.

[0102] That is, the integrated insulating film IF is formed inside the trench TR so as to be located between each of the semiconductor substrate SUB, the field plate electrode FP, and the gate electrode GE. The integrated insulating film IF electrically insulates the semiconductor substrate SUB, the field plate electrode FP, and the gate electrode GE from each other.

[0103] Incidentally, a part of the gate electrode GE is also formed as a buried portion GEa between the field plate electrode FP and the semiconductor substrate SUB.

[0104] As described above, one of the main features of the first embodiment is that the upper surface of the embedded insulating film EF1 is curved and rises toward the field plate electrode FP. Therefore, even if the thickness of the insulating film IF2 is thin near the embedded insulating film EF1, the thickness can be compensated for by the embedded insulating film EF1.

[0105] 6, the thickness T1 of the integrated insulating film IF formed between the buried portion GEa and the field plate electrode FP is the thickest between the deepest part of the buried portion GEa and the field plate electrode FP. For example, the thickness T2 of the integrated insulating film IF at a depth near the middle between the top of the field plate electrode FP and the deepest part of the buried portion GEa is thinner than the thickness T1.

[0106] Moreover, the upper surface of the embedded insulating film EF1 rises as it approaches the side of the semiconductor substrate SUB. The thickness T3 of the integrated insulating film IF formed between the embedded portion GEa and the side of the semiconductor substrate SUB is the thickest between the deepest part of the embedded portion GEa and the semiconductor substrate SUB. For example, the thickness T4 of the integrated insulating film IF at a depth near the middle between the top of the field plate electrode FP and the deepest part of the embedded portion GEa is thinner than the thickness T3.

[0107] Since the integral insulating film IF is formed in this manner, it is possible to ensure not only the dielectric strength between the semiconductor substrate SUB and the gate electrode GE, but also the dielectric strength between the field plate electrode FP and the gate electrode GE.

[0108] Although the present invention has been specifically described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0109] For example, in the above-described first embodiment, it has been described that, after the field plate electrode FP is formed as shown in Fig. 9, and before the insulating film IF1 is isotropically etched as shown in Fig. 13, the upper portions of the field plate electrode FP and the lead portion FPa exposed from the insulating film IF1 are isotropically etched as shown in Fig. 12. However, the isotropic etching performed on the upper portions of the field plate electrode FP and the lead portion FPa shown in Fig. 12 may be omitted. However, in order to more reliably suppress the occurrence of the above-described void 40, it is preferable to perform the isotropic etching on the upper portions of the field plate electrode FP and the lead portion FPa after the field plate electrode FP is formed and before the insulating film IF1 is isotropically etched as in the above-described first embodiment. [Explanation of symbols]

[0110] 100 Semiconductor device 10, 11 Starting point of isotropic etching process 20 Protrusions 30 Thin Film Areas 40 void 1A area BS Bottom surface of semiconductor substrate CF1, CF2 conductive film CH1, CH2, CH3 holes CP Field plate electrode corner CR Cell Area DE Drain electrode EF1 Buried insulating film FP field plate electrode FPa drawer GE gate electrode GEa embedded part GI Gate Insulator GP Gate Pad GW Gate wiring HM Hard Mask IF Integrated Insulator IF1, IF2, IF3 insulating film IL Interlayer insulating film ND drain region NS source region NV drift region OR outer area OX1, OX2, OX3 Silicon oxide film PB Body Region PG plug PR high concentration diffusion region RP1 Resist pattern SP Source Pad SUB Semiconductor Substrate SE source electrode TR Trench TS Top surface of semiconductor substrate

Claims

1. (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; (c) after the step (b), forming a first insulating film inside the trench and on the top surface of the semiconductor substrate; (d) after the step (c), forming a field plate electrode on the first insulating film in the interior of the trench; (e) after the step (d), removing the first insulating film located on the upper surface of the semiconductor substrate, and recessing the first insulating film located inside the trench toward a bottom of the trench so that a position of an upper surface of the first insulating film located inside the trench is lower than a position of an upper surface of the field plate electrode in a cross-sectional view; (f) after the step (e), forming a buried insulating film on the top surface of the semiconductor substrate and within the trench so as to cover the field plate electrode and the first insulating film; (g) after the step (f), removing the embedded insulating film located on the upper surface of the semiconductor substrate, and recessing the embedded insulating film located inside the trench toward the bottom of the trench so that a position of an upper surface of the embedded insulating film located inside the trench is lower than a position of the upper surface of the field plate electrode in a cross-sectional view; (h) after the step (g), performing a dry oxidation process to form a gate insulating film in the interior of the trench located on the upper surface of the buried insulating film, and forming a second insulating film so as to cover the field plate electrode exposed from the buried insulating film by the step (g); (i) after the step (h), forming a gate electrode on the field plate electrode in the inside of the trench via the second insulating film; A manufacturing method of a semiconductor device comprising:

2. 2. The method of manufacturing a semiconductor device according to claim 1, The step (f) is carried out by a film formation process using a CVD method, The method for manufacturing a semiconductor device, wherein the step (g) is performed by an isotropic etching process.

3. 3. The method of manufacturing a semiconductor device according to claim 2, the buried insulating film is a silicon oxide film, The method for manufacturing a semiconductor device, wherein the isotropic etching treatment in the step (g) is performed using a solution containing hydrofluoric acid.

4. 3. The method of manufacturing a semiconductor device according to claim 2, a top surface of the buried insulating film having a curved shape that rises as it approaches the semiconductor substrate and also rises as it approaches the field plate electrode after the step (g).

5. 2. The method of manufacturing a semiconductor device according to claim 1, The step (h) comprises: (h1) forming a first silicon oxide film in the interior of the trench located on the upper surface of the buried insulating film by the dry oxidation treatment performed using oxygen gas under conditions of 1000° C. or more and 1200° C. or less, and forming the first silicon oxide film so as to cover the field plate electrode exposed from the buried insulating film by the (g) step; (h2) after the step (h1), forming a second silicon oxide film on the first silicon oxide film by a film formation process using a CVD method; having the gate insulating film and the second insulating film include the first silicon oxide film and the second silicon oxide film, respectively.

6. 2. The method of manufacturing a semiconductor device according to claim 1, (j) between the steps (d) and (e), a step of reducing a thickness of the first insulating film and exposing an upper portion of the field plate electrode from the first insulating film; (k) performing an isotropic etching process on the upper portion of the field plate electrode exposed from the first insulating film between the step (j) and the step (e); The method for manufacturing a semiconductor device further comprises:

7. 7. The method of manufacturing a semiconductor device according to claim 6, The step (d) comprises: (d1) forming a first conductive film on the first insulating film so as to fill the inside of the trench; (d2) removing the first conductive film formed outside the trench after the step (d1); (d3) after the step (d2), a step of recessing a position of an upper surface of the first conductive film in the interior of the trench by an anisotropic etching process, thereby forming the first conductive film remaining in the interior of the trench as the field plate electrode; The method for manufacturing a semiconductor device comprising the steps of:

8. 8. The method of manufacturing a semiconductor device according to claim 7, the field plate electrode is made of a polycrystalline silicon film, The isotropic etching process in the step (k) is performed using CF ４ A method for manufacturing a semiconductor device, the method being a chemical dry etching process using a gas.

9. 9. The method for manufacturing a semiconductor device according to claim 8, the upper corners of the field plate electrode are chamfered or rounded by the chemical dry etching process.

10. 8. The method of manufacturing a semiconductor device according to claim 7, the first insulating film is made of a silicon oxide film, The method for manufacturing a semiconductor device, wherein the step (j) and the step (e) are each performed by an isotropic etching process using a solution containing hydrofluoric acid.

11. a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a trench formed in the semiconductor substrate to a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; a field plate electrode formed inside the trench; a gate electrode formed in the interior of the trench above the field plate electrode; an insulating film formed inside the trench so as to be located between the semiconductor substrate, the field plate electrode, and the gate electrode; Equipped with The corners of the top of the field plate electrode are chamfered or rounded; a portion of the gate electrode is also formed as a buried portion between the field plate electrode and the semiconductor substrate; a thickness of the insulating film formed between the buried portion and the field plate electrode being greatest between a deepest portion of the buried portion and the field plate electrode.

12. 12. The semiconductor device according to claim 11, a thickness of the insulating film formed between the buried portion and the semiconductor substrate being greatest between the deepest portion of the buried portion and the semiconductor substrate;

13. 13. The semiconductor device according to claim 12, The semiconductor device, wherein the insulating film is a silicon oxide film.

14. 13. The semiconductor device according to claim 12, a body region of a second conductivity type opposite to the first conductivity type, the body region being formed in the semiconductor substrate such that a depth from the upper surface of the semiconductor substrate is shallower than a depth of the trench; a source region of the first conductivity type formed in the body region; a drain region of the first conductivity type formed in the semiconductor substrate so as to reach a predetermined depth from the lower surface of the semiconductor substrate toward the upper surface of the semiconductor substrate; Further comprising: A gate potential is supplied to the gate electrode, a source potential is supplied to the field plate electrode, the body region, and the source region; A drain potential is supplied to the semiconductor substrate and the drain region.

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