Methods and apparatus for facilitating alignment of optical components

Abstract

To provide systems, apparatus, articles of manufacture, and methods for facilitating alignment of optical components.SOLUTION: An example apparatus includes programmable circuitry to at least either instantiate or execute machine-readable instructions to monitor optical power outputs of different cores in a linear array of cores in a multi-core optical fiber as a lens is moved relative to the multi-core optical fiber. The optical power outputs are based on light that is emitted from a photonic integrated circuit and passes through the lens. The programmable circuitry is configured to determine a final position of the lens relative to the photonic integrated circuit based on the optical power outputs.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates generally to optical devices, and more particularly to methods and apparatus for facilitating alignment of optical components. [Background technology]

[0002] Integrated circuit (IC) chips and / or semiconductor dies are often connected via a package substrate to a larger circuit board, such as a motherboard and other types of printed circuit boards (PCBs). As technology advances, IC chips have seen increasing density of interconnects. Recently, IC chips have been implemented with optical components that allow for the transmission of information via light. Such IC chips are sometimes referred to as photonic integrated circuits (PICs). PICs often include a light source (such as a laser) to emit light, and optical elements (such as lenses) to direct or focus the light into a waveguide (such as an optical fiber) that carries the light to a different location. The quality and / or reliability of the signal transmission depends on the alignment of the laser, lens, and optical fiber. [Brief description of the drawings]

[0003] [Figure 1] 1 illustrates an exemplary optical alignment system for facilitating alignment of an optical component to a light source (e.g., a laser) on a photonic integrated circuit (PIC).

[0004] [Diagram 2] 2 is a cross-sectional view of an exemplary multi-core optical fiber of the exemplary optical alignment system of FIG. 1.

[0005] [Diagram 3] 1 is a cross-sectional view of another exemplary multi-core optical fiber. [Figure 4] 1 is a cross-sectional view of another exemplary multi-core optical fiber.

[0006] [Diagram 5]3 is a graph illustrating the relationship between core position in the example multicore fiber of FIG. 1 and / or FIG. 2, the peak power output detected through each of the cores, and the lens position associated with the detected peak power output. [Figure 6] 3 is a graph illustrating the relationship between core position in the example multicore fiber of FIG. 1 and / or FIG. 2, the peak power output detected through each of the cores, and the lens position associated with the detected peak power output. [Figure 7] 3 is a graph illustrating the relationship between core position in the example multicore fiber of FIG. 1 and / or FIG. 2, the peak power output detected through each of the cores, and the lens position associated with the detected peak power output.

[0007] [Figure 8] 2 is a block diagram of an example implementation of the example alignment controller circuitry of FIG. 1.

[0008] [Figure 9] 9 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the alignment controller circuitry 118 of FIG. 8. [Figure 10] 9 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the alignment controller circuitry 118 of FIG. 8. [Figure 11] 9 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the alignment controller circuitry 118 of FIG. 8. [Figure 12]9 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the alignment controller circuitry 118 of FIG. 8. [Figure 13] 9 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the alignment controller circuitry 118 of FIG. 8.

[0009] [Figure 14] FIG. 14 is a block diagram of an exemplary processing platform including programmable circuitry having a structure to execute, instantiate, and / or perform exemplary machine-readable instructions to implement the alignment controller circuitry 118 of FIG. 8 and / or perform the exemplary operations of FIGS. 9-13.

[0010] [Figure 15] FIG. 15 is a block diagram of an example implementation of the programmable circuitry of FIG. 14.

[0011] [Figure 16] FIG. 15 is a block diagram of another exemplary implementation of the programmable circuitry of FIG.

[0012] Generally, the same reference numbers are used throughout the drawings and the accompanying written description to refer to the same or like parts. The drawings are not necessarily to scale.

[0013] As used herein, unless otherwise specified, the term "above" describes the relationship of two portions to the Earth. A first portion is above a second portion if the second portion has at least one portion between the Earth and the first portion. Similarly, as used herein, a first portion is "below" a second portion if the first portion is closer to the Earth than the second portion. As described above, the first portion may be above or below the second portion, with one or more of: with other portions therebetween, with no other portions therebetween, with the first and second portions being in contact, or without the first and second portions being in direct contact with each other.

[0014] As used in this patent, a description of any part (e.g., a layer, film, area, region, or plate) being on (e.g., positioned on, located on, disposed on, or formed on) another part in any manner indicates that the referenced part is either in contact with the other part, or that the referenced part is on the other part with one or more intermediate parts disposed therebetween.

[0015] As used herein, unless otherwise specified, connection references (e.g., attached, coupled, connected, and coupled) may include intermediate members between the elements referenced by the connection reference and / or relative movement between those elements. As such, a connection reference does not necessarily imply that the two elements are directly connected and / or in fixed relationship to one another. As used herein, the phrase that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0016] Unless otherwise stated, descriptors such as "first," "second," "third," and the like are used herein without negatively or otherwise implying any sense of priority, physical order, placement within a list, and / or ordering in any way, but are merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some instances, the descriptor "first" may be used to refer to an element in the detailed description, but the same element may be referred to in the claims using a different descriptor such as "second" or "third." In such instances, it should be understood that such descriptors are merely used to separately identify those elements within the context of the description (e.g., in the claims) (wherein the elements may otherwise share the same name, for example).

[0017] As used herein, "approximately" and "about" modify their objects / values ​​to recognize the existence of potential variations that occur in real-world applications. For example, "approximately" and "about" may modify a dimension that may not be exact due to manufacturing tolerances and / or other real-world imperfections, as would be understood by one of ordinary skill in the art. For example, "approximately" and "about" may indicate that such a dimension may be within a tolerance range of ±10%, unless otherwise specified in the description below.

[0018] As used herein, "substantially real-time" refers to occurring nearly instantaneously, but it is recognized that there may be real-world delays due to computing time, transmission, etc. Thus, unless otherwise specified, "substantially real-time" refers to real-time plus one second.

[0019] As used herein, the phrase "communicate" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components and does not require direct physical (e.g., wired) communication and / or constant communication, and additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.

[0020] As used herein, "programmable circuitry" is defined to include (i) one or more special purpose electrical circuits (e.g., application specific circuits (ASICs)) having a structure to perform a particular operation and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general purpose semiconductor-based electrical circuits that are programmable with instructions to perform a particular function and / or operation and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors, such as a central processor unit (CPU) that can execute first instructions to perform one or more operations and / or functions; a field programmable gate array (FPGA) that can be programmed with second instructions to instantiate one or more operations and / or functions corresponding to the first instructions into the configuration and / or structure of the FPGA; a graphics processor unit (GPU) that can execute the first instructions to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) that can execute the first instructions to perform one or more operations and / or functions; one or more microcontrollers that can execute the first instructions to perform one or more operations and / or functions; and / or integrated circuits, such as application specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and an orchestration technique (e.g., an application programming interface (API) that can allocate a computing task to any one of multiple types of programmable circuitry that is suitable and available to perform the computing task).

[0021] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages that include one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate combining multiple circuit elements, a system on a chip (SoC), etc. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Many photonic integrated circuits (PICs) include one or more light sources (e.g., optical transmitters, lasers) that emit light that serves as a transmission signal that is communicated to one or more other optical devices. In many cases, the light emitted by the PIC is directed to a fiber array unit (FAU) that includes one or more optical fibers or waveguides that carry or propagate the emitted light to a corresponding optical receiver associated with the other optical device. The quality or strength (e.g., power) of the optical signal transmitted along the optical fiber depends on the alignment of the laser (e.g., light source) on the PIC and the lenses (e.g., microlenses and / or other similar optical elements) that are located in the path of the light to focus the light into the optical fiber. The quality or strength of the optical signal also depends on the alignment of the optical fiber with the laser and the intervening lens. Thus, to enhance (e.g., optimize or maximize) the optical coupling of the laser with the optical fiber, both the lens and the optical fiber need to be aligned with each other and with the laser. A typical procedure for aligning these three components involves moving both the lens and the optical fiber in all three XYZ directions and comparing the power of the optical signal through the fiber at various positions to determine the optimal position for both the lens and the fiber (e.g., the position where the power of the optical signal is highest). Moving both the lens and the fiber relative to the laser and relative to each other to find the optimal position for both elements can take a significant amount of time, thereby adding to the cost of producing the optical device.

[0023] More specifically, the optical alignment of the lens and optical fiber with the laser is a multi-step process in which a calibration position for a reference fiber block is first determined through a reference fiber block calibration process (or simply, "fiber calibration process" for short). The reference fiber block is a separate optical fiber that is distinct from the final optical fiber used in the optical device including the PIC (with the laser and attached lens). That is, the reference fiber block is distinct from the FAU optically coupled to the PIC in the final product. Rather, as the name suggests, the reference fiber block is an optical fiber used as a reference to facilitate the alignment of the lens with the laser of the PIC. However, as described above, before the lens alignment can be completed, a fiber calibration process is performed to determine a calibration position for the reference fiber block. Existing fiber calibration process techniques involve the movement of both the lens and the reference fiber block relative to each other and relative to the laser of the PIC. The optical power of the signal passing through the reference fiber block is monitored and recorded for various positions to identify the position where the optical power is highest. This process may be repeated multiple times with different samples / instances of the PIC and different samples / instances of the lens. The calibration position for the reference fiber block may then be determined as the average of the positions associated with the peak power detected associated with each sample.

[0024] The calibration positions determined from the fiber calibration process define the appropriate (e.g., optimal) positions of the reference fiber block in all three XYZ directions relative to the laser (e.g., and / or relative to one or more fiducial markers on the PIC that includes the laser). Thus, the calibration positions defined along the three XYZ directions include a depth position (distance position) along the longitudinal / depth axis (which generally extends away from the laser in the direction of the light path), a lateral / horizontal position along the lateral / horizontal axis (which generally extends perpendicular to the longitudinal / depth axis), and a vertical position along the vertical axis (which generally extends perpendicular to both the longitudinal / depth axis and the lateral / horizontal axis). The terms used to distinguish the different axes (e.g., lateral, horizontal, vertical, etc.) used in this context are for convenience of explanation and are not intended to be fixed to any particular orientation in the real world independent of the laser. That is, as used herein, the longitudinal axis generally points away from the laser in the direction of the light path emitted therefrom, regardless of the direction of the light path relative to the surrounding real-world environment. Similarly, as used herein, the lateral / horizontal and vertical axes are perpendicular or orthogonal to the longitudinal axis and to each other, regardless of their orientation relative to the surrounding real-world environment.

[0025] As described above for known calibration techniques, averaging multiple samples during the fiber calibration process allows for a relatively accurate determination of an optimal position for the reference fiber block along the longitudinal or depth axis, which corresponds to the distance from the laser, since the distance is not affected by sample-to-sample variations. However, averaging different samples does not necessarily result in a suitable (e.g., optimal) position for the reference fiber block along the transverse / horizontal and vertical axes, since sample-to-sample variations may have a relatively large effect along these axes. For example, sample-to-sample variations may result from (i) differences in beam pitch angles for edge-emitting lasers based on how the laser die (e.g., PIC) was cut or etched, (ii) differences in parallelism of the substrate, (iii) differences in optical properties of the laser and / or lenses, (iv) differences in the output of the machine vision system used in positioning the components of the different samples, etc. Thus, even if we assume that the average position between the tested samples is acceptable for those samples, there is no guarantee that the average will be suitable for a subsequent unit of the optical device that requires optical alignment.

[0026] After the fiber calibration process is completed, a lens alignment process is implemented to determine a final position for the lens relative to the laser. The lens alignment process assumes that the FAU optically coupled to the laser is at a fixed XYZ position (relative to the laser) that corresponds to the calibration position of the reference fiber block. Thus, by fixing the reference fiber block at a fixed position (the calibration position determined during the fiber calibration process), the reference fiber block does not need to be moved during the lens alignment process. Instead, only the lens is moved or scanned relative to the laser and the reference fiber block until a final lens position is determined based on the highest power (e.g., peak power) detected through the reference fiber block for the various positions tested for the lens. Once the final lens position is determined, the lens is attached to the PIC at that position. At this point, the PIC (with the lens attached) can be removed from the reference fiber block and then further processed to align the final optical fiber (e.g., FAU) with the laser and associated (attached) lens.

[0027] In some cases, the same reference fiber block is used repeatedly in the lens alignment process at the same calibration position (e.g., fixed XYZ position) for different lenses associated with different instances of the PIC (e.g., different production units). Thus, once the calibration position for the reference fiber block is determined, only the lens needs to be moved to identify the final position associated with the peak power detected for the optical signal passing through the reference fiber block. However, as explained above, this can be problematic because the calibration position for the reference fiber block may not correspond to the optimal position for the optical fiber due to differences in subsequent units of the PIC and lens relative to the previously aligned PIC and lens.

[0028] Existing reference fiber blocks are implemented using a single unitary optical fiber that includes a single core that defines a single path, waveguide, or channel through which light may propagate. Examples disclosed herein involve reference fiber blocks that are implemented using a multicore optical fiber (or, for short, multicore fiber) that includes multiple different cores extending along the multicore fiber. The different cores correspond to different paths, waveguides, or channels through which light may propagate along the multicore fiber. In some examples, the different cores are distributed in the cross section of the multicore fiber with a relatively small pitch (e.g., 50 μm or less, 35 μm or less, etc.) or space. As long as the multicore fiber is generally aligned with the longitudinal axis for the component (generally aligned with the path of the light), different positions of the cores in the multicore fiber correspond to different positions along the lateral and vertical axes. As a result, the optical power delivered from the different cores corresponds to optical power associated with different lateral and vertical positions. Thus, as disclosed in further detail below, the calibration position of a reference fiber block (implemented with a multi-core fiber) can be determined without the need to move the fiber laterally and vertically to test different positions for the reference fiber block. That is, while the reference fiber block can be moved in a first direction (e.g., longitudinally), the reference fiber block is calibrated without moving the reference fiber block in any direction transverse to the first direction. This can significantly reduce the amount of time required to determine the calibration position compared to existing calibration techniques that require fiber movement in all three XYZ directions. Furthermore, in some examples, the fiber calibration process is completed for a single sample (single PIC and lens) without the need to repeat the process across multiple samples that are averaged, thereby further reducing the time required. Still further, in some examples, the multiple different cores in the exemplary reference fiber blocks disclosed herein can be used to compensate for variations in the properties of optical components (e.g., lasers and lenses) between different units or samples during the lens alignment process.As a result, the examples disclosed herein not only reduce the time for the fiber calibration process, but also improve the accuracy of the lens alignment process, thereby producing a final product with a higher quality optical signal (e.g., higher optical coupling) in less time than known approaches.

[0029] FIG. 1 illustrates an exemplary optical alignment system 100 for facilitating alignment of optical components to a laser (e.g., light emitter, light transmitter, light source) 102 on a photonic integrated circuit (PIC) 104 (e.g., photonic die). In this example, the PIC 104 is a semiconductor (e.g., silicon) die that includes at least one laser 102 for generating an optical signal (e.g., a beam of light 106). In some examples, the PIC 104 includes more than one laser 102. Additionally, in some examples, the PIC 104 includes one or more optical receivers for detecting and / or receiving the optical signal. In some examples, the PIC 104 includes one or more electronic components (e.g., transistors, capacitors, resistors, inductors, etc.) electrically coupled in a circuit with the at least one laser 102.

[0030] As depicted in FIG. 1, an optical element such as a lens 108 is positioned adjacent to the PIC 104 in the path of the light 106 from the laser 102 to direct and / or focus the light toward the reference fiber block 110. In this example, the reference fiber block 110 is implemented with a multi-core fiber 112 that includes multiple optical cores 114. As used herein, an optical core (or simply a core) refers to a waveguide or channel through which light may propagate. In contrast, as used herein, an optical fiber (or simply a fiber) refers to a cable or other housing that includes an optical core. Thus, a multi-core optical fiber (or simply a multi-core fiber) is an optical fiber that includes multiple different cores that correspond to separate channels or waveguides through which light may propagate independently. In the illustrated example of FIG. 1, seven different cores 114 are shown in the multi-core fiber 112. However, any other suitable number of cores 114 may be implemented in the multi-core fiber 112, as described in further detail below in connection with FIGS. 2-4.

[0031] In the illustrated example, each optical channel of the reference fiber block 110 (e.g., each core 114 of the multicore fiber 112) is optically coupled to a corresponding optical power meter 116 that is in turn communicatively coupled to the alignment controller circuitry 118. The optical power meter 116 measures and / or detects the power of the optical signals transmitted through each of the cores 114. In some examples, there are fewer power meters 116 than cores 114 in the multicore fiber 112. In such examples, more than one (or all) of the cores 114 are optically coupled to a single meter 116 having one or more switches, allowing the single meter 116 to monitor the power of signals delivered through each of the corresponding cores 114.

[0032] Based on the output of the power meter 116, the alignment controller circuitry 118 can determine the coupling loss between the laser 102 and the cores 114. In general, cores 114 that are closer to alignment with the laser 102 and lens 108 are associated with smaller coupling losses (e.g., higher optical power) than cores 114 that are out of alignment with the laser 102 and lens 108. As a result, the alignment controller circuitry 118 can relatively quickly identify an approximation for the optimal position for the cores to receive and propagate the light 106 based on the peak power (e.g., smallest coupling loss) detected across all of the monitored cores 114. This can also be done without having to move the reference fiber block 110 in a direction transverse to the path of the light 106. That is, there is no need to move the reference fiber block 110 along a vertical axis (represented by the Z-axis 120 in the coordinate system shown in FIG. 1 with the origin 122 at the laser 102) and no need to move the reference fiber block 110 along a transverse or horizontal axis (into and out of the drawing from the perspective of FIG. 1 which corresponds to the X-axis 214 (shown in FIG. 2) of the coordinate system). In other examples, the origin 122 can be defined at a different location along the Y-axis 124 (e.g., the lens 108 instead of the laser 102).

[0033] Although the location on the reference fiber block 110 associated with the peak power detected by the alignment controller circuitry 118 may be determined without moving the reference fiber block 110 in the vertical and lateral directions, the reference fiber block 110 may still need to be moved in a longitudinal or depth direction (corresponding to the Y-axis 124 of the coordinate system of FIG. 1 ) to fully define a calibration position for the reference fiber block 110. Thus, in some examples, the alignment controller circuitry 118 is operably coupled to a fiber positioner 126 capable of moving the reference fiber block 110 along the Y-axis 124 (e.g., along the longitudinal axis). In some examples, the fiber positioner 126 can also move the reference fiber block 110 along the X-axis 214 and Z-axis 120 (e.g., for initial positioning prior to implementation of a fiber calibration process and / or to move the reference fiber block to a final calibration position determined after completion of the fiber calibration process). However, as mentioned above, once the reference fiber block 110 is positioned, in some instances, it is not necessary to move the reference fiber block 110 along either the X-axis 214 or the Z-axis 120 during the fiber calibration process to determine a calibration position for the reference fiber block 110.

[0034] Although the reference fiber block 110 may remain fixed in the X and Z directions during the fiber calibration process, the lens 108 still needs to move relative to the laser 102 and relative to the reference fiber block 110 to identify the peak powers detected through the different cores 114. Thus, in some examples, the alignment controller circuitry 118 is operably coupled to a lens positioner 128 capable of moving the lens 108 in all three X, Y, and Z directions. In addition, to move the lens 108 during the fiber calibration process, the lens positioner 128 may also move the lens 108 during a lens alignment process implemented after the completion of the fiber calibration process. That is, as described above, the calibration position of the reference fiber block 110 is a fixed position in all three X, Y, and Z directions at which the reference fiber block 110 is fixed to subsequently align the lens 108 with the laser 102 during the lens alignment process (as determined through the fiber calibration process). Additionally, the same calibration position is used in a subsequent lens alignment process to align other lenses 108 with lasers 102 of other PICs 104 (e.g., separate production units of the same optical device). In some examples, the lens positioner 128 includes and / or operates in conjunction with a lens attachment mechanism (e.g., an adhesive dispenser) to facilitate attachment of the lens to the PIC 104 when the lens 108 is positioned in a final lens position determined by the lens alignment process.

[0035] 2 is a cross-sectional view of an exemplary multicore fiber 112 of the exemplary optical alignment system of FIG. 1. As shown in the illustrated example, the multiple cores 114 of the multicore fiber 112 are distributed in two dimensions. More specifically, in this example, the cores 114 are distributed along two linear arrays 202, 204 that intersect or cross each other at the center of the fiber 112. Thus, in this example, the linear arrays 202, 204 define a cross or T-shape. In this example, the first linear array 202 is aligned with the Z-axis 120 (e.g., vertical axis) and the second linear array 204 is aligned with the X-axis 214 (e.g., transverse or horizontal axis). For purposes of illustration, the cores 114 in the first linear array 202 are labeled with numbers representing the Z-axis core positions 206. Similarly, the cores 114 in the second linear array 204 are labeled with a number representing the X-axis core position 208. In this example, the two linear arrays 202, 204 of cores 114 share a common core 114 at the center of both arrays (core position 0 on both the X-axis 214 and the Z-axis 120). In other examples, the two linear arrays 202, 204 may cross or intersect each other without sharing a common core 114. In this example, both linear arrays 202, 204 have the same number of cores. However, in other examples, the number of cores in each linear array 202, 204 may differ from one another. Additionally, in some examples, one or both of the linear arrays 202, 204 may have fewer or more cores 114 than shown in the illustrated example.

[0036] Any other suitable arrangement of the cores 114 is possible. For example, Figure 3 shows another example multicore fiber 300 with a different example arrangement of the cores 114 including linear arrays 302, 304 that are angled with respect to the X-axis 214 and the Z-axis 120. In some examples, the vertical and horizontal arrays may be omitted such that only the angled arrays (e.g., in an X-shape) are included. Figure 4 shows another example multicore fiber 400 with a different example arrangement of the cores 114 that corresponds to a two-dimensional grid including multiple vertical arrays of cores 114 and multiple horizontal arrays of cores 114.

[0037] The individual cores 114 may be of any suitable size. In some examples, the cores 114 have a diameter 210 of approximately 9 μm. In some examples, adjacent ones of the cores 114 are positioned with a relatively small pitch or space 212. For example, in some examples, the pitch 212 is less than 75 μm (e.g., 50 μm or less, 40 μm or less, 35 μm or less, 30 μm or less, etc.). The cores 114 are positioned relatively close together to increase the granularity with which the optical coupling between the laser 102 and the multi-core fiber 112 can be measured at different positions in the XZ plane. That is, each core 114 functions as a separate channel or signal path for light to travel and be measured via a corresponding power meter 116 shown in FIG. 1. Measurements of optical coupling (e.g., signal power) delivered through different ones of the cores 114 are used in the fiber calibration process to determine a calibration position for the reference fiber block 110 in a manner that reduces movement of the reference fiber block 110 compared to known approaches that use optical fibers with a single core. In particular, the different cores 114 in the multi-core fiber 112 effectively act as different positions of a single-core fiber in the XZ plane, allowing approximation of an optimal position in the XZ plane without requiring movement of the reference fiber block 110 in that plane.

[0038] Additionally, measuring the optical coupling (e.g., signal power) delivered through different ones of the cores 114 also serves to more accurately determine the final position of the lens 108 during the lens alignment process than is possible using known techniques. In particular, as described in more detail below, measuring the optical power through different ones of the cores 114 during the lens alignment process provides multiple data points from which an optimal position for the lens may be determined through interpolation. Additionally, the multiple cores 114 allow the lens alignment process to compensate for variations in the optical components for different units (e.g., different instances) of the PIC 104 and lens 108.

[0039] In some examples, the objective of the fiber calibration process is to find an optimal Y position for the reference fiber block 110 that corresponds to a position on the Y axis 124 for the reference fiber block 110 that results in the highest optical power delivered through the reference fiber block 110. As described further below, this is determined without requiring movement of the reference fiber block 110 in the XZ plane. Once the optimal Y position is determined, the reference fiber block 110 is moved to an optimal XZ position at the optimal Y position that corresponds to the final calibration position for the reference fiber block 110. In some examples, the optimal XZ position is also determined without requiring movement of the reference fiber block 110 in the XZ plane (although after this optimal XZ position is determined, the reference fiber block 110 may be moved to a position in the XZ plane). In some examples, moving the reference fiber block 110 to the optimal XZ position means that one of the cores 114 in the multi-core fiber 112 is centered or aligned with the optimal XZ position. In some examples, the core 114 at the center of the multicore fiber 112 (e.g., the core 114 at the 0 position on both the X-axis 214 and the Z-axis 120 in FIG. 2) is centered or aligned with the optimal XZ position. However, in other examples, the reference fiber block 110 may be moved to the optimal XZ position by centering or aligning a different core 114 that is not at the center of the multicore fiber 112 with respect to the optimal XZ position.

[0040] When different Y positions for the reference fiber block 110 are tested during the fiber calibration process, the Y position for the lens 108 needs to be changed, thereby causing a change in the magnification (M) of the light 106 passing through the lens 108. In a fiber optic system, the lens magnification is set so that the beam spot size (object) from the laser 102 is magnified to match the mode size (image) for the optical fiber carrying the light 106. Theoretically, the optimal Y position for the reference fiber block 110 and the lens 108 corresponds to when the lens magnification is equal to the ratio of the numerical aperture of the laser 102 to the numerical aperture of the optical fiber (e.g., when M=NA_Laser / NA_Fiber). However, the optimal Y position cannot be determined directly. Rather, in some examples, the reference fiber block 110 is moved to a particular Y position and the lens 108 is scanned or moved relative to the multiple cores 114 in the multicore fiber 112 while monitoring the optical power output through the different cores 114 to identify the peak power detected for different ones of the cores 114. The XZ position of the lens 108 at each peak power detected for each core 114 is recorded and the process is repeated for different Y positions of the reference fiber block 110. The lens position associated with the detected peak power is referred to herein as the peak power lens position. Although it is possible to determine the peak power lens position in both the X and Z directions in a single process, in some examples the XZ position is determined by separately determining the peak power lens position along the X-axis 214 and the peak power lens position along the Z-axis 120.

[0041] The XZ position of the lens 108 at the peak power associated with different cores 114 arranged in a line (e.g., along one of the linear arrays 202, 204, 302, 304) varies linearly with changes in the XZ position of the cores 114. Thus, when the XZ positions of the cores 114 are plotted against the corresponding peak power lens positions, the plot defines the lines shown in the exemplary graph 500 of Figure 5. In particular, the graph 500 of Figure 5 shows three lines 502, 504, 506 corresponding to three different distances (e.g., lens FAU distances) of the reference fiber block 110 from the lens 108 corresponding to positions or distances along the Y-axis 124. The first line 502 corresponds to the reference fiber block 110 at a distance of 1077 μm from the lens 108, the second line 504 corresponds to the reference fiber block 110 at a distance of 639 μm from the lens 108, and the third line 506 corresponds to the reference fiber block 110 at a distance of 478 μm from the lens. These distances can be converted to Y positions on the Y axis 124 relative to the origin 122 of the laser 102 by adding the distance between the laser 102 and the lens 108. The three lines 502, 504, 506 in the graph 500 follow a plot of different Z positions of the lens 108 at peak power associated with five different Z positions of the core 114 (X positions are assumed to be fixed in this example). As shown, the Z positions for the cores 114 are constant across all three lines 502, 504, 506 (e.g., fiber core #2 is always at 70 μm, fiber core #1 is always at 35 μm, etc.). This is because the reference fiber block 110 does not move in the XZ direction during this process, but the Z position of the lens 108 changes for any particular core 114 as the Y position changes. The slopes of the lines 502, 504, 506 are referred to herein as slope M+1 values ​​because they relate to the M+1 of the optical system.More specifically, in a single lens system (object-lens-image), the sensitivity between the image offset distance (e.g., the distance the fiber core is offset from the Y-axis 124 (e.g., in the X and Z directions)) and the lens offset distance (e.g., the distance the lens 108 is offset from the Y-axis 124) relative to the object position (e.g., the position of the laser 102) is equal to M+1. Similar to M+1, as used herein, the slope M+1 value can be defined as the ratio of the change in the XZ position (or only X or Z, if the axes 120, 214 are analyzed independently) between the two cores 114 to the change in the XZ position (or only X or Z) of the lens 108 in the peak power detected for the two cores 114. In other words, the slope M+1 value is the ratio of the distance between the two cores 114 to the distance between the peak power lens positions associated with the two cores 114.

[0042] In the graph 500 of FIG. 5, peak power values ​​are plotted for each core 114 along the linear array 202. However, in some examples, the slopes (e.g., slope M+1 values) of the lines 502, 504, 506 may be determined based on peak power lens positions associated with only two cores 114. In some examples, the slope M+1 values ​​are determined based on the two outermost cores 114 at either end of the linear array of cores (e.g., cores 114 at Z positions of −3 and 3 along the Z axis 120 in FIG. 2 and / or cores 114 at X positions of −3 and 3 along the X axis 214 in FIG. 2). Although the lens positions associated with the two cores 114 are sufficient to determine the slope M+1 values ​​at the corresponding Y positions (e.g., the corresponding distance between the reference fiber block 110 and the lens 108) at which the reference fiber block 110 is set, the peak values ​​detected for each core 114 along the linear array are still used to determine the optimal Y position for the reference fiber block 110. Thus, in some examples, lens 108 is still scanned or moved relative to each core 114 while monitoring the optical output power.

[0043] Moving the lens 108 for each core 114 individually to find where the peak power is detected can take a lot of time. In some examples, the length of time of this process is shortened by determining the peak power lens positions for two cores along the linear array of cores and then defining a vector or path for the lens 108 that corresponds to a line that passes through the two peak power lens positions associated with the two cores. In some examples, the two cores 114 correspond to the same two cores 114 used to determine the slope M+1 value described above. Once the vector or lens path is defined between the cores 114 (and crosses every other core 114 along the corresponding linear array), the lens 108 is moved or scanned along the vector or path and the peak power detected at each core 114 in the linear array is recorded. As long as the cores are arranged along a linear line and the lens path is defined based on the peak power lens positions for two cores along that linear path, the defined lens path should pass through the positions of the peak power for each core, so the lens 108 does not need to be moved to find the peak power for all cores 114 in the linear array.

[0044] As explained above, in some examples, to simplify the calculations, the X-axis 214 is analyzed independently from the Z-axis 120. In some such examples, since the output beam of a laser (e.g., laser 102) may be elliptical, the lens 108 positions at peak power for different cores 114 along both the X-axis 214 and the Z-axis 120 are analyzed. That is, the numerical aperture of the laser 102 may differ between the X-axis 214 and the Z-axis 120. As a result, the optimal Y position for the reference fiber block 110 determined based on the analysis of the X-axis 214 can be different from the optimal Y position determined based on the analysis of the Z-axis 120. In some such examples, the two different optimal Y positions are averaged to arrive at a final optimal Y position for the reference fiber block 110.

[0045] To determine the optimal Y position for the reference fiber block 110, the highest peak power detected for each of a number of different slope M+1 values ​​corresponding to different Y positions is identified. As explained above, a separate peak power is recorded for each core 114 in the linear array through which the lens 108 is scanned. Thus, in this context, the highest peak power refers to the highest of the different peak powers corresponding to each of the cores 114 through which the lens 108 is scanned. A plot of the various highest peak values ​​at different slope M+1 values ​​(associated with the Y positions) forms a downwardly opening parabola or curve 602 with a local maximum, as represented at the top of the graph 600 of FIG. 6. In the graph 600 of FIG. 6, the leftmost plot 604 corresponds to the third line 506 in the graph 500 of FIG. 5 with a slope M+1 value of approximately 3.3. The rightmost plot 606 in the graph 600 of FIG. 6 corresponds to the first line 502 in the graph 500 of FIG. 5 with a slope M+1 value of approximately 7.5. The top plot 608 in the graph 600 of FIG. 6 corresponds to the second line 504 in the graph 500 of FIG. 5 with a slope M+1 value of approximately 4.4. In some examples, a curve 602 is calculated to fit the plot of the highest peak value, and then the slope M+1 value corresponding to the maximum point on the curve 602 is identified. The slope M+1 value at this point is then used to identify a corresponding lens-FAU distance in the lower portion of the graph 600 along a line 610, which is calculated to fit a plot of different slope M+1 values ​​calculated for each Y position analyzed during the fiber calibration process. The resulting lens-FAU distance corresponds to an optimal Y position for the calibration position of the reference fiber block 110. The graphs 500, 600 of FIGS. 5 and 6 are specific to the analysis performed along the Z axis 120. As explained above, the analysis may be repeated along the X axis, resulting in a slightly different optimal Y position. In such a situation, the two different optimal Y-positions may be averaged to define a final optimal Y-position for the calibration position of the reference fiber block 110.

[0046] Once the final optimal Y position is determined, the reference fiber block 110 is moved to that position, and then the lens 108 is scanned along the cores 114 of the multi-core fiber 112 while monitoring the signal output power through each core 114. The position of the particular core 114 where the highest peak power is detected is identified as the calibrated XZ position for the reference fiber block 110. In some examples, the reference fiber block 110 is moved in the XZ plane to position the central core 114 at the calibrated XY position, and to position the reference fiber block 110 at its final calibrated position in all three XYZ directions. In some examples, different cores 114 other than the central core 114 are moved to the calibrated XYZ positions. As explained above, including multiple cores 114 in the multi-fiber cores 112 used for the reference fiber block 110 eliminates the need for the reference fiber block 110 to be moved in the XZ direction during the fiber calibration process (although it may be moved to a position once the calibrated position is determined). As a result, the fiber calibration process can be completed significantly faster than existing approaches involving a single-core fiber that must be moved in all three XYZ directions in addition to moving the lens 108.

[0047] Once the calibration position for the reference fiber block 110 is determined and the block is moved to that position, it is possible to move on to the lens alignment process. In some examples, the process for determining the final lens position through the lens alignment process is similar to the process described above for the fiber calibration process. In particular, during lens alignment, the lens 108 is moved or scanned along a linear array of cores (e.g., linear arrays 202, 204) to two cores 114 located at different positions while the optical power through the two cores 114 is monitored. The location of the lens 108 associated with the peak power detected through each core 114 is recorded and used to define a vector or lens path along the linear array of cores. The alignment controller circuitry 118 then moves the lens 108 along the lens path that is scanned across all the cores 114 in the linear array. The location along the lens path where the highest peak power is detected is identified and stored as the final lens position for the lens 108.

[0048] While the above lens alignment process may be suitable for finding an optimal lens position for the lens 108 used in the fiber calibration process, the lens alignment process may not identify the optimal lens position for a subsequent lens 108 that is aligned with a different laser 102 on the PIC 104 or on an entirely different PIC 104 (e.g., an entirely separate production unit) due to variations in optical components.

[0049] As a specific example, one variation that may occur between different lasers 102 is the angle (e.g., chief ray angle) of the beam of light emitting from the PIC 104. Assuming that the same lens 108 is used in the same position, the variation in the beam angle between different lasers 102 results in a variation in the angle of the incident light on the optical fiber core (e.g., core 114). However, there is a specific angle of the incident light on the core 114 that satisfies the conditions of Snell's law and maximizes the propagation of light through the core 114. Thus, any deviation from the specific angle results in higher coupling losses (e.g., lower power). Thus, in this example, the lens 108 needs to shift position to achieve peak power in response to the variation in the angle of the beam of light. Multiple different cores 114 in the exemplary multicore fiber 112 of the reference fiber block 110 can be used to interpolate optimal lens positions to compensate for variations in the angle of the beam of light based on a plot of the peak power detected in each core 114 of the reference fiber block 110 as the lens 108 is scanned, as shown in the lower part of graph 700 in FIG. 7.

[0050] In particular, the bottom portion of the graph 700 of FIG. 7 includes three lines (e.g., parabolas, curves) 702, 704, 706 that are fitted to a plot of peak power (e.g., coupling loss) detected at different core positions corresponding to three different angles of light from the laser 102 (e.g., associated with three different instances of the PIC 104). The first line 702 is associated with a chief ray angle for the light of −12.8 degrees, the second line 704 is associated with a chief ray angle for the light of −7.8 degrees, and the third line 706 is associated with a chief ray angle for the light of −2.8 degrees. As shown in the illustrated example, the maximum point (e.g., highest peak power) of the second line 704 approximately aligns with the central (position 0) core 114. Thus, the peak power is detected directly during the scanning of the lens 108 across the core 114. However, the maximum points of the first and third lines 702, 706 are shifted to a location between adjacent ones of the cores 114 (e.g., the first line 702 is shifted to the left in the graph 700 and the third line 706 is shifted to the right). In some examples, the final lens position may be interpolated from a fit of the lines 708, 710, 712 (which all overlap in FIG. 7) to a plot of the peak power lens positions identified for each core 114, as shown at the top of the graph 700. Specifically, the point of the interpolation that corresponds to the final position for the lens 108 corresponds to the maximum point on the lines 702, 706 at the bottom of the graph 700. Thus, in this example, the final lens position for light with a chief ray angle of −12.8 degrees (associated with the first line 702) is approximately −2.5 μm. The final lens position for light with a chief ray angle of −7.8 degrees (associated with the second line 704) is approximately 1.5 μm. The final lens position for light with a chief ray angle of -2.8 degrees (associated with the third line 704) is approximately 6 μm. Note that these final lens positions are specific to the Z axis 120. The process can be repeated to interpolate the final lens position along the X axis. This process of interpolation is not possible using known lens alignment techniques with reference fiber blocks that contain only a single core.Therefore, the examples disclosed herein may improve the accuracy of lens alignment to compensate for variations between different production units.

[0051] 8 is a block diagram of an example implementation of the alignment controller circuitry 118 of FIG. 1 for calibrating a position of the reference fiber block 110 (e.g., implementing the fiber calibration process described above) and then determining a final lens position for the lens 108 (e.g., implementing the lens alignment process described above). The example alignment controller circuitry 118 of FIG. 8 includes example communication interface circuitry 802, example fiber position controller circuitry 804, example lens position controller circuitry 806, example optical power analyzer circuitry 808, example alignment analyzer circuitry 810, and example memory 812. The alignment controller circuitry 118 of FIG. 8 may be instantiated (e.g., create an instance of it, cause it to occur for any length of time, embody, implement, etc.) by programmable circuitry, such as a central processor unit (CPU) executing a first instruction. Additionally or alternatively, the alignment controller circuitry 118 of FIG. 8 may be instantiated (e.g., instantiate, cause to occur for any length of time, embody, implement, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) structured and / or configured in response to execution of the second instruction to perform operations corresponding to the first instruction. Thus, it should be understood that some or all of the circuitry of FIG. 8 may be instantiated at the same time or at different times. Some or all of the circuitry of FIG. 8 may be instantiated in one or more threads executing simultaneously on hardware and / or serially on hardware, for example. Also, in some examples, some or all of the circuitry of FIG. 8 may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0052] The example alignment controller circuitry 118 of Figure 8 includes example communications interface circuitry 802 that enables communication with one or more external components and / or devices. For example, the communications interface circuitry 802 receives sensor feedback data from an optical power meter 116 coupled to a core 114 of the multicore fiber 112 of Figure 1. Additionally, in some examples, the communications interface circuitry 802 enables communication with a fiber positioner 126 and a lens positioner 128. In some examples, the communications interface circuitry 802 is instantiated by programmable circuitry configured to execute communications interface instructions and / or perform operations such as those represented by the flowcharts of Figures 9-13.

[0053] In some examples, the alignment controller circuitry 118 includes a means for communicating. For example, the means for communicating may be implemented by a communications interface circuitry 802. In some examples, the communications interface circuitry 802 may be instantiated by a programmable circuitry, such as the example programmable circuitry 1412 of FIG. 14. In some examples, the communications interface circuitry 802 may be instantiated by hardware logic circuitry, such as may be implemented by the ASIC, XPU, or FPGA circuitry 1600 of FIG. 16, configured and / or constructed to perform operations corresponding to machine-readable instructions. Additionally or alternatively, the communications interface circuitry 802 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the communications interface circuitry 802 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (opamps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the executed machine-readable instructions without software or firmware, although other structures are suitable as well.

[0054] 8 includes example fiber position controller circuitry 804 for controlling and / or directing operation of fiber positioner 126. In some examples, fiber position controller circuitry 804 is instantiated by programmable circuitry configured to execute fiber position controller instructions and / or perform operations such as those represented by the flowcharts of FIGS.

[0055] In some examples, the alignment controller circuitry 118 includes a means for controlling the movement of the reference fiber block 110 (e.g., a means for controlling the movement of the multi-core optical fiber). For example, the means for controlling the movement may be implemented by the fiber position controller circuitry 804. In some examples, the fiber position controller circuitry 804 may be instantiated by a programmable circuitry, such as the example programmable circuitry 1412 of FIG. 14. For example, the fiber position controller circuitry 804 may be instantiated by the example microprocessor 1500 of FIG. 15 executing machine-executable instructions, such as those implemented by at least block 904 of FIG. 9 and blocks 1004 and 1024 of FIG. 10. In some examples, the fiber position controller circuitry 804 may be instantiated by hardware logic circuitry, which may be implemented by the ASIC, XPU, or FPGA circuitry 1600 of FIG. 16, configured and / or constructed to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the fiber position controller circuitry 804 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the fiber position controller circuitry 804 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (opamps), logic circuits, etc.) configured and / or structured to carry out some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the executed machine-readable instructions without software or firmware, although other structures are suitable as well.

[0056] 8 includes example lens position controller circuitry 806 for controlling and / or directing operation of the lens positioner 128. In some examples, the lens position controller circuitry 806 is instantiated by programmable circuitry configured to execute lens position controller instructions and / or perform operations such as those represented by the flowcharts of FIGS.

[0057] In some examples, the alignment controller circuitry 118 includes means for controlling movement of the lens 108. For example, the means for controlling movement may be implemented by the lens position controller circuitry 806. In some examples, the lens position controller circuitry 806 may be instantiated by programmable circuitry, such as the example programmable circuitry 1412 of FIG. 14. For example, the lens position controller circuitry 806 may be instantiated by the example microprocessor 1500 of FIG. 15 executing machine-executable instructions, such as those implemented by at least block 908 of FIG. 9, blocks 1010, 1026 of FIG. 10, block 1202 of FIG. 12, and block 1304 of FIG. 13. In some examples, the lens position controller circuitry 806 may be instantiated by hardware logic circuitry, which may be implemented by the ASIC, XPU, or FPGA circuitry 1600 of FIG. 16, configured and / or constructed to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the lens position controller circuitry 806 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the lens position controller circuitry 806 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (opamps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the executed machine-readable instructions without software or firmware, although other structures are suitable as well.

[0058] 8 includes example optical power analyzer circuitry 808 for monitoring and / or analyzing sensor feedback data from the optical power meter 116 (obtained via the communication interface circuitry 802). In some examples, the optical power analyzer circuitry 808 determines and / or identifies the peak power (e.g., lowest coupling loss) detected through a particular core 114. In some examples, the optical power analyzer circuitry 808 is instantiated by programmable circuitry configured to execute optical power analyzer instructions and / or perform operations such as those represented by the flowcharts of FIGS. 9-13.

[0059] In some examples, the alignment controller circuitry 118 includes means for monitoring optical power through the optical fiber core. For example, the means for monitoring may be implemented by optical power analyzer circuitry 808. In some examples, the optical power analyzer circuitry 808 may be instantiated by programmable circuitry, such as the example programmable circuitry 1412 of FIG. 14. For example, the optical power analyzer circuitry 808 may be instantiated by the example microprocessor 1500 of FIG. 15 executing machine-executable instructions, such as those implemented by at least block 1012 of FIG. 10, block 1204 of FIG. 12, and block 1306 of FIG. 13. In some examples, the optical power analyzer circuitry 808 may be instantiated by hardware logic circuitry, which may be implemented by ASIC, XPU, or FPGA circuitry 1600 of FIG. 16, configured and / or constructed to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the optical power analyzer circuitry 808 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the optical power analyzer circuitry 808 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (opamps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the executed machine-readable instructions without software or firmware, although other structures are suitable as well.

[0060] The example alignment controller circuitry 118 of FIG. 8 includes an example alignment analyzer circuitry 810 for implementing and / or guiding optical alignment procedures, including a fiber calibration process and a lens alignment process. That is, in some examples, the alignment analyzer circuitry 810 determines and / or defines different Y positions at which the reference fiber block 110 is set (as controlled via the fiber position controller circuitry 804) during a fiber calibration process. Furthermore, the example alignment analyzer circuitry 810 determines an optimal Y position (and optimal X and Z positions) for the reference fiber block 110 (e.g., a calibration position) based on an analysis of the power output of the core 114 (monitored and provided via the optical power analyzer circuitry 808) at the different Y positions selected for the fiber calibration process. Similarly, in some examples, the alignment analyzer circuitry 810 determines an optimal XYZ position (e.g., a final lens position) for the lens 108 during a lens alignment process based on an analysis of the power output of the core 114. For example, in some examples, the alignment analyzer circuitry 810 (in addition to or instead of the optical power analyzer circuitry 808) determines the peak power detected for any particular core 114 and / or determines the highest peak power among multiple different ones of the cores 114. Additionally, in some examples, the alignment analyzer circuitry 810 determines and / or defines a position to which the lens 108 moves and / or a vector or path along which the lens 108 moves (which may be provided to the lens position controller circuitry 806 to implement the movement). Furthermore, the example alignment analyzer circuitry 810 may determine a slope M+1 value based on a relative change in the position of the core 114 relative to a change in the position of the lens 108 when the peak power for each core 114 is detected.In some examples, the alignment analyzer circuitry 810 analyzes the peak powers detected at the different cores 114, the positions of the cores 114, and / or the positions of the lens 108 when each peak power was detected, and interpolates a location or position for the lens 108 and / or core 114 associated with the maximum power to improve optical coupling between the laser 102, the lens 108, and the core 114. In some examples, the alignment analyzer circuitry 810 is instantiated by programmable circuitry configured to execute alignment analyzer instructions and / or perform operations such as those represented by the flowcharts of FIGS.

[0061] In some examples, the alignment controller circuitry 118 includes means for determining a position for at least one of the lens 108 or the reference fiber block 110. For example, the means for determining may be implemented by the alignment analyzer circuitry 810. In some examples, the alignment analyzer circuitry 810 may be instantiated by a programmable circuitry, such as the example programmable circuitry 1412 of FIG. 14. For example, the alignment analyzer circuitry 810 may be instantiated by the example microprocessor 1500 of FIG. 15 executing machine-executable instructions, such as those implemented by at least blocks 902 and 906 of FIG. 9, blocks 1004, 1006, 1008, 1014, 1016, 1018, 1020, and 1022 of FIG. 10, blocks 1104 and 1106 of FIG. 11, block 1206 of FIG. 12, and blocks 1302 and 1308 of FIG. 13. In some examples, the alignment analyzer circuitry 810 may be instantiated by hardware logic circuitry, which may be implemented by the ASIC, XPU, or FPGA circuitry 1600 of FIG. 16 configured and / or constructed to perform operations corresponding to machine-readable instructions. Additionally or alternatively, the alignment analyzer circuitry 810 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the alignment analyzer circuitry 810 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the executed machine-readable instructions without software or firmware, although other structures are suitable as well.

[0062] The example alignment controller circuitry 118 of FIG. 8 includes an example memory 812 for storing peak values ​​for the optical output of the core 114 determined by the optical power analyzer circuitry 808 and / or the alignment analyzer circuitry 810. Additionally, the example memory 812 may store other values ​​generated and / or determined by the alignment analyzer circuitry 810 for use in a fiber calibration process and / or a lens alignment process (e.g., the position of the core 114 and / or the lens 108 associated with the detected peak power, the slope M+1 value, the optimal XYZ position for the reference fiber block 110 and the lens 108, etc.). The example memory 812 is implemented by any memory, storage device, and / or storage disk for storing data, such as, for example, flash memory, magnetic media, optical media, solid state memory, hard drives, sub-drives, etc. Additionally, the data stored in the example memory 812 may be in any data format, such as, for example, binary data, comma-separated data, tab-separated data, Structured Query Language (SQL) structures, etc. In the depicted example, memory 812 is shown as a single component, although the example memory 812 and / or any other data storage devices described herein may be implemented with any number and / or type of memory.

[0063] An exemplary manner of implementing the alignment controller circuitry 118 of Figure 1 is illustrated in Figure 8, although one or more of the elements, processes, and / or devices illustrated in Figure 8 may be combined, divided, rearranged, omitted, removed, and / or implemented in any other manner. Additionally, the exemplary communications interface circuitry 802, the exemplary fiber position controller circuitry 804, the exemplary lens position controller circuitry 806, the exemplary optical power analyzer circuitry 808, the exemplary alignment analyzer circuitry 810, and / or, more generally, the exemplary alignment controller circuitry 118 of Figure 8 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the exemplary communications interface circuitry 802, the exemplary fiber position controller circuitry 804, the exemplary lens position controller circuitry 806, the exemplary optical power analyzer circuitry 808, the exemplary alignment analyzer circuitry 810, and / or, more generally, the exemplary alignment controller circuitry 118 may be implemented by programmable circuitry (e.g., firmware or software) in combination with machine-readable instructions, processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs), such as FPGAs. Still further, the exemplary alignment controller circuitry 118 of FIG. 8 may include one or more elements, processes, and / or devices in addition to or instead of those shown in FIG. 8 and / or may include any one or all of the elements, processes, and devices shown.

[0064] Flowcharts representing example machine-readable instructions that may be performed by a programmable circuitry to implement and / or instantiate the alignment controller circuitry 118 of FIG. 8 and / or representing example operations that may be performed by a programmable circuitry to implement and / or instantiate the alignment controller circuitry 118 of FIG. 8 are shown in FIGS. 9-13. The machine-readable instructions may be one or more executable programs or parts of one or more executable programs for execution by a programmable circuitry, such as the programmable circuitry 1412 shown in the example processor platform 1400 described below in connection with FIG. 14, and / or may be one or more functions or parts of functions performed by the example programmable circuitry (e.g., FPGA) described below in connection with FIG. 15 and / or FIG. 16. In some examples, the machine-readable instructions cause an operation, task, etc. to be performed and / or accomplished in an automated manner in the real world. As used herein, "automated" means without human involvement.

[0065] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as a cache memory, a magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), an optical storage device or disk (e.g., a Blu-ray disk, a compact disk (CD), a digital versatile disk (DVD), etc.), a redundant array of independent disks (RAID), registers, a ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., an Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or disk. The instructions of the non-transitory computer-readable and / or machine-readable medium may be programmed and / or executed by programmable circuitry located in one or more hardware devices, although the entire program and / or portions thereof may alternatively be executed and / or instantiated by one or more hardware devices other than the programmable circuitry and / or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by more than one hardware device (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an end-point client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN) that may facilitate communication between a server and an end-point client hardware device). Similarly, a non-transitory computer-readable storage medium may include one or more media. Additionally, although an exemplary program is described with reference to the flowcharts shown in FIGS. 9-13, many other methods of implementing the exemplary alignment controller circuitry 118 may alternatively be used.For example, the order of execution of the blocks of the flowcharts may be changed, and / or some of the illustrated blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowcharts may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (opamps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed across different network locations and / or local to one or more hardware devices (e.g., a single-core processor (e.g., single-core CPU), a multi-core processor (e.g., multi-core CPU, XPU, etc.)). For example, the programmable circuitry may be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0066] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., a portion of instructions, code, a representation of code, etc.) that can be utilized to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be fragmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations of a network or collection of networks (e.g., cloud, edge devices, etc.). Machine-readable instructions may require one or more of installing, modifying, adapting, updating, combining, supplementing, configuring, decrypting, decompressing, unpacking, distributing, reallocating, compiling, etc., to render them directly readable, interpretable, and / or executable by computing devices and / or other machines. For example, machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, where the portions, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that may together form a program, such as those described herein.

[0067] In another example, machine-readable instructions may be stored in a state that can be read by programmable circuitry, but may require the addition of a library (e.g., a dynamic link library (DLL), a software development kit (SDK), an application programming interface (API), etc.) to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., stored settings, data input, recorded network addresses, etc.) before the machine-readable instructions and / or corresponding programs are executable in whole or in part. Thus, as used herein, machine-readable, computer-readable, and / or machine-readable media may include instructions and / or programs, regardless of the particular format or state of the machine-readable instructions and / or programs.

[0068] The machine-readable instructions described herein may be expressed in any past, present, or future command language, scripting language, programming language, etc. For example, the machine-readable instructions may be expressed using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0069] As mentioned above, the example operations of Figures 9-13 may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media. Examples of such non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk in which information is stored for any length of time (e.g., long-term, permanent, short-term, temporary buffering, and / or caching of information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware for retaining information over a period of time, but to exclude propagating signals and to exclude transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a machine and / or electrical equipment, hardware, and / or circuitry, that may or may not be configured with computer-readable instructions, machine-readable instructions, etc., and / or that may or may not be manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0070] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "include" or "comprise" (e.g., "comprises," "includes," "comprising," "including," "having," etc.) as a preamble or in any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitation. As used herein, the phrase "at least" is open-ended in the same manner that the terms "including" and "comprising" are open-ended, for example, when used as a transitional phrase in a claim preamble. When the term "and / or" is used in the form, for example, A, B, and / or C, it refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. When used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. When used herein in the context of describing the performance or execution of a process, instruction, operation, activity, and / or step, the phrase “at least one of A and B” is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, when used herein in the context of describing the performance or execution of a process, instruction, operation, activity, and / or step, the phrase “at least one of A or B” is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0071] As used herein, a singular reference (e.g., "a", "an", "first", "second", etc.) does not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of that object. The terms "a" (or "an"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although individually listed, multiple means, elements or actions may be implemented, for example, by the same entity or object. Additionally, although individual features may be included in different embodiments or different claims, they may be potentially combined, and their inclusion in different embodiments or different claims does not imply that a combination of features is not feasible and / or advantageous.

[0072] 9 is a flow chart depicting example machine-readable instructions and / or example operations 900 that may be executed, instantiated, and / or performed by programmable circuitry to implement a fiber calibration process and, subsequently, a lens alignment process to position a lens (e.g., lens 108) in a final position where it is attached to an associated PIC (e.g., PIC 104). The example machine-readable instructions and / or example operations 900 of FIG. 9 begin at block 902, when the example alignment controller circuitry 118 determines (e.g., using the example alignment analyzer circuitry 810) a calibration position for a reference fiber block (e.g., reference fiber block 110). In other words, the example alignment controller circuitry 118 implements an example fiber calibration process according to the teachings disclosed herein. An example implementation of block 902 is provided in further detail below in connection with FIG. 10. Thereafter, in block 904, the example fiber position controller circuitry 804 moves the reference fiber block 110 (using the fiber positioner 126) to the calibration position.

[0073] In block 906, the example alignment controller circuitry 118 determines a final position for the lens 108 (e.g., using the example alignment analyzer circuitry 810). In other words, the example alignment controller circuitry 118 implements an example lens alignment process according to the teachings disclosed herein. An example implementation of block 906 is provided below in connection with FIG. 11. Then, in block 908, the example lens position controller circuitry 806 moves the lens 108 to a final position (using the lens positioner 128) and allows the lens 108 to be attached to the PIC 104. In block 910, the example alignment controller circuitry 118 determines whether there is another lens 108 to be aligned and attached (e.g., in association with another laser 102 on the PIC 104 and / or in association with a separate PIC 104). If there is, control returns to block 906 to repeat the lens alignment process with the new lens 108. Thus, the fiber calibration process need not be repeated multiple times, but the reference fiber block 110 in the calibration position may be used for lens alignment of different lenses. Additionally, as described in detail above and further described below in connection with FIG. 12, the example lens alignment process disclosed herein may compensate for variations in optical properties of different lenses and / or other optical components for improved optical coupling. If, at block 910, there are no more lenses to be aligned and mounted, the example operations 900 of FIG. 9 end.

[0074] FIG. 10 is a flow chart representing example machine-readable instructions and / or example operations 1000 that may be executed, instantiated, and / or performed by a programmable circuit configuration to implement block 902 of FIG. 9. In other words, the example operations 1000 of FIG. 10 implement an example fiber calibration process for determining a calibration position for the reference fiber block 110. The example machine-readable instructions and / or example operations 1000 of FIG. 10 begin at block 1002, where the example fiber position controller circuit configuration 804 positions (using the fiber positioner 126) the multi-core fiber 112 of the reference fiber block 110 aligned with the laser 102 at a set depth position (e.g., a specific Y position) relative to the laser 102. In some examples, the reference fiber block 110 is aligned with the laser 102 by centering the central core 114 of the multi-core fiber 112 to the laser 102 (e.g., centering the central core 114 on the Y axis 124). However, in other examples, the distinct core 114 may be centered on the laser 102. In other examples, the core 114 is not centered on the laser 102.

[0075] In block 1004, the exemplary alignment controller circuitry 118 determines (e.g., using the exemplary alignment analyzer circuitry 810) a first peak power lens position associated with the first core 114 in the linear array of cores (e.g., linear arrays 202, 204) in the multicore fiber 112, the linear array extending along an axis of interest. In some examples, the axis of interest corresponds to either the X-axis 214 or the Z-axis 120. In other examples, the axis of interest corresponds to some other axis perpendicular to the longitudinal or Y-axis 124 (e.g., an axis at an angle relative to the X-axis 214 and the Z-axis 120). Further details regarding the implementation of block 1004 are provided below in connection with the flow chart in FIG. 12. In block 1006, the exemplary alignment controller circuitry 118 determines (e.g., using the exemplary alignment analyzer circuitry 810) a second peak power lens position associated with the second core 114 in the linear array of cores. In some examples, the implementation of block 1006 follows the same process as block 1004, except that the process is performed in association with a different (e.g., second) core 114. Thus, similar to block 1004, further details regarding the implementation of block 1006 are also provided below in association with the flowchart in FIG.

[0076] At block 1008, the exemplary alignment analyzer circuitry 810 defines a vector that passes through both the first and second peak power lens positions. The vector passes through other cores 114 in the linear array as long as both the first and second peak power lens positions are on the linear array. At block 1010, the exemplary lens position controller circuitry 806 moves the lens (using the lens positioner 128) along the path defined by the vector. At block 1012, the exemplary optical power analyzer circuitry 808 monitors the optical power through each core 114 in the linear array while the lens is being moved. At block 1014, the alignment analyzer circuitry 810 identifies and stores (e.g., in memory 812) the peak power detected for each core 114 along the linear array and the associated peak power lens position (e.g., the position of the lens 108 where each peak power was detected). At block 1016, the exemplary alignment analyzer circuitry 810 determines a slope M+1 value for the linear array of cores 114 at a particular depth position of the reference fiber block 110 (set at block 1002). In other words, the exemplary alignment analyzer circuitry 810 determines the ratio of the distance between two cores 114 along the linear array (e.g., change in fiber core offset distance) to the distance between the peak power lens positions associated with the two cores 114 (e.g., change in lens offset distance). This determination is similar to determining the slopes of lines 502, 504, 506 in graph 500 of FIG. 5.

[0077] At block 1018, the exemplary alignment analyzer circuitry 810 determines whether to repeat the process for a different axis of interest. For example, in some instances, if the X axis 214 is the first axis of interest, the process may be repeated for the Z axis 120. In some instances, if the first axis of interest is angled with respect to both the X axis 214 and the Z axis 120 (e.g., along one of the angled linear arrays 302, 304 of FIG. 3), it may be possible to analyze both the X and Z directions in a single iteration of the process. If, at block 1018, the exemplary alignment analyzer circuitry 810 determines to repeat the process for a different axis, control returns to block 1004. Otherwise, control proceeds to block 1020.

[0078] In block 1020, the exemplary alignment analyzer circuitry 810 determines whether to repeat the process for a different depth position (e.g., a different Y position). If so, control returns to block 1002 to move the reference fiber block 110 to a different depth position. Note that in some examples, this movement along the Y axis 124 is the only movement of the reference fiber block 110 during the fiber calibration process. That is, the reference fiber block 110 does not need to be moved in the XZ plane. If a different depth position is not to be tested, the process proceeds to block 1022, where the exemplary alignment analyzer circuitry 810 determines the calibration depth position corresponding to the slope M+1 value where the power is maximum. This determination is similar to finding the Y position associated with the point on the line 610 at the bottom of the graph 600 in FIG. 6 that corresponds to the maximum point on the curve 602 at the top of the graph 600 in FIG. 6. As explained above, in some examples, this analysis is performed separately for the X axis 214 and the Z axis 120. Thus, in some instances, the separate calibration depth positions are averaged to arrive at a final calibration depth position.

[0079] Once the calibration depth position (e.g., calibrated Y position) is determined (block 1022), the calibration positions in the lateral and vertical directions (X and Z directions) can be determined. Thus, in block 1024, the exemplary fiber position controller circuitry 804 moves the reference fiber block 110 to the calibration depth position. In block 1026, the exemplary lens position controller circuitry 806 scans the lens 108 across the cores 114 of the multi-core fiber 112, allowing the exemplary alignment analyzer circuitry to identify the core 114 associated with the highest peak power detected. In block 1028, the exemplary alignment analyzer circuitry 810 determines the calibration vertical position and the calibration lateral position based on the highest peak power. Once the calibration positions in each of the depth, lateral, and vertical directions are determined, the exemplary operation 1000 of FIG. 10 ends and returns to the completion of the process of FIG. 9.

[0080] 11 is a flow chart representing example machine-readable instructions and / or example operations 1100 that may be executed, instantiated, and / or performed by a programmable circuit configuration to implement block 906 of FIG. 9. In other words, the example operations 1100 of FIG. 11 implement an example lens alignment process to determine a final position for the lens 108. The example machine-readable instructions and / or example operations 1100 of FIG. 11 begin at block 1102, where the example alignment controller circuitry 118 (e.g., using the example alignment analyzer circuitry 810) determines a first peak power lens position associated with a first core 114 in a first linear array of cores (e.g., linear arrays 202, 204) in the multicore fiber 112, the first linear array extending along a first axis of interest. In some examples, the first axis of interest corresponds to either the X-axis 214 or the Z-axis 120. In other examples, the axis of interest corresponds to some other axis perpendicular to the longitudinal or Y-axis 124 (e.g., an axis at an angle relative to the X-axis 214 and Z-axis 120). In some examples, the implementation of block 1102 follows the same process as blocks 1004 and 1006 of FIG. 10. Thus, similar to blocks 1004 and 1006 of FIG. 10, further details regarding the implementation of block 1102 are provided below in conjunction with the flowchart in FIG. 12. In block 1104, the example alignment controller circuitry 118 determines (e.g., using the example alignment analyzer circuitry 810) a second peak power lens position associated with a second core 114 in the first linear array of cores. In some examples, the implementation of block 1104 follows the same process as block 1102, which is described in further detail below in conjunction with FIG. 12. In block 1106, the example alignment controller circuitry 118 (e.g., the example alignment analyzer circuitry 810) determines a final position for the lens along the first axis of interest. An example implementation of block 1106 is provided in further detail below in connection with FIG.

[0081] Blocks 1108, 1110, 1112 generally repeat the process of blocks 1102, 1104, 1106, except that blocks 1108, 1110, 1112 involve a second linear array of cores extending along a second axis of interest. For example, in some examples, the first axis of interest corresponds to the X-axis 214 and the second axis of interest corresponds to the Z-axis 120. In such examples, the final position of the lens 108 defined along the two axes (in blocks 1106 and 1112) defines a final XZ position for the lens 108. The example operations 1100 of FIG. 11 then end, returning to the completion of the process of FIG. 9.

[0082] 12 is a flowchart representing example machine-readable instructions and / or example operations 1200 that may be executed, instantiated, and / or performed by a programmable circuit configuration to implement any one of blocks 1004, 1006 of FIG. 10 and / or blocks 1102, 1104, 1108, 1110 of FIG. 11. In other words, the example operations 1100 of FIG. 11 may be executed, instantiated, and / or performed by a programmable circuit configuration to determine a peak power lens position associated with a target core 114 in a linear array of cores in a multicore fiber 112, the linear array extending along an axis of interest. The example machine-readable instructions and / or example operations 1200 of FIG. 12 begin at block 1202, where the example lens position controller circuit configuration 806 moves the lens 108 (using the lens positioner 128) relative to the target core 114. At block 1204, while the lens 108 is moving, the example optical power analyzer circuitry 808 monitors the optical power through the core of interest 114. At block 1206, the example alignment analyzer circuitry 810 identifies lateral and vertical positions of the lens 108 associated with the peak power for the core of interest 114. In other words, the example alignment analyzer circuitry 810 determines the peak power lens position associated with the core of interest 114. At block 1208, the example memory 812 stores the identified lateral and vertical positions of the lens 108. Thereafter, the example operation 1200 of FIG. 12 ends, returning to the completion of the process of FIG. 10 and / or FIG. 11.

[0083] FIG. 13 is a flow chart representing example machine-readable instructions and / or example operations 1300 that may be executed, instantiated, and / or performed by programmable circuitry to implement blocks 1106 and 1112 of FIG. 11. In other words, the example operations 1100 of FIG. 11 may be executed, instantiated, and / or performed by programmable circuitry to determine a final position for the lens along an axis of interest (e.g., a first axis associated with block 1106 and a second axis associated with block 1112). The example machine-readable instructions and / or example operations 1300 of FIG. 13 begin at block 1302, where the example alignment analyzer circuitry 810 defines a vector that passes through both the first and second peak power lens positions. At block 1304, the example lens position controller circuitry 806 moves the lens 108 (using the lens positioner 128) along a path defined by the vector. In block 1306, the exemplary optical power analyzer circuitry 808 monitors the optical power through each core 114 in the linear array while the lens 108 is being moved. In block 1308, the alignment analyzer circuitry 810 determines and stores (e.g., in memory 812) a final position for the lens along the axis of interest that corresponds to where the power is maximum. In some examples, this determination involves interpolating between the peak powers detected for adjacent ones of the cores 114. Specifically, this determination is similar to finding the peak power lens position associated with the point on the lines 708, 710, 712 at the top of the graph 700 in FIG. 7 that corresponds to the maximum point on the corresponding curves 702, 704, 706 at the bottom of the graph 700 in FIG. 7. The exemplary operation 1300 of FIG. 13 then ends, returning to the completion of the process of FIG. 11.

[0084] Figure 14 is a block diagram of an example programmable circuitry platform 1400 configured to execute and / or instantiate the example machine-readable instructions and / or example operations of Figures 9-13 to implement the alignment controller circuitry 118 of Figure 8. The programmable circuitry platform 1400 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., neural networks), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad), a personal digital assistant (PDA), an Internet appliance, or any other type of computing and / or electronic device.

[0085] The programmable circuitry platform 1400 of the illustrated example includes programmable circuitry 1412. The programmable circuitry 1412 of the illustrated example is hardware. For example, the programmable circuitry 1412 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuitry 1412 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuitry 1412 implements the exemplary communication interface circuitry 802, the exemplary fiber position controller circuitry 804, the exemplary lens position controller circuitry 806, the exemplary optical power analyzer circuitry 808, and the exemplary alignment analyzer circuitry 810.

[0086] The programmable circuitry 1412 of the illustrated example includes a local memory 1413 (e.g., cache, registers, etc.). The programmable circuitry 1412 of the illustrated example communicates with a main memory 1414, 1416 including a volatile memory 1414 and a non-volatile memory 1416 via a bus 1418. The volatile memory 1414 can be implemented with synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1416 may be implemented with flash memory and / or any other desired type of memory device. Access to the main memory 1414, 1416 of the illustrated example is controlled by a memory controller 1417. In some examples, the memory controller 1417 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer to manage the flow of data to and from the main memories 1414, 1416.

[0087] The programmable circuitry platform 1400 of the illustrated example also includes interface circuitry 1420. The interface circuitry 1420 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0088] In the depicted example, one or more input devices 1422 are coupled to the interface circuitry 1420. The input devices 1422 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 1412. The input devices 1422 may be implemented by, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touch screens, track pads, track balls, isopoint devices, and / or voice recognition systems.

[0089] One or more output devices 1424 are also connected to the interface circuitry 1420 of the illustrated example. The output device(s) 1424 may be implemented by, for example, a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. The interface circuitry 1420 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or graphics processor circuitry such as a GPU.

[0090] The interface circuitry 1420 of the illustrated example also includes communications devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external equipment (e.g., any type of computing device) over the network 1426. Communications may be by way of, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a non-line-of-sight wireless communication system, a line-of-sight wireless communication system, a cellular telephone system, an optical connection, etc.

[0091] The programmable circuit configuration platform 1400 of the illustrated example also includes one or more mass storage disks or devices 1428 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1428 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0092] The machine-readable instructions 1432 that may be implemented by the machine-readable instructions of Figures 9-13 may be stored in at least one non-transitory computer-readable storage medium, such as the mass storage device 1428, the volatile memory 1414, the non-volatile memory 1416, and / or a CD or DVD, which may be removable.

[0093] FIG. 15 is a block diagram of an exemplary implementation of the programmable circuitry 1412 of FIG. 14. In this example, the programmable circuitry 1412 of FIG. 14 is implemented by a microprocessor 1500. For example, the microprocessor 1500 may be a general-purpose microprocessor (e.g., general-purpose microprocessor circuitry). The microprocessor 1500 executes some or all of the machine-readable instructions of the flowcharts of FIGS. 9-13, effectively instantiating the circuitry of FIG. 8 as a logic circuit and performing operations corresponding to those machine-readable instructions. In some such examples, the circuitry of FIG. 8 is instantiated by the hardware circuitry of the microprocessor 1500 in combination with the machine-readable instructions. For example, the microprocessor 1500 may be implemented by a multi-core hardware circuitry such as a CPU, DSP, GPU, XPU, etc. Although any number of exemplary cores 1502 (e.g., one core) may be included, the microprocessor 1500 of this example is a multi-core semiconductor device including N cores. The cores 1502 of the microprocessor 1500 may operate independently or cooperate to execute machine-readable instructions. For example, a firmware program, an embedded software program, or machine code corresponding to a software program may be executed by one of the cores 1502, or may be executed by multiple cores 1502 at the same time or at different times. In some examples, the firmware program, the embedded software program, or machine code corresponding to a software program is divided into threads and executed in parallel by two or more cores 1502. The software program may correspond to some or all of the machine-readable instructions and / or operations represented by the flowcharts of FIGS. 9-13.

[0094] The cores 1502 may communicate via a first exemplary bus 1504. In some examples, the first bus 1504 may be implemented by a communication bus to achieve communication associated with one of the cores 1502. For example, the first bus 1504 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1504 may be implemented by any other type of computing or electrical bus. The cores 1502 may obtain data, instructions, and / or signals from one or more external devices via the exemplary interface circuitry 1506. The cores 1502 may output data, instructions, and / or signals to one or more external devices via the interface circuitry 1506. The cores 1502 in this example include an exemplary local memory 1520 (e.g., a level 1 (L1) cache, which may be divided into an L1 data cache and an L1 instruction cache), but the microprocessor 1500 also includes an exemplary shared memory 1510 (e.g., a level 2 (L2) cache) that may be shared by the cores for fast access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1510. The local memory 1520 and the shared memory 1510 of each core 1502 may be part of a hierarchy of storage devices that includes multiple levels of cache memories and main memories (e.g., main memories 1414, 1416 of FIG. 14). Typically, memories at higher levels in the hierarchy exhibit lower access times and smaller storage capacities than memories at lower levels. Changes in the cache hierarchy at various levels are managed (e.g., coordinated) by a cache coherency policy.

[0095] Each core 1502 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 1502 includes control unit circuitry 1514, arithmetic and logic (AL) circuitry (sometimes referred to as ALU) 1516, a number of registers 1518, a local memory 1520, and a second exemplary bus 1522. Other structures may exist. For example, each core 1502 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load / store unit (LSU) circuitry, branch / jump unit circuitry, floating point unit (FPU) circuitry, etc. The control unit circuitry 1514 includes semiconductor-based circuitry configured to control (e.g., coordinate) data movement within the corresponding core 1502. The AL circuitry 1516 includes semiconductor-based circuitry configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1502. In some examples, the AL circuitry 1516 performs integer-based operations. In other examples, the AL circuitry 1516 also performs floating-point operations. In yet other examples, the AL circuitry 1516 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, the AL circuitry 1516 may be referred to as an arithmetic logic unit (ALU).

[0096] The registers 1518 are semiconductor-based structures for storing data and / or instructions, such as results of one or more of the operations performed by the AL circuitry 1516 of the corresponding core 1502. For example, the registers 1518 may include vector registers, SIMD registers, general purpose registers, flag registers, segment registers, machine specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. The registers 1518 may be arranged in banks as shown in FIG. 15. Alternatively, the registers 1518 may be organized in any other arrangement, format, or structure, such as by being distributed throughout the core 1502 to reduce access time. The second bus 1522 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0097] Each core 1502 and / or microprocessor 1500 more generally may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergent / common mesh stops (CMS), one or more shifters (e.g., barrel shifters), and / or other circuitry. Microprocessor 1500 is a semiconductor device fabricated to include many transistor interconnects to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.

[0098] The microprocessor 1500 may include and / or interface with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, an accelerator is implemented by logic circuitry to perform a particular task more quickly and / or efficiently than can be performed by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. An accelerator may be on-board the microprocessor 1500 in the same chip package as the microprocessor 1500 and / or in one or more packages separate from the microprocessor 1500.

[0099] FIG. 16 is a block diagram of another example implementation of the programmable circuitry 1412 of FIG. 14. In this example, the programmable circuitry 1412 is implemented by an FPGA circuitry 1600. For example, the FPGA circuitry 1600 may be implemented by an FPGA. The FPGA circuitry 1600 may be used, for example, to perform operations that could otherwise be performed by the example microprocessor 1500 of FIG. 15 executing corresponding machine-readable instructions. However, once configured, the FPGA circuitry 1600 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware and may therefore often perform the operations / functions faster than could be performed by a general-purpose microprocessor executing corresponding software.

[0100] More specifically, in contrast to the microprocessor 1500 of FIG. 15 described above (which is a general-purpose device that may be programmed to execute some or all of the machine-readable instructions represented by the flowcharts of FIGS. 9-13, but which has fixed interconnect and logic circuitry once assembled), the example FPGA circuitry 1600 of FIG. 16 includes interconnect and logic circuitry that may be configured, structured, programmed, and / or interconnected in different ways after assembly, e.g., to instantiate some or all of the operations / functions corresponding to the machine-readable instructions represented by the flowcharts of FIGS. 9-13. In particular, the FPGA circuitry 1600 may be considered an array of logic gates, interconnects, and switches. The switches can be programmed to change the manner in which the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (unless the FPGA circuitry 1600 is reprogrammed). The configured logic circuits allow the logic gates to cooperate in different ways to perform different operations on data received by the input circuitry. Those operations may correspond to some or all of the instructions (e.g., software and / or firmware) represented by the flowcharts of Figures 9-13. As such, FPGA circuitry 1600 may be configured and / or constructed to effectively instantiate some or all of the operations / functions corresponding to the machine-readable instructions of the flowcharts of Figures 9-13 as special purpose logic circuitry to perform the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. As such, FPGA circuitry 1600 may perform the operations / functions corresponding to some or all of the machine-readable instructions of Figures 9-13 faster than a general purpose microprocessor could.

[0101] In the example of FIG. 16, the FPGA circuitry 1600 is configured and / or constructed in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program corresponding to one or more operations / functions in the HDL. The code / program may be translated into a low-level language as needed. The code / program (e.g., code / program in a low-level language) may be converted into a binary file (e.g., by a compiler, a software application, etc.). In some examples, the FPGA circuitry 1600 of FIG. 16 may access and / or load the binary file, such that the FPGA circuitry 1600 of FIG. 16 is configured and / or constructed to perform one or more operations / functions. For example, a binary file may be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions that are accessible to the FPGA circuitry 1600 of FIG. 16 to cause the configuration and / or structure of the FPGA circuitry 1600 of FIG. 16 or portions thereof.

[0102] In some examples, the binary file is compiled, generated, translated, and / or otherwise output from a uniform software platform utilized to program the FPGA. For example, the uniform software platform may translate first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output from the uniform software platform based on the second instructions. In some examples, the FPGA circuitry 1600 of FIG. 16 may access and / or load the binary file such that the FPGA circuitry 1600 of FIG. 16 is configured and / or constructed to perform one or more operations / functions. For example, a binary file may be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions that are accessible to the FPGA circuitry 1600 of FIG. 16 to cause the configuration and / or structure of the FPGA circuitry 1600 of FIG. 16 or portions thereof.

[0103] The FPGA circuitry 1600 of FIG. 16 includes exemplary input / output (I / O) circuitry 1602 for obtaining and / or outputting data to and from the exemplary configuration circuitry 1604 and / or external hardware 1606. For example, the configuration circuitry 1604 may be implemented by interface circuitry that may obtain a binary file that may be implemented by bitstreams, data, and / or machine-readable instructions to configure the FPGA circuitry 1600 or a portion thereof. In some such examples, the configuration circuitry 1604 may obtain the binary file from a user, a machine (e.g., hardware circuitry (e.g., programmable or dedicated circuitry) that may implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file, etc., and / or any combination thereof). In some examples, the external hardware 1606 may be implemented by external hardware circuitry. For example, the external hardware 1606 may be implemented by the microprocessor 1500 of FIG. 15.

[0104] The FPGA circuitry 1600 also includes an array of exemplary logic gate circuitry 1608, a plurality of exemplary configurable interconnects 1610, and exemplary storage circuitry 1612. The logic gate circuitry 1608 and the configurable interconnects 1610 are configurable to instantiate one or more operations / functions that may correspond to at least a portion of the machine-readable instructions of FIGS. 9-13 and / or other desired operations. The logic gate circuitry 1608 shown in FIG. 16 is assembled in blocks or groups. Each block includes semiconductor-based electrical structures that may be configured into a logic circuit. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide the basic building blocks of a logic circuit. Electrically controllable switches (e.g., transistors) are present in each of the logic gate circuitry 1608, enabling the configuration of the electrical structures and / or logic gates to form a circuit to perform a desired operation / function. The logic gate circuitry 1608 may include other electrical structures such as look-up tables (LUTs), registers (eg, flip-flops or latches), multiplexers, and the like.

[0105] The configurable interconnects 1610 in the depicted example are conductive paths, traces, vias, or the like that may include electrically controllable switches (e.g., transistors) whose state may be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 1608 to program a desired logic circuit.

[0106] The storage circuitry 1612 in the illustrated example is constructed to store one or more results of the operations performed by the corresponding logic gates. The storage circuitry 1612 may be implemented by registers, etc. In the illustrated example, the storage circuitry 1612 is distributed among the logic gate circuitry 1608 for ease of access and speed of execution.

[0107] The exemplary FPGA circuitry 1600 of FIG. 16 also includes exemplary dedicated operation circuitry 1614. In this example, the dedicated operation circuitry 1614 includes special purpose circuitry 1616 that may be called upon to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry 1616 include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry 1600 may also include exemplary general purpose programmable circuitry 1618, such as an exemplary CPU 1620 and / or an exemplary DSP 1622. There may additionally or alternatively be other general purpose programmable circuitry 1618 that may be programmed to perform other operations, such as a GPU, XPU, etc.

[0108] 15 and 16 show two example implementations of the programmable circuitry 1412 of FIG. 14, many other approaches are envisioned. For example, the FPGA circuitry may include an on-board CPU, such as one or more of the example CPUs 1620 of FIG. 15. Thus, the programmable circuitry 1412 of FIG. 14 may additionally be implemented by combining at least the example microprocessor 1500 of FIG. 15 and the example FPGA circuitry 1600 of FIG. 16. In some such hybrid examples, one or more cores 1502 of FIG. 15 may execute a first portion of the machine-readable instructions represented by the flowcharts of FIGS. 9-13 to perform a first operation / function, the FPGA circuitry 1600 of FIG. 16 may be configured and / or constructed to perform a second operation / function corresponding to a second portion of the machine-readable instructions represented by the flowcharts of FIGS. 9-13, and / or the ASIC may be configured and / or constructed to perform a third operation / function corresponding to a third portion of the machine-readable instructions represented by the flowcharts in FIGS. 9-13.

[0109] It should be understood that some or all of the circuitry of Figure 8 may thus be instantiated at the same time or at different times. For example, the same and / or different portions of microprocessor 1500 of Figure 15 may be programmed to execute portions of the machine-readable instructions at the same time and / or different times. In some examples, the same and / or different portions of FPGA circuitry 1600 of Figure 16 may be configured and / or constructed to perform operations / functions corresponding to portions of the machine-readable instructions at the same time and / or different times.

[0110] In some examples, some or all of the circuitry of FIG. 8 may be instantiated in one or more threads that execute simultaneously and / or sequentially, for example. For example, microprocessor 1500 of FIG. 15 may execute machine-readable instructions in one or more threads that execute simultaneously and / or sequentially. In some examples, FPGA circuitry 1600 of FIG. 16 may be configured and / or constructed to perform operations / functions simultaneously and / or sequentially. Also, in some examples, some or all of the circuitry of FIG. 8 may be implemented within one or more virtual machines and / or containers executing within microprocessor 1500 of FIG. 15.

[0111] In some examples, the programmable circuitry 1412 of FIG. 14 may be in one or more packages. For example, the microprocessor 1500 of FIG. 15 and / or the FPGA circuitry 1600 of FIG. 16 may be in one or more packages. In some examples, an XPU may be implemented by the programmable circuitry 1412 of FIG. 14, which may be in one or more packages. For example, an XPU may include a CPU (e.g., the microprocessor 1500 of FIG. 15, the CPU 1620 of FIG. 16, etc.) in one package, a DSP (e.g., the DSP 1622 of FIG. 16) in another package, a GPU in yet another package, and an FPGA (e.g., the FPGA circuitry 1600 of FIG. 16) in yet another package.

[0112] From the above, it is understood that exemplary systems, apparatus, products, and methods are disclosed that allow the fiber calibration process to be completed in a much lesser time than existing calibration techniques by reducing how far the reference fiber block to be calibrated needs to be moved. Specifically, in some examples, the fiber calibration process can be accomplished while moving the reference fiber block along only one of the three axes of the XYZ coordinate system (e.g., without moving the reference fiber block along the horizontal (X) and vertical (Z) axes). This is made possible by implementing the reference fiber block using a multi-core optical fiber having one or more linear arrays of cores. The examples disclosed herein also improve the lens alignment process (after the fiber calibration process) by allowing the variation of optical components of different production units to be compensated for in a manner not possible with existing lens alignment processes. Specifically, the linear array of multi-cores in the reference fiber block provides multiple data points that allow for interpolating an advantageous (e.g., optimal) position for the lens, regardless of the variation in lenses, lasers, and / or other factors between different production units. The disclosed systems, apparatus, products, and methods thus relate to one or more improvements in the operation of a machine, such as a computer or other electronic and / or mechanical device.

[0113] Further examples and combinations thereof include:

[0114] Example 1 shows the interface circuit configuration; machine-readable instructions; and monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and determining a final position for the lens relative to the photonic integrated circuit based on the optical power output; A programmable circuit arrangement for at least one of instantiating or executing machine-readable instructions for The present invention includes an apparatus comprising:

[0115] Example 2 includes the apparatus of Example 1, wherein the multi-core optical fiber is associated with a reference fiber block, and the programmable circuit configuration is for determining a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction.

[0116] Example 3 includes the apparatus of Example 2, wherein the programmable circuit configuration is for determining the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction.

[0117] Example 4 includes the apparatus of example 1, wherein the programmable circuitry: determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and A vector is defined along the linear array of cores based on the first lens position and the second lens position, and movement of the lens follows a path defined by the vector.

[0118] Example 5 includes the apparatus of example 4, wherein the programmable circuitry: determining the ratio of the change in fiber core offset distance to the change in lens offset distance; and A maximum peak power for the path is determined, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens is determined based on the ratio and the maximum peak power.

[0119] Example 6 includes the apparatus of example 5, wherein the ratio is a first ratio, the maximum peak power is a first maximum peak power, and the programmable circuitry is: determining other ratios of changes in other fiber core offset distances along other paths of the lens to changes in other lens offset distances along corresponding ones of the other paths; determining another highest peak power for the other path, the first ratio and the first highest peak power associated with the multi-core optical fiber at a first distance from the photonic integrated circuit, the other ratio and the other highest peak power associated with the multi-core optical fiber at another distance from the photonic integrated circuit, the other distance different from the first distance; determining a calibration depth position for the multi-core optical fiber based on the first ratio and the other ratio and based on the first highest peak power and the other highest peak power; and When the multi-core optical fiber is fixed at the calibrated depth position, the final position for the lens is determined.

[0120] Example 7 includes the apparatus of example 4, wherein the programmable circuitry interpolates the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power.

[0121] Example 8 includes the apparatus of example 1, wherein the programmable circuitry moves the lens to the final position to facilitate attachment of the lens to the photonic integrated circuit.

[0122] Example 9 includes the apparatus of example 1, further comprising a multi-core optical fiber.

[0123] Example 10 includes the device of Example 9, wherein the linear array of cores is a first linear array extending in a first direction across a cross-section of the multicore optical fiber, and the multicore optical fiber includes a second linear array of cores extending in a second direction transverse to the first direction.

[0124] Example 11 includes the device of Example 9, where adjacent ones of the cores in the linear array of cores are spaced 35 μm or less apart.

[0125] Example 12 provides a programmable circuit configuration including at least: monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and determining a final position for the lens relative to the photonic integrated circuit based on the optical power output; The present invention includes a non-transitory machine-readable storage medium that includes instructions for causing the

[0126] Example 13 includes the non-transitory machine-readable storage medium of Example 12, wherein the multi-core optical fiber is associated with a reference fiber block, and the instructions cause the programmable circuit configuration to determine a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction.

[0127] Example 14 includes the non-transitory machine-readable storage medium of Example 13, wherein the instructions cause the programmable circuit configuration to determine the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction.

[0128] Example 15 includes the non-transitory machine-readable storage medium of example 12, wherein the instructions cause the programmable circuitry to: determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, the movement of the lenses following a path defined by the vector. Have them carry out the procedure.

[0129] Example 16 includes the non-transitory machine-readable storage medium of example 15, wherein the instructions cause the programmable circuitry to: Determining the ratio of the change in fiber core offset distance to the change in lens offset distance; and A maximum peak power for the path is determined, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens is determined based on the ratio and the maximum peak power.

[0130] Example 17 includes the non-transitory machine-readable storage medium of example 16, wherein the ratio is a first ratio, the maximum peak power is a first maximum peak power, and the instructions to the programmable circuit configuration: determining other ratios of changes in other fiber core offset distances along other paths of the lens to changes in other lens offset distances along corresponding ones of the other paths; determining another highest peak power for the other path, the first ratio and the first highest peak power associated with the multi-core optical fiber at a first distance from the photonic integrated circuit, the other ratio and the other highest peak power associated with the multi-core optical fiber at another distance from the photonic integrated circuit, the other distance different from the first distance; determining a calibration depth position for the multi-core optical fiber based on the first ratio and the other ratio and based on the first highest peak power and the other highest peak power; and determining the final position for the lens when the multi-core optical fiber is fixed at the calibration depth position; Have them carry out the procedure.

[0131] Example 18 includes the non-transitory machine-readable storage medium of example 15, wherein the instructions cause the programmable circuitry to interpolate the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power.

[0132] Example 19 includes monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and Fixing a final position for the lens relative to the photonic integrated circuit based on the optical power output. The method includes the steps of:

[0133] Example 20 includes the method of Example 19, wherein the multi-core optical fiber is associated with a reference fiber block, and the method further includes determining a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction.

[0134] Example 21 includes the method of Example 20, further comprising determining the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction.

[0135] Example 22 includes the method of example 19, further comprising: determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, and the movement of the lenses follows a path defined by the vector. It further comprises:

[0136] Example 23 includes the method of example 22, further comprising: determining a ratio of a change in fiber core offset distance to a change in lens offset distance; and determining a maximum peak power for the path, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens being determined based on the ratio and the maximum peak power. It further comprises:

[0137] Example 24 includes the method of example 23, wherein the ratio is a first ratio and the maximum peak power is a first maximum peak power, the method further comprising: determining other ratios of changes in other fiber core offset distances along other paths of the lens to changes in other lens offset distances along corresponding ones of the other paths; determining another highest peak power for the other path, the first ratio and the first highest peak power associated with the multi-core optical fiber at a first distance from the photonic integrated circuit, the other ratio and the other highest peak power associated with the multi-core optical fiber at another distance from the photonic integrated circuit, the other distance being different from the first distance; determining a calibration depth position for the multi-core optical fiber based on the first ratio and the other ratio and based on the first highest peak power and the other highest peak power; and determining the final position for the lens when the multi-core optical fiber is fixed at the calibrated depth position; Equipped with.

[0138] Example 25 includes the method of example 22, further comprising: interpolating the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power.

[0139] Example 26 shows an interface circuit configuration; machine-readable instructions; and determining different peak powers detected through different cores of a multi-core optical fiber, each of the different cores extending along a first axis of an XYZ coordinate system, the cores being distributed in two dimensions corresponding to a second axis and a third axis of the XYZ coordinate system, the first axis being orthogonal to the second and third axes, the second axis being orthogonal to the third axis, the different peak powers detected through the different cores based on light from a photonic integrated circuit passing through a lens, the different peak powers being based on movement of the multi-core fiber along only one of the first axis, the second axis, or the third axis; and determining a final position for the lens relative to the photonic integrated circuit based on the different peak powers; a programmable circuit configuration for at least one of instantiating or executing the machine-readable instructions for The present invention includes an apparatus comprising:

[0140] Example 27 includes the apparatus of example 26, wherein the different peak power is based on moving the multicore fiber along only the first axis.

[0141] Example 28 includes the apparatus of example 27, wherein the different sets of different peak powers are detected at different fixed positions along the first axis while moving a lens relative to the multicore fiber.

[0142] The following claims are hereby incorporated by reference into this detailed description. Although certain exemplary systems, apparatus, products, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, products, and methods that fall even slightly within the scope of the claims. [Other possible items] (Item 1) Interface circuit configuration; machine-readable instructions; and monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and determining a final position for the lens relative to the photonic integrated circuit based on the optical power output; A programmable circuit arrangement for at least one of instantiating or executing machine-readable instructions for An apparatus comprising: (Item 2) 2. The apparatus of claim 1, wherein the multi-core optical fiber is associated with a reference fiber block, and the programmable circuit configuration is for determining a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction. (Item 3) 3. The apparatus of claim 2, wherein the programmable circuit configuration is for determining the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction. (Item 4) The programmable circuitry comprises: determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, and the movement of the lenses follows a path defined by the vector. Item 1. The device according to item 1. (Item 5) The programmable circuitry comprises: determining the ratio of the change in fiber core offset distance to the change in lens offset distance; and determining a maximum peak power for the path, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens is determined based on the ratio and the maximum peak power. 5. The apparatus according to item 4. (Item 6) the ratio is a first ratio, the maximum peak power is a first maximum peak power, and the programmable circuitry is: determining other ratios of changes in other fiber core offset distances along other paths of the lens to changes in other lens offset distances along corresponding ones of the other paths; determining another highest peak power for the other path, the first ratio and the first highest peak power associated with the multi-core optical fiber at a first distance from the photonic integrated circuit, the other ratio and the other highest peak power associated with the multi-core optical fiber at another distance from the photonic integrated circuit, the other distance different from the first distance; determining a calibration depth position for the multi-core optical fiber based on the first ratio and the other ratio and based on the first highest peak power and the other highest peak power; and determining the final position for the lens when the multi-core optical fiber is fixed at the calibration depth position; Item 5. The device according to item 5. (Item 7) Item 5. The apparatus of item 4, wherein the programmable circuitry interpolates the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power. (Item 8) 2. The apparatus of claim 1, wherein the programmable circuitry moves the lens to the final position to facilitate attachment of the lens to the photonic integrated circuit. (Item 9) Item 1, further comprising the multi-core optical fiber. (Item 10) 10. The apparatus of claim 9, wherein the linear array of cores is a first linear array extending in a first direction across a cross-section of the multicore optical fiber, and the multicore optical fiber includes a second linear array of cores extending in a second direction transverse to the first direction. (Item 11) 10. The device of claim 9, wherein adjacent ones of the cores in the linear array of cores are spaced 35 μm or less apart. (Item 12) Programmable circuit configuration includes at least: monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and determining a final position for the lens relative to the photonic integrated circuit based on the optical power output; A non-transitory machine-readable storage medium containing instructions for causing a (Item 13) Item 13. The non-transitory machine-readable storage medium of item 12, wherein the multi-core optical fiber is associated with a reference fiber block, and the instructions cause the programmable circuit configuration to determine a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction. (Item 14) Item 14. The non-transitory machine-readable storage medium of item 13, wherein the instructions cause the programmable circuit configuration to determine the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction. (Item 15) The instructions to the programmable circuitry: determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, the movement of the lenses following a path defined by the vector. 13. The non-transitory machine-readable storage medium of item 12, (Item 16) The instructions to the programmable circuitry: Determining the ratio of the change in fiber core offset distance to the change in lens offset distance; and determining a maximum peak power for the path, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens is determined based on the ratio and the maximum peak power. Item 16. The non-transitory machine-readable storage medium of item 15. (Item 17) The ratio is a first ratio, the maximum peak power is a first maximum peak power, and the instructions to the programmable circuitry: determining other ratios of changes in other fiber core offset distances along other paths of the lens to changes in other lens offset distances along corresponding ones of the other paths; determining another highest peak power for the other path, the first ratio and the first highest peak power associated with the multi-core optical fiber at a first distance from the photonic integrated circuit, the other ratio and the other highest peak power associated with the multi-core optical fiber at another distance from the photonic integrated circuit, the other distance different from the first distance; determining a calibration depth position for the multi-core optical fiber based on the first ratio and the other ratio and based on the first highest peak power and the other highest peak power; and determining the final position for the lens when the multi-core optical fiber is fixed at the calibration depth position; 17. The non-transitory machine-readable storage medium of item 16, (Item 18) Item 16. The non-transitory machine-readable storage medium of item 15, wherein the instructions cause the programmable circuitry to interpolate the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power. (Item 19) monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and Fixing a final position for the lens relative to the photonic integrated circuit based on the optical power output. A method for providing the above. (Item 20) 20. The method of claim 19, wherein the multi-core optical fiber is associated with a reference fiber block, and the method further comprises determining a calibration position for the reference fiber block based on a movement of the reference fiber block in a first direction, without moving the reference fiber block in any direction transverse to the first direction. (Item 21) 21. The method of claim 20, further comprising determining the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction. (Item 22) determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, the movement of the lenses following a path defined by the vector. 20. The method of claim 19, further comprising: (Item 23) determining a ratio of a change in fiber core offset distance to a change in lens offset distance; and determining a maximum peak power for the path, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens being determined based on the ratio and the maximum peak power. 23. The method of claim 22, further comprising: (Item 24) The ratio is a first ratio and the highest peak power is a first highest peak power, and the method further comprises: determining other ratios of changes in other fiber core offset distances along other paths of the lens to changes in other lens offset distances along corresponding ones of the other paths; determining another highest peak power for the other path, the first ratio and the first highest peak power associated with the multi-core optical fiber at a first distance from the photonic integrated circuit, the other ratio and the other highest peak power associated with the multi-core optical fiber at another distance from the photonic integrated circuit, the other distance being different from the first distance; determining a calibration depth position for the multi-core optical fiber based on the first ratio and the other ratio and based on the first highest peak power and the other highest peak power; and determining the final position for the lens when the multi-core optical fiber is fixed at the calibrated depth position; 24. The method of claim 23, comprising: (Item 25) 23. The method of claim 22, further comprising: interpolating the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power. (Item 26) Interface circuit configuration; machine-readable instructions; and determining different peak powers detected through different cores of a multi-core optical fiber, each of the different cores extending along a first axis of an XYZ coordinate system, the cores being distributed in two dimensions corresponding to a second axis and a third axis of the XYZ coordinate system, the first axis being orthogonal to the second and third axes, the second axis being orthogonal to the third axis, the different peak powers detected through the different cores based on light from a photonic integrated circuit passing through a lens, the different peak powers being based on movement of the multi-core fiber along only one of the first axis, the second axis, or the third axis; and determining a final position for the lens relative to the photonic integrated circuit based on the different peak powers; a programmable circuit configuration for at least one of instantiating or executing the machine-readable instructions for An apparatus comprising: (Item 27) Item 27. The apparatus of item 26, wherein the different peak powers are based on a movement of the multicore fiber along only the first axis. (Item 28) Item 28. The apparatus of item 27, wherein the different sets of different peak powers are detected at different fixed positions along the first axis while moving a lens relative to the multicore fiber.

Claims

1. Interface circuit configuration; machine-readable instructions; and monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and determining a final position for the lens relative to the photonic integrated circuit based on the optical power output; a programmable circuit configuration for at least one of instantiating or executing the machine-readable instructions for An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the multi-core optical fiber is associated with a reference fiber block, and the programmable circuit configuration is for determining a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction.

3. 3. The apparatus of claim 2, wherein the programmable circuitry is for determining the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction.

4. The programmable circuitry comprises: determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, and the movement of the lenses follows a path defined by the vector.

2. The apparatus of claim 1.

5. The programmable circuitry comprises: Determining the ratio of the change in fiber core offset distance to the change in lens offset distance; and determining a maximum peak power for the path, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens is determined based on the ratio and the maximum peak power.

5. The apparatus of claim 4.

6. the ratio is a first ratio, the maximum peak power is a first maximum peak power, and the programmable circuitry is: determining other ratios of changes in other fiber core offset distances along other paths of the lens to changes in other lens offset distances along corresponding ones of the other paths; determining another highest peak power for the other path, the first ratio and the first highest peak power associated with the multi-core optical fiber at a first distance from the photonic integrated circuit, the other ratio and the other highest peak power associated with the multi-core optical fiber at another distance from the photonic integrated circuit, the other distance different from the first distance; determining a calibration depth position for the multi-core optical fiber based on the first ratio and the other ratio and based on the first highest peak power and the other highest peak power; and determining the final position for the lens when the multi-core optical fiber is fixed at the calibration depth position; 6. The apparatus of claim 5.

7. 5. The apparatus of claim 4, wherein the programmable circuitry interpolates the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power.

8. 8. The apparatus of claim 1, wherein the programmable circuitry moves the lens to the final position to facilitate attachment of the lens to the photonic integrated circuit.

9. The apparatus of claim 1 , further comprising the multi-core optical fiber.

10. 10. The apparatus of claim 9, wherein the linear array of cores is a first linear array extending in a first direction across a cross-section of the multicore optical fiber, and the multicore optical fiber includes a second linear array of cores extending in a second direction transverse to the first direction.

11. 10. The device of claim 9, wherein adjacent ones of the cores in the linear array of cores are spaced 35 μm or less apart.

12. When implemented by programmable circuitry, The programmable circuitry comprises at least: monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and determining a final position for the lens relative to the photonic integrated circuit based on the optical power output; A program having instructions to perform the above.

13. 13. The program of claim 12, wherein the multi-core optical fiber is associated with a reference fiber block, and the instructions cause the programmable circuit configuration to determine a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction.

14. 14. The program of claim 13, wherein the instructions cause the programmable circuitry to determine the calibration position for the reference fiber block based on different peak power outputs detected along the linear array of cores at different depth positions for the reference fiber block relative to the photonic integrated circuit, the different depth positions corresponding to different points along the first direction.

15. The instructions to the programmable circuitry: determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, the movement of the lenses following a path defined by the vector. The program according to claim 12,

16. The instructions to the programmable circuitry: Determining the ratio of the change in fiber core offset distance to the change in lens offset distance; and determining a maximum peak power for the path, the maximum peak power corresponding to a highest value detected for the optical power output, and the final position for the lens being determined based on the ratio and the maximum peak power. The program according to claim 15.

17. 16. The program of claim 15, wherein the instructions cause the programmable circuitry to interpolate the final position for the lens between the first lens position and the second lens position based on a maximum point on a curve fit to a plot of the first peak power and the second peak power.

18. monitoring optical power outputs of different cores in a linear array of cores in a multi-core optical fiber while a lens is moved relative to the multi-core optical fiber, the optical power outputs being based on light emitted from a photonic integrated circuit and passing through the lens; and Fixing a final position for the lens relative to the photonic integrated circuit based on the optical power output. A method for providing the above.

19. 20. The method of claim 18, wherein the multi-core optical fiber is associated with a reference fiber block, the method further comprising determining a calibration position for the reference fiber block based on movement of the reference fiber block in a first direction, without movement of the reference fiber block in any direction transverse to the first direction.

20. determining a first lens position corresponding to a first peak power associated with a first core in the linear array of cores; determining a second lens position corresponding to a second peak power associated with a second core in the linear array of cores; and defining a vector along the linear array of cores based on the first lens position and the second lens position, the movement of the lenses following a path defined by the vector.

20. The method of claim 18 or 19, further comprising:

21. A machine-readable storage medium storing a program according to any one of claims 12 to 17.

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