Semiconductor device

Abstract

To provide a semiconductor device capable of improving reliability and an electric characteristic.SOLUTION: A semiconductor device according to the present invention, comprises: a substrate containing an active pattern; and a channel pattern onto the active pattern. Here, the channel pattern contains a plurality of semiconductor patterns laminated so as to be separated each other, and includes: a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode that is crossed to the channel pattern, and is extended to a first direction. Here, the gate electrode includes an inner side gate electrode interposed between a first semiconductor pattern and a second semiconductor pattern that are adjacent each other in the plurality of semiconductor patterns, and includes an inner side gate spacer interposed between the inner side gate electrode and the source / drain pattern. The inner side gate spacer includes a center part and an edge part that is adjacent to the first direction on one side of the center part. The center part has a first thickness to a second direction crossed to the first direction. The edge part has a second thickness to the second direction, and a first thickness is thicker than the second thickness.SELECTED DRAWING: Figure 6B

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including field effect transistors. [Background technology]

[0002] The semiconductor device includes an integrated circuit configured with MOS field effect transistors (MOS (Metal Oxide Semiconductor) FETs). 2. Description of the Related Art As the size and design rules of semiconductor devices continue to shrink, the scale down of MOS field effect transistors is also accelerating.

[0003] There is a problem that the operating characteristics of semiconductor elements deteriorate as the size of MOS field effect transistors decreases. Therefore, various methods are being researched to overcome the limitations imposed by the high integration of semiconductor devices and to form semiconductor devices with superior performance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 11,309,421 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems in the conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device having improved reliability and electrical characteristics. [Means for solving the problem]

[0006] In order to achieve the above object, a semiconductor device according to the present invention includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of stacked semiconductor patterns spaced apart from each other, a source / drain pattern connected to the plurality of semiconductor patterns, and a gate electrode extending in a first direction across the channel pattern, the gate electrode including an inner gate electrode interposed between a first semiconductor pattern and a second semiconductor pattern adjacent to each other among the plurality of semiconductor patterns, and an inner gate spacer interposed between the inner gate electrode and the source / drain pattern, the inner gate spacer including a central portion and an edge portion adjacent to one side of the central portion in the first direction, the central portion having a first thickness in a second direction intersecting the first direction, and the edge portion having a second thickness in the second direction, the first thickness being greater than the second thickness.

[0007] a gate electrode extending in a first direction across the channel pattern, the gate electrode including an inner gate electrode interposed between a first semiconductor pattern and a second semiconductor pattern adjacent to each other among the plurality of semiconductor patterns, an inner gate spacer interposed between the inner gate electrode and the source / drain pattern, and an inner high dielectric layer between the inner gate electrode and the inner gate spacer, the inner gate spacer including a first portion and a second portion adjacent to one side of the first portion in the first direction, the first portion including a first outer side in contact with the inner high dielectric layer, and the second portion including a second outer side in contact with the inner high dielectric layer, the first outer side being recessed further toward the inner gate electrode than the second outer side.

[0008] According to another embodiment of the present invention, there is provided a semiconductor device comprising: a substrate including an active region; an isolation layer defining an active pattern on the active region; a channel pattern and a source / drain pattern on the active pattern; wherein the channel pattern comprises a plurality of semiconductor patterns vertically stacked apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; and a gate electrode extending in a first direction across the channel pattern; wherein the gate electrode comprises an inner gate electrode interposed between first and second semiconductor patterns adjacent to each other among the plurality of semiconductor patterns; the inner gate insulating film includes an inner gate spacer interposed between the inner gate electrode and the source / drain pattern, an inner high dielectric film between the inner gate electrode and the inner gate spacer, and a gate spacer on a sidewall of the gate electrode, the inner gate spacer including a first edge portion, a second edge portion spaced apart from the first edge portion in a first direction, and a center portion between the first edge portion and the second edge portion, the thickness of the inner gate spacer increasing from the first edge portion to the center portion and reaching a maximum value at the center portion, and then decreasing from the center portion to the second edge portion. Effect of the Invention

[0009] In the semiconductor device according to the present invention, the gate insulating film of the three-dimensional field effect transistor may include an inner gate spacer capable of preventing leakage current of the gate. In plan view, the thickness of the inner gate spacer can decrease from the center portion to the edge portion. Therefore, the inner gate electrode can be filled uniformly and stably. As a result, the electrical characteristics of the semiconductor device according to the present invention are improved. [Brief description of the drawings]

[0010] [Figure 1]1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a plan view illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 5A] 5 is a cross-sectional view taken along line AA' in FIG. 4. [Figure 5B] 5 is a cross-sectional view taken along line BB' in FIG. 4. [Figure 5C] 5 is a cross-sectional view taken along line CC' in FIG. 4. [Figure 5D] 5 is a cross-sectional view taken along line DD' in FIG. 4. [Figure 6A] FIG. 5B is an enlarged view of an embodiment of region M of FIG. 5A. [Figure 6B] FIG. 5C is a cross-sectional view taken along line XX' in FIG. 5B. [Figure 7A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10A]1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10D] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14B] 1A to 1C are views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15B] 1A to 1C are views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16B]1A to 1C are views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17B] 1A to 1C are views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] FIG. 5C is a cross-sectional view taken along line XX' of FIG. 5B, showing another embodiment of the present invention. [Figure 19] FIG. 5C is a cross-sectional view taken along line XX' of FIG. 5B, showing another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out a semiconductor device according to the present invention will be described with reference to the drawings.

[0012] 1 to 3 are conceptual diagrams illustrating a logic cell of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, a Single Height Cell (SHC) is provided. Specifically, a first power wiring (M1_R1) and a second power wiring (M1_R2) are provided on a substrate 100. The first power wiring (M1_R1) is a path through which a source voltage VSS, for example a ground voltage, is provided. The second power wiring (M1_R2) is a path through which a drain voltage VDD, for example a power voltage, is provided.

[0013] A single height cell SHC is defined between the first power wiring (M1_R1) and the second power wiring (M1_R2). The single height cell SHC includes one first active area AR1 and one second active area AR2. Any one of the first and second active regions (AR1, AR2) is a PMOSFET region, and the other of the first and second active regions (AR1, AR2) is an NMOSFET region. That is, the single height cell SHC has a CMOS structure provided between a first power wiring (M1_R1) and a second power wiring (M1_R2). For example, the first active area AR1 is an NMOSFET area, and the second active area AR2 is a PMOSFET area.

[0014] Each of the first and second active regions AR1 and AR2 has a single width W_SHC in a first direction D1. The length of the single height cell SHC in the first direction D1 is defined as a first height HE1. The first height HE1 is substantially the same as the distance (eg, pitch) between the first power wiring (M1_R1) and the second power wiring (M1_R2). The single height cell SHC constitutes one logic cell. In this specification, a logic cell refers to a logic element (eg, AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic cell includes transistors for forming a logic element and wiring for connecting the transistors to each other.

[0015] Referring to FIG. 2, a double height cell (DHC) is provided. Specifically, a first power wiring (M1_R1), a second power wiring (M1_R2), and a third power wiring (M1_R3) are provided on a substrate 100. The first power wiring (M1_R1) is disposed between the second power wiring (M1_R2) and the third power wiring (M1_R3). The third power wiring (M1_R3) is a path through which the source voltage VSS is provided. A double height cell DHC is defined between the second power wiring (M1_R2) and the third power wiring (M1_R3). The double height cell DHC includes two first active areas AR1 and two second active areas AR2.

[0016] One of the two second active regions AR2 is adjacent to the second power wiring (M1_R2). The other of the two second active regions AR2 is adjacent to the third power wiring (M1_R3). The two first active regions AR1 are adjacent to the first power wiring (M1_R1). In a plan view, the first power wiring (M1_R1) is disposed between the two first active regions AR1. The length of the double height cell DHC in the first direction D1 is defined as a second height HE2. The second height HE2 may be approximately twice the first height HE1 of FIG. The two first active regions AR1 of the double-height cell DHC are bundled together and operate as one active region. In the present invention, the double height cell DHC shown in FIG. 2 is defined as a multi-height cell. Although not shown in the figure, the multi-height cells may include triple-height cells, which have a cell height approximately three times that of the single-height cells SHC.

[0017] Referring to FIG. 3, a first single height cell SHC1, a second single height cell SHC2, and a double height cell DHC are two-dimensionally arranged on a substrate 100. As shown in FIG. The first single height cell SHC1 is disposed between the first and second power wirings (M1_R1, M1_R2). The second single height cell SHC2 is disposed between the first and third power wirings (M1_R1, M1_R3). The second single height cell SHC2 is adjacent to the first single height cell SHC1 in the first direction D1. The double height cell DHC is disposed between the second and third power wirings (M1_R2, M1_R3). The double height cell DHC is adjacent to the first and second single height cells (SHC1, SHC2) in the second direction D2. Isolation structures DB are provided between the first single height cell SHC1 and the double height cell DHC, and between the second single height cell SHC2 and the double height cell DHC. The active area of ​​the double height cell DHC is electrically isolated from the active areas of each of the first and second single height cells (SHC1, SHC2) by the isolation structure DB.

[0018] FIG. 4 is a plan view for explaining the schematic configuration of a semiconductor element according to an embodiment of the present invention, FIGS. 5A to 5D are cross-sectional views taken along lines A-A', B-B', CC', and D-D' in FIG. 4, respectively, FIG. 6A is an enlarged view showing one embodiment of region M in FIG. 5A, and FIG. 6B is a cross-sectional view taken along line X-X' in FIG. 5B. The semiconductor device shown in FIG. 4 and FIGS. 5A to 5D is a more specific example of the single height cell SHC of FIG.

[0019] 4 and 5A to 5D, a single height cell SHC is provided on a substrate 100. As shown in FIG. Logic transistors that constitute a logic circuit are disposed on the single height cell SHC. The substrate 100 may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., or may be a compound semiconductor substrate. As an example, the substrate 100 can be a silicon substrate. The substrate 100 includes a first active area AR1 and a second active area AR2. Each of the first and second active regions AR1 and AR2 extends in a second direction D2. In one embodiment, the first active area AR1 is an NMOSFET area and the second active area AR2 is a PMOSFET area.

[0020] A first active pattern AP1 and a second active pattern AP2 are defined by trenches TR formed in the upper portion of the substrate 100. A first active pattern AP1 is provided on the first active area AR1, and a second active pattern AP2 is provided on the second active area AR2. The first and second active patterns AP1 and AP2 extend in a second direction D2. The first and second active patterns AP1 and AP2 are parts of the substrate 100 that protrude vertically. An element isolation film ST is provided on a substrate 100 . The element isolation film ST fills the trench TR. The element isolation film ST includes a silicon oxide film. The element isolation film ST does not cover first and second channel patterns CH1 and CH2, which will be described later.

[0021] A first channel pattern CH1 is provided on the first active pattern AP1. A second channel pattern CH2 is provided on the second active pattern AP2. Each of the first and second channel patterns CH1 and CH2 includes a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 which are sequentially stacked. The first to third semiconductor patterns SP1, SP2, and SP3 are spaced apart from each other in a vertical direction (ie, a third direction D3). Each of the first to third semiconductor patterns (SP1, SP2, SP3) may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns (SP1, SP2, SP3) may include crystalline silicon. As an embodiment of the present invention, the first to third semiconductor patterns (SP1, SP2, SP3) may be stacked nanosheets.

[0022] A plurality of first source / drain patterns SD1 are provided on the first active pattern AP1. A plurality of first recesses RS1 are formed on the first active pattern AP1. First source / drain patterns SD1 are respectively provided in the first recesses RS1. The first source / drain pattern SD1 is a first conductive type (eg, n-type) impurity region. A first channel pattern CH1 is interposed between a pair of first source / drain patterns SD1. That is, the stacked first to third semiconductor patterns (SP1, SP2, SP3) connect the pair of first source / drain patterns SD1 to each other.

[0023] A plurality of second source / drain patterns SD2 are provided on the second active pattern AP2. A plurality of second recesses RS2 are formed on the second active pattern AP2. Second source / drain patterns SD2 are respectively provided in the second recesses RS2. The second source / drain pattern SD2 is a second conductive type (eg, p-type) impurity region. A second channel pattern CH2 is interposed between a pair of second source / drain patterns SD2. That is, the stacked first to third semiconductor patterns (SP1, SP2, SP3) connect the pair of second source / drain patterns SD2 to each other.

[0024] The first and second source / drain patterns SD1 and SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the top surface of each of the first and second source / drain patterns SD1 and SD2 is higher than the top surface of the third semiconductor pattern SP3. As another example, a top surface of at least one of the first and second source / drain patterns SD1 and SD2 may be located at substantially the same level as a top surface of the third semiconductor pattern SP3.

[0025] In one embodiment of the present invention, the first source / drain pattern SD1 includes the same semiconductor element as the substrate 100 (eg, Si). The second source / drain pattern SD2 includes a semiconductor element (eg, SiGe) having a lattice constant larger than that of the semiconductor element of the substrate 100. Thus, the pair of second source / drain patterns SD2 provides a compressive stress to the second channel pattern CH2 therebetween. The sidewalls of each of the first and second source / drain patterns SD1 and SD2 have an uneven embossing shape. That is, the sidewalls of each of the first and second source / drain patterns SD1, SD2 have a corrugated profile. Each sidewall of the first and second source / drain patterns SD1 and SD2 protrudes toward first to third portions PO1, PO2, and PO3 of a gate electrode GE, which will be described later.

[0026] A gate electrode GE is provided extending in a first direction D1 across the first and second channel patterns CH1 and CH2. The gate electrodes GE are arranged in the second direction D2 according to the first pitch. Each gate electrode GE vertically overlaps the first and second channel patterns CH1 and CH2. The gate electrode GE includes a first portion PO1 interposed between the active pattern (AP1 or AP2) and the first semiconductor pattern SP1, a second portion PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0027] Referring to FIG. 5D, a gate electrode GE is provided on a top surface TS, a bottom surface BS and both side walls SW of each of the first to third semiconductor patterns (SP1, SP2, SP3). That is, the transistor according to this embodiment is a three-dimensional field effect transistor (for example, MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel. Referring again to FIG. 4 and FIG. 5A to FIG. 5D, a pair of gate spacers GS are disposed on both sidewalls of the fourth portion PO4 of the gate electrode GE, respectively. The gate spacer GS extends in a first direction D1 along the gate electrode GE. The upper surface of the gate spacer GS is higher than the upper surface of the gate electrode GE. The upper surface of the gate spacer GS is coplanar with the upper surface of a first interlayer insulating film 110, which will be described later. In one embodiment, the gate spacer GS may include at least one of SiCN, SiCON, and SiN. In another embodiment, the gate spacer GS may include a multi-layer made of at least two of SiCN, SiCON, and SiN.

[0028] A gate capping pattern GP is provided on the gate electrode GE. The gate capping pattern GP extends in a first direction D1 along the gate electrode GE. The gate capping pattern GP includes a material having an etch selectivity with respect to the first and second interlayer insulating films 110 and 120 described below. Specifically, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN. A gate insulating film GI is interposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI covers the top surface TS, bottom surface BS, and both side walls SW of each of the first to third semiconductor patterns (SP1, SP2, SP3). The gate insulating film GI covers the upper surface of the element isolation film ST below the gate electrode GE.

[0029] As an embodiment of the present invention, referring to FIG. 6A, a gate insulating film GI includes an inner spacer IS and a high dielectric film HK. In one embodiment, the inner spacer IS includes an inner gate spacer IGS and an outer gate spacer OGS. Each of the inner gate spacer IGS and the outer gate spacer OGS includes an insulating material containing silicon (Si). Each of the inner gate spacer IGS and the outer gate spacer OGS may include a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.

[0030] The high dielectric film HK includes a high dielectric constant material having a higher dielectric constant than a silicon oxide film. As an example, the high dielectric film HK may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In another embodiment, the semiconductor device of the present invention includes a NC (Negative Capacitance) FET using a negative capacitor.

[0031] For example, the high dielectric film HK includes a ferroelectric material film having ferroelectric properties, a paraelectric material film having paraelectric properties, or a combination thereof. The ferroelectric material film has a negative capacitance, and the paraelectric material film has a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance will be less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance has a positive value and is greater than the absolute value of each individual capacitance. When a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the overall capacitance value of the ferroelectric material film and the paraelectric material film connected in series increases. By taking advantage of the increased overall capacitance, a transistor including a ferroelectric material film has a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0032] The ferroelectric material film has ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide is a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide is a compound of hafnium (Hf), zirconium (Zr) and oxygen (O).

[0033] The ferroelectric material film further includes a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium GE, scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant contained in the ferroelectric material film varies depending on the type of ferroelectric material contained in the ferroelectric material film. When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). When the dopant is aluminum (Al), the ferroelectric material film contains 3 to 8 at % (atomic %) of aluminum. Here, the dopant ratio is the ratio of aluminum to the sum of hafnium and aluminum.

[0034] When the dopant is silicon (Si), the ferroelectric material film contains 2 to 10 at % of silicon. When the dopant is yttrium (Y), the ferroelectric material film contains 2 to 10 at % of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film contains 1 to 7 at % gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film contains 50 to 80 at % of zirconium.

[0035] The paraelectric material film has paraelectric properties. The paraelectric material film may include at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide. The ferroelectric material film and the paraelectric material film include the same material. A ferroelectric material film has ferroelectric properties, whereas a paraelectric material film does not necessarily have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material layer may be different from the crystal structure of the hafnium oxide contained in the paraelectric material layer.

[0036] The ferroelectric material film has a thickness such that it has ferroelectric properties. The thickness of the ferroelectric material film is 0.5 to 10 nm, but is not limited thereto. Since each ferroelectric material has a different critical thickness at which it exhibits ferroelectric properties, the thickness of the ferroelectric material film may vary depending on the ferroelectric material. As an example, the gate insulating film GI includes one ferroelectric material film. As another example, the gate insulating film GI may include a plurality of ferroelectric material layers spaced apart from one another. The gate insulating film GI may have a laminated film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately laminated.

[0037] Referring again to FIG. 4 and FIG. 5A to FIG. 5D, the gate electrode GE includes a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern is provided on the gate insulating film GI and is adjacent to the first to third semiconductor patterns (SP1, SP2, SP3). The first metal pattern includes a workfunction metal that adjusts the threshold voltage of the transistor. The thickness and composition of the first metal pattern is adjusted to achieve a desired threshold voltage of the transistor. For example, the first to third portions (PO1, PO2, PO3) of the gate electrode GE are formed of a first metal pattern that is a work function metal.

[0038] The first metal pattern includes a metal nitride film. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Furthermore, the first metal pattern may further contain carbon (C). The first metal pattern may include multiple work function metal films stacked together. The second metal pattern includes a metal having a lower resistivity than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion PO4 of the gate electrode GE includes a first metal pattern and a second metal pattern on the first metal pattern.

[0039] A first interlayer insulating film 110 is provided on a substrate 100 . The first interlayer insulating film 110 covers the gate spacer GS and the first and second source / drain patterns SD1 and SD2. The top surface of the first interlayer insulating film 110 is substantially coplanar with the top surfaces of the gate capping patterns GP and the gate spacers GS. A second interlayer insulating film 120 is disposed on the first interlayer insulating film 110 to cover the gate capping pattern GP. A third interlayer insulating film 130 is provided on the second interlayer insulating film 120 . A fourth interlayer insulating film 140 is provided on the third interlayer insulating film 130 . As an example, the first to fourth interlayer insulating films (110 to 140) include a silicon oxide film.

[0040] The single height cell SHC has a first boundary BD1 and a second boundary BD2 facing each other in the second direction D2. The first and second boundaries (BD1, BD2) extend in a first direction D1. The single height cell SHC has a third boundary BD3 and a fourth boundary BD4 facing each other in the first direction D1. The third and fourth boundaries (BD3, BD4) extend in the second direction D2. A pair of separation structures DB facing each other in the second direction D2 are provided on either side of the single height cell SHC. For example, a pair of isolation structures DB are provided on the first and second boundaries (BD1, BD2) of a single height cell SHC, respectively. The isolation structure DB extends in a first direction D1 parallel to the first and second gate electrodes GE1 and GE2. The pitch between the isolation structure DB and the first and second gate electrodes (GE1, GE2) adjacent thereto is the same as the first pitch.

[0041] The isolation structure DB penetrates the first and second interlayer insulating layers 110 and 120 and extends into the first and second active patterns AP1 and AP2. The isolation structure DB penetrates the top of each of the first and second active patterns AP1 and AP2. The isolation structure DB electrically isolates the active area of ​​the single height cell SHC from the active areas of other adjacent cells. Active contacts AC are provided through the first and second interlayer insulating layers 110 and 120 and electrically connected to the first and second source / drain patterns SD1 and SD2, respectively. A pair of active contacts AC are provided on either side of the gate electrode GE, respectively. In a plan view, the active contacts AC have a bar shape extending in the first direction D1.

[0042] The active contacts AC are self-aligned contacts. That is, the active contacts AC are formed in a self-aligned manner using the gate capping patterns GP and the gate spacers GS. For example, the active contact AC covers at least a portion of the sidewall of the gate spacer GS. Although not shown in the figure, the active contact AC covers a part of the upper surface of the gate capping pattern GP. A metal-semiconductor compound layer SC, for example a silicide layer, is interposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2, respectively. The active contacts AC are electrically connected to the source / drain patterns (SD1, SD2) through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

[0043] Gate contacts GC are provided through the second interlayer insulating film 120 and the gate capping pattern GP and are electrically connected to the gate electrodes GE. In a plan view, the gate contact GC is disposed so as to overlap the first active region AR1 and the second active region AR2. As an example, a gate contact GC is provided on the second active pattern AP2 (see FIG. 5B). As an embodiment of the present invention, referring to FIG. 5B, the top of the active contact AC adjacent to the gate contact GC is filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP is lower than the bottom surface of the gate contact GC. That is, the top surface of the active contact AC adjacent to the gate contact GC is lowered below the bottom surface of the gate contact GC by the upper insulating pattern UIP. Therefore, it is possible to prevent the gate contact GC from coming into contact with the adjacent active contact AC, which would otherwise cause a short circuit.

[0044] Each of the active contacts AC and the gate contacts GC includes a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal among aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM covers the side walls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal film / metal nitride film. The metal film may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0045] A first metal layer M1 is provided in the third interlayer insulating film 130. For example, the first metal layer M1 includes a first power wiring (M1_R1), a second power wiring (M1_R2), and a first wiring (M1_I). The wirings (M1_R1, M1_R2, M1_I) of the first metal layer M1 extend parallel to each other in the second direction D2. Specifically, the first and second power wirings (M1_R1, M1_R2) are provided on the third and fourth boundaries (BD3, BD4) of the single height cell SHC, respectively. The first power wiring (M1_R1) extends in the second direction D2 along the third boundary BD3. The second power wiring (M1_R2) extends in the second direction D2 along the fourth boundary BD4. The first wiring (M1_I) of the first metal layer M1 is disposed between the first and second power wirings (M1_R1, M1_R2). The first wirings (M1_I) of the first metal layer M1 are arranged at a second pitch along the first direction D1. The second pitch is smaller than the first pitch. The line width of each of the first wirings (M1_I) is smaller than the line width of each of the first and second power wirings (M1_R1, M1_R2).

[0046] The first metal layer M1 further includes a first via VI1. The first vias VI1 are provided under the wirings (M1_R1, M1_R2, M1_I) of the first metal layer M1, respectively. The active contact AC and the wiring of the first metal layer M1 are electrically connected to each other through the first via VI1. The gate contact GC and the wiring of the first metal layer M1 are electrically connected to each other through the first via VI1. The wiring of the first metal layer M1 and the first via VI1 thereunder are formed in separate processes. That is, each of the wiring of the first metal layer M1 and the first via VI1 can be formed in a single damascene process. The semiconductor device according to this embodiment can be formed using a process of less than 20 nm.

[0047] A second metal layer M2 is provided in the fourth interlayer insulating film 140. The second metal layer M2 includes a plurality of second wirings (M2_I). Each of the second wirings (M2_I) of the second metal layer M2 has a line shape or a bar shape extending in the first direction D1. That is, the second wirings (M2_I) extend parallel to each other in the first direction D1. The second metal layer M2 further includes second vias VI2 each provided under the second wiring (M2_I). The wiring of the first metal layer M1 and the wiring of the second metal layer M2 are electrically connected to each other through the second via VI2. As an example, the wiring of the second metal layer M2 and the second via VI2 therebelow can be formed together in a dual damascene process.

[0048] The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may comprise the same or different conductive materials. For example, the wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not shown in the figure, metal layers (eg, M3, M4, M5, . . . ) stacked on the fourth interlayer insulating film 140 may be additionally disposed. Each of the stacked metal layers contains wiring for routing between cells.

[0049] The gate electrode GE and the gate insulating film GI will be described in more detail with reference to FIGS. 6A and 6B. Referring to FIG. 6A, the first source / drain pattern SD1 includes protrusions PRP protruding toward the first to third portions PO1, PO2, and PO3 of the gate electrode GE, respectively. The protrusion portion PRP of the first source / drain pattern SD1 has a bulging sidewall. The bulging side walls of the protrusions PRP bulge toward the corresponding parts among the first to third parts (PO1, PO2, PO3). As an embodiment of the present invention, the first to third portions (PO1, PO2, PO3) have widths different from each other. For example, the maximum width of the first portion PO1 in the second direction D2 is greater than the maximum width of the second portion PO2 in the second direction D2. The maximum width of the second portion PO2 in the second direction D2 is greater than the maximum width of the first portion PO1 in the second direction D2.

[0050] The first source / drain pattern SD1 includes a first semiconductor layer SEL1 and a second semiconductor layer SEL2 on the first semiconductor layer SEL1. In one embodiment, when the first source / drain pattern SD1 has an n-type, the first semiconductor layer SEL1 includes the same semiconductor material as the second semiconductor layer SEL2, for example, silicon (Si). However, the concentration of n-type impurities (eg, phosphorus or arsenic) in the second semiconductor layer SEL2 is greater than the concentration of n-type impurities in the first semiconductor layer SEL1. In another embodiment, when the first source / drain pattern SD1 has a p-type, the first semiconductor layer SEL1 includes the same semiconductor material as the second semiconductor layer SEL2, for example, silicon-germanium (SiGe). However, the germanium concentration in the second semiconductor layer SEL2 is higher than the germanium concentration in the first semiconductor layer SEL1. Moreover, the concentration of p-type impurities (for example, boron) in the second semiconductor layer SEL2 is higher than the concentration of p-type impurities in the first semiconductor layer SEL1.

[0051] The first semiconductor layer SEL1 is in direct contact with the first to third semiconductor patterns (SP1, SP2, SP3). The first semiconductor layer SEL1 includes the above-mentioned protrusion portion PRP. An inner gate spacer IGS, which will be described later, directly covers the first semiconductor layer SEL1. The first to third portions (PO1, PO2, PO3) of the gate electrode GE are spaced apart from the first semiconductor layer SEL1 via an inner spacer IS. An inner region IRG is provided between the pair of first source / drain patterns SD1. In the inner region IRG, first to third portions (PO1, PO2, PO3) of the gate electrode GE are provided. Within each of the inner regions IRG, an inner spacer IS and a high dielectric film HK are further provided. The inner spacer IS partially fills the inner region IRG. The inner gate spacer IGS provides an inner gate space IGE. In the inner gate space IGE, a high dielectric film HK and corresponding portions among the first to third portions (PO1, PO2, PO3) are provided.

[0052] Representatively, the second portion PO2 of the gate electrode GE and the gate insulating film GI surrounding the second portion PO2 will be described with reference to FIG. 6B. The gate insulating film GI is interposed between the second portion PO2 and the first semiconductor pattern SP1, between the second portion PO2 and the second semiconductor pattern SP2, and between the second portion PO2 and the first source / drain pattern SD1. The gate insulating film GI includes an inner gate spacer IGS and a high dielectric film HK. The inner gate spacer IGS directly covers the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the first source / drain pattern SD1. The high dielectric film HK is interposed between the inner gate spacer IGS and the second portion PO2. The high dielectric film HK directly covers the surface of the second portion PO2 of the gate electrode GE.

[0053] The inner gate spacer IGS includes a center portion CNT and an edge portion EG adjacent to one side of the center portion CNT in the first direction D1. In one embodiment, the central portion CNT and the first and second edge portions (EG1, EG2) on either side of it are defined by dividing the inner gate spacer IGS into three equal parts of the same length. The central portion CNT has a first thickness TK1 in a second direction D2 intersecting with the first direction D1. The edge portion EG has a second thickness TK2 in the second direction D2. The first thickness TK1 is greater than the second thickness TK2. The ratio of the second thickness TK2 to the first thickness TK1 is 0.2 to 0.8. The thickness of the inner gate spacer IGS decreases from the central portion CNT to the edge portion EG.

[0054] The edge portion EG includes a first edge portion EG1 and a second edge portion EG2 spaced apart from the first edge portion EG1 in a first direction D1. The central portion CNT is provided between the first edge portion EG1 and the second edge portion EG2. The thickness of the inner gate spacer IGS increases from the first edge portion EG1 toward the central portion CNT, and reaches a maximum value at the central portion CNT. Thereafter, the thickness of the inner gate spacer IGS decreases from the central portion CNT to the second edge portion EG2. That is, the thickness of the inner gate spacer IGS increases and then decreases in the first direction D1. The inner gate spacer IGS includes a first sidewall GSW1 adjacent to the second portion PO2 of the gate electrode GE.

[0055] The first side wall GSW1 is a side wall that bulges out toward the second portion PO2 of the gate electrode GE. The second portion PO2 of the gate electrode GE includes a recessed sidewall PSW1 corresponding to the first sidewall GSW1. The recessed sidewall PSW1 contacts the inner gate spacer IGS. A high dielectric film HK is provided between the recessed sidewall PSW1 and the inner gate spacer IGS. The central portion CNT includes a first outer side surface GSWa in contact with the high dielectric film HK. The first edge portion EG1 includes a second outer side surface GSWb in contact with the high dielectric film HK. At this time, the first outer surface GSWa is recessed further toward the second portion PO2 compared to the second outer surface GSWb. That is, the inner gate spacer IGS has a structure in which the central portion CNT is further recessed toward the second portion PO2 from the first edge portion EG1. The central portion CNT is recessed further toward the second portion PO2 than the second edge portion EG2.

[0056] According to this embodiment, the thickness of the inner gate spacer IGS becomes thinner from the center portion CNT to the edge portion EG. Therefore, when the gate electrode GE is filled in the inner gate space IGE, an inlet for injecting metal is widened. Therefore, the gate electrode GE can be formed uniformly without any voids. As a result, according to the present invention, the electrical characteristics of a semiconductor device can be improved by varying the thickness of the inner gate spacer IGS. The first to third portions (PO1, PO2, PO3) and the inner gate spacer IGS described with reference to FIG. 6A can be similarly applied to the second active region AR2 shown in FIG. 5B. The first to third portions (PO1, PO2, PO3) and the inner gate spacer IGS described with reference to FIG. 6B can be similarly applied to the first active region AR1 shown in FIG. 5A.

[0057] 7A to 17B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, FIGS. 7A, 8A, 9A, 10A, 11A, and 12A are cross-sectional views taken along line AA' in FIG. FIG. 10B is a cross-sectional view taken along line BB' in FIG. 7B, 9B, 10C, 11B, and 12B are cross-sectional views taken along line CC' in FIG. 7B, 8B, 9C, 10D, 11C, and 12C are cross-sectional views taken along line DD' in FIG.

[0058] Referring to Figures 7A and 7B, a substrate 100 including first and second active regions (AR1, AR2) is provided. On the substrate 100, active layers ACL and sacrificial layers SAL are formed, which are alternately stacked. The active layer ACL includes one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layer SAL includes another one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). The sacrificial layer SAL includes a material having an etching selectivity with respect to the active layer ACL. For example, the active layer ACL includes silicon (Si) and the sacrificial layer SAL includes silicon-germanium (SiGe). The concentration of germanium (Ge) in each of the sacrificial layers SAL is 10 at % to 30 at %.

[0059] Mask patterns are formed on the first and second active regions AR1 and AR2 of the substrate 100, respectively. The mask pattern has a line shape or a bar shape extending in a second direction D2. A patterning process is performed using the mask pattern as an etching mask to form trenches TR that define the first and second active patterns AP1 and AP2. The first active pattern AP1 is formed on the first active region AR1. The second active pattern AP2 is formed on the second active region AR2. A stack pattern STP is formed on each of the first and second active patterns AP1 and AP2. The laminated pattern STP includes active layers ACL and sacrificial layers SAL that are alternately laminated with each other. The stack pattern STP is formed together with the first and second active patterns AP1 and AP2 during a patterning process.

[0060] An element isolation film ST is formed to fill the trench TR. Specifically, an insulating film is formed on the entire surface of the substrate 100 to cover the first and second active patterns AP1 and AP2 and the stack pattern STP. The insulating film is recessed until the stack pattern STP is exposed, thereby forming an isolation film ST. The element isolation film ST includes an insulating material such as a silicon oxide film. The stacked pattern STP is exposed on the element isolation film ST. That is, the stack pattern STP protrudes vertically onto the element isolation film ST.

[0061] 8A and 8B, a sacrificial pattern PP is formed on a substrate 100 so as to cross a stack pattern STP. Each of the sacrificial patterns PP is formed in a line shape or a bar shape extending in a first direction D1. The sacrificial patterns PP are arranged along a second direction D2 at a first pitch. Specifically, forming the sacrificial pattern PP includes forming a sacrificial film on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial film, and patterning the sacrificial film using the hard mask pattern MP as an etching mask. The sacrificial film includes polysilicon. A pair of gate spacers GS are formed on both side walls of each of the sacrificial patterns PP. Forming the gate spacer GS includes conformally forming a gate spacer film on the entire surface of the substrate 100 and anisotropically etching the gate spacer film. In one embodiment of the present invention, the gate spacer GS is a multi-membrane comprising at least two membranes.

[0062] 9A to 9C, a first recess RS1 is formed in a stack pattern STP on a first active pattern AP1. A second recess RS2 is formed in the stack pattern STP on the second active pattern AP2. During the formation of the first and second recesses RS1 and RS2, the isolation layers ST on both sides of each of the first and second active patterns AP1 and AP2 are further recessed (see FIG. 9B). Specifically, the stack pattern STP on the first active pattern AP1 is etched using the hard mask pattern MA and the gate spacer GS as an etching mask to form the first recess RS1. The first recess RS1 is formed between a pair of sacrificial patterns PP. Forming the first recess RS1 includes additionally performing a selective etching step on the exposed sacrificial layer SAL.

[0063] By means of a selective etching process, each sacrificial layer SAL is indented to form an indentation area IDE. The first recess RS1 therefore has a corrugated inner wall. The second recess RS2 in the stack pattern STP on the second active pattern AP2 is formed in the same manner as the first recess RS1. First to third semiconductor patterns SP1, SP2, and SP3 are formed in the active layer ACL between the adjacent first recesses RS1. The first to third semiconductor patterns (SP1, SP2, SP3) between the adjacent first recesses RS1 constitute a first channel pattern CH1. The first to third semiconductor patterns (SP1, SP2, SP3) between the adjacent second recesses RS2 form a second channel pattern CH2.

[0064] 10A to 10D, first source / drain patterns SD1 are formed in the first recesses RS1, respectively. Specifically, a SEG process is performed using the inner wall of the first recess RS1 as a seed layer to form an epitaxial layer that fills the first recess RS1. The epitaxial layer grows using the first to third semiconductor patterns (SP1, SP2, SP3) exposed by the first recess RS1 and the substrate 100 as a seed. As an example, the SEG process may include a Chemical Vapor Deposition (CVD) process or a Molecular Beam Epitaxy (MBE) process.

[0065] In one embodiment of the present invention, the first source / drain pattern SD1 includes the same semiconductor element as the substrate 100 (eg, Si). During the formation of the first source / drain pattern SD1, impurities (eg, phosphorus, arsenic, or antimony) that cause the first source / drain pattern SD1 to have an n-type conductivity are implanted in-situ. As another example, after the first source / drain pattern SD1 is formed, impurities are implanted into the first source / drain pattern SD1. Second source / drain patterns SD2 are formed in the second recesses RS2. Specifically, the second source / drain pattern SD2 is formed by performing a SEG process using the inner wall of the second recess RS2 as a seed layer.

[0066] In one embodiment of the present invention, the second source / drain pattern SD2 includes a semiconductor element (eg, SiGe) having a lattice constant greater than the lattice constant of the semiconductor element of the substrate 100. During the formation of the second source / drain pattern SD2, an impurity (eg, boron, gallium, or indium) that causes the second source / drain pattern SD2 to have a p-type is implanted in-situ. As another example, after the second source / drain pattern SD2 is formed, impurities are implanted into the second source / drain pattern SD2.

[0067] 11A to 11C, a first interlayer insulating film 110 is formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. As an example, the first interlayer insulating film 110 includes a silicon oxide film. The first interlayer insulating film 110 is planarized until the top surface of the sacrificial pattern PP is exposed. The first interlayer insulating film 110 is planarized by using an etch back or chemical mechanical polishing (CMP) process. During the planarization step, all of the hard mask pattern MP is removed. As a result, the upper surface of the first interlayer insulating film 110 is coplanar with the upper surfaces of the sacrificial pattern PP and the gate spacer GS.

[0068] The exposed sacrificial pattern PP is selectively removed. By removing the sacrificial pattern PP, an outer region ORG exposing the first and second channel patterns CH1 and CH2 is formed (see FIG. 11C). Removing the sacrificial pattern PP involves a wet etch utilizing an etchant that selectively etches polysilicon. The sacrificial layer SAL exposed through the outer region ORG is selectively removed to form an inner region IRG (see FIG. 11C). Specifically, an etching process is performed to selectively etch the sacrificial layer SAL, and only the sacrificial layer SAL is removed while leaving the first to third semiconductor patterns (SP1, SP2, SP3) as they are.

[0069] The etching process has a high etch rate for silicon-germanium having a relatively high germanium concentration. For example, the etching process has a high etch rate for silicon-germanium where the germanium concentration is greater than 10 at.%. During the etching step, the sacrificial layer SAL on the first and second active areas (AR1, AR2) is removed. The etching step may be a wet etch. The etching material used in the etching process can quickly remove the sacrificial layer SAL having a relatively high germanium concentration.

[0070] Referring again to FIG. 11C, the sacrificial layer SAL is selectively removed, so that only the first to third semiconductor patterns (SP1, SP2, SP3) stacked on each of the first and second active patterns (AP1, AP2) remain. First to third inner regions (IRG1, IRG2, IRG3) are formed through the regions where the sacrificial layer SAL has been removed. Specifically, a first inner region IRG1 is formed between the active pattern (AP1 or AP2) and the first semiconductor pattern SP1, a second inner region IRG2 is formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third inner region IRG3 is formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0071] Referring again to FIGS. 11A to 11C, a gate insulating film GI is formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating film GI is formed so as to surround each of the first to third semiconductor patterns (SP1, SP2, SP3). A gate insulating film GI is formed in each of the first to third inner regions (IRG1, IRG2, IRG3). A gate insulating film GI is formed in the outer region ORG.

[0072] 13 to 17B are diagrams for explaining a method for forming the M region in FIG. 11A. Figures 13, 14B, 15B, 16B, and 17B are enlarged views of region M in Figure 5A and are views for explaining the manufacturing method of the inner gate spacer IGS, and Figures 14A, 15A, 16A, and 17A are cross-sectional views cut along line X-X' in Figure 5B and are cross-sectional views for explaining the manufacturing method of the inner gate spacer IGS.

[0073] 13, 14A and 14B, the sacrificial pattern PP is selectively removed to form the outer region ORG as described above. The sacrificial layer SAL exposed through the outer region ORG is selectively removed to form first to third inner regions IRG1 to IRG3. Each of the first to third inner regions IRG1 to IRG3 is located between a pair of first source / drain patterns SD1. Due to the indentation region IDE shown in FIG. 9A, the first source / drain pattern SD1 includes a protrusion portion PRP. The protrusion PRP has a bulging sidewall. The second inner region IRG2 exposes the top surface of the first semiconductor pattern SP1 and the bottom surface of the second semiconductor pattern SP2.

[0074] 15A and 15B, a first insulating film IL1 is conformally formed in the first to third inner regions (IRG1 to IRG3) and the outer region ORG. The first insulating film IL1 is formed through a deposition process such as ALD or CVD. The first insulating film IL1 is formed so as not to completely fill the first to third inner regions (IRG1 to IRG3) but to partially fill them. Therefore, an inner gate space IGE surrounded by the first insulating film IL1 is defined in the first to third inner regions (IRG1 to IRG3). For example, the first insulating film IL1 may include a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.

[0075] 16A and 16B, the first insulating film IL1 is partially and selectively etched. Etching the first insulating film IL1 includes a wet etching process using an etching solution that selectively etches only the first insulating film IL1. The above etching process is an isotropic etching process. In particular, an etching material is provided through the inner gate space IGE to etch the first insulating film IL1 to form the inner gate spacer IGS. An etching material is provided through the outer region ORG to etch the first insulating film LI1 to form an outer gate spacer OGS.

[0076] Referring to FIG. 16B, after the etching process, the first insulating film IL1 remains on the surface of the second source / drain pattern SD2, forming an inner gate spacer IGS. In particular, the first insulating film IL1 remains in a relatively larger amount at the center portion CNT of the inner gate spacer IGS than at the first and second edge portions EG1 and EG2. That is, the thickness of the inner gate spacer IGS in the second direction D2 is greater in the central portion CNT than in the first and second edge portions (EG1, EG2). The central portion CNT is formed thicker than the first and second edge portions (EG1, EG2), so that the inner gate spacer IGS includes a first sidewall GSW1 that bulges toward the inner gate space IGE.

[0077] 17A and 17B, a high dielectric film HK is formed in the outer region ORG and the first to third inner regions IRG1 to IRG3. A high dielectric film HK is formed in the inner gate space IGE. The inner gate spacer IGS, the outer gate spacer OGS, and the high dielectric film HK constitute a gate insulating film GI. In one embodiment of the present invention, the high dielectric film HK is formed conformally. The horizontal thickness of the high dielectric film HK is substantially the same as its vertical thickness. According to the present invention, by forming the edge portion EG of the inner gate spacer IGS thinner than the central portion CNT, a predetermined space, i.e., an inner gate space IGE, in which the gate electrode GE is sufficiently filled is secured within each of the first to third inner regions (IRG1, IRG2, IRG3). In a process to be described later, when the inner gate space IGE is filled with the gate electrode GE, the gate electrode GE can be formed uniformly and stably without any void. As a result, the electrical characteristics of the semiconductor device can be improved.

[0078] With reference to FIGS. 12A to 12C, a gate electrode GE is formed on a gate insulating film GI. The gate electrode GE includes first to third portions (PO1, PO2, PO3) formed in the first to third inner regions (IRG1, IRG2, IRG3), respectively, and a fourth portion PO4 formed in the outer region ORG. Each of the first to third portions (PO1, PO2, PO3) fills the inner gate space IGE in FIG. 17A. The gate electrode GE is recessed to reduce its height. A gate capping pattern GP is formed on the recessed gate electrode GE.

[0079] 5A to 5D, the second interlayer insulating film 120 is formed on the first interlayer insulating film 110. As shown in FIG. The second interlayer insulating film 120 includes a silicon oxide film. An active contact AC is formed through the second interlayer insulating film 120 and the first interlayer insulating film 110 to be electrically connected to the first and second source / drain patterns SD1 and SD2. A gate contact GC is formed through the second interlayer insulating film 120 and the gate capping pattern GP to be electrically connected to the gate electrode GE. Forming each of the active contacts AC and the gate contacts GC includes forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM is conformally formed and includes a metal film / metal nitride film. The conductive pattern FM includes a low resistance metal.

[0080] An isolation structure DB is formed at each of a first boundary BD1 and a second boundary BD2 of the single height cell SHC. The isolation structure DB extends from the second interlayer insulating film 120 through the gate electrode GE into the active pattern (AP1 or AP2). The isolation structure DB includes an insulating material such as a silicon oxide film or a silicon nitride film. A third interlayer insulating film 130 is formed on the active contacts AC and the gate contacts GC. A first metal layer M1 is formed in the third interlayer insulating film 130. A fourth interlayer insulating film 140 is formed on the third interlayer insulating film 130 . A second metal layer M2 is formed in the fourth interlayer insulating film 140.

[0081] Various other embodiments of the present invention will now be described. In the embodiments of the present invention described below, detailed descriptions of technical features that overlap with those described above with reference to FIGS. 1 to 6B will be omitted, and differences will be described in detail. 18 and 19 are cross-sectional views taken along line XX' of FIG. 5B according to other embodiments of the present invention.

[0082] Referring to FIG. 18, the inner gate spacer IGS includes a second sidewall GSW2 in contact with the second source / drain pattern SD2. The second side wall GSW2 is a concave side wall recessed toward the second portion PO2. At this time, the curvature of the first side wall GSW1 is greater than the curvature of the second side wall GSW2. Therefore, the thickness TK1 of the central portion CNT remains greater than the thicknesses (TK2, TK3) of the first and second edge portions (EG1, EG2).

[0083] Referring to FIG. 19, the first sidewall GSW1 of the inner gate spacer IGS is a recessed sidewall recessed toward the second source / drain pattern SD2. Corresponding to the first sidewall GSW1, the second portion PO2 includes a sidewall PSW1 that bulges toward the inner gate spacer IGS. The second sidewall GSW2 of the inner gate spacer IGS is a sidewall that protrudes toward the second source / drain pattern SD2. At this time, the curvature of the second side wall GSW2 is greater than the curvature of the first side wall GSW1. Therefore, the thickness TK1 of the central portion CNT remains greater than the thicknesses (TK2, TK3) of the first and second edge portions (EG1, EG2). The central portion CNT includes a second source / drain pattern SD2 and a third outer side surface GSWc. The first edge portion EG1 includes a fourth outer side surface GSWd in contact with the high dielectric film HK. At this time, the third outer side surface GSWc is further recessed toward the second source / drain pattern SD2 than the fourth outer side surface GSWd. That is, the inner gate spacer IGS has a structure in which the central portion CNT is further recessed toward the second source / drain pattern SD2 from the first edge portion EG1. The central portion CNT is further recessed from the second edge portion EG2 toward the second source / drain pattern SD2.

[0084] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0085] 100 Substrates 110, 120, 130, 140 (1st to 4th) interlayer insulating films AC Active Contact AP1, AP2 (1st, 2nd) activation patterns AR1, AR2 (1st, 2nd) active region BM Barrier Pattern CH1, CH2 (1st, 2nd) channel pattern DB separation structure DHC Double Height Cell FM Conductive Pattern SHC1, SHC2 (1st, 2nd) Single Height Cells GC Gate Contact GE gate electrode GI Gate Insulator GP Gate Capping Pattern GS Gate Spacer HK High dielectric film IGS Inner Gate Spacer IS Inner Spacer M1, M2 (1st, 2nd) metal layer M1_I, M2_I (1st, 2nd) wiring M1_R1, M1_R2, M1_R3 (1st to 3rd) power wiring OGS Outer Gate Spacer PO1, PO2, PO3, PO4 (1st to 4th) parts of the gate electrode PRP protrusion RS1, RS2 (1st, 2nd) recess VI1, VI2 (1st, 2nd) vias SC Metal-semiconductor compound layer SEL1, SEL2 (first, second) semiconductor layers SD1, SD2 (1st, 2nd) source / drain patterns SHC Single Height Cell SHC1, SHC2 (1st, 2nd) Single Height Cells SP1, SP2, SP3 (1st to 3rd) semiconductor patterns ST element separation membrane

Claims

1. a substrate including an active pattern; a channel pattern on the active pattern; Here, the channel pattern includes a plurality of semiconductor patterns stacked and spaced apart from each other, a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode extending in a first direction across the channel pattern; wherein the gate electrode includes an inner gate electrode interposed between a first semiconductor pattern and a second semiconductor pattern adjacent to each other among the plurality of semiconductor patterns; an inner gate spacer interposed between the inner gate electrode and the source / drain pattern; the inner gate spacer includes a center portion and an edge portion adjacent to one side of the center portion in the first direction; the central portion has a first thickness in a second direction intersecting the first direction; the edge portion has a second thickness in the second direction; The first thickness is greater than the second thickness.

2. 2. The semiconductor device of claim 1, wherein a ratio of the second thickness to the first thickness is between 0.2 and 0.

8.

3. 2. The semiconductor device of claim 1, wherein the thickness of the inner gate spacer decreases from the center portion to the edge portion.

4. 2. The semiconductor device of claim 1, further comprising a high dielectric layer between the inner gate spacer and the inner gate electrode.

5. The semiconductor device of claim 1 , wherein the inner gate spacer includes a first sidewall that bulges toward the inner gate electrode.

6. The semiconductor device of claim 5 , wherein the inner gate spacer further comprises a recessed second sidewall in contact with the source / drain pattern.

7. The semiconductor device of claim 6 , wherein the curvature of the first sidewall is greater than the curvature of the second sidewall.

8. The semiconductor device of claim 1 , wherein the inner gate electrode includes a recessed sidewall that contacts the inner gate spacer.

9. the inner gate spacer has a first outer wall that contacts the source / drain pattern and bulges toward the source / drain pattern; 2. The semiconductor device of claim 1, further comprising: a second outer wall in contact with the inner gate electrode and recessed toward the source / drain pattern.

10. a substrate including an active pattern; a channel pattern on the active pattern; Here, the channel pattern includes a plurality of semiconductor patterns stacked and spaced apart from each other, a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode extending in a first direction across the channel pattern; wherein the gate electrode includes an inner gate electrode interposed between a first semiconductor pattern and a second semiconductor pattern adjacent to each other among the plurality of semiconductor patterns; an inner gate spacer interposed between the inner gate electrode and the source / drain pattern; an inner high dielectric film between the inner gate electrode and the inner gate spacer; the inner gate spacer includes a first portion and a second portion adjacent to one side of the first portion in the first direction; the first portion includes a first outer surface in contact with the inner high dielectric film; the second portion includes a second outer surface in contact with the inner high dielectric film; The semiconductor device, wherein the first outer side is recessed further toward the inner gate electrode than the second outer side.

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