Semiconductor rectifier element and manufacturing method of the same

Abstract

To provide a conductor rectifier and a manufacturing method of the same.SOLUTION: A semiconductor rectifier element comprises: an epitaxial layer having a top surface and a bottom surface; a first concave groove 41 that includes a first side wall 41C and a second side wall 41D that are extended from the top surface to the bottom surface and are opposite each other, and a first bottom surface 41B connecting both side walls; a second concave groove 42 that includes a third side wall 42C and a fourth side wall 42D that are adjacent to the first concave groove and are opposite to each other, and a second bottom surface 42B connecting both side walls; a first dope region 221 that is extended from the top surface to the bottom surface and is adjacent to the first bottom surface of at least a part of the first side wall of the first concave groove; a second dope region 222 that is adjacent to the first dope region, is separated therefrom, is extended from the top surface to the bottom surface, and is adjacent to the third side wall of the second concave group, the fourth side wall, and the second bottom surface; a gate structure that is installed on the top surface between the first and second concave grooves and has a bottom surface adjacent to the first and second dope regions; and a contact metal layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor rectifying device structure and a method for manufacturing the same, and more particularly to a structure having a semiconductor rectifying device formed on silicon carbide and a method for manufacturing the same. [Background technology]

[0002] As is well known, semiconductor materials have a wide band gap (e.g., a band gap energy value Eg greater than 1.1 eV), a low on-resistance (RON), a high thermal conductivity, a high operating frequency, and a high charge carrier saturation velocity, making them very suitable for the production of electronic components such as diodes and transistors, especially for power supply applications. A material that has the above characteristics and is designed for manufacturing electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polymorphs (e.g., 3C-SiC, 4H-SiC, 6H-SiC), is superior to silicon in the properties listed above.

[0003] Electronic devices on silicon carbide substrates have many advantages over similar devices on silicon substrates, including lower dynamic output resistance, lower leakage current, higher operating temperature, and higher operating frequency.Semiconductor structures based on silicon carbide substrates require activation through a high-temperature (e.g., 1700°C or higher) annealing process, but polycrystalline silicon and common gate materials cannot withstand such high-temperature annealing processes, which makes process integration difficult and increases the overall process cost. Summary of the Invention

[0004] An embodiment of the present disclosure relates to a semiconductor rectifying device, the semiconductor rectifying device including: an epitaxial layer having a top surface and a bottom surface facing each other; a first groove extending from the top surface to the bottom surface and including first and second sidewalls facing each other and a first bottom surface connecting the first sidewall and the second sidewall; a second groove extending from the top surface to the bottom surface and adjacent to the first groove, the second groove including third and fourth sidewalls facing each other and a second bottom surface connecting the third sidewall and the fourth sidewall; and a second groove extending from the top surface to the bottom surface and connecting the second sidewall and at least the a first doped region adjacent to a portion of the first bottom surface; a second doped region adjacent to the first doped region and separated from each other, extending from the top surface to the bottom surface and adjacent to the third sidewall, the fourth sidewall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench, with its bottom surface adjacent to the first doped region and the second doped region; and a contact metal layer disposed on the top surface of the epitaxial layer along the first trench, the gate structure and the second trench.

[0005] An embodiment of the present disclosure relates to a method for manufacturing a semiconductor rectifying device, the method including: forming a patterned layer on a silicon carbide layer; etching the silicon carbide layer using the patterned layer as a mask to form a first trench and a second trench adjacent to the first trench; implanting ions into the silicon carbide layer using the patterned layer as a mask; thermally annealing the silicon carbide layer; and, after the thermal annealing, forming a gate structure on the silicon carbide layer between the first trench and the second trench, wherein the gate structure has a first sidewall and a second sidewall opposite to each other, the first sidewall and one sidewall of the first trench being continuous, and the second sidewall and one sidewall of the second trench being also continuous.

[0006] Aspects of certain exemplary embodiments of the present disclosure can be best understood by reading the following detailed description in conjunction with the drawings, in which: It should be noted that the various features may not be drawn to scale, and in fact the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 2] FIG. 2 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 3] FIG. 3 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 4] FIG. 4 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 5] FIG. 5 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 6] FIG. 6 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 7] FIG. 7 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 8] FIG. 8 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 9] FIG. 9 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 10] FIG. 10 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 11]FIG. 11 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 12] FIG. 12 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 13] FIG. 13 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 14] FIG. 14 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 15] FIG. 15 is a top view of a semiconductor rectifying device according to another embodiment of the present invention. [Figure 16] FIG. 16 is a top view of a semiconductor rectifying device according to another embodiment of the present invention. [Figure 17] FIG. 17 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 18] FIG. 18 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 19] FIG. 19 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 20] FIG. 20 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 21] FIG. 21 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 22] FIG. 22 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 23] FIG. 23 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 24] FIG. 24 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 25] FIG. 25 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 26] FIG. 26 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 27] FIG. 27 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present subject matter. [Figure 28] FIG. 28 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present disclosure. [Figure 29] FIG. 29 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present disclosure. [Figure 30] FIG. 30 illustrates one or more stages in a method for fabricating a semiconductor rectifying device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008]

[0013] Certain embodiments of the present disclosure can be more readily understood from the following detailed description and drawings, in which:

[0014] Like reference numerals are used in the drawings and in which the same or similar parts are designated by the same reference numerals throughout the drawings.

[0015] Certain embodiments of the present disclosure can be more readily understood from the following detailed description and drawings, in which:

[0009] The following disclosure provides many different embodiments or examples for implementing various features of the provided targets. Specific examples of components and arrangements are described below. Of course, these are merely exemplary and are not intended to be limiting. In this disclosure, a reference to forming a first feature above or on a second feature can include embodiments in which the first and second features form direct contact, and can also include embodiments in which the first and second features form separate features between them, where the first and second features do not necessarily form direct contact. Also, in this disclosure, drawing numbers and / or letters may be duplicated within each embodiment. This duplication is done for simplicity and clarity and does not, in itself, indicate a relationship between each embodiment and / or arrangement being discussed.

[0010] Although the following detailed discussion of exemplary embodiments of the present disclosure provides numerous application concepts that can be embodied in a variety of specific environments, it should be understood that the specific embodiments discussed are illustrative and are not intended to limit the scope of the present disclosure.

[0011] The present disclosure provides a semiconductor rectifying device structure and a manufacturing method thereof. Compared with conventional semiconductor rectifying device manufacturing methods, the manufacturing method of the present disclosure includes an activation step before forming a polycrystalline silicon material or a dielectric material, thereby properly aligning the rectifying device on the silicon carbide. Furthermore, the manufacturing method of the present disclosure further includes a self-alignment step of the gate structure, thereby reducing damage to the substrate that may be caused by the patterning process, and also reducing the use of photomasks, thereby reducing the overall process cost.

[0012] 1-14 illustrate one or more stages in a method for manufacturing a semiconductor rectifying device 1 according to some embodiments of the present disclosure. At least some of these drawings have been simplified to better understand aspects of the present disclosure.

[0013] Referring to FIG. 1 , the method for manufacturing a semiconductor rectifying device 1 includes epitaxially growing a silicon carbide layer 12 on a surface 11A of a semiconductor material layer 11 and forming a doped region 21 in the silicon carbide layer 12. The semiconductor material layer 11 has opposing surfaces 11A and 11B. In some embodiments, the surfaces 11A and 11B may be horizontal. For ease of explanation, the direction perpendicular to the surfaces 11A and 11B is defined as the vertical direction, and the direction perpendicular to the vertical direction is defined as the horizontal direction. In some embodiments, the surface 11A is the top surface of the semiconductor material layer 11, and the surface 11B is the bottom surface of the semiconductor material layer 11. In some embodiments, the surface 11A is the top surface of a silicon wafer. The material of the semiconductor material layer 11 may be polycrystalline silicon or single crystal silicon. The semiconductor material layer 11 may include a doped region. For example, the semiconductor material layer 11 includes a p-type doped region and an n-type doped region (which can be configured as a p-type transistor) that can be configured as an n-type transistor. The n-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, or other n-type dopants, or a combination thereof. The p-type doped region is doped with a p-type dopant, such as boron, indium, or other p-type dopants, or a combination thereof. The n-type or p-type doped region can be formed by performing an ion implantation process, a diffusion process, and / or other appropriate doping process. The semiconductor material layer 11 has a first-type doped region that extends from the surface 11A to the surface 11B and covers the entire surface 11A. For ease of explanation, the first type will be described below as an n-type example, but the present disclosure is not limited thereto. The n-type (first type) or p-type (second type) semiconductor material layer 11 can be adjusted depending on the conductivity type of the semiconductor rectifying device 1.

[0014] Silicon carbide layer 12 has the same conductivity type as semiconductor material layer 11, i.e., first-type doping. In some embodiments, N-type silicon carbide layer 12 is formed by implanting ions having N-type conductivity during epitaxial growth, eliminating the need for a separate ion implantation. Because the N-type ions are distributed throughout silicon carbide layer 12, doped regions 25 can be formed throughout silicon carbide layer 12. Silicon carbide layer 12 has surface 12A and surface 12B opposite surface 12A. In some embodiments, surface 12A and surface 12B may be horizontal surfaces. In some embodiments, surface 12A is the top surface of silicon carbide layer 12, and surface 12B is the bottom surface of silicon carbide layer 12. In some embodiments, surface 12B of silicon carbide layer 12 contacts surface 11A of semiconductor material layer 11.

[0015] Next, ion implantation is performed on the surface 12A of the silicon carbide layer 12 to form a doped region 21 having a second doping type. In some embodiments, the doped region 21 is a doped region serving as a circuit termination and is also referred to as a termination doped region. In some embodiments, the doped region 21 functions as a guard ring. In some embodiments, the doped region 21 has a ring shape when viewed from a top view (not shown in the figures). The doped region 21 is formed by forming an oxide layer on the surface 12A of the silicon carbide layer 12 and then forming a patterned photomask on the oxide layer. The oxide layer is patterned using the patterned photomask, and after removing the photomask, ion implantation is performed on the surface 12A of the silicon carbide layer 12 using the patterned oxide layer as a mask. The patterned oxide layer is removed after the ion implantation step. The above-mentioned method for forming the doped region 21 has been described based on examples provided in some embodiments of the present disclosure, but the present disclosure is not limited thereto. Also, doped region 21 offsets the conductivity of doped region 25 so that, electrically speaking, the coverage of doped region 25 is defined as the portion of silicon carbide layer 12 outside doped region 21 .

[0016] 2 , the method for fabricating semiconductor rectifying device 1 includes forming patterned layer 51 on surface 12A of silicon carbide layer 12 of semiconductor material, exposing a portion of silicon carbide layer 12 and covering a portion of doped region 21. In some embodiments, patterned layer 51 exposes a portion of doped region 21 and a portion of silicon carbide layer 12 in contact with doped region 21. In some embodiments, patterned layer 51 has openings 511 and 512, exposing a portion of silicon carbide layer 12. Patterned layer 51 may be a material layer suitable as a mask for a subsequent etching step, such as a photomask, a hardening layer, or a dielectric layer (e.g., an oxide or nitride layer). In some embodiments, patterned layer 51 comprises an oxide (e.g., silicon oxide). In some embodiments, an oxide layer is formed to cover the entire surface 12A of the silicon carbide layer 12, a patterned photomask is formed on the oxide layer, a portion of the oxide layer is removed using the patterned photomask, and then the photomask is removed to form a patterned layer 51 that exposes a portion of the silicon carbide layer 12.

[0017] Referring to FIG. 3 , the method for manufacturing the semiconductor rectifying device 1 includes performing an etching process on the silicon carbide layer 12 using the patterned layer 51 as a mask to form a plurality of grooves (grooves 41 and 42 shown in FIG. 3 ). The grooves are adjacent to each other and extend from the surface 12A to the surface 12B of the silicon carbide layer 12. Because they are formed through the same etching step, the grooves have approximately the same depth. In some embodiments, the bottom surfaces of the grooves are located on approximately the same horizontal plane 12D. In some embodiments, the depth D41 of the groove 41 is approximately the same as the depth D42 of the groove 42. In some embodiments, the depth D41 of the groove 41 or the depth D42 of the groove 42 is between 4000 and 5000 angstroms. In some embodiments, the bottom surface 41B of the groove 41 and the sidewall 42D of the groove 41 have approximately the same horizontal height and are located on the horizontal plane 12D. In some embodiments, the bottom surface 41B of the trench 41 and the sidewalls 42D of the trench 41 are located on the same horizontal plane 12D. In some embodiments, the depth of the trenches 41, 42 is less than the depth of the doped region 21. The patterned layer 51 exposes a portion of the doped region 21, and the depth of the trench 41 is less than the depth of the doped region 21, so that the doped region 21 is adjacent to a portion of the sidewalls 41D and bottom surface 41B of the trench 41. Furthermore, the trenches (including the trenches 41, 42) are formed using the patterned layer 51 as a mask, so that the patterned layer 51 corresponds to the openings of the trenches. Sidewalls 41C, 41D of groove 41 are aligned with sidewalls of corresponding first openings 511 in patterned layer 51, and sidewalls 42C, 42D of groove 42 are aligned with sidewalls of corresponding second openings 512 in patterned layer 51, whereby sidewalls 41C, 41D are individually connected to bottom surface 41B and face each other, and sidewalls 42C, 42D are individually connected to bottom surface 42B and face each other. In some embodiments, first opening 511 in patterned layer 51 overlaps a portion of doped region 21 along the vertical direction, as shown in FIG. 3 .

[0018] 4 , the method for manufacturing the semiconductor rectifying device 1 includes implanting ions into the silicon carbide layer 12 using the patterned layer 51 as a mask to form a plurality of doped regions 22, among which the plurality of doped regions 22 have the same conductivity type as the doped region 21. Similar to the above description, the doped region 22 offsets the conductivity of the doped region 25, so that, electrically speaking, the coverage of the doped region 25 is defined as the portion of the silicon carbide layer 12 outside the doped regions 21, 22.

[0019] The plurality of doped regions 22 includes doped region 221 and doped region 222. In some embodiments, doped region 221 extends from surface 12A to surface 12B and is adjacent to a portion of sidewall 41C and bottom surface 41B of trench 41. In some embodiments, doped region 221 extends along a portion of sidewall 41C and bottom surface 41B of trench 41 into silicon carbide layer 12. To individually diffuse each of the plurality of doped regions 22 laterally along its corresponding trench sidewall, the step illustrated in FIG. 4 includes at least one angled ion implantation. In some embodiments, the step illustrated in FIG. 4 includes multiple ion implantations, at least one of which is an angled ion implantation. In some embodiments, the step illustrated in FIG. 4 includes multiple angled ion implantations, each of which can have a different tilt angle to achieve a desired lateral diffusion extent. In some embodiments, the depth of doped region 21 from surface 12A to surface 12B is equal to or greater than the depth of doped region 22 from surface 12A to surface 12B.

[0020] Patterned layer 51 exposes a portion of doped region 21, so that doped region 221 is in contact with doped region 21. In some embodiments, ions are implanted into exposed doped region 21 during the ion implantation step of FIG. 4 . Region 211, shown by the dashed box in FIG. 4 , represents a region of doped region 21 where secondary ions are implanted, and thus region 211 has a higher doping concentration. Multiple doped regions 22 are bulk doped regions of semiconductor rectifying device 1, and doped region 21 is a terminal doped region. Region 211 is covered with a dielectric material in a subsequent step, and therefore does not function as a bulk doped region but as a terminal doped region. For ease of explanation, region 211 is defined as part of doped region 21, and the boundary between region 211 and doped region 221 corresponds to the boundary between doped region 21 and doped region 221. In some embodiments, region 211 has a higher doping concentration than doped region 221. In some embodiments, region 211 has a higher doping concentration than the rest of doped region 21. In some embodiments, doped region 22 has a different doping concentration than doped region 21. In some embodiments, the doping concentration of doped region 21 is 1*10 per cubic centimeter or less. 17 ~1*10 18 (cm -3 ) In some embodiments, the doping concentration of doped region 22 is between 1*10 16 ~1*10 17 cm -3 It is between.

[0021] Doped region 222 is adjacent to and spaced apart from doped region 221. In some embodiments, doped region 222 extends from surface 12A to surface 12B and is adjacent to opposing sidewalls 42C, 42D and bottom surface 42B of trench 42. In some embodiments, doped region 222 extends along sidewalls 42C, 42D and bottom surface 42B of trench 42 into silicon carbide layer 12. Doped region 222 is formed via the same ion implantation step as doped region 221 and therefore has approximately the same depth and doping concentration as doped region 221.

[0022] Referring to FIG. 5 , the method for fabricating the semiconductor rectifying device 1 includes forming a carbon-containing layer 52 to cover the silicon carbide layer 12, followed by high-temperature annealing of the silicon carbide layer 12. In some embodiments, the carbon-containing layer 52 covers the entire silicon carbide layer 12. In some embodiments, the carbon-containing layer 52 conformally covers the silicon carbide layer 12. The silicon carbide layer 12 is subsequently subjected to high-temperature annealing to activate ions in the doped regions 21, 22, thereby preventing silicon precipitation at high temperatures. After the carbon-containing layer 52 is formed, the silicon carbide layer 12 is subjected to high-temperature annealing. In some embodiments, the temperature of the high-temperature annealing step is between 1400 and 2500 degrees (°C). In some embodiments, the time for performing the high-temperature annealing step is between 20 and 40 minutes. The carbon-containing layer 52 is removed after the high-temperature annealing step.

[0023] 6, the method for manufacturing the semiconductor rectifying device 1 includes, after the high-temperature annealing step, forming a dielectric layer 13 to cover the doped region 21. To ensure that the dielectric layer 13 covers the entire doped region 21, the dielectric layer 13 also covers a portion of the doped region 21 and the adjacent doped region 221. The method for forming the dielectric layer 13 can refer to the method for forming the patterned layer 51 described above, and therefore will not be described again here. In some embodiments, the dielectric layer 13 covers the sidewall 41D and a portion of the bottom surface 41B of the groove 41. In some embodiments, the dielectric layer 13 includes an oxide (e.g., silicon oxide).

[0024] 7, the method for manufacturing semiconductor rectifying device 1 includes forming dielectric layer 14 to fill remaining grooves 41 and 42 after forming dielectric layer 13. In some embodiments, a deposition process is performed to form a dielectric material to cover the entire silicon carbide layer 12, and then dry etching the dielectric material to remove the dielectric material above surface 12A, thereby forming dielectric layer 14. In some embodiments, the dielectric material and silicon carbide layer 12 have an etching selectivity, so that the dry etching step is stopped at surface 12A of silicon carbide layer 12.

[0025] The top surface 14A of the dielectric layer 14 is flush or coplanar with the surface 12A of the silicon carbide layer 12. The dielectric layer 14 may include multiple portions filling the multiple grooves. In some embodiments, the dielectric layer 14 includes a partial dielectric layer 141 located in the groove 41 and a partial dielectric layer 142 located in the groove 42. In some embodiments, the top surface 141A of the partial dielectric layer 141 is flush or coplanar with the surface 12A of the silicon carbide layer 12. In some embodiments, the top surface 142A of the partial dielectric layer 142 is flush or coplanar with the surface 12A of the silicon carbide layer 12. In some embodiments, the top surface 142A of the partial dielectric layer 142 is located at approximately the same horizontal height as the top surface 142A of the partial dielectric layer 142. Furthermore, the dielectric layer 14 has a different dielectric material from the dielectric layer 13 so that an etching selectivity can be achieved between the dielectric layer 13 and the dielectric layer 14 in a subsequent etching step. In some embodiments, dielectric layer 14 comprises a nitride (eg, silicon nitride).

[0026] Referring to FIG. 8 , the method for manufacturing the semiconductor rectifying device 1 includes removing a portion of the silicon carbide layer 12 to lower the top surface of the exposed portion of the silicon carbide layer 12 below the top surface 14A of the dielectric layer 14. In some embodiments, the silicon carbide layer 12 is dry-etched to remove the portion of the silicon carbide layer 12 not covered by the dielectric layers 13 and 14. After the dry-etching step, the silicon carbide layer 12 has an exposed surface 12C, and the horizontal height of the surface 12C is lower than the horizontal height of the surface 12A and higher than the horizontal height of the bottom surfaces of the plurality of grooves (including 41 and 42). In some embodiments, the surface 12C may be a horizontal surface. In some embodiments, the top surface of the silicon carbide layer 12 after the dry-etching step includes a horizontal surface having different horizontal heights. In some embodiments, the top surface of the silicon carbide layer 12 after the dry-etching step includes the surface 12A and the surface 12C, and the horizontal height of the surface 12A is higher than the horizontal height of the surface 12C. The dry etching step removes a predetermined thickness of the silicon carbide layer 12, and the predetermined thickness is less than the depth of the groove 41. Because a gate structure will be formed on the surface 12C in a subsequent step, the thickness of the gate structure is determined by the thickness of the removed silicon carbide layer 12. Therefore, the predetermined thickness can be adjusted based on the desired thickness of the gate structure. In some embodiments, the dry etching step may be performed in a time mode, in which the thickness of the removed silicon carbide layer 12 is controlled to reach the predetermined thickness by performing the dry etching step for a predetermined time. In some embodiments, the predetermined thickness is between 1000 angstroms and 3000 angstroms. In other words, the vertical distance D12 from the surface 12C of the silicon carbide layer 12 to the top surface 14A (including the top surfaces 141A and 142A) of the dielectric layer 14 is between 1000 angstroms and 3000 angstroms. In some embodiments, the portion of silicon carbide layer 12 that is covered by dielectric layer 13 partially leaves surface 12A, and the vertical distance (same as D12) between surface 12C and surface 12A is between 1000 angstroms and 3000 angstroms. In some embodiments, sidewalls 41C, 42C, and 42D have approximately the same height.In some embodiments, the height of sidewall 41D exceeds the height of sidewalls 41C, 42C, or 42D.

[0027] It should be noted that, since a gate structure will be formed on the surface 12C of the silicon carbide layer 12 in a subsequent step, a path will be formed in the silicon carbide layer 12 near the surface 12C between the grooves 41, 42 during operation of the semiconductor rectifying device 1, and the doped regions 221, 222 will extend laterally in the silicon carbide layer 12 below the gate structure, favoring current flow. As shown in FIG. 4 above, the oblique ion implantation limits the extent of the contact surface 12A of the doped regions 221, 222 due to the presence of the patterned layer 51. However, the dry etching step of FIG. 8 increases the extent of the contact surface 12C of the doped regions 221, 222, favoring current flow and improving the efficiency of the semiconductor rectifying device 1. In some embodiments, after the dry etching step, the height of the sidewall 41C is less than the height of the sidewall 41D. In some embodiments, after the dry etching step, the doped region 221 has a corner of the surface 12C adjacent to the sidewall 41C. In some embodiments, after the dry etching step, doped region 221 has sidewall 41C and a portion of surface 12C adjacent to it. Similarly, the heights of sidewalls 42C and 42D of groove 42 are approximately the same as the height of sidewall 41C. Furthermore, the positional relationship between doped region 222 and surface 12C is similar to the positional relationship between doped region 221 and sidewall 41C, and therefore will not be repeated here.

[0028] Referring to FIG. 9 , the method for fabricating semiconductor rectifying device 1 includes forming dielectric layer 15 on exposed surface 12C of silicon carbide layer 12. In some embodiments, dielectric layer 15 includes an oxide (e.g., silicon oxide). In some embodiments, dielectric layer 15 is formed by thermally oxidizing silicon carbide layer 12. In some embodiments, dielectric layer 15 has a thickness between 50 angstroms and 200 angstroms. In some embodiments, dielectric layer 15 is a gate dielectric layer of a subsequently formed gate structure. In some embodiments, dielectric layer 15 covers the entire exposed surface 12C of silicon carbide layer 12. Dielectric layer 15 includes multiple portions, each extending between adjacent portions of dielectric layer 14. For example, dielectric layer 15 includes partial dielectric layer 151 and partial dielectric layer 152. In some embodiments, portions of dielectric layers 151, 152 therein are separated from each other. In some embodiments, partial dielectric layer 151 extends over surface 12C between grooves 41, 42. In some embodiments, partial dielectric layer 151 is located between and in contact with partial dielectric layers 141, 142. In some embodiments, partial dielectric layer 152 extends over surface 12C between partial dielectric layer 142 and another portion (not shown) of another adjacent dielectric layer 14.

[0029] 10 , the method for fabricating the semiconductor rectifying device 1 includes forming a gate electrode layer 16 on the dielectric layer 15. In some embodiments, the gate electrode layer 16 includes polycrystalline silicon. In some embodiments, a deposition step is performed to form a gate electrode material that covers the entire silicon carbide layer 12, and then an etching step is performed to remove the gate electrode material above the top surface 14A of the dielectric layer 14, thereby forming the gate electrode layer 16. Similar to the dielectric layer 15, the gate electrode layer 16 also includes multiple portions, each formed on a different portion of the dielectric layer 15. For example, the gate electrode layer 16 includes a gate electrode 161 on the partial dielectric layer 151 and a gate electrode 162 on the partial dielectric layer 152 adjacent to the gate electrode 161, and the gate electrodes 161 and 162 are separated from each other.

[0030] The gate electrode layer 16 and the dielectric layer 14 have an etching selectivity, such that an etching step performed on the gate electrode material stops on the top surface 14A of the dielectric layer 14. Thus, the top surface 16A of the gate electrode layer 16 and the top surface 14A of the dielectric layer 14 are located at approximately the same horizontal height. In some embodiments, the top surface 16A of the gate electrode layer 16 is flush or coplanar with the top surface 14A of the dielectric layer 14. In other words, the top surface 161A of the gate electrode 161 is located at the same horizontal height or coplanar with any one or more of the top surface 141A of the partial dielectric layer 141, the top surface 142A of the partial dielectric layer 142, and the top surface 162A of the gate electrode 162. Furthermore, because the top surface 14A of the dielectric layer 14 is flush or coplanar with the surface 12A of the silicon carbide layer 12, the top surface 16A of the gate electrode layer 16 is flush or coplanar with the surface 12A of the silicon carbide layer 12. In other words, one or more of top surface 161A of gate electrode 161 and top surface 162A of gate electrode 162 are located at the same horizontal height as surface 12A of silicon carbide layer 12.

[0031] 11 , the method for fabricating the semiconductor rectifying device 1 includes removing the dielectric layer 14. In some embodiments, wet etching is performed to remove the dielectric layer 14 in the grooves 41, 42. The gate electrode 161 and the partial dielectric layer 151 collectively form a gate structure 171, and the gate electrode 162 and the partial dielectric layer 152 collectively form a gate structure 172. In some embodiments, the sidewall adjacent to the sidewall 41C of the gate structure 171 and the sidewall 41C are aligned in a cross-sectional view, and the sidewall adjacent to the sidewall 42D of the gate structure 171 and the sidewall 42D are aligned in a cross-sectional view. The gate structure 172 has a similar configuration to the gate structure 171 and will not be described again here.

[0032] 12 , the method for fabricating the semiconductor rectifying device 1 includes conformally forming a contact metal layer 31 on the silicon carbide layer 12 and the gate structure 17. The contact metal layer 31 may include a suitable metal material, such as titanium (Ti), nickel (Ni), molybdenum (Mo), titanium nitride (TiN), molybdenum nitride (MoN), or a combination thereof. In some embodiments, the contact metal layer 31 contacts a sidewall 41C and a portion of a bottom surface 41B of the trench 41, and also contacts sidewalls 42C, 42D, and a bottom surface 42B of the trench 42. During or after forming the contact metal layer 31, a step at a temperature of 400 to 600°C may be performed to form metal silicides between the contact metal layer 31 and the silicon carbide layer 12 and between the contact metal layer 31 and the gate electrode layer 16. The formation of metal silicide can reduce the electrical resistance between the contact metal layer 31 and the silicon carbide layer 12 or between the contact metal layer 31 and the gate electrode layer 16, thereby helping to improve the performance of the semiconductor rectifying element 1.

[0033] Referring to FIG. 13 , the method for fabricating the semiconductor rectifying device 1 includes forming a first electrode layer 32 on a contact metal layer 31. The first electrode layer 32 may include a suitable metal material or alloy, such as, but not limited to, titanium tungsten (TiW), aluminum-silicon-copper (AlSiCu), or a combination thereof. After forming the first electrode layer 32, the first electrode layer 32 and the contact metal layer 31 are etched to electrically connect some gate structures 17 and electrically isolate some gate structures 17. Since the etching step is performed based on the required circuit design, the drawings do not depict the etching step. However, those skilled in the art can adjust the etching step based on the above content of this disclosure to form the required patterns of the first electrode layer 32 and the contact metal layer 31.

[0034] Referring to FIG. 14 , the method for fabricating the semiconductor rectifying device 1 includes forming a passivation layer 33 on the first electrode layer 32 and forming a second electrode layer 34 below the silicon carbide layer 12. In some embodiments, the passivation layer 33 can be formed through deposition and patterning steps. The exposed portions of the first electrode layer 32 are used to electrically connect to a conductive plug (not shown) in a subsequent process of forming the conductive plug. In some embodiments, the second electrode layer 34 has the same conductive material as the first electrode layer 32. The second electrode layer 34 and the first electrode layer 32 are located on opposite sides of the silicon carbide layer 12. In some embodiments, the second electrode layer 34 is formed on a surface 11B of the semiconductor material layer 11. In some embodiments, the second electrode layer 34 contacts the semiconductor material layer 11. In some embodiments, the semiconductor material layer 11 is polished or etched to reduce its thickness before forming the second electrode layer 34.

[0035] The arrows in FIG. 14 indicate the direction of current flow during operation of semiconductor rectifier device 1, and it can be understood that a larger extent of lateral contact surface 12C of doped region 221 aids in current flow. As explained above, the angled ion implantation of FIG. 4 facilitates horizontal extension of doped region 22 along trench sidewalls (e.g., 41C, 42C, 42D), but patterned layer 51 limits the horizontal extent of the portion of doped region 22 adjacent to surface 12A. This problem is solved by the step of FIG. 8 . The portion of doped region 221 at the bottom of gate structure 171 can provide an extension of the doped region (similar to a lightly doped drain extension (LDD) of a transistor), thereby enhancing the operating speed of semiconductor rectifier device 1.

[0036] The self-aligned gate process not only helps reduce the use of photomasks, avoiding alignment issues, but also lowers overall process costs. However, conventional gate structure self-alignment processes use the gate structure as a mask to implant ions into the substrate, so the annealing step to activate the ions must be performed after the gate structure is formed, making self-aligned gates unsuitable for silicon carbide materials. According to the steps shown in Figures 1 through 14, the high-temperature annealing step of the present disclosure is performed before the gate structure 17 formation step, thereby solving the problem of gate structure damage caused by excessively high annealing temperatures in the prior art and further promoting its application to silicon carbide materials. Both the doped region 22 and the gate structure 17 can be defined by the patterned layer 51, achieving the effects of the prior art self-aligned gate process without requiring a separate photomask. Furthermore, because the doped region 22 is formed by an angled ion implantation step, the present disclosure achieves the effect of self-aligned extension of the doped region.

[0037] 15 and 16 are top views of semiconductor rectifiers 2 and 3 according to various embodiments of the present disclosure, illustrating that the gate structures 17 can have various configurations. It should be noted that the configurations of the gate structures 17 shown in FIGS. 15 and 16 are for illustrative purposes only and are not intended to limit the present disclosure.

[0038] Referring to FIG. 15 , in some embodiments, gate structures 17 include multiple groups, and the extension directions of gate structures 17 of adjacent groups are perpendicular to each other. In some embodiments, doped region 21 is annular and surrounds all of gate structures 17. In some embodiments, gate structures 171 and 172 in FIG. 14 are connected to each other. In some embodiments, gate structures 171 and 172 belong to both sides of the same gate structure, where the both sides are opposite and parallel to each other. In some embodiments, FIGS. 1-14 are schematic cross-sectional views of multiple stages taken along line A-A′ of FIG. 15 . In some embodiments, FIGS. 1-14 are schematic cross-sectional views of multiple stages taken along line B-B′ of FIG. 15 . In some embodiments, doped region 25 is adjacent to surface 12A and surrounds doped region 221 in a top view.

[0039] Referring to FIG. 16 , in some embodiments, gate structure 17 includes a plurality of adjacent gate structures 17 that are parallel to one another. In some embodiments, doped region 21 is annular and surrounds all of gate structures 17. In some embodiments, gate structures 17 extend parallel to one side of semiconductor rectifier device 3 and are connected to one another. In some embodiments, gate structures 171 and 172 in FIG. 14 are connected to one another. In some embodiments, gate structures 171 and 172 belong to both sides of the same gate structure, where the both sides are opposite and parallel to one another. In some embodiments, FIGS. 1-14 are schematic cross-sectional views of multiple stages taken along line C-C′ in FIG. 16 . In some embodiments, doped region 25 is adjacent to surface 12A and surrounds doped region 221 in a top view.

[0040] According to the structure and process of the present disclosure described above, the same or similar vertical power semiconductor device or semiconductor rectifier device can be realized by adjusting or rearranging the steps in the above process while maintaining the same purpose and concept. FIGS. 17-23 illustrate one or more stages in a method for manufacturing a semiconductor rectifier device 4 according to other embodiments of the present disclosure. At least some of these drawings have been simplified to facilitate a better understanding of the aspects of the present disclosure. For simplicity's sake, the following description will focus on differences from the process shown in FIGS. 1-14, and will not include repeated descriptions of identical or similar steps.

[0041] 17 to 18, a plurality of trenches are formed according to the steps of FIGS. 1 to 3, except that in the embodiment of FIG. 18, the plurality of trenches further includes trench 43 adjacent to trench 42, trench 43 and trench 41 are located on opposite sides of trench 42, and trench 41 is formed within doped region 21. In some embodiments, patterned layer 51 further includes opening 513 corresponding to trench 43. In some embodiments, opening 511 is located within the coverage of doped region 21 projected along the vertical direction in a cross-sectional view. In some embodiments, sidewalls 41C, 41D and bottom surface 41B are adjacent to trench 41 in doped region 21 in a cross-sectional view.

[0042] 19, multiple doped regions 22 are formed based on the steps of FIG. 4, except that in the ion implantation step shown in FIG. 19, the trench 41 is formed within the area covered by the doped region 21 of the silicon carbide layer 12, so that the doped region 221 overlaps the doped region 21. In other words, the doped region 21 adjacent to the sidewalls 41C, 41D and bottom surface 41B of the trench 41 is simultaneously ion-implanted during the step of forming the doped region 22. In some embodiments, the doped region 221 is formed within the doped region 21. In some embodiments, the doped region 221 has a higher doping concentration than the doped region 21 or other doped regions 22 (e.g., doped regions 222, 223). After the steps of FIG. 19, a carbon-containing layer is formed based on the steps of FIG. 5, followed by a high-temperature annealing step, and the carbon-containing layer is removed after the high-temperature annealing step.

[0043] Referring to Figure 20, a dielectric layer 14 is formed based on the steps of Figure 7 described above, but the difference is that the dielectric layer 14 shown in Figure 20 further includes a partial dielectric layer 143 located in the groove 43, and the opposing side walls and bottom surface of the partial dielectric layer 141 are adjacent to the doped region 221.

[0044] 21 , a portion of the silicon carbide layer 12 adjacent to the surface 12A is removed based on the steps of FIG. 8 . However, the difference is that the silicon carbide layer 12 shown in FIG. 20 is not covered by the dielectric layer 13 of FIG. 8 , and therefore the silicon carbide layer 12 cannot simultaneously have surfaces 12A and 12C located at different horizontal heights. In some embodiments, the etching step is performed on all of the surface 12A where the dielectric layer 14 is exposed. In other words, in some embodiments, the top surface of the silicon carbide layer 12 (corresponding to surface 12C) after the etching step is lower than the top surface 14A of the dielectric layer 14.

[0045] 22, a dielectric layer 13 is formed based on the steps of FIG. 6 above, except that the dielectric layer 13 shown in FIG. 22 is located on the surface 12C and does not cover the groove 41. In some embodiments, the dielectric layer 13 is separated from the partial dielectric layer 141.

[0046] 23 , the semiconductor rectifying device 4 is formed based on the steps of FIGS. 9 to 14 , except that the gate structure 17 of FIG. 23 further includes gate structures 173 and 174. In some embodiments, the dielectric layer 15 further includes partial dielectric layers 153 and 154, where the partial dielectric layer 153 is located on a portion of the surface 12C adjacent to the groove 43 and on a side of the groove 43 opposite the partial dielectric layer 152, and the partial dielectric layer 154 is located on the surface 12C between the groove 41 and the dielectric layer 13. In some embodiments, the gate electrode layer 16 further includes a gate electrode 163 located on the partial dielectric layer 153 and a gate electrode 164 located on the partial dielectric layer 154. In some embodiments, the gate structure 173 includes the partial dielectric layer 153 and the gate electrode 163, and the gate structure 174 includes the partial dielectric layer 154 and the gate electrode 164. The gate structure 174 is adjacent to the dielectric layer 13 and is also referred to as a dummy gate because it does not contribute to the operation and performance of the semiconductor rectifying device 4 .

[0047] Based on the structure and process of the present disclosure described above, the same or similar semiconductor rectifiers can be realized with the same purpose and concept by adjusting or rearranging the steps in the above processes. FIGS. 24 to 30 show one or more stages in a method for manufacturing a semiconductor rectifier 5 according to other embodiments of the present disclosure. At least some of these drawings have been simplified to allow a better understanding of the aspects of the present disclosure. For simplicity's sake, only the differences from the processes shown in FIGS. 17 to 23 will be described below, and the same or similar steps will not be described repeatedly.

[0048] 24, multiple doped regions 22 are formed based on the steps of FIG. 18 described above, except that in the embodiment of FIG. 24, the ion implantation step involves vertically implanting ions into silicon carbide layer 12. In some embodiments, the ion implantation step includes vertical ion implantation. In some embodiments, the ion implantation step does not include angled ion implantation. By adjusting the parameters of the ion implantation process, the multiple doped regions 22 formed can be adjusted to be separated from or adjacent to surface 12A. In some embodiments, each doped region 22 (including 221, 222, and 223) is separated from surface 12A, and a vertical distance D13 between each doped region 22 (including 221, 222, and 223) and surface 12A is between 1000 and 2000 angstroms. In some embodiments, each doped region 22 (including 221, 222, 223) is adjacent to surface 12A (similar to doped regions 221, 222, 223 in FIG. 19).

[0049] 25 , the method for manufacturing the semiconductor rectifying device 5 further includes forming sidewall spacers 54 on the sidewalls of the openings 511, 512, and 513 in the patterned layer 53. The formation of the sidewall spacers 54 includes, for example, conformally depositing a dielectric material on the patterned layer 53 and the silicon carbide layer 12, and then performing an etching process on the dielectric material to remove the dielectric material in the horizontal portions.

[0050] 26, multiple trenches (including 41, 42, and 43) are formed based on the etching steps of FIG. 18 (or FIG. 3) described above, except that the embodiment of FIG. 26 uses patterned layer 53 and sidewall spacers 54 as a mask to etch silicon carbide layer 12. In some embodiments, the widths of trenches 41, 42, and 43 are less than the widths of openings 511, 512, and 513, respectively. In some embodiments, patterned layer 53 and sidewall spacers 54 comprise the same dielectric material. In some embodiments, patterned layer 53 and sidewall spacers 54 can be removed simultaneously (or in a single etching step).

[0051] 27 to 30, the semiconductor rectifying device 5 is formed based on the steps of the aforementioned FIGS. 20 to 23, except that the step of forming the doped regions 22 in FIG. 30 does not include angled ion implantation, so the arrangement of the doped regions 22 in the semiconductor rectifying device 5 may be slightly different from the arrangement of the doped regions 22 in the semiconductor rectifying device 4. Furthermore, in some embodiments, since the doped regions 22 in the semiconductor rectifying device 5 are separated from the surface 12A (as shown in FIG. 27), the predetermined thickness of the etching step in FIG. 28 will be controlled to be equal to or greater than the distance D13 shown in FIG. 24 to ensure that the plurality of doped regions 221, 222, and 223 (especially 222 and 223) contact the surface 12C.

[0052] The semiconductor rectifiers 4 and 5 formed according to the above methods have a similar structure to the semiconductor rectifier 1, and their advantages over the prior art are the same as those of the semiconductor rectifier 1, so they will not be described again here. The semiconductor rectifiers provided in the present disclosure can reduce power consumption and improve switching efficiency thanks to the material properties of silicon carbide, and the manufacturing method provided in the present disclosure effectively aligns the self-alignment process on silicon oxide materials, avoiding damage to the gate structure caused by the high-temperature annealing process, while also reducing the overall process cost.

[0053] For ease of description, spatial terms such as "below," "lower," "bottom," "above," "top," "left side," and "right side" are used throughout the text to describe the relationship of one component or feature shown in the drawings to one or more other components or features. In addition to the orientation depicted in the drawings, spatial terms may also cover different orientations of the device during use or operation. Other methods of orientation (such as rotated 90 degrees or other orientations) of the device may be used, and spatial terms used throughout the text may be interpreted accordingly. When a component is described as being "connected" or "coupled" to another component, it should be understood that the component may be directly connected or coupled to the other component, or that intermediate components may be present.

[0054] As used herein, the terms "generally," "nearly," "essentially," and "about" are used to describe and interpret small variations. When used in connection with an event or circumstance, the term can refer to instances in which the event or circumstance definitely occurred and instances in which the event or circumstance is imminent. When used in connection with a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints unless expressly stated otherwise. The term "substantially coplanar" can refer to two surfaces positioned along the same plane being within a few micrometers (μm) of each other, e.g., within 10 μm, 5 μm, 1 μm, or 0.5 μm of each other. When numerical values ​​or characteristics are referred to as being "approximately" the same, the term can refer to values ​​within ±10%, ±5%, ±1% or ±0.5% of the mean value of the value.

[0055] The foregoing has outlined certain exemplary features and detailed aspects of the present disclosure. The exemplary embodiments described herein may readily be used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the exemplary embodiments described herein. Various alterations, substitutions, and modifications may be made to such equivalent structures without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0056] 1, 2, 3, 4, 5 Semiconductor rectifier 11 Semiconductor material layer 11A, 11B surface 12 Silicon carbide layer 12A, 12B, 12C surface 12D horizontal plane 13 Dielectric layer 14 Dielectric layer 141, 142, 143 Partial dielectric layer 14A, 141A, 142A Top 15 Dielectric layer 151, 152, 153, 154 Partial dielectric layer 16 gate electrode layer 161, 162, 163, 164 Gate electrodes 16A, 161A, 162A Top 17 Gate Structure 171, 172, 173, 174 Gate structure 21 Doped Region 211 areas 22 Doped Region 221, 222, 223 doped regions 25 doped region 31 Contact metal layer 32 1st electrode layer 33 Passivation layer 34 Second electrode layer 41 Groove 41B Bottom 41C, 41D side wall 42 Groove 42B bottom 42C, 42D sidewalls 43 Groove 51 Patterned Layer 511, 512, 513 aperture 52 Carbon-containing layer 53 Patterned Layer 54 Sidewall spacer D12, D13 distance D41, D42 depth

Claims

1. In semiconductor rectifying elements, an epitaxial layer having opposing top and bottom surfaces; a first groove extending from the top surface to the bottom surface and including a first side wall and a second side wall opposed to each other, and a first bottom surface connecting the first side wall and the second side wall; a second groove extending from the top surface to the bottom surface and adjacent to the first groove, the second groove including a third side wall and a fourth side wall opposed to each other and a second bottom surface connecting the third side wall and the fourth side wall; a first doped region extending from the top surface to the bottom surface and adjacent to the first sidewall of the first groove and at least a portion of the first bottom surface; a second doped region adjacent to the first doped region and separated from the first doped region, extending from the top surface to the bottom surface, and adjacent to the third sidewall, the fourth sidewall and the second bottom surface of the second groove; a gate structure disposed on the top surface between the first groove and the second groove and having a bottom surface adjacent to the first doped region and the second doped region; and a contact metal layer disposed on the top surface of the epitaxial layer along the first groove, the gate structure and the second groove. Semiconductor rectifier element.

2. 2. The semiconductor rectifier element of claim 1, wherein the gate structure includes a fifth sidewall and a sixth sidewall opposing each other, the fifth sidewall and the second sidewall of the first groove are aligned in a cross-sectional view, and the sixth sidewall of the gate structure and the third sidewall of the second groove are aligned in a cross-sectional view.

3. 2. The semiconductor rectifying element according to claim 1, wherein the first sidewall of the first groove is connected to a first portion of the top surface, a portion of the top surface between the first groove and the second groove is a second portion of the top surface, and the first portion and the second portion are located at approximately the same horizontal height.

4. 2. The semiconductor rectifier element of claim 1, wherein the first sidewall of the first groove is connected to a first portion of the top surface, a portion of the top surface between the first groove and the second groove is a second portion of the top surface, and a horizontal height of the first portion is greater than a horizontal height of the second portion.

5. a third doped region extending from the top surface to the bottom surface and overlapping at least a portion of the first doped region and having a depth greater than a depth of the first doped region. The semiconductor rectifying element according to claim 1 .

6. The semiconductor rectifying element according to claim 5 , wherein a portion of the third doped region close to the first doped region has a high doping concentration.

7. 2. The semiconductor rectifier element of claim 1, wherein the contact metal layer is in contact with the second sidewall of the first groove, the bottom surface of the first groove, the third sidewall and the fourth sidewall of the second groove, and the bottom surface of the second groove.

8. The semiconductor rectifying device of claim 1 , wherein the first doped region further adjoins the first sidewall of the first trench.

9. 2. The semiconductor rectifying element of claim 1, wherein a first height of the first sidewall of the first groove is greater than a second height of the second sidewall, a third height of the third sidewall of the second groove is approximately the same as a fourth height of the fourth sidewall, and the second height, the third height, and the fourth height are approximately the same.

10. In a method for manufacturing a semiconductor rectifying element, forming a patterned layer on the silicon carbide layer; Etching the silicon carbide layer using the patterned layer as a mask to form a first groove and a second groove adjacent to the first groove; implanting ions into the silicon carbide layer using the patterned layer as a mask; subjecting the silicon carbide layer to a thermal anneal; and forming a gate structure on the silicon carbide layer between the first trench and the second trench after the thermal annealing, the gate structure having a first sidewall and a second sidewall opposite each other, the first sidewall and one sidewall of the first trench being a continuous sidewall, and the second sidewall and one sidewall of the second trench being a continuous sidewall. A method for manufacturing a semiconductor rectifier.

11. forming a carbon-containing layer overlying the silicon carbide layer prior to the thermal anneal; and removing the carbon-containing layer after the thermal anneal. The method of claim 10.

12. forming a first dielectric layer for filling the first trench and the second trench, a top surface of the first dielectric layer being flush with a top surface of the silicon carbide layer; removing an exposed portion of the silicon carbide layer adjacent the top surface of the silicon carbide layer to form a first surface lower than the top surface of the silicon carbide layer, the first surface being higher than a bottom surface of the first trench; and forming the gate structure on the first surface. The method of claim 10.

13. forming a gate structure on the first surface; forming a second dielectric layer on the first surface; forming a gate electrode layer on the second dielectric layer, the gate electrode layer having a top surface coplanar with the top surface of the first dielectric layer. The method of claim 12.

14. The method of claim 12, wherein the vertical distance between the first surface and the top surface of the silicon carbide layer is between 1500 and 2000 Angstroms.

15. and forming a termination doped region in the silicon carbide layer prior to forming the patterned layer. The method of claim 10.

16. The method of claim 15 , wherein the patterned layer exposes a portion of the termination doped region, and the termination doped region is adjacent to the first trench.

17. 16. The method of claim 15, wherein the patterned layer includes an opening that defines the first trench, and in a cross-sectional view, the opening vertically overlaps a portion of the termination doped region.

18. 16. The method of claim 15, wherein the patterned layer includes an opening that defines the first trench, and when viewed in cross section, the opening is located within a coverage area of ​​a vertical projection of the termination doped region.

19. and forming a third dielectric layer to cover the termination doped region and a portion of the first trench adjacent to the termination doped region prior to forming the gate structure on the silicon carbide layer between the first trench and the second trench. The method of claim 15.

20. conformally forming a contact metal layer on the silicon carbide layer and the gate structure in contact with the sidewalls and bottom surface of the first trench and in contact with the sidewalls and bottom surface of the second trench; forming a first electrode layer on the contact metal layer; forming a second electrode layer below the silicon carbide layer, the first electrode layer and the second electrode layer being located on opposite sides of the silicon carbide layer. The method of claim 10.

21. Providing a substrate; epitaxially growing on the substrate to form the silicon carbide layer; Reducing a thickness of the substrate; and forming the second electrode layer in contact with the substrate. The method of claim 20.

22. The method of claim 10, wherein the first groove or the second groove has a depth between 4000 and 5000 angstroms.

23. The method of claim 10 , wherein the ion implantation comprises angled ion implantation.

24. forming sidewall spacers on sidewalls of the patterned layer prior to the ion implantation. The method of claim 10.

25. The method of claim 24 , wherein the ion implantation is performed on the silicon carbide layer using the patterned layer and the sidewall spacers as a mask.

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