Storage devices for managing sub-block reclaim operations

Abstract

To provide a storage device capable of reducing performance degradation due to uncorrectable errors.SOLUTION: A storage device of the present invention includes a first memory block having first and second memory sub-blocks, and a second memory block having third and fourth memory sub-blocks, and is configured to determine whether the second memory sub-block is a reclaim sub-block when the first memory sub-block has an uncorrectable error UECC therein, and reclaim the first and second memory sub-blocks to the third and fourth memory sub-blocks, respectively, when the second memory sub-block is determined to be a reclaim sub-block.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to semiconductor memory devices, and more particularly to a storage device including a sub-block management module and a sub-block reclaim operation thereof. [Background technology]

[0002] Semiconductor memory devices can be broadly divided into volatile memory and non-volatile memory. Volatile memory (e.g., DRAM and SRAM) has fast read and write speeds, but the stored data is lost when the power supply is cut off. On the other hand, non-volatile memory can retain data even when the power supply is interrupted.

[0003] A typical example of non-volatile memory is a flash memory. A flash memory can store multi-bit data (two or more bits) in one memory cell. A flash memory that stores multi-bit data has one erased state and multiple programmed states according to a threshold voltage distribution.

[0004] It is important for flash memory to have a read margin between each program state. However, the threshold voltage of flash memory may change due to various reasons. For example, the erased state may overlap with the program state due to an increase in the threshold voltage of the memory cell. As a result, an uncorrectable error (UECC) may occur. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Pat. No. 1,071,2954 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a storage device that, when an uncorrectable error occurs in any one of the sub-blocks in a memory block, can reduce performance degradation due to the uncorrectable error by determining in advance whether or not other sub-blocks in the same memory block can be reclaimed and performing a sub-block reclaim operation. [Means for solving the problem]

[0007] In order to achieve the above object, according to one aspect of the present invention, a storage device includes a first memory block having first and second sub-blocks, and a second memory block having third and fourth sub-blocks, and when an uncorrectable error UECC occurs in the first sub-block, it determines whether the second sub-block is a reclaim sub-block, and if it is determined that the second sub-block is a reclaim sub-block, it reclaims the first and second sub-blocks to the third and fourth sub-blocks, respectively.

[0008] According to another aspect of the present invention, which has been made to achieve the above object, a storage device includes a first memory block having first to third sub-blocks, the second sub-block being a sub-block that is in use and the third sub-block being an unused sub-block, and a second memory block having fourth to sixth sub-blocks, and is characterized in that if an uncorrectable error UECC occurs in the first sub-block, the first to third sub-blocks are reclaimed to the fourth and sixth sub-blocks, respectively.

[0009] In accordance with yet another aspect of the present invention, which has been made to achieve the above object, a storage device includes a memory device including a first memory block having first and second sub-blocks and a second memory block having third and fourth sub-blocks; and a memory controller that controls the flash memory to reclaim the first and second sub-blocks to the third and fourth sub-blocks, respectively, if the second sub-block is a sub-block in use when an uncorrectable error UECC occurs in the first sub-block. Effect of the Invention

[0010] The storage device according to the present invention can perform a sub-block reclaim operation between memory blocks. The sub-block management module checks in advance the reclaim operation of other sub-blocks in the same memory block, and designates a reclaim sub-block according to a degradation level, and performs a reclaim operation on the other memory blocks, thereby reducing performance degradation due to an uncorrectable error UECC. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a block diagram illustrating a storage device according to an embodiment of the present invention. [Diagram 2] 2 is a block diagram illustrating an example of the memory device illustrated in FIG. 1; [Diagram 3] 3 is a circuit diagram showing an example of a memory block BLK1 of the memory cell array described in FIG. 2. [Figure 4] 4 is a circuit diagram showing a cell string selected by a first string selection line SSL1 among the cell strings of the memory block BLK1 shown in FIG. 3. [Diagram 5] 5 is a diagram showing an example of a threshold voltage distribution of the memory cell shown in FIG. 4. [Figure 6] 2 is a block diagram illustrating an example of a memory controller of FIG. 1. [Figure 7]7 is a flowchart illustrating a subblock reclaim operation method of the subblock management module illustrated in FIG. 6. [Figure 8] 8 is a diagram illustrating an example of the sub-block reclaim operation and the sub-block erase operation described in FIG. 7. [Figure 9] 7 is a flowchart illustrating an example in which the subblock management module illustrated in FIG. 6 designates all subblocks as reclaim subblocks. [Figure 10] 7 is a diagram showing an example in which the subblock management module shown in FIG. 6 designates all subblocks as reclaim subblocks. [Figure 11] 7 is a flowchart showing an example in which the subblock management module shown in FIG. 6 designates a subblock in use as a reclaim subblock. [Figure 12] 7 is a diagram showing an example in which the subblock management module shown in FIG. 6 designates a subblock in use as a reclaim subblock. [Figure 13] 7 is a flowchart illustrating an example in which the sub-block management module illustrated in FIG. 6 designates a reclaim sub-block based on the number of error bits of the sub-block. [Figure 14] 7 is a diagram showing an example in which the sub-block management module shown in FIG. 6 designates a reclaim sub-block based on the number of error bits of the sub-block; [Figure 15] 7 is a diagram showing an example in which the sub-block management module shown in FIG. 6 designates a reclaim sub-block based on the number of error bits of the sub-block; [Figure 16] 7 is a diagram showing an example in which the sub-block management module shown in FIG. 6 designates a reclaim sub-block based on the number of error bits of the sub-block; [Figure 17] 7 is a flowchart illustrating an example of a sub-block erase operation of the sub-block management module illustrated in FIG. 6; [Figure 18]7 is a diagram illustrating an example of a sub-block erase operation of the sub-block management module illustrated in FIG. 6; [Figure 19] 1 is a diagram illustrating an example of a flash memory having a multi-stack structure; [Figure 20] 1 is a block diagram illustrating an example in which a storage device according to an embodiment of the present invention is implemented as a solid state drive (SSD). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the embodiments of the present invention will be described clearly and in detail to such an extent that those skilled in the art can easily practice the present invention.

[0013] 1 is a block diagram illustrating a storage device according to an embodiment of the present invention. Referring to FIG. 1, a storage device 1000 includes a memory device 1100 and a memory controller 1200.

[0014] The memory device 1100 receives an input / output signal IO through an input / output line, a control signal CTRL through a control line, and an external power supply PWR through a power supply line from the memory controller 1200. The storage device 1000 stores data in the memory device 1100 under the control of the memory controller 1200.

[0015] The memory device 1100 includes a memory cell array 1110 and a peripheral circuit 1115. The memory cell array 1110 has a planar two-dimensional structure or a vertical three-dimensional structure. The memory cell array 1110 is composed of a plurality of memory cells. Each memory cell stores single-bit data or multi-bit data.

[0016] The memory cell array 1110 may be located to the side or above the peripheral circuit 1115 depending on the design layout structure. A structure in which the memory cell array 1110 is located on the peripheral circuit 1115 is called a COP (cell on peripheral) structure. The memory cell array 1110 is manufactured on a chip separate from the peripheral circuit 1115. An upper chip including the memory cell array 1110 and a lower chip including the peripheral circuit 1115 are connected to each other by a bonding method. This structure is called a C2C (chip to chip) structure.

[0017] The memory cell array 1110 includes a plurality of memory blocks BLK1 to BLKn. Each memory block is composed of a plurality of sub-blocks. For example, the first memory block BLK1 includes first to third sub-blocks.

[0018] The peripheral circuits 1115 include all analog and digital circuits necessary to store data in or read data stored in the memory cell array 1110. The peripheral circuits 1115 receive an external power supply PWR through a power supply line and generate various levels of internal powers.

[0019] The peripheral circuit 1115 receives commands, addresses, and data from the memory controller 1200 through input / output lines. The peripheral circuit 1115 stores data in the memory cell array 1110 according to a control signal CTRL. The peripheral circuit 1115 also reads data stored in the memory cell array 1110 and provides the read data to the memory controller 1200.

[0020] The memory controller 1200 includes a sub-block management module 2000. When an uncorrectable error UECC occurs in the first sub-block of the first memory block BLK1, the sub-block management module 2000 reclaims the first and second sub-blocks to the second memory block if the second sub-block is determined to be a reclaim sub-block.

[0021] When any one of the sub-blocks is repeatedly read, the number of error bits may increase due to problems such as read disturbance. When an uncorrectable error (UECC) occurs in data stored in the first sub-block, an operation of moving data stored in the second sub-block to the second memory block is called a sub-block reclaim. The sub-block management module 2000 manages the sub-block reclaim operation of the memory device 1100.

[0022] Fig. 2 is a block diagram of an example of the memory device illustrated in Fig. 1. The storage device 1000 in Fig. 1 is a flash storage device based on a flash memory. For example, the storage device 1000 may be implemented as an SSD, a UFS, a memory card, or the like.

[0023] 1 and 2, a memory device 1100 includes a memory cell array 1110 and peripheral circuits 1115. The peripheral circuits 1115 include an address decoder 1120, a page buffer circuit 1130, an input / output circuit 1140, a word line voltage generator 1150, and control logic 1160.

[0024] The memory cell array 1110 includes a plurality of memory blocks BLK1 to BLKn. Each memory block is composed of a plurality of sub-blocks. For example, the first memory block BLK1 is composed of first to third sub-blocks SB11, SB12, and SB13, the second memory block BLK2 is composed of fourth to sixth sub-blocks SB21, SB22, and SB23, and the n-th memory block BLKn is composed of seventh to ninth sub-blocks SBn1, SBn2, and SBn3.

[0025] Each sub-block is connected to multiple word lines, and each page is composed of one or more pages. Each page is composed of multiple memory cells. Each memory cell stores multi-bit data. Each memory block or sub-block is an erase unit, and each page is a read or write unit.

[0026] The memory cell array 1110 is formed in a direction perpendicular to the substrate. Gate electrode layers and insulation layers are alternately deposited on the substrate. Each memory block (e.g., BLK1) is connected to one or more string selection lines SSL, a plurality of word lines WL1 to WLm, and one or more ground selection lines GSL. WLk is a selected word line (selected WL), and the remaining word lines (WL1 to WLk-1, WLk+1 to WLm) are unselected word lines (unselected WL).

[0027] The address decoder 1120 is connected to the memory cell array 1110 through the selection lines SSL and GSL and the word lines WL1 to WLm. The address decoder 1120 selects a word line during a program or read operation. The address decoder 1120 receives a word line voltage VWL from a word line voltage generator 1150 and provides a program voltage or a read voltage to the selected word line.

[0028] The page buffer circuit 1130 is connected to the memory cell array 1110 through bit lines BL1 to BLz. The page buffer circuit 1130 temporarily stores data to be stored in the memory cell array 1110 or data read from the memory cell array 1110. The page buffer circuit 1130 includes page buffers PB1 to PBz connected to the respective bit lines. Each page buffer includes a plurality of latches for storing or reading multi-bit data.

[0029] The I / O circuit 1140 is internally connected to the page buffer circuit 1130 through a data line DATA and externally connected to the memory controller (see FIG. 1, 1200) through I / O lines IO1 to IOn. The I / O circuit 1140 receives program data from the memory controller 1200 during a program operation. The I / O circuit 1140 also provides data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0030] A word line voltage generator 1150 receives an internal power supply from a control logic 1160 and generates a word line voltage VWL required for reading data. The word line voltage VWL is provided to a selected word line (sWL) or an unselected word line (uWL) through an address decoder 1120.

[0031] The word line voltage generator 1150 includes a program voltage generator (Vpgm generator) 1151 and a pass voltage generator (Vpass generator) 1152. The program voltage generator 1151 generates a program voltage Vpgm that is provided to a selected word line sWL during a program operation. The pass voltage generator 1152 generates a pass voltage Vpass that is provided to the selected word line sWL and the unselected word lines uWL.

[0032] The word line voltage generator 1150 includes a read voltage generator (Vrd generator) 1153 and a read pass voltage generator (Vrdps generator) 1154. The read voltage generator 1153 generates a selected read voltage Vrd provided to a selected word line sWL during a read operation. The read pass voltage generator 1154 generates a read pass voltage Vrdps provided to unselected word lines uWL. The read pass voltage Vrdps is a voltage sufficient to turn on memory cells coupled to unselected word lines uWL during a read operation.

[0033] The control logic 1160 uses a command CMD, an address ADDR, and a control signal CTRL provided from the memory controller 1200 to control operations such as reading, writing, and erasing of the memory device 1100. The address ADDR includes a block selection address for selecting one memory block, a row address for selecting one page, and a column address for selecting one memory cell.

[0034] Fig. 3 is a circuit diagram showing an example of a memory block BLK1 of the memory cell array described in Fig. 2. Referring to Fig. 3, in the memory block BLK1, 11th to 8th cell strings STR11 to STR8z are formed between the 1st to zth bit lines BL1 to BLz and a common source line CSL. Each cell string includes a string selection transistor SST, a plurality of memory cells MC1 to MCm, and a ground selection transistor GST.

[0035] The string selection transistors SST are connected to the first to eighth string selection lines SSL1 to SSL8. The ground selection transistors GST are connected to the first to eighth ground selection lines GSL1 to GSL8. The string selection transistors SST are connected to the first to zth bit lines BL1 to BLz. The ground selection transistors GST are connected to a common source line CSL.

[0036] The first to m-th word lines WL1 to WLm are connected to the first to m-th memory cells MC1 to MCm in the row direction, and the first to z-th bit lines BL1 to BLz are connected to the first to m-th memory cells MC1 to MCm in the column direction.

[0037] The first word line WL1 is located above the first to eighth ground selection lines GSL1 to GSL8. The first word line WL1 is connected to the first memory cell MC1 at the same height from the substrate. The mth word line WLm is located below the first to eighth string selection lines SSL1 to SSL8. The mth memory cell MCm at the same height from the substrate is connected to the mth word line WLm. Similarly, the 2nd to (m-1)th word lines WL2 to WLm-1 are connected to the 2nd to (m-1)th memory cells MC2 to MCm-1 at the same height from the substrate, respectively.

[0038] 4 is a circuit diagram showing a cell string selected by a first string selection line SSL1 among the cell strings of the memory block BLK1 shown in FIG. 3. The 11th to 1zth cell strings STR11 to STR1z are selected by the first string selection line SSL1. The 11th to 1zth cell strings STR11 to STR1z are connected to the 1st to zth bit lines BL1 to BLz, respectively. The 1st to zth bit lines BL1 to BLz are connected to the 1st to zth page buffers PB1 to PBz, respectively.

[0039] The eleventh cell string STR11 is connected to the first bit line BL1 and the common source line CSL. The eleventh cell string STR11 includes a string selection transistor SST selected by a first string selection line SSL1, first to ninth memory cells MC1 to MC9 connected to the first to ninth word lines WL1 to WL9, and a ground selection transistor GST selected by a first ground selection line GSL1. The twelfth cell string STR12 is connected to the second bit line BL2 and the common source line CSL. The 1zth cell string STR1z is connected to the zth bit line BLz and the common source line CSL.

[0040] A set of memory cells selected by one string selection line and connected to one word line is one page. For example, memory cells selected by the first string selection line SSL1 and connected to the fifth word line WL5 constitute one page. For example, eight pages are configured in the fifth word line WL5. Among the eight pages, the page connected to the first string selection line SSL1 is the selected page, and the pages connected to the second to eighth string selection lines SSL2 to SSL8 are unselected pages.

[0041] The first memory block BLK1 is divided into a plurality of smaller sub-blocks SB11, SB12, and SB13. Each of the sub-blocks SB11, SB12, and SB13 is divided in the word line direction, the channel direction, or the bit line direction. Regardless of the basis by which the sub-blocks are divided, each sub-block is erased independently of other sub-blocks within the first memory block BLK1.

[0042] Sub-block SB11 includes memory cells connected to the first to third word lines WL1, WL2, and WL3 among the memory cells included in the first memory block BLK1. Sub-block SB12 includes memory cells connected to the fourth to sixth word lines WL4, WL5, and WL6 among the memory cells included in the first memory block BLK1. Sub-block SB13 includes memory cells connected to the seventh to ninth word lines WL7, WL8, and WL9 among the memory cells included in the first memory block BLK1. That is, one or more of the sub-blocks SB1, SB2, and SB3 are simultaneously selected and erased. Word line voltage generator 1150 of FIG. 2 provides a bias for erasing memory cells in units of sub-blocks SB.

[0043] Figure 5 is a diagram showing an example of a threshold voltage distribution of the memory cells shown in Figure 4. The horizontal axis indicates the threshold voltage Vth, and the vertical axis indicates the number of cells.

[0044] 5 shows an example in which 3-bit data is stored in one memory cell. The 3-bit memory cell has one of eight states E0, P1 to P7 according to the threshold voltage distribution. Here, E0 indicates the erase state, and P1 to P7 indicate the program states.

[0045] During a read operation, selected read voltages Vrd1 to Vrd7 are provided to selected word lines, and pass voltages Vps or read pass voltages Vrdps are provided to unselected word lines. The pass voltages Vps or read pass voltages Vrdps are sufficient to turn on memory cells. For example, the pass voltages Vps are provided to adjacent word lines of the selected word line, and the read pass voltages Vrdps are provided to the remaining unselected word lines except for the adjacent word lines.

[0046] The first selected read voltage Vrd1 is a voltage level between the erased state E0 and the first programmed state P1. The second selected read voltage Vrd2 is a voltage level between the first and second programmed states P1, P2. In this manner, the seventh selected read voltage Vrd7 is a voltage level between the sixth and seventh programmed states P6, P7.

[0047] When the first selective read voltage Vrd1 is applied, memory cells having the erased state E0 become on cells, and memory cells having the first to seventh programmed states P1 to P7 become off cells. When the second selective read voltage Vrd2 is applied, memory cells having the erased state E0 and the first programmed state P1 become on cells, and memory cells having the second to seventh programmed states P2 to P7 become off cells. In this manner, when the seventh selective read voltage Vrd7 is applied, memory cells having the erased state E0 and the first to sixth programmed states P1 to P6 become on cells, and memory cells having the seventh programmed state P7 become off cells.

[0048] During a read operation, the string select line SSL1 and the ground select line GSL1 are provided with a power supply voltage, the string select transistor SST and the ground select transistor GST are turned on, the selected word line is provided with a selected read voltage Vrd, and the unselected word lines are provided with a pass voltage Vps or a read pass voltage Vrdps.

[0049] When the selected word line of the sub-block SB11 is repeatedly read, the remaining word lines are repeatedly provided with a high pass voltage Vps or a read pass voltage Vrdps. At this time, a read disturbance occurs in the sub-blocks SB11, SB12, and SB13 of the first memory block BLK1, causing the threshold voltage of the memory cells in the erased state E0 to rise to the programmed state. The threshold voltage is distorted, causing an uncorrectable error UECC.

[0050] Fig. 6 is a block diagram illustrating an example of the memory controller of Fig. 1. Referring to Fig. 6, the memory controller 1200 includes a host interface 1201, a flash interface 1202, a control unit 1210, a working memory 1220, and an ECC circuit 1240. The working memory 1220 drives a flash translation layer (FTL) 1230.

[0051] The host interface 1201 provides an interface between the host 1500 and the memory controller 1200. Standard interfaces include various interface methods such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCI-E), IEEE1394, universal serial bus (USB), secure digital (SD) card, multi-media card (MMC), embedded multi-media card (eMMC), universal flash storage device (UFS), compact flash (CF) card interface, and the like.

[0052] The flash interface 1202 provides an interface between the flash memory 1100 and the memory controller 1200. For example, write or read data is sent to or received from the flash memory 1100 through the flash interface 1202. The flash interface 1202 provides commands and addresses to the flash memory 1100. The flash interface 1202 also provides data read from the flash memory 1100 to the memory controller 1200.

[0053] The control unit 1210 includes a central processing unit, a microprocessor, or the like, and controls the overall operation of the memory controller 1200. The control unit 1210 drives firmware loaded into the working memory 1220 to control the memory controller 1200.

[0054] The working memory 1220 is implemented with various types of memory, for example, DRAM, SRAM, or PRAM. The working memory 1220 drives a flash translation layer (FTL) 1230 under the control of the control unit 1210. The flash translation layer 1230 is loaded from a flash memory (1100, see FIG. 1) to the working memory 1220 during a booting operation of the storage device (1000, see FIG. 1). The flash translation layer 1230 includes an address mapping module 1231, a garbage collection module 1232, a wear-leveling module 1233, and a sub-block management module 2000 according to functions implemented by firmware.

[0055] The address mapping module 1231 performs an address mapping operation on a page or block basis. The page address mapping operation is an operation for converting a logical page address received from the file system into a physical page address in the flash memory 1100. For this purpose, an address mapping table on a page basis must be maintained in the work memory 1220. The page address mapping operation provides excellent garbage collection performance, but requires a large capacity address mapping table.

[0056] The block address mapping operation is an operation of converting a logical block address received from the file system into a physical block address in the flash memory 1100. At this time, pages belonging to the same logical block belong to the same physical block. For this reason, the block address mapping operation must maintain an address mapping table in units of blocks in the work memory 1220. The block address mapping operation requires a small-sized address mapping table, but can perform an additional garbage collection operation.

[0057] The flash translation layer 1230 performs a hybrid mapping operation that combines the advantages of a page address mapping operation and a block address mapping operation. The flash translation layer 1230 performs a hybrid mapping operation based on a log buffer. The log buffer-based hybrid mapping operation requires a small memory space but can provide excellent garbage collection performance.

[0058] The garbage collection module 1232 performs a garbage collection operation by referring to the address mapping table. For example, in order to secure one or more free blocks, the garbage collection module 1232 writes one or more valid data stored in a source block to an arbitrary block using the address mapping table, and secures a pre-block by erasing the source block from which all the valid data has been moved.

[0059] The wear-leveling module 1233 manages the wear level of the memory cells of the flash memory 1100. The memory cells deteriorate due to recording (programming) and erasing operations, etc. The deteriorated memory cells cause defects. The wear-leveling module 1233 prevents a specific cell region from wearing out faster than other cell regions by managing the program and erase cycles of the memory cell array. The wear-leveling module 1233 controls the address mapping module 1231 so that the program and erase counts are evenly assigned to the cell regions of the memory cell array.

[0060] The ECC circuit 1240 generates an error correction code (ECC) for correcting fail bits or error bits in data received from the flash memory 1100. The ECC circuit 1240 performs error correction encoding on data provided to the flash memory 1100 to form data to which a parity bit is added. The parity bit is stored in the flash memory 1100.

[0061] Meanwhile, the ECC circuit 1240 performs error correction decoding on the data output from the flash memory 1100. The ECC circuit 1240 corrects errors using parity. The ECC circuit 1240 corrects errors using coded modulation such as a low density parity check (LDPC) code, a BCH code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), or a block coded modulation (BCM).

[0062] The ECC circuit 1240 has an error correction tolerance. For example, the ECC circuit 1240 can correct a maximum of 40-bit error for a 2K-byte page data. In this case, the maximum tolerance range in which the ECC circuit 1240 can correct errors is 40 bits. That is, if an error of more than 40 bits occurs, the ECC circuit 1240 cannot correct the error of the page. A page in which errors cannot be corrected in this manner is called a defective page. A memory cell in which an error occurs in a defective page is called a defective cell.

[0063] The sub-block management module 2000 checks the error status of the memory blocks or sub-blocks of the memory cell array 1110, and manages the sub-block reclaim operation and / or the sub-block erase operation when an error status occurs. The sub-block management module 2000 designates the sub-block on which the reclaim operation is to be performed. The sub-block management module 2000 controls the sub-block reclaim operation to be performed within the flash memory 1100.

[0064] The sub-block management module 2000 determines which sub-blocks are to be erased. The sub-block management module 2000 simultaneously erases all sub-blocks SB11, SB12, and SB13 in a memory block (e.g., BLK1), or erases only the reclaim sub-block. When multiple erase sub-blocks are designated, the sub-block management module 2000 simultaneously or sequentially performs the sub-block erase operation.

[0065] 7 is a flowchart illustrating a sub-block reclaim operation method of the sub-block management module 2000 shown in FIG 6. The flash memory 1100 performs a sub-block reclaim operation and / or a sub-block erase operation under the control of the sub-block management module 2000.

[0066] In step S110, a UECC occurs in one sub-block of the memory cell array 1110. The sub-block management module 2000 checks an error status of a memory block or a sub-block of the memory cell array 1110, and manages a sub-block reclaim operation and / or a sub-block erase operation when an uncorrectable error UECC occurs.

[0067] In step S120, the sub-block management module 2000 determines a sub-block that performs a reclaim operation (hereinafter, referred to as a reclaim sub-block). The sub-block management module 2000 determines a reclaim sub-block in various ways. For example, when a UECC occurs in one sub-block (e.g., SB11), the sub-block management module 2000 may determine whether the remaining sub-blocks (e.g., SB12, SB13) are also reclaim sub-blocks.

[0068] The subblock management module 2000 may designate all subblocks SB1, SB2, and SB3, including the remaining subblocks, as reclaim subblocks. Alternatively, the subblock management module 2000 may designate a reclaim subblock based on the number of error bits of the remaining subblocks. For example, if the number of error bits of the remaining subblock SB12 or SB13 is greater than the reference number of bits, the corresponding subblock is designated as a reclaim subblock.

[0069] In step S130, the sub-block management module 2000 controls to perform a sub-block reclaim operation within the flash memory 1100. The flash memory 1100 receives a command, address, and control signal for the sub-block reclaim operation from the memory controller 1200, and performs the sub-block reclaim operation. When multiple reclaim sub-blocks are specified, the sub-block reclaim operations are performed simultaneously or sequentially.

[0070] In step S140, the sub-block management module 2000 determines a sub-block for performing an erase operation (hereinafter, referred to as an erase sub-block). The sub-block management module 2000 determines the erase sub-block in various ways. For example, the sub-block management module 2000 erases all sub-blocks SB11, SB12, and SB13 in a memory block (e.g., BLK1) or erases only the reclaim sub-block.

[0071] In step S150, the sub-block management module 2000 controls to perform a sub-block erase operation within the flash memory 1100. The flash memory 1100 receives a command, address, and control signal for the sub-block erase operation from the memory controller 1200, and performs the sub-block erase operation. When multiple sub-blocks to be erased are specified, the sub-block erase operations are performed simultaneously or sequentially.

[0072] Figure 8 is a diagram illustrating an example of the sub-block reclaim operation and the sub-block erase operation described in Figure 7. Referring to Figure 8, a first memory block BLK1 includes three sub-blocks SB11, SB12, and SB13, and a second memory block BLK2 includes three sub-blocks SB21, SB22, and SB23.

[0073] The first memory block BLK1 is an old block (Old BLK) in which UECC has occurred, and the second memory block BLK2 is a new block (New BLK) to which data is moved through a reclaim operation. UECC occurs in sub-block SB11 of the first memory block BLK1. Some pages of sub-block SB12 are programmed and the remaining pages are in an erased state. That is, sub-block SB12 is a sub-block that is in use (using Sub-BLK). Programming has not yet progressed to sub-block SB13 and all pages are in an erased state. That is, sub-block SB13 is a sub-block that is not used (Not Used Sub-BLK).

[0074] When a UECC occurs in subblock SB11 of the first memory block BLK1, the subblock management module 2000 determines whether the remaining subblocks SB12 and SB13 are reclaim subblocks. The subblock management module 2000 can designate all subblocks SB1, SB2, and SB3 in the first memory block BLK1 as reclaim subblocks.

[0075] Alternatively, the subblock management module 2000 may designate the subblock SB12 that is in use as a reclaim subblock and may not designate the unused subblock SB13 as a reclaim subblock, or the subblock management module 2000 may designate the subblock SB12 that is in use as a reclaim subblock based on a specific criterion.

[0076] Here, the specification criteria may vary. For example, the reclaim subblock may be designated based on the number of error bits of memory cells connected to a particular word line of the subblock SB12 in use. If the number of error bits of the subblock SB12 in use is greater than a threshold value, the subblock SB12 is designated as a reclaim subblock.

[0077] Here, the critical value may be fixed regardless of program-erase cycles, or may be adjusted upward in response to program-erase cycles, or may vary depending on whether the sub-block is in use or not and whether the sub-block is unused or not.

[0078] If the subblock SB12 in use is not designated as a reclaim subblock, the subblock management module 2000 reclaims only the reclaim subblock SB11 to the second memory block BLK2. If the subblock SB12 in use is designated as a reclaim subblock, the subblock management module 2000 reclaims both the reclaim subblocks SB11 and SB12 to the second memory block BLK2.

[0079] After the sub-block reclaim operation is performed, the sub-block management module 2000 performs a sub-block erase operation on the first memory block BLK1. The sub-block management module 2000 determines the sub-blocks to be erased. The sub-block management module 2000 erases all the sub-blocks SB11, SB12, and SB13 in the first memory block BLK1 simultaneously or sequentially.

[0080] Alternatively, the subblock management module 2000 erases the reclaim subblocks. For example, if the subblock SB12 in use is not designated as a reclaim subblock, the subblock management module 2000 erases only the reclaim subblock SB11. If the subblock SB12 in use is designated as a reclaim subblock, the subblock management module 2000 erases the reclaim subblocks SB11 and SB12. The subblock management module 2000 erases the reclaim subblocks SB11 and SB12 simultaneously or sequentially.

[0081] 9 and 10 are a flowchart and a diagram showing an example in which the subblock management module shown in FIG. 6 designates all subblocks as reclaim subblocks. Referring to FIG. 10, a first memory block BLK1 includes three subblocks SB11, SB12, and SB13, and a second memory block BLK2 includes three subblocks SB21, SB22, and SB23.

[0082] The flash memory 1100 reclaims all the sub-blocks in the first memory block BLK1 to the second memory block BLK2 under the control of the sub-block management module 2000. The sub-block management module 2000 also erases all the sub-blocks in the first memory block BLK1 simultaneously or sequentially.

[0083] In step S210, a UECC occurs in one of the sub-blocks in the first memory block BLK1. The sub-block management module 2000 checks the error bits of the sub-blocks of the first memory block BLK1, and determines that the error bits are UECC if they exceed a tolerance. When a UECC occurs in one of the sub-blocks, the sub-block management module 2000 manages a sub-block reclaim operation and / or a sub-block erase operation of the flash memory 1100.

[0084] In step S220, the sub-block management module 2000 designates all sub-blocks in the first memory block BLK1 as reclaim sub-blocks and reclaims them to the second memory block BLK2. If a UECC occurs in sub-block SB11, the sub-block SB12 in use and the unused sub-block SB13 are all reclaimed to the second memory block BLK2. The sub-block SB11 of the first memory block BLK1 is reclaimed to the sub-block SB21 of the second memory block, the sub-block SB12 in use is reclaimed to the sub-block SB22, and the unused sub-block SB13 is reclaimed to the sub-block SB23.

[0085] In step S230, the sub-block management module 2000 performs a sub-block erase operation. The sub-block management module 2000 erases all of the sub-blocks SB11, SB12, and SB13 in the first memory block BLK1 simultaneously or sequentially. The sub-blocks SB11, SB12, and SB13 of the first memory block BLK1 become erased sub-blocks (Erased Sub-BLK).

[0086] 11 and 12 are a flowchart and a diagram showing an example in which the subblock management module shown in Fig. 6 designates an in-use subblock as a reclaim subblock. Referring to Fig. 12, a first memory block BLK1 includes three subblocks SB11, SB12, and SB13, and a second memory block BLK2 includes three subblocks SB21, SB22, and SB23.

[0087] The flash memory 1100 designates a sub-block (using Sub-BLK) in the first memory block BLK1 as a reclaim sub-block under the control of the sub-block management module 2000. In addition, the sub-block management module 2000 erases the reclaim sub-blocks in the first memory block BLK simultaneously or sequentially.

[0088] In step S310, a UECC occurs in a first sub-block in a first memory block BLK1. In FIG. 12, the first sub-block is SB11. The sub-block management module 2000 determines that an UECC has occurred when an error bit in the first sub-block exceeds a tolerable range. The sub-block management module 2000 manages a sub-block reclaim operation and / or a sub-block erase operation of the flash memory 1100 when a UECC has occurred in the first sub-block.

[0089] In step S320, the sub-block management module 2000 checks the next sub-block (next Sub-BLK) in the first memory block BLK1. If a UECC occurs in the first sub-block (e.g., SB11) of the first memory block BLK1, the sub-block management module 2000 checks the second sub-block (e.g., SB12). Here, the second sub-block does not necessarily have to be SB12, but may be SB13.

[0090] In step S330, the sub-block management module 2000 determines whether the second sub-block is in use. If the second sub-block is in use (YES), step S340 is performed, and if not (NO), step S350 is performed. The sub-block management module 2000 determines whether the second sub-block (e.g., SB12) is a sub-block in use (Using Sub-BLK) in various ways. For example, the sub-block management module 2000 determines whether the second sub-block is in use by checking the programmed pages and the erased pages of the second sub-block.

[0091] In step S340, the sub-block management module 2000 designates the second sub-block (e.g., SB12) as a reclaim sub-block if it is a sub-block in use. If the second sub-block is an unused sub-block, the sub-block management module 2000 does not designate it as a reclaim sub-block.

[0092] In step S350, the sub-block management module 2000 determines whether the second sub-block is the last sub-block. If the second sub-block is the last sub-block (YES), the sub-block management module 2000 ends the operation of designating a reclaim sub-block. If the second sub-block is not the last sub-block (NO), the sub-block management module 2000 performs step S320.

[0093] The sub-block management module 2000 checks the third sub-block (e.g., SB13) in step S320. If the third sub-block is an unused sub-block, the sub-block management module 2000 does not designate it as a reclaim sub-block. The sub-block management module 2000 reclaims the sub-block designated as the reclaim sub-block to the second memory block BLK2.

[0094] If a UECC occurs in sub-block SB11, all of the sub-blocks SB12 that are in use are reclaimed to the second memory block BLK2. Sub-block SB11 of the first memory block BLK1 is reclaimed to sub-block SB21 of the second memory block, and the sub-block SB12 that is in use is reclaimed to sub-block SB22.

[0095] The sub-block management module 2000 performs a sub-block erase operation following a sub-block reclaim operation. The sub-block management module 2000 erases designated sub-blocks SB11 and SB12 in the first memory block BLK1 simultaneously or sequentially. The designated sub-blocks SB11 and SB12 in the first memory block BLK1 become erased sub-blocks (Erased Sub-BLK).

[0096] 13 to 16 are flowcharts and diagrams showing an example in which the sub-block management module shown in FIG. 6 designates a reclaim sub-block based on the number of error bits of the sub-block. Referring to FIG. 14 to 16, the first memory block BLK1 includes three sub-blocks SB11, SB12, and SB13, and the second memory block BLK2 includes three sub-blocks SB21, SB22, and SB23.

[0097] The flash memory 1100 designates reclaim sub-blocks in the first memory block BLK1 based on the number of error bits ERRs of the sub-blocks (Sub-BLK) under the control of the sub-block management module 2000. In addition, the sub-block management module 2000 erases the reclaim sub-blocks in the first memory block BLK simultaneously or sequentially.

[0098] In step S410, a UECC occurs in a first sub-block in a first memory block BLK1. The first sub-block is SB11. The sub-block management module 2000 determines that the first sub-block has an UECC when an error bit in the first sub-block exceeds a tolerable range. The sub-block management module 2000 manages a sub-block reclaim operation and / or a sub-block erase operation of the flash memory 1100 when a UECC occurs in the first sub-block.

[0099] In step S420, the sub-block management module 2000 checks the next sub-block (next Sub-BLK) in the first memory block BLK1. If a UECC occurs in the first sub-block (e.g., SB11) of the first memory block BLK1, the sub-block management module 2000 checks the second sub-block (e.g., SB12). Here, the second sub-block does not necessarily have to be SB12, but may be SB13.

[0100] In step S430, the sub-block management module 2000 reads a predefined word line (predefined WL) of the second sub-block. Here, the sub-block management module 2000 pre-designates the word line in various ways. For example, the sub-block management module 2000 pre-designates the word line that is first programmed in the sub-block (e.g., SB12) that is in use. Alternatively, the sub-block management module 2000 pre-designates the word line that is most susceptible to error correction. Alternatively, the sub-block management module 2000 may pre-designate the word line of the second sub-block that is in the same position as the word line of the first sub-block in which the UECC has occurred.

[0101] In step S440, the sub-block management module 2000 determines whether the number of error bits ERRs of a pre-specified word line of the second sub-block is greater than a first threshold value Th1. If the number of error bits ERRs is greater than the first threshold value Th1 (YES), step S450 is performed, and if not (NO), step S460 is performed. The sub-block management module 2000 can know the number of error bits ERRs of the second sub-block (e.g., SB12) in various ways. For example, the sub-block management module 2000 can know the number of error bits by using an ECC circuit (see FIG. 6, 1240).

[0102] The sub-block management module 2000 may set different thresholds depending on whether the second sub-block is a sub-block being used (Using Sub-BLK) or a sub-block not being used (Not Used). If the second sub-block is a sub-block being used, a first threshold value Th1 may be applied, and if the second sub-block is not used, a second threshold value Th2 may be applied. The first threshold value Th1 is greater than the second threshold value Th2.

[0103] In step S450, the sub-block management module 2000 designates a second sub-block (e.g., SB12) as a reclaim sub-block if the number of error bits ERRs of the second sub-block is greater than the first threshold value Th1. The sub-block management module 2000 does not designate the second sub-block as a reclaim sub-block if the number of error bits ERRs of the second sub-block is not greater than the first threshold value Th1.

[0104] 14, the sub-block management module 2000 designates sub-block SB12 as a reclaim sub-block because the number of error bits ERRs of sub-block SB12 is greater than the first threshold value Th1, and FIG 15, the sub-block management module 2000 does not designate sub-block SB12 as a reclaim sub-block because the number of error bits ERRs of sub-block SB12 is equal to or less than the first threshold value Th1.

[0105] In step S460, the sub-block management module 2000 determines whether the second sub-block is the last sub-block. If the second sub-block is the last sub-block (YES), the sub-block management module 2000 ends the operation of designating a reclaim sub-block. If the second sub-block is not the last sub-block (NO), the sub-block management module 2000 performs step S420.

[0106] The sub-block management module 2000 checks the third sub-block (e.g., SB13) in step S420. If the third sub-block is a not used sub-block (Not Used Sub-BLK), the sub-block management module 2000 applies a second threshold value Th2 to designate a reclaim sub-block.

[0107] 16, the sub-block management module 2000 designates sub-block SB13 as a reclaim sub-block because the number of error bits ERRs of sub-block SB13 is greater than a second threshold value Th2. The sub-block management module 2000 reclaims the sub-blocks SB11, SB12, and SB13 designated as reclaim sub-blocks to the second memory block BLK2.

[0108] If a UECC occurs in the sub-block SB11, the sub-block management module 2000 performs a reclaim operation based on the number of error bits in the remaining sub-blocks SB12 and SB13. The sub-block management module 2000 sets different threshold values ​​for the sub-block SB12 that is in use and the sub-block SB13 that is not in use.

[0109] The sub-block management module 2000 performs a sub-block erase operation following a sub-block reclaim operation. The sub-block management module 2000 erases designated sub-blocks in the first memory block BLK1 simultaneously or sequentially. The designated sub-blocks in the first memory block BLK1 become erased sub-blocks (Erased Sub-BLK).

[0110] Figures 17 and 18 are a flowchart and a diagram illustrating an example of a sub-block erase operation of the sub-block management module illustrated in Figure 6. Referring to Figure 18, a first memory block BLK1 includes three sub-blocks SB11, SB12, and SB13. SB11 is a sub-block in which a UECC has occurred, SB12 is a sub-block that is in use, and SB13 is an unused sub-block.

[0111] In step S510, the sub-block management module 2000 determines whether the sub-blocks are to be erased simultaneously. After the sub-block reclaim operation is completed, the sub-block management module 2000 erases the sub-blocks in the first memory block BLK simultaneously or sequentially. If the sub-blocks are to be erased simultaneously (YES), step S515 is performed. If not, step S520 is performed.

[0112] In step S515, the sub-block management module 2000 controls the flash memory 1100 to simultaneously erase all sub-blocks. Here, the erase blocks to be simultaneously erased are all sub-blocks in the first memory block BLK1. Alternatively, the sub-block management module 2000 may simultaneously erase sub-blocks designated as reclaim sub-blocks.

[0113] In step S520, the sub-block management module 2000 erases a first sub-block. Referring to A of Figure 18, the first sub-block is a sub-block SB11 in a first memory block BLK1. The sub-block SB11 is a sub-block in which a UECC has occurred and is therefore erased first.

[0114] In step S530, the sub-block management module 2000 checks the next sub-block (next Sub-BLK) in the first memory block BLK1. After erasing the first sub-block (e.g., SB11) of the first memory block BLK1, the sub-block management module 2000 checks the second sub-block. Here, the second sub-block is designated among all sub-blocks in the first memory block BLK1 or among the reclaim sub-blocks. The second sub-block does not necessarily have to be SB12, but may be SB13.

[0115] In step S540, the sub-block management module 2000 erases the second sub-block. Referring to FIG. 18B, the second sub-block is sub-block SB12 in the first memory block BLK1. Sub-block SB12 is an in-use sub-block and is erased after SB11. If the sub-block management module 2000 performs an erase operation only on the reclaim sub-blocks and sub-block SB12 is not designated as a reclaim sub-block, the sub-block management module 2000 does not erase sub-block SB12.

[0116] In step S550, the sub-block management module 2000 determines whether the second sub-block is the last sub-block. If the second sub-block is the last sub-block (YES), the sub-block management module 2000 ends the sub-block erase operation. If the second sub-block is not the last sub-block (NO), the sub-block management module 2000 performs step S530.

[0117] The sub-block management module 2000 checks a third sub-block (e.g., SB13) in step S530. The sub-block management module 2000 erases the sub-block SB12 of the first memory block BLK1 and then checks the sub-block SB13. The sub-block management module 2000 erases the sub-block SB13. Referring to FIG. 18C, the sub-block SB12 is an unused sub-block and is erased after SB12. If the sub-block management module 2000 performs an erase operation only on the reclaim sub-blocks and the sub-block SB13 is not designated as a reclaim sub-block, the sub-block management module 2000 does not erase the sub-block SB13.

[0118] 19 is a diagram illustrating an example of a flash memory having a multi-stack structure. Referring to FIG 19, the flash memory 3000 has a first stack ST1 and a second stack ST2. The first stack ST1 is located at the bottom, and the second stack ST2 is located at the top.

[0119] A pillar of the flash memory 3000 is formed by the junction of the first and second stacks ST1 and ST2. A plurality of dummy word lines (e.g., Dummy1 WL, Dummy2 WL) are included at the junction of the first and second stacks ST1 and ST2. The first stack ST1 is located between the common source line CSL and the first dummy word line (Dummy1 WL). The second stack ST2 is located between the second dummy word line (Dummy2 WL) and the bit line BL.

[0120] The first stack ST1 includes a ground selection line GSL, a first edge word line (Edge1 WL), and a first stack word line (Stack1 WLs). The second stack ST2 includes a second stack word line (Stack2 WLs) and a second edge word line (Edge2 WL). The memory cells connected to the first and second edge word lines (Edge1 WL, Edge2 WL) store bit data different from the remaining memory cells. For example, the memory cells connected to the first and second edge word lines (Edge1 WL, Edge2 WL) may be SLC or MLC, and the memory cells connected to the remaining word lines may be TLC or QLC.

[0121] When a UECC occurs in the first sub-block SB11 of the first stack ST1, the sub-block management module 2000 determines whether the second sub-block SB12 is a reclaim sub-block. If the second sub-block SB12 is a reclaim sub-block, the sub-block management module 2000 reclaims the first and second sub-blocks SB11 and SB12 to the third sub-block SB21 and the fourth sub-block SB22 of the second stack ST2. After performing the sub-block reclaim operation, the sub-block management module 2000 erases the sub-blocks SB11 and SB12 of the first stack ST1 simultaneously or sequentially.

[0122] The sub-block management module 2000 can transfer data stored in a deteriorated sub-block of the first stack ST1 to a sub-block of the second stack ST2 through a sub-block reclaim operation. The sub-block management module 2000 can reduce a write amplification factor (WAF) and increase a quality of service (QoS) by performing a sub-block reclaim operation in a flash memory having a multi-stack structure.

[0123] 20 is a block diagram showing an example of a storage device implemented as a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 20, an SSD 4000 includes a plurality of flash memories 4101 to 4104 and an SSD controller 4200.

[0124] The first and second flash memories 4101 and 4102 are connected to the SSD controller 4200 through a first channel CH1. The third and fourth flash memories 4103 and 4104 are connected to the SSD controller 4200 through a second channel CH2. The number of channels connected to the SSD controller 4200 may be more than two. And, the number of flash memories connected to one channel may be more than two.

[0125] The SSD controller 4200 includes a host interface 4201, a flash interface 4202, a buffer interface 4203, a control unit 4210, and a working memory 4220. The SSD controller 4200 is connected to the host 1500 through the host interface 4201. The SSD controller 4200 writes data to a corresponding flash memory or reads data from a corresponding flash memory in response to a request from the host 1500.

[0126] The SSD controller 4200 is connected to a plurality of flash memories 4101 to 4104 through a flash interface 4202, and is connected to the buffer memory 1300 through a buffer interface 4203. The flash interface 4202 provides data temporarily stored in the buffer memory 1300 to the flash memories through the respective channels CH1 and CH2. The flash interface 4202 also transfers data read from the flash memories 4101 to 4104 to the buffer memory 1300.

[0127] The control unit 4210 analyzes and processes a signal input from the host 1500. The control unit 4210 controls the host 1500 and the flash memories 4101 to 4104 through a host interface 4201 and a flash interface 4202. The control unit 4210 controls the operation of the flash memories 4101 to 4104 in accordance with firmware for driving the SSD 4000.

[0128] The SSD controller 4200 manages the data stored in the flash memories 4101 to 4104. In the event of a sudden power-off operation, the SSD controller 4200 backs up the data stored in the work memory 4220 and the buffer memory 1300 to the flash memories 4101 to 4104.

[0129] The SSD controller 4200 includes the sub-block management module 2000 described above in the control unit 4210. The sub-block management module 2000 performs a sub-block reclaim operation within each of the flash memories 4101 to 4104 or between different flash memories. The sub-block management module 2000 designates a reclaim sub-block based on the deterioration level of other sub-blocks in the same memory block, and performs a reclaim operation on the other memory blocks.

[0130] The above is a specific embodiment for carrying out the present invention. In addition to the above-described embodiment, the present invention also includes embodiments that can be simply modified or easily modified. The present invention also includes techniques that can be easily modified and carried out using the embodiment. Therefore, the scope of the present invention is not limited to the above-described embodiment, but should be determined by equivalents to the present invention. [Explanation of symbols]

[0131] 1000 Storage Unit 1100 Memory devices (flash memory) 1110 Memory Cell Array 1115 Peripheral circuit 1120 Address Decoder 1130 Page buffer circuit 1140 Input / Output Circuit 1150 Wordline Voltage Generator 1160 Control Logic 1200 Memory Controller 1201 Host Interface 1202 Flash Interface 1210 Control Unit 1220 Working Memory 1230 Flash Translation Layer (FTL) 1240 ECC circuit 2000 Sub-block Management Module

Claims

1. a first memory block having first and second sub-blocks; a second memory block having third and fourth sub-blocks; a storage device comprising: a storage unit for storing data in a first sub-block; a storage unit for storing data in a second sub-block; a storage unit for storing data in a third sub-block;

2. 2. The storage device of claim 1, wherein after reclaiming the first and second sub-blocks into the third and fourth sub-blocks, respectively, the first and second sub-blocks are simultaneously erased.

3. 2. The storage device of claim 1, wherein after reclaiming the first and second sub-blocks into the third and fourth sub-blocks, respectively, the first and second sub-blocks are erased in sequence.

4. if the second subblock is a subblock that is in use, it is designated as a reclaim subblock; 2. The storage device of claim 1, wherein the second sub-block is not designated as a reclaim sub-block if it is an unused sub-block.

5. 2. The storage device of claim 1, wherein the second sub-block is designated as a reclaim sub-block if it is a sub-block that is in use or if it is an unused sub-block.

6. 2. The storage device of claim 1, wherein the second sub-block is determined to be a reclaim sub-block based on a number of error bits in the second sub-block.

7. 7. The storage device of claim 6, further comprising: comparing a number of error bits of a pre-specified word line of the second sub-block with a threshold value; and determining whether the second sub-block is a reclaim sub-block according to a comparison result.

8. 8. The storage device of claim 7, wherein the predesignated word line is an initially programmed word line.

9. 8. The storage device of claim 7, wherein the pre-specified word line is determined based on an error correctable level.

10. 8. The storage device of claim 7, wherein the pre-specified word line is determined according to a location of a word line in which an uncorrectable error UECC occurs in the first sub-block.

11. 8. The storage device of claim 7, wherein the threshold value is changed according to program-erase cycles.

12. 8. The storage device of claim 7, wherein the threshold value varies depending on whether the second sub-block is a sub-block that is in use or an unused sub-block.

13. a first memory block having first to third sub-blocks, the second sub-block being a sub-block in use and the third sub-block being a sub-block not in use; a second memory block having fourth through sixth sub-blocks; a first sub-block having a first uncorrectable error UECC and a second sub-block having a second uncorrectable error UECC, the first sub-block having a second uncorrectable error UECC and a second sub-block having a third ...

14. 14. The storage device of claim 13, wherein after reclaiming the first through third sub-blocks to the fourth through sixth sub-blocks, respectively, the first through third sub-blocks are simultaneously erased.

15. 14. The storage device of claim 13, wherein after reclaiming the first through third sub-blocks to the fourth through sixth sub-blocks, respectively, the first through third sub-blocks are erased in sequence.

16. a memory device including a first memory block having first and second sub-blocks and a second memory block having third and fourth sub-blocks; and a memory controller that controls the flash memory to reclaim the first and second sub-blocks to the third and fourth sub-blocks, respectively, if the second sub-block is a sub-block in use when an uncorrectable error UECC occurs in the first sub-block.

17. 17. The storage device of claim 16, wherein if the second sub-block is an unused sub-block, the first sub-block is reclaimed to the third sub-block.

18. 17. The storage device of claim 16, wherein after reclaiming the first and second sub-blocks into the third and fourth sub-blocks, respectively, the first and second sub-blocks are simultaneously erased.

19. 17. The storage device of claim 16, wherein after reclaiming the first and second sub-blocks into the third and fourth sub-blocks, respectively, the first and second sub-blocks are erased in sequence.

20. 20. The storage device of claim 16, wherein the memory device is a flash memory.

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