Method and system for multi-type probabilistic quantum error mitigation

Abstract

To provide a computer implemented method, for mitigating errors in a quantum circuit comprising at least one occurrence of a quantum logic operation G.SOLUTION: A method including implementation of quasi-probability decomposition on a quantum processor includes a step of computing a set of coefficients {cp}, associated with a set of basis operations B={Bp}, to obtain the following quasi-probability decomposition on the set of basis operations B. The quasi-probability decomposition is of a target version of a quantum logic operation G, denoted G0. The set of basis operations {Bp} forms a multi-type basis, constructed from the quantum logic operation G and elements of a set S of mitigation operations. The decomposition is computed so as to reach a decomposition target, being based on at least one of a decomposition accuracy target, and a decomposition sampling overhead target.SELECTED DRAWING: None

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 524,046, entitled "Methods and Systems for Multi-Type Probabilistic Quantum Error Mitigation," filed June 29, 2023, which is incorporated by reference in its entirety.

[0002] The present disclosure relates to the field of quantum computing, and in particular to the field of quantum error mitigation. [Background technology]

[0003] Quantum computers are expected to dramatically expand the range of computational problems that can be solved efficiently, and have far-reaching applications across a wide range of industrial and academic fields. However, the development of quantum computers that can realize this potential is critically dependent on reducing the errors that are the difference between actual and ideal implementations of quantum logical operations.

[0004] Certain types of errors, namely coherent errors (including probabilistic coherent errors and coherent interactions with the environment below the relevant correlation time), can be significantly reduced through quantum error suppression (QES). A feature of QES is that it does not require significant overhead in the number of qubits, circuit depth, or number of circuit iterations required to obtain a result up to a given statistical error (total number of "shots"). A prototypical example of QES is "dynamic decoupling", where a non-idle quantum circuit implements a better quantum memory than an idle circuit. An additional important example is given by "Pauli Twiring", where a single noisy circuit is replaced by an average over noisy circuits obtained by randomly adding certain Pauli layers. Although several separate circuits must be used, the total number of shots required is similar to that of the original circuit. In both QES examples, all the circuits mentioned are ideally equal, i.e. identical in the absence of errors, and the effect of QES is to average out the rotated coherent errors, thus reducing them. Furthermore, QES may be implemented by accurately characterizing coherent errors and adding small unitary gates to invert these errors.

[0005] Other types of errors, namely dissipative errors (especially due to stochastic coherent errors and coherent interactions with the environment, beyond the relevant correlation times), cannot be eliminated using QES, i.e. without significant resource overhead. A long-term strategy to address such errors is Quantum Error Correction (QEC), where quantum information is encoded into a redundant number of qubits so that errors can be measured and corrected during the computation. However, known QEC schemes require the error rate to first be below a very low threshold, with further excessive overhead of a polynomial in the number of qubits and circuit depth. Furthermore, QEC requires reliable and efficient adaptive "syndrome" measurements, including intermediate circuit measurements, non-trivial real-time classical logic to decode the measurement results, and the ability to apply correction gates conditioned on this logic.

[0006] Recently, a family of methods that complement QEC have been developed for existing quantum processing units (QPUs) that do not yet meet the requirements of QEC. These are known as quantum error mitigation (QEM) methods, and require overhead in the total number of shots, but little or no overhead in the number of qubits and circuit depth. The shot overhead of QEM is known to be exponential in IF × V "total infidelity" in the noisy circuit to be mitigated, where the circuit volume V is the total number of noisy gates and IF is the infidelity per gate. Thus, while QEM is exponential in the circuit volume, the shot overhead is moderate for circuits where V is up to a few times 1 / IF, which grows as the hardware improves and infidelity decreases. Currently, state-of-the-art QPUs achieve 2-qubit gate infidelity IF~10 -3 -10 -2(and an order of magnitude lower single-qubit gate fidelity). Thus, QEM now enables noise-free results for circuits with hundreds to thousands of two-qubit gates, approaching volumes far beyond the reach of classical simulations, a necessary condition for the benefit of quantum algorithms. QEM not only allows for error reduction on current and near-future hardware, but can also be combined with QEC, smoothing the otherwise sharp transition from noisy to error-corrected QPUs as hardware evolves.

[0007] A notable method for QEM is known as "probabilistic error cancellation" (PEC) or "quasi-probabilistic probability method" (QP method). To the applicant's knowledge, it is the only known QEM method that is theoretically guaranteed to produce an unbiased estimator for the outcome of an ideal quantum circuit (assuming the errors are precisely known). The QP method is based on the following expression:

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[0009] Equation 1 shows the available noisy operation B pWe denote the ideal operation G0 that is not available as a quasi-expectation value for G0, and the result of an ideal quantum circuit including G0 is represented by the operation B sampled according to the QP expression 1. p It can be implemented on a given QPU by replacing G with an appropriate average over the results of the noisy quantum circuit obtained by randomly permuting G in . Assuming an error in operation B, the coefficient c i A linear equation for B can be set up. Knowledge of the error in B can be obtained via detailed quantum characterization protocols such as gated-set tomography or cycle benchmarking.

[0010] A fundamental challenge in applying QP methods is the construction of a basis B that is expressive enough to mitigate all significant errors, but is composed of operations that are natively available on the QPU and preferably have short duration and high fidelity. p An additional useful feature when operates on a subset of qubits in an ideal circuit (e.g., single or two qubit operations) is that operation B p can be applied simultaneously to each other and to other gates in the circuit.

[0011] QP bases that are expressive enough to allow the reduction of arbitrary quantum operations on n qubits and contain only a layer of noisy operations G and single-qubit operations have been proposed and have been used in two-qubit experiments. However, a practical difficulty with the proposed bases is that they contain non-unitary operations. In particular, the proposed bases

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[0013] In accordance with the above difficulties, large-scale QEM experiments that utilize QP methods do not utilize non-unitary operations. Instead, these experiments utilize the following mitigation strategy, based on two-qubit Clifford gates, such as the unconditional gate CX. All quantum circuits can be compiled on alternating layers of CX gates and single-qubit gates. Ignoring errors in single-qubit gates for errors in CX gates, which are usually a reasonable approximation, the method focuses on the CX layer. These can be Pauli-twirled, resulting in a simple Pauli error channel before (or equivalently after) the ideal gate, which can be used to derive the basis

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[0015] For the layer of non-Clifford two-qubit gates, it is unclear how to apply QP methods without the drawbacks of non-unitary operations. Although non-Clifford two-qubit gates can be constructed using single-qubit gates and two-qubit Clifford gates, using natively implemented non-Clifford two-qubit gates typically leads to a significant reduction in the non-fidelity IF, which translates into a potential reduction in the shot overhead of the QEM. In fact, the reduction in the above IF is the reason why many quantum hardware manufacturers support native non-Clifford two-qubit gates. Nevertheless, existing QP methods either require the use of non-unitary operations for the mitigation of non-Clifford gates or are based on highly non-optimal composite implementations based on Clifford gates. Summary of the Invention

[0016] As mentioned above, state-of-the-art QP methods generally require expensive operations in terms of execution time, availability, and / or noise. The present disclosure provides a method in which these shortcomings are remedied. The need for non-unitary operations is reduced, and in some embodiments, eliminated. The need for non-optimal compilation of multi-qubit gates is also reduced, and in some embodiments eliminated.

[0017] In this disclosure, "multitype" QP bases are introduced. These can be defined in terms of a restricted set S of "mitigation operations" that one wishes to use to construct QP basis elements and enable optimal mitigation given this restriction. Furthermore, in numerical simulations, it is demonstrated that multitype QP bases enable efficient mitigation of errors in quantum circuits compiled using two-qubit non-Clifford gates, without relying on non-unitary operations or on significantly noisy compilation onto two-qubit Clifford gates. Furthermore, a scalable algorithm for the construction of multitype QP decompositions, i.e., the coefficient c in Eq. pA classical algorithm for is introduced, given a multitype QP basis B based on n qubits, whose running time is polynomial in n.

[0018] A multitype basis B may be defined by a noisy operation G (with target version G0) and a user-specified set S of "reduced operations" that correspond to the set of "simple" quantum operations available on the associated QPU. Given a set S, a multitype basis B may be defined by a set of basis elements B that are subcircuits constructed from elements of G and S. p ∈B, where each "type" corresponds to a particular subcircuit structure. In other words, the different types of the multitype basis B may be defined by particular ways of forming composite operations from G and S. The definition of the types may depend, among other things, on the particular reduction operations used, the way in which the reduction operations are combined with the gate G, the number of reduction operations used, and the ordering of the reduction operations. As an example, consider a multitype basis:

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[0023] The elements of S operate on the same number of qubits as G. The set S may, at least ideally, be closed under multiplication (forming a semigroup) and further under inversion (forming a group). As a simple but already useful example, S may be a set of layers of single-qubit unitary gates; in particular, S may be a group of Pauli layers P. Another useful example is G=G α is an element of a parameterized gate family (the parameter α can be, for example, a rotation angle), and S is an additional element G α’ Includes.

[0024] An operation G may be a single gate, a layer of gates operating in parallel, or a subcircuit containing several such layers, i.e., G=L k ...L1. In the latter case, the base element B i is the set of layers L={L1,...,L k} and a set of reduction operations S. Each type corresponds to a subcircuit structure of the form

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[0026] Given a noisy circuit to be mitigated, there is freedom in decomposing it into subcircuits G on which a QP decomposition is constructed. Taking larger subcircuits (working on a larger subset of qubits or a larger subset of layers) allows for the mitigation of errors that cannot be mitigated with smaller subcircuits. First, larger subcircuits span a potentially larger space of mitigable errors, since they allow more types of basis elements. Second, once the decomposition into subcircuits is fixed, it can be more difficult to mitigate errors involving different subcircuits, i.e. crosstalk or temporal correlation between subcircuits separated in space or time, respectively. On the other hand, multi-type QP decompositions for larger subcircuits are computationally more difficult to construct, and either the depth or width of the subcircuits (but not both) must be limited to allow efficient computation. In particular, constructing a QP decomposition for an entire circuit is computationally more difficult than simulating an ideal circuit, and thus less tractable for useful quantum circuits.

[0027] It is possible to allow different sets S1, S2, ... for different instances of S, in which case

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[0030] A target computation G0 may have several available noisy implementations given by a set G, in which case G and {G} in Equation 1 may be replaced by the set G.

[0031] According to a first aspect of the subject matter of the present disclosure, a computer-implemented method is provided for mitigating errors in a quantum circuit. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor, denoted G. The method includes: p}. The set of coefficients {c p} is B = {B p The computation of a set of coefficients is associated with a set of basis operations (sometimes called subcircuits) denoted by}. The computation of a set of coefficients is performed on the set of basis operations B by a quasi-probability decomposition

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[0033] According to an embodiment of the present disclosure, the implementation of the quasi-probability decomposition isp} based on the set of base operations {B p} to obtain at least one corresponding set of sampled operations. The sampling is performed for each of at least one occurrence of a quantum operation G in the quantum circuit. The implementation of the quasi-probabilistic decomposition further includes executing the set of sampled quantum circuits on a quantum processor. The set of sampled quantum circuits is determined by replacing at least one occurrence in the quantum circuit G with one sampled operation of the corresponding set of sampled operations. The execution of the set of sampled quantum circuits is to obtain a sampled quantum circuit result. The implementation of the quasi-probabilistic decomposition further includes estimating a result of the target quantum circuit based on the sampled quantum circuit result.

[0034] In addition to the features described above, a computer-implemented method for mitigating errors in a quantum circuit according to this aspect of the presently disclosed subject matter may optionally include one or more of the following features (i)-(xli) in any technically possible combination or permutation. i. A set of base operations {B p} contains at least two base operation types. ii. Set of base operations {B p} is a multiple base operation type GS i ,S j G.S. k GS l ,S m At least two base operation types selected from S i ,...,S m is an element of the set S of reduction operations. iii. A permutation of at least one occurrence of G in the quantum circuit is performed by replacing each occurrence of G by a sample from the corresponding set of basis operations. iv. Sampling is weighted

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[0039] According to a second aspect of the subject matter of the present disclosure, there is provided a computer-implemented method for mitigating errors in a quantum circuit. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor, denoted G. The method includes: p}. The set of coefficients {c p} is {B p The step of computing a set of coefficients is associated with a set of basis operations (sometimes called subcircuits) denoted by {B p Quasi-probability decomposition on

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[0041] According to one embodiment of the present disclosure, the usage target of the ideal non-unitary basis operation is minimized by computing a quasi-probability decomposition to obtain a set of basis operations {B p} forms a multitype basis. The multitype basis is constructed from quantum logic operations G and ideal unitary elements S of a set of reduced operations. Furthermore, the usage target of the ideal non-unitary basis operations is minimized by computing a set of complementary coefficients. The set of complementary coefficients is

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[0046] In addition to the features described above, a computer-implemented method for mitigating errors in a quantum circuit according to this aspect of the presently disclosed subject matter may optionally include one or more of the following features (i)-(iv), in any technically possible combination or permutation. i.Set of complementary basis operations i.

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[0058] According to a third aspect of the subject matter of the present disclosure, there is provided a computer-implemented method for mitigating errors in a quantum circuit. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor, denoted G. The method includes: p}. The set of coefficients {c p} is {B p The step of computing a set of coefficients is associated with a set of basis operations (sometimes called subcircuits) denoted by {B p Quasi-probability decomposition on

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[0062] According to a fourth aspect of the subject matter of the present disclosure, there is provided a computer-implemented method for mitigating errors in a quantum circuit. The quantum circuit includes at least one occurrence of a quantum logic operation of a quantum processor, denoted G. The method includes: p}. The set of coefficients {c p} is {B p The step of computing a set of coefficients is associated with a set of basis operations (sometimes called subcircuits) denoted by {B p Quasi-probability decomposition on

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[0076] The methods according to the second, third and fourth aspects may be generalized. Instead of the distinction between (ideal) unitary and non-unitary operations, operations may be distinguished as "easy" and "hard", with "easy" operations being preferred over "hard" operations. That is, for example, it is preferred that the probability of sampling a "hard" operation is minimized. The distinction between "easy" and "hard" operations may be based, for example, on duration, fidelity, availability as native operations, or parallelism of the operations.

[0077] According to a fifth aspect of the subject matter of the present disclosure, there is provided a computer-implemented method for mitigating errors in a quantum circuit. The quantum circuit includes at least one occurrence of a quantum logical operation G in a quantum processor. The method includes implementing a quasi-probabilistic decomposition. The quasi-probabilistic decomposition is implemented using a basis operation including the quantum logical operation G and a basis operation selected from a multitype basis B.

[0078] According to one embodiment, the multitype base B is of type GS i ,Sj G.S. k GS l ,S m Contains at least two types from S i ,...,S m are elements of the set of reduced operations S. Alternatively or in addition to these types, a set of base operations {B p} includes a subcircuit that includes two or more occurrences of a generation G of a quantum logic operation, or that includes two or more reduction operations selected from a set S of reduction operations.

[0079] According to one embodiment, the quantum logic operation G is made up of sub-operations

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[0082] In the method according to any aspect, the quantum operation G is not necessarily an ideal unitary operation, for example, the quantum operation G may be a state-prepared measurement (SPAM) operation.

[0083] In general, the methods according to any of the aspects may be used to mitigate errors in a linear combination of outputs from multiple circuits, or more generally, in a function that may require multiple circuits to be calculated. The different circuits may be decomposed (if preferred, according to different aspects), the decomposition may be implemented on a quantum processor, and the measurements may then be processed to estimate the value of the function.

[0084] According to a sixth aspect of the subject matter of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, the computer instructions being used to cause a computer to perform a method according to the first to fifth aspects of the subject matter of the present disclosure.

[0085] According to a seventh aspect of the subject matter of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a computer, implements the methods according to the first to fifth aspects of the subject matter of the present disclosure.

[0086] According to an eighth aspect of the subject matter of the present disclosure, there is provided a computer system for mitigating errors in a quantum circuit. The computer system includes a classical processor executing computer-executable components stored in a memory and a quantum processor. The quantum processor includes at least one qubit and a measurement device. The quantum processor is configured to receive commands from the classical processor. The computer system is configured to implement a method according to the first to fourth aspects of the subject matter of the present disclosure.

[0087] According to one embodiment, a computer system is configured to read the non-transitory computer readable storage medium disclosed in the sixth aspect of the presently disclosed subject matter and / or to execute the computer program product disclosed in the seventh aspect of the presently disclosed subject matter.

[0088] According to a ninth aspect of the subject matter of the present disclosure, there is provided a computer system comprising a quantum processor and a classical processor. The classical processor is configured to execute computer-executable components stored in a memory, the computer-executable components including a decomposition component and an implementation component. The decomposition component implements a set of basis operations {B p Quasiprobability decomposition of the target version G0 of quantum logical operations on G

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[0090] In this disclosure, the following terms and their derivatives may be understood according to the following explanations: The term "unbiased estimator" may refer to a random variable X, which is meant to approximate or estimate a quantity x such that X reproduces the expected x, E[X]=x.

[0091] The term "ideal" may refer to "free of implementation errors or noise." Thus, the term "ideal unitary" may refer to a quantum operation or gate that can be represented by a unitary matrix in the absence of noise. Similarly, the term "ideal non-unitary" may refer to a quantum operation or gate that cannot be represented by a unitary matrix even in the absence of noise.

[0092] When referring to qubits on which a quantum logical operation may be applied (acted upon), these qubits may include qubits that are (or are expected to be) affected by the operation, but that the operation is not configured (intended) to affect. Such unintended actions may result from implementation errors, particularly crosstalk errors.

[0093] The term "Pauli gate" refers to the Pauli group P nwhere n is the number of qubits on which the gate acts. The Pauli group is defined as a subgroup of the unitary group that contains tensor products of Pauli matrices with possible multiplication by integer powers of the imaginary unit, where

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[0095] The term "Clifford gate" comes from Clifford Group C n where n is the number of qubits the gate acts on. n is a group of unitary matrices that, when acting through a similarity transformation, maps the Pauli group onto itself, where

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[0097] The term "hypergraph" may refer to a generalization of a graph in which edges can connect any number of vertices.

[0098] The notation P·Q denotes a super operator that operates by left and right multiplication, where P and Q are operators.

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[0100] The notation SS' can be used to denote a set of products SS' where S and S' are sets of (super)operators, such as S∈S, S'∈S'. Similarly, the notation SG can be used to denote a set of products SG where G is a (super)operator, such as S∈S. This notation is applicable to more than two operator / set combinations, such as SS'S''. [Brief description of the drawings]

[0101] In order to better understand the subject matter disclosed herein, and to illustrate how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which: [Figure 1] 1 shows a flowchart illustrating a method for mitigating errors according to an embodiment of the present disclosure. [Figure 2A] 1 illustrates a schematic diagram of a set of quantum gates according to an embodiment of the present disclosure; [Figure 2B] 1 illustrates a schematic diagram of a set of quantum gates according to an embodiment of the present disclosure; [Figure 3A] 1 illustrates features of quantum logic operations and basis operations according to embodiments of the present disclosure. [Figure 3B] 1 illustrates features of quantum logic operations and basis operations according to embodiments of the present disclosure. [Figure 3C] 1 illustrates features of quantum logic operations and basis operations according to embodiments of the present disclosure. [Figure 3D] 1 illustrates features of quantum logic operations and basis operations according to embodiments of the present disclosure. [Figure 3E] 1 illustrates features of quantum logic operations and basis operations according to embodiments of the present disclosure. [Figure 4] 13 illustrates generally further features of a method for mitigating errors according to an embodiment of the present disclosure; [Diagram 5] 4 is a flow chart illustrating some steps of a method according to an embodiment of the present disclosure. [Figure 6]10 is a flow chart illustrating a variation of a method for mitigating errors according to an embodiment of the present disclosure. [Figure 7] 4 is a flowchart illustrating several steps of a method for mitigating errors, according to an embodiment of the present disclosure. [Figure 8A] 1 shows graphs demonstrating the performance of methods for mitigating errors according to embodiments of the present disclosure compared to methods for mitigating errors known in the art. [Figure 8B] 1 shows graphs demonstrating the performance of methods for mitigating errors according to embodiments of the present disclosure compared to methods for mitigating errors known in the art. [Figure 9] 1 shows graphs demonstrating the performance of a method for mitigating errors according to an embodiment of the present disclosure. [Figure 10] 1 illustrates a schematic diagram of a computer for implementing a method according to an embodiment of the present disclosure. [Figure 11] 1 illustrates a schematic diagram of a system for implementing a method according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0102] Described herein are some example systems and methods that are useful for mitigating errors in quantum circuits.

[0103] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the subject matter. However, those skilled in the art will appreciate that some examples of the subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter of the present disclosure.

[0104] As used herein, phrases such as "for example," "such as," "for example," and variations thereof describe non-limiting embodiments of the subject matter of the present disclosure.

[0105] References herein to "one example," "several examples," "another example," "other example," "one instance," "several instances," "another instance," "other instance," "one case," "several cases," "other case," "other cases," or variations thereof, mean that a particular described feature, structure, or characteristic is included in at least one example of the subject matter, but appearances of the same term do not necessarily refer to the same example.

[0106] It will be understood that certain features, structures, and / or characteristics disclosed herein that are described in the context of separate examples for clarity may also be provided in combination in a single example. Conversely, various features, structures, and / or characteristics disclosed herein that are described in the context of a single example for brevity may also be provided separately or in any suitable subcombination.

[0107] Unless otherwise indicated, and as will become apparent from the following description, it will be understood that throughout this specification, descriptions utilizing terms such as "calculate," "determine," "execute," "implement," "use," "run," and the like may refer to any combination of software, hardware, and / or firmware actions and / or processes. For example, these terms may refer to programmable machine actions and / or processes that, in some cases, manipulate and / or transform data represented as physical quantities, such as electronic quantities, in registers and / or memories of the programmable machine into other data that is similarly represented as physical quantities in memories, registers, and / or other such information storage, transmission, and / or display elements of the programmable machine.

[0108] mathematical form Quantum operation G0 (G with a noisy version) and B in Eq. p can be written as a superoperator that maps density operators (which describe quantum states) to density operators. In particular, such a superoperator is Hermitian preserving, and therefore 4 n ×4 nwhere n is the number of qubits. These matrices can be written explicitly in the Pauli basis, for example:

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[0112] All errors corresponding to a noisy gate G that need to be mitigated are considered as opposed to, say, the number of qubits that G acts on non-trivially. For example, suppose G is a two-qubit gate acting on qubits q1, q2, and suffers from a crosstalk error coupling q2 to qubit q3. In this case, the noisy gate G acts on n=3 qubits, and a three-qubit QP decomposition may be required to mitigate the latter crosstalk error. Similarly, suppose

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[0114] Sampling overhead and accuracy of QP decomposition Given a desired but unavailable ideal operation G0 and an “ideal” quantum circuit containing the QP decomposition in Equation 1, error mitigation can be achieved by applying the noisy operation B p and the probability w p =|c p Randomly sample with | / W and apply the "QP norm" W=||c||1=Σ to the corresponding circuit results. p |c p | and the sign s p =sgn(c p ) Averaging over N such permutations gives an unbiased estimate for the "ideal" circuit result, but the limit obtained by running a single noisy circuit N times (shots) is

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[0117] Coefficient c p The positive and negative parts,

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[0121] The last equation is the QP norm W, and therefore the sampling overhead is negative W - The terms "sampling overhead" and "negative" refer to the QP norm W or W 2 These terms are often used interchangeably in the literature to refer to closely related quantities such as

[0122] Equation 1 expresses the W (entanglement) infidelity, IF, between a noisy G and an ideal G0. e (G)=IF e It can be shown that for (G,G0)∈[0,1] this implies overhead infidelity.

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[0124] "Entanglement infidelity" is

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[0127] The QP norm W is multiplicative, so this method is the V G When applied to an ideal circuit with an instance, the overall QP norm is

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[0132] The exact implementation of the ideal gate G0 is a very strict requirement, and an approximate QP representation,

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[0135] Equation 3.2 is also applicable when intentionally removing only partially noise or adding noise, as may be relevant when using the QP decomposition with various QEM methods such as zero-noise extrapolation, Clifford or free-fermion data regression, error detection, symmetry-based postselection or multiple voting. When adding noise, the IF e (G QP )>IF e If (G), then the overhead infidelity limit is less than the trivial limit W≧1, meaning that adding noise, as opposed to removing noise, can be performed without sampling overhead. Thus, the methods disclosed herein are directly applicable to any target quantum logical operation and any target quantum circuit (whether noise reduction, noise amplification, noise shaping, etc.), and are not only applicable to the required ideal quantum logical operation. In other words, the methods disclosed herein are applicable to any required quantum logical operation and any required quantum circuit. For convenience and brevity, this disclosure shall refer to examples where the ideal quantum logical operation is the target quantum logical operation, and generalization to any target quantum logical operation is implied.

[0136] The main challenge involved in error mitigation with QP methods is the construction of a QP basis and a corresponding representation that minimizes both inaccuracy and sampling overhead as much as possible, and prioritizes them according to given specifications when minimizing both is not possible. Generally speaking, good accuracy requires that the basis B spans a sufficiently large subspace in the space of required super-operators. To identify the required subspace, a noisy gate is defined as an ideal gate multiplied by the prior error, i.e.,

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[0143] The condition number of the basis B (viewed as a matrix whose columns are the vectorized basis elements) determines the efficiency with which B' spans the space of mitigable errors and controls the sampling overhead according to the QP norm W. Generally speaking, a large condition number means a large W. As an example of a basis B' for the multi-type case, Equation 2 can be rephrased as follows:

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[0146] An example basis for this subspace is given by:

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[0151] Applicants have found that QP methods may be improved in accordance with the subject matter of the present disclosure. In some embodiments disclosed in more detail herein, the improved QP methods may be referred to as "multi-type QP" methods. In some embodiments, as described in more detail herein, the improved QP methods may reduce the use of (ideal) non-unitary and multi-qubit operations. In some embodiments, the improved QP methods may replace the use of non-unitary and multi-qubit operations with a QP basis that includes sub-circuits having multiple types of sub-circuit structures.

[0152] FIG. 1 shows a flow chart illustrating steps of a broad aspect of a computer-implemented method 100 for mitigating errors in a quantum circuit, according to an embodiment of the present disclosure. The quantum circuit may include at least one occurrence of a quantum logic operation G of a quantum processor. The quantum logic operation G may be noisy, i.e., may deviate from the intended ideal operation G0. This deviation may be referred to as a coherent error (e.g.,

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[0156] Note that the base operation types may conform to the expression given in Equation 5. That is, the base operation types may include:

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[0158] The use of multiple basis operation types may advantageously allow for avoiding the use of resource-expensive operations in the decomposition. For example, the use of (ideal) non-unitary operations such as reset operations or intermediate circuit measurements may be advantageously avoided or reduced. The absence of such resource-expensive operations may be compensated for by multiple basis operation types, providing operations that span linearly equivalent or similar subspaces in the space of quantum operations. Furthermore, non-optimal compilation of multi-qubit non-Clifford gates into multi-qubit Clifford gates and single-qubit gates may be avoided.

[0159] Union of a set of quantum operations

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[0161] The decomposition 120 may be calculated to reach a decomposition target 130. The decomposition target may be based on a decomposition accuracy target, a decomposition sampling overhead target, or both targets. In other words, the decomposition accuracy target may include a condition that the decomposition accuracy may remain below (and not exceed) a predefined accuracy threshold ε. Alternatively, or in addition, the decomposition sampling overhead target may include a condition that the decomposition sampling overhead may remain below (and not exceed) a predefined sampling overhead threshold η. In some embodiments, the decomposition sampling overhead target may include a condition that the quasi-probability norm may be below a predefined sampling overhead threshold η, i.e., W≦η.

[0162] The method 100 may include a step 140 of implementing the quasi-probabilistic decomposition on a quantum processor. The step 140 of implementing the quasi-probabilistic decomposition may be for estimating the outcome of an ideal quantum circuit in which an ideal version G0 of a quantum logic operation G replaces at least one occurrence of the quantum logic operation G, and in particular, the step 140 of implementing the quasi-probabilistic decomposition may be for estimating the outcome of a quantum circuit in which G0 replaces G, preferably for each occurrence of G in the quantum circuit. The step 140 of implementing the quasi-probabilistic decomposition may be for estimating the outcome of a quantum circuit in which G0 replaces G, preferably for each occurrence of G in the quantum circuit. p}(121)。 Quantum logic operations may be performed on a quantum processor included in the quantum

[0163] In some embodiments, the step of implementing 140 the quasi-probabilistic decomposition includes a set of basis operations {B p}(121). p The step of sampling {c}(121) may include computing a set (i.e., list) of operations, which may be selected from a set of base operations. This set (list) of operations may include several occurrences of the same base operation. Sampling may involve computing a set of coefficients {c pIn some embodiments, the sampling may be based on a probability distribution defined by probabilities or weights.

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[0165] In some embodiments, the method 100 may include calculating a statistical error of the estimated ideal computation result.

[0166] In some embodiments, the method 100 may include a step of characterizing the errors (not shown). The step of characterizing the errors may include obtaining a characterization of the errors in the quantum logic operation G to find an error model of the quantum logic operation G. In other words, the quantum logic operation G may be characterized to find how it deviates from an ideal version G0. The characterizing step may include obtaining a characterization of the errors in the quantum logic operation G to find an error model of the quantum logic operation G. p}, we use the basis operations {B p}. p The characterization of (at least one of)} may include obtaining a characterization of the error in at least one mitigation operation in the set S. Given a quantum logic operation G, a set of basis operations {B p Characterization of errors in} or the mitigation operation S may be required if these error models are not known with sufficient detail or accuracy, e.g., if the quantum processor has not yet been (fully) characterized, or if the noise in the processor is suspected to have changed since the last characterization, e.g., due to naturally occurring fluctuations or drift, or technological changes such as recalibration. The characterization step may utilize characterization protocols such as, for example, randomized benchmarking, cycle benchmarking, process tomography, state tomography, measurement tomography, or gate set tomography. In some embodiments, the characterization may include training the coefficients of the QP decomposition. That is, a model of the noise may be found using an iterative process of refinement of candidate models. The iterative process may use techniques such as machine learning tools and may use known result noise sensitive circuits. The known result noise sensitive circuits may be referred to as training circuits or characterization circuits.

[0167] Method 100 is the ideal version

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[0175] 2A illustrates further characteristics of the set of reduction operations S210 in some embodiments of the present disclosure. In some embodiments, the set of reduction operations S210 may exclude intermediate circuit measurements 215. In some embodiments, the set of reduction operations S210 may exclude adaptation operations 217. The adaptation operations 217 are quantum gates controlled by classical logic that are applied to the results of the intermediate circuit measurements. For example, the reset operation may be a classically controlled X π may be implemented by a gate, and after an intermediate circuit measurement of that qubit in the computational base, the result of the measurement

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[0177] 2B illustrates further characteristics of the mitigation operation S and the sets S1,...,S5 in some embodiments of the present disclosure. In some embodiments, at least one of the sets S1,...,S5 is about 10 nqubits on which G acts, including qubits on which G is ideally meant to act non-trivially, and additional qubits on which G is known or assumed to act unintentionally due to noise (i.e., crosstalk). Preferably, n is (approximately) 10 n Or more elements may be linearly independent. Preferably, each set S1,...,S5 has about 10 n or more elements. As noted above, in some embodiments, ideal non-unitary and multi-qubit operations may be excluded from the sets S1,...,S5. Thus, when G applies to a single qubit, the operations included in each of the sets S1,...,S5 may span up to a 10-dimensional vector space, instead of the full 16-dimensional space of single-qubit quantum operations. For more than two qubits, the dimension is 16. n Instead of 10 n In some embodiments, at least one of the sets S1,...,S5 may have linearly dependent elements, i.e., span a vector space with a dimension smaller than the number of elements 245. Note that linear dependency is defined in terms of super-operators, as discussed above. Having linearly dependent sets S1,...,S5 allows for the same reduction operation

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[0181] 3A-3E illustrate a quantum logic operation G and a set of basis operations {B p 3A, in some embodiments, quantum logic operation G305 may be a layer of gates that operate on non-overlapping sets of qubits (i.e., quantum gates that can be compiled to operate in parallel), such as two-qubit gates

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[0186] 3B, in some embodiments, an idealized version of a quantum logic operation G0310 may be a gate 315 that is non-Clifford, i.e., the unitary operator representing the gate may not be included in the Clifford group 316. As indicated above, the Clifford group C nis the group of unitary matrices that, when acting through a similarity transformation, maps a Pauli group onto itself. A Pauli group P on n qubits is the tensor product of four single-qubit Pauli matrices (including identities), 4 n "Paulist Ring" P s The elements of a Pauli group are Pauli rings with phases ±i or up to ±1.

[0187] Referring to FIG. 3C, in some embodiments, a set of basis operations {B p} is a subcircuit B constructed from an arbitrary number of reduction operations S selected from a set of an arbitrary number of generation and reduction operations of a quantum logic operation G. p , i.e., types or sub-circuit structures having two or more occurrences of a quantum logic operation G or having two or more reduction operations that are not of the types described above (i.e., not of the type shown in FIG. 1). For example, the basis operation 352 may consist of two successive applications of a quantum logic operation G preceded by an operation from set S. The basis operation 354 may consist of two successive applications of an operation from set S followed by an application of a quantum logic operation G from set S, and in yet another example, the basis operation (not shown) may consist of two successive applications of a reduction operation included in set S. In some embodiments, the sub-circuit B pSubcircuits may be size-limited by requiring that certain metrics of the subcircuit, such as the depth or volume of the subcircuit, be below a certain threshold. Subcircuit depth may be defined as the number of layers in the subcircuit, and subcircuit volume may be defined as the total number of gates in the subcircuit. For example, assuming that each operation in the figure corresponds to a single layer, subcircuit 352 has a depth of 3 and subcircuit 354 has a depth of 4. Certain characteristics of the layers or gates may be incorporated into these metrics, for example, only multi-qubit gates or layers of multi-qubit gates may be counted. For example, if the reduction operations in S are layers of single-qubit gates that are ignored in the definition of depth, and G contains one multi-qubit operation, then subcircuit 354 has a depth of 2 and subcircuit 352 has a depth of 1.

[0188] Referring to FIG. 3D, in some embodiments, a quantum logic operation G360 may be a sub-circuit provided by a sequence of sub-operations, namely:

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[0196] Note that the quantum logical operation G360 may, in some embodiments, consist of a single sub-operation (e.g., an operation natively available for the QPU). If the quantum logical operation G360 includes any two sub-operations ξ1, ξ2 that can be operated in parallel, then the combined operation

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[0199] Twiring and restricted Pauli twirling Assuming that both the reduction operations in operations G and S are (ideally) unitary, the multitype basis constructed from G and S is the error generator L b (see Equation 5). More generally, the chosen basis B may not be able to (efficiently) span the space of all n-qubit superoperators, resulting in certain types of errors that cannot be (efficiently) mitigated. In this scenario, it is useful to restrict the noise channels to be mitigated, which is typically done by "twiring" noisy gates. In some embodiments, the quantum logic operation G320 may be twirl. Mathematically speaking, twirl may be considered as "averaging over group actions", which is further detailed below.

[0200] Superoperator representation of the subgroup G ⊆ U(n)

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[0207] When twirling with the Pauli group, i.e., G=P n In the case of , the twilling operation tw p (A) is the Pauli channel, i.e., the diagonal superoperator. The Pauli basis is

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[0228] Here, the generator Q∈P s n-qubit Pauli rotation gate G0=R Q Considering (α), the operator e iαQ / 2 For α that is not a multiple of π / 2, the ideal gate G0 is non-Clifford,

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[0240] Therefore, gate R ZZ (α) Twiring commutator P ZZWhen twirling with, an X-shaped forward error occurs.

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[0243] Generalizing the above example, consider any (ideal unitary) two-qubit gate G, which is generally non-Clifford. In the absence of noise, the gate can be described in terms of its "KAK decomposition",

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[0252] General P Q The twirl- ed super-operator takes the 4x4 block diagonal form.

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[0256] In particular, the above example of twirling a noisy gate G can of course be incorporated into a QP method, essentially "free" with respect to sampling overhead. More generally, this applies to any twirling of G, which can be broadly defined as replacing a single noisy operation G with a probability distribution (see expectation).

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[0262] As explained above, an implementation of twiring is shown in FIG. 3E. A set of gates {g j} may be combined with quantum logic operations G 320 to form a set of intermediate operations 325. In some embodiments, the set of gates {g j} can be commutative 335 with the quantum logic operation G 320. The intermediate operation 325 is a set {g j} and followed by the inverse (Hermitian conjugate) of the gate preceding the quantum logic operation G320. In other words, the set of intermediate operations 325 may be represented by a set of similarity transformations of the quantum logic operation G320, and the transformation matrices may form a subgroup of the unitary group. j is the twiring operation G tw Each base operation Bp In the quantum logic operation G320, the corresponding QP coefficients {c p a j}350 with base operation {B p,j Probability of forming a modified set of j Intermediate operations with

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[0264] From a different perspective, the set of intermediate operations 325 is a set of base operations {B p}, twiring can be combined (by recompilation) with a set of "raw" base operations. In this view, twiring is a set of base operations {B p} can be seen as part of a method for constructing

[0265] Calculating multitype QP decompositions Figure 4 shows the selected multitype basis {B p}, the decomposition coefficients {c p4 illustrates a feature of the computation of {}. In tracking 410 the decomposition target, the computation may include a constraint that the sum of the coefficients may be equal to 1, whereby the decomposition may be trace-preserving 420. The computation may include computing 430 a quasi-probability norm. Computing 430 the quasi-probability norm may be for computing a decomposition sampling overhead. Computing the decomposition sampling overhead may be for satisfying a decomposition sampling overhead target. The computation may include optimizing 440 a tradeoff between accuracy and quasi-probability norm, i.e., a cost function that may depend on the quasi-probability norm and accuracy may be minimized. In some embodiments, the step of optimizing the tradeoff may include optimizing the decomposition accuracy by solving a least squares problem. In some embodiments, the step of optimizing the tradeoff may include minimizing the sampling overhead by solving a linear program. The computation may include computing a distance measure 450 between the decomposition and an ideal version of the quantum logic operation G0. Exemplary distance measures that may be used to define the accuracy of the decomposition are the infidelity 460, the Frobenius distance 470, the diamond distance 480, or the l p These include, but are not limited to, operator norm 490 .

[0266] FIG. 5 illustrates the decomposition coefficients {c p 5 shows a flowchart detailing an algorithm 500 that can be used to compute . The input 505 to the algorithm is a pre-error generator

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[0270] In the following, we consider a fixed multitype base {B p}Noisy operations

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[0275] The above least-squares problem is solved by solving the problem that the vector space of superoperators on n qubits is 16 n dimensional, it can be solved directly only for a small number of qubits. poly(n) complexity, extended L b This may be performed in several selected orders to obtain the following least squares problem with L b Assuming locality of , the resulting superoperator is an element of a subspace with poly(n) dimension.

[0276] As an example, a first order expansion may be considered,

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[0290] To show the complexity poly(n) of the least-squares problem in equation 11, the error generator L b may be assumed to be r-local, that is, it may be assumed to be a sum of k < r qubit terms, and each term acts on the tensor product with the identity on a subset of n - k qubits. The set of qubits on which the k-qubit superoperator A acts non-trivially may be called the support of A and may be denoted by supp(A). The set of r-local superoperators is poly(n)-dimensional

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[0295] r-localL b The assumption is true, the expansion is a linear equation (equation 11), and the basis

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[0304] The algorithm 500 can include a step 530 of generating data for the least-squares problem. The Choi basis (obtained in step 520 of constructing a set of basis vectors) is orthonormal in the Hilbert-Schmidt inner product. Thus, Equation 11 can be rewritten as:

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[0310] If r-local is not assumed, or

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[0314] The algorithm 500 may include a step of computing a singular value decomposition (SVD) of the matrix M 535. The algorithm 500 may include a step 540 of solving the least squares problem Equation 12,

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[0318] A matrix M may have a non-trivial kernel ker(M), i.e., one or more singular values ​​equal to 0 or numerically less than a threshold ε. If M may have a non-trivial kernel, then

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[0326] The algorithm 500 calculates the l2-optimal solution (found in the step of calculating the least squares 540).

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[0330] The result of decision 550 is

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[0333] The results of test 550 were:

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[0337] The algorithm 500 may include a step 560 of projecting,

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[0340] The algorithm 500 may include a step 570 of solving a linear program.

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[0355] The above linear program is transformed

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[0361] Solution to Linear Programs

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[0364] In some embodiments, algorithm 500 may include sanity checks (not shown), i.e., checks that the results of intermediate and / or final calculations may be considered reasonably correct by verifying that some general properties that should theoretically hold may in fact hold. For example, sanity checks may be required due to numerical stability limitations of subroutines that may be incorporated into algorithm 500. Sanity checks may also help to verify that algorithm 500 has been implemented correctly. Sanity checks may include verifying the following properties:

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[0366] In some embodiments, algorithm 500 may include a step 590 of calculating a performance metric. The performance metric may estimate how much the performance of the decomposition calculated by algorithm 500 may improve over an existing QP decomposition or over the performance of the quantum logic operation G, if the decomposition may be implemented on a quantum processor.

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[0372] In some embodiments, the algorithm 500 may iterate according to the results 595 of the step 590 of calculating the performance metric. An iteration of the algorithm 500 may be required if the performance metric may not be satisfied, for example if the QP norm may not satisfy a decomposition sampling overhead target or if the distance measure may not satisfy a decomposition accuracy target. In some embodiments, the algorithm 500 may iterate if any of the sanity checks fail.

[0373] To further reduce classical computational resources, a divide-and-conquer modification of the above primary algorithm can be used. b is assumed to be r-local, so the sum

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[0381] Since the sum of the Frobenius distances achieved by the solutions to the r' qubit problem on the right bounds the Frobenius distance of the solution to the complete first-order problem on the left, we use the above algorithm to solve r' and obtain the resulting n-qubit QP decomposition.

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[0386] where

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[0390] In some embodiments of the present disclosure, for example, with respect to a parameterization of the error in G, the QP factor c p It is possible to obtain a simple formula for θ = θ θ θ (θ = θ θ ) and solve some of the optimization problems mentioned above analytically (i.e., symbolically rather than numerically). In such cases, the computation of the QP decomposition by the above algorithm can be reduced to plugging the error parameters into the simple formula.

[0391] 2-step multi-type relief 6 shows a flow chart illustrating steps of a broad aspect of a modified computer-implemented method 600 for mitigating errors in a quantum circuit, according to an embodiment of the present disclosure. The quantum circuit may include at least one occurrence of a quantum logic operation G of a quantum processor. The quantum logic operation G may be noisy, i.e., subject to implementation errors, including coherent errors and dissipative errors. The method 600 includes: p} may be calculated. p} is the set of base operations {B p}, i.e., the coefficient c p The corresponding base operation B for each p The step of calculating 610 may include a set of basis operations {B p}. That is, if the quantum logical operation G is a set of basis operations {B p}612, the decomposition

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[0393] The method 600 may include a step 620 of implementing the quasi-probabilistic decomposition on a quantum processor. The step 620 of implementing the quasi-probabilistic decomposition may be for estimating the outcome of an ideal quantum circuit in which an ideal version G0 of a quantum logic operation G replaces at least one occurrence of the quantum logic operation G. In other words, the step 620 of implementing the quasi-probabilistic decomposition may be for estimating the outcome of a quantum circuit in which G0 replaces G. The step 620 of implementing the quasi-probabilistic decomposition may include estimating the outcome of a quantum circuit in which G0 replaces G. p} on a quantum processor.

[0394] The decomposition target 614 may include a step 615 of optimizing the decomposition, i.e., minimizing a cost function that may depend on any of the following: sampling overhead, precision, a usage metric of ideal non-unitary basis operations, and a usage metric of ideal unitary basis operations. In some embodiments, the optimizing step 615 may include minimizing the usage of ideal non-unitary basis operations, for example, minimizing the number of ideal non-unitary basis operations included in the decomposition 611, or minimizing the relative weight of one or more basis operations included in the decomposition 611 that are ideal non-unitary. The relative weight of one or more basis operations included in the decomposition 611 may be defined as the sum of the absolute values ​​of the coefficients corresponding to these basis operations divided by a quasi-probability norm.

[0395] The step of minimizing the use of ideal non-unitary basis operations may include computing a quasi-probabilistic decomposition 612, where the set of basis operations {B p} may include a quantum logic operation G and a basis operation selected from at least two basis operation types. The basis operation types may include the following types: i ,S j G.S. k GS l ,S m}That is, the base operation types may include the following types: 1.GS i A quantum operation, where a quantum logical operation G may be preceded by a quantum operation included in a set S1 of quantum operations. 2.S j G-quantum operation, where the quantum logical operation G may be succeeded by a quantum operation included in the set S2 of quantum operations. 3.S k GS l - quantum operations, where the quantum logical operation G may be preceded or succeeded by quantum operations contained in the sets of quantum operations S3 and S4, respectively. 4.S ma quantum operation, which is included in the set of quantum operations S5, and the quantum logic operation G may not be present.

[0396] Union of a set of quantum operations

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[0398] The step of minimizing the use of ideal non-unitary basis arithmetic is the residual error

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[0410] In some embodiments, the step 620 of implementing the quasi-probability decomposition includes a set of basis operations {B p}, i.e., compiling a set (i.e., list) of operations, which may include a set of base operations {B p}. This set (list) of operations may include several occurrences of the same base operation. Sampling 622 selects a set of coefficients {c p In some embodiments, the sampling 622 may be based on a probability distribution defined by probabilities or weights.

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[0421] Implementing 620 the quasi-probabilistic decomposition may further include executing 626 a set of sampled quantum circuits on a quantum processor. The set of sampled quantum circuits may be determined by replacing 624 at least one occurrence of a quantum logic operation G in the quantum circuit with one sampled operation from a corresponding set of sampled operations. Executing 626 the sampled quantum circuit may be to obtain a sampled quantum circuit result. Implementing 620 the quasi-probabilistic decomposition may further include estimating 628 a result of an ideal quantum circuit based on the sampled quantum circuit result. In some embodiments, replacing 624 at least one occurrence of a quantum logic operation G in the quantum circuit may be performed by replacing each occurrence of the quantum logic operation G by a sample from a corresponding set of basis operations.

[0422] In some embodiments, the method 600 may include calculating a statistical error of the estimated ideal computation result.

[0423] In some embodiments, the method 600 may include a characterizing step (not shown). The characterizing step may include obtaining a characterization of errors in the quantum logic operation G in order to find an error model of the quantum logic operation G. In other words, the quantum logic operation G may be characterized in order to find how it deviates from an ideal version G0. The characterizing step may include obtaining a characterization of errors in the quantum logic operation G in order to find an error model of the quantum logic operation G. In other words, the quantum logic operation G may be characterized in order to find how it deviates from an ideal version G0. p}, we use a set of basis operations {B p}. The characterizing step may include obtaining a characterization of the error in at least one operation in the set S of reduced operations.

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[0427] Method 600 is a corresponding ideal version {G0 [β] Multiple quantum logic operations with

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[0439] In some embodiments, a set of basis operations {B p} is subcircuit B p Subcircuit B may further include p may include two or more occurrences of the quantum logic operation G, or may include two or more reduction operations selected from the set of reduction operations S. In some embodiments, the set of complementary basis operations

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[0444] Further features that some embodiments of the method 600 may assume may be found above in the discussion of Figures 2A-5. It should be noted that the set of basis operations {B p The characteristics that} can assume are that, except for excluding any (in all sense) ideal non-unitary operations, the set of complementary basis operations

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[0447] Method 600 can be generalized. Instead of distinguishing between unitary and non-unitary operations, one may distinguish between "easy" and "hard" operations. "Easy" operations are preferred over "hard" operations. That is, for example, it is preferred that the probability of sampling a "hard" operation is minimized. This generalization is well understood on the basis that on one QPU, some operations may have negligible noise (or are generally not resource intensive), while the same operations on a different QPU may be very noisy (or even natively unavailable).

[0448] 7 shows a flowchart illustrating a computer-implemented method 700 for mitigating errors in a quantum circuit, according to an embodiment of the present disclosure. A quantum circuit Cir 705 may include at least one occurrence of a quantum logic operation G of a quantum processor, which may be noisy. The goal may be to mitigate errors in the quantum circuit 705 resulting from G.

[0449] The method 700 may include a step 710 of characterizing the error. The step 710 of characterizing the error may include characterizing an error in a quantum logic operation G, the set of basis operations {B p}.

[0450] The method 700 may include a step 720 of computing coefficients. The step 720 of computing coefficients may receive as input the quantum circuit 705 and the characterization of the error obtained in the step 710 of characterizing the error. The step 720 of computing coefficients may include a step 720 of computing coefficients. p}. p} is the set of base operations {B p}. The set of coefficients {c p} is a quasi-probability decomposition

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[0452] The set of coefficients {cp} may be used to calculate a probability measure 730. The probability measure is determined by the weights

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[0454] The method 700 comprises: Q}. The probability measurement 730 may include a step of generating 740 a set of sampled quantum circuits {Cir Q}. The set of sampled quantum circuits {Cir Q} may be determined by replacing at least one occurrence in the quantum circuit G with one sampled operation of the corresponding set of sampled operations. The generation of the set of sampled circuits may be done in a typical manner, e.g., by storing a list of lists of indexes, each index pointing to a sample and each list corresponding to a sampled circuit. For each sampled quantum circuit in the set of sampled quantum circuits, a corresponding sampled circuit code

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[0462] The method 700 comprises: Q}. Q} may be performed 750 to obtain a sampled quantum circuit result. Q For Q may be performed, the state of the qubit may be measured, and the measurement result o Q may be registered.

[0463] The first test 760 is to test the sampled circuit Cir Q The number of repetitions required to perform a "shot" N s If the result of the first test 760 is negative, then the Cir Qmay be executed again (sampled circuit {Cir Q} 750). If the result of the first test 760 is positive, a second test 770 may be performed. The second test 770 may test whether all sampled circuits have been executed. If the result of the second test is negative, the next sampled circuit may be executed again (sampled circuit {Cir Q}).

[0464] If the result of the second test 770 is positive, the method continues by sampling the results of the sampled quantum circuit. Q , may proceed to step 780 of estimating the outcome o of the ideal quantum circuit based on . The step 780 of estimating the outcome o of the ideal quantum circuit based on the outcome o Q Average the results. Q is the corresponding sign

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[0467] The method may proceed to step 790 of calculating the statistical error of the estimate obtained in step 780 of estimating the outcome o of the ideal quantum circuit. Step 790 of estimating the statistical error may include visually presenting the error, for example as an error bar.

[0468] Numerical simulation To demonstrate the advantages of the method according to the present disclosure over known techniques, applicants have simulated several methods for mitigating errors on a classical computer, including methods according to embodiments of the present disclosure and methods known in the art. In all methods, the gates being mitigated are non-Clifford gates, and the permitted mitigation operations are ideal and unitary.

[0469] 8A-8B show graphs demonstrating the performance of methods implemented for mitigating errors according to embodiments of the present disclosure compared to methods implemented for mitigating errors known in the art.

[0470] The simulated noisy quantum logic operation is a two-qubit ZZ rotation gate Gα=R with rotation angle α∈(0,π / 2). ZZ (α) family. These are non-Clifford gates for α that is not a multiple of π / 2. We did not simulate the gates for angles α=0, π / 2, as they are Clifford gates. As explained above, Clifford gates can be optimally reduced using "Clifford reduction", which allows us to reduce the gates to twirling in the full Pauli group P, and to the ideal unitary monotype basis.

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[0472] Non-Clifford R ZZ The (α) gate is interesting because it appears commonly in quantum algorithms and because it can be implemented as a native gate on various types of QPUs. ZZ The (α) gate has been implemented natively in tunable frequency-coupled transmon qubits, as well as trapped ion qubits. Up to single qubit basis change, R ZZThe (α) gate also functions as a cross-resonant gate R at fixed frequency and coupled transmonk bits. ZX (α) in the trapped ion qubit

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[0474] In all simulated methods, the basis operation B in all bases B considered i is the gate G to be mitigated. α , and a set of ideally unitary reduction operations S. These reduction operations are constructed from 16 2-qubit Pauli layers

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[0476] The method according to an embodiment of the present disclosure implemented is as follows. a) Two non-trivial types G α S and SG α Multitype bases, including

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[0485] In the above methods according to the present disclosure that were simulated, the QP decomposition of the multitype basis was calculated according to the first-order algorithm described above (in the section "Computation of the Multitype QP Decomposition"). To allow for a simple comparison with methods known in the art, the same algorithm was applied to the single-type basis in the following methods (d) and (e).

[0486] The art known method that was carried out is as follows. d) A single non-trivial type

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[0491] The mitigation method "composite mitigation" is briefly as follows. Non-Clifford Family G α A known approach to reducing errors in α That is, to compile G α as a subcircuit containing a two-qubit Clifford gate and a single-qubit gate. The "Clifford mitigation" described above is then applied to each of the two-qubit Clifford gates, while ignoring the generally negligible error in the single-qubit gates. As an example, a combined implementation is as follows:

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[0497] G α The simulated noise model for

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[0502] Generalization to any single-qubit dissipative process occurring during a gate operation does not qualitatively change the results presented below.

[0503] Noisy G α Gate: Group P ZZ , i.e., the group of Pauli layers commutable with ZZ (see above for twiling).

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[0505] As discussed above, FIGS. 8A-8B show graphs demonstrating the performance of methods implemented for error mitigation according to embodiments of the present disclosure compared to methods implemented for error mitigation known in the art.

[0506] The difference between FIG. 8A and FIG. 8B is simply the marking of different data sets in the graph. In FIG. 8A, different data sets are marked by different line styles (e.g., solid / dashed lines, gray / black). In FIG. 8B, different data sets are marked by different markers (e.g., square / triangle / circle, solid / hollow). For clarity, two types of data set markings are shown. Due to this similarity, when both figures can be referenced, the shorthand representation FIG. 8 may refer to either figure.

[0507] Four panels are shown in Fig. 8. In panels (a) and (c) (top and bottom left), ε is ε = 5 × 10 -3 and α is in the range α∈(0,π / 2). In panels (b) and (d) (top right and bottom right), α is fixed at α=π / 4 and ε is in the range ε∈(10 -4 ,10 -1 ) range.

[0508] The markings of the datasets corresponding to the enumeration of the simulated methods used above are as follows: a) Black uneven dashed line / black circle. b) Black even number of dashed / downward solid triangles. c) Solid black line / upward pointing black triangle. d) Grey uneven dashed line / hollow circle. e) Grey even-dashed line / open square. f) Upward-pointing solid grey line / open triangle.

[0509] Please note that methods according to embodiments of the present disclosure are indicated by black / solid symbols, and methods known in the art are indicated by grey / hollow symbols.

[0510] A legend for the dataset is provided in panel (a) of Figure 8. The top-to-bottom order of the legend corresponds to the enumeration of the simulated methods used above (e.g., the top item corresponds to method (a), the bottom item corresponds to method (f)). The legend further describes the reduction operation (G α(Except for

[0511] As a first performance metric for the QP decomposition, the QP norm W is used as a measure for the sampling overhead. It is shown in panels (a) and (b). More specifically, the “blow-up speed” (W-1) / IF is considered. The “blow-up speed” is the ratio of the QP-norm W of a volume V circuit to the “total infidelity” IF×V. V We quantify the exponential dependence of the blow-up rate on the y-axis. As mentioned above, the blow-up rate has an optimal value of 2, which sets the lower limit of the y-axis in panels (a) and (b). Note that in both panels (a) and (b), the overlapping lines are slightly separated vertically for better visibility. Panel (b) shows that, as expected, the blow-up rate

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[0513] As a second performance metric, we use the relative residual Frobenius distance.

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[0515] To demonstrate the advantages of multi-type mitigation, several single-type mitigation strategies are considered (methods (d)-(f)). The first single-type mitigation considered is combined mitigation (method (f) above). This method can be easily applied non-linearly and therefore gives vanishing imprecision (which is why there is no corresponding data set in panels (c) and (d)). Moreover, this method

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[0520] As will be explained below, multi-type mitigation allows full first-order mitigation of the noise models considered while achieving optimal blow-up rates.

[0521] We now describe in detail the implementation of the multi-type QP decomposition as shown in Figure 8. The simplest multi-type QP basis considered is

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[0523] α→π / 2, B a The excess QP norm obtained for is due to the angle α appearing in both types of basis elements involved. This results in a QP basis that has a high condition number (when viewed as a matrix), essentially spanning the space of mitigable errors inefficiently. Indeed, for α=π / 2, the gate G α =G π / 2 is (ideally) a Clifford gate, mapping the Pauli group onto itself via conjugation. As a result, G π / 2P=PG π / 2, and for α = π / 2, the multitype basis B a effectively reduces to a single-type basis. The solution to this problem is to use an additional two-qubit gate G α’ As an example, the basis using α'=π / 2-α

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[0525] Multitype Bases

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[0529] In summary, in contrast to single-type mitigation strategies known in the art, multi-type mitigation according to embodiments of the present disclosure enables optimal first-order mitigation of rotation gates with non-Clifford ZZ single-qubit dissipation occurring during the gate operation, without relying on non-unitary mitigation operations.

[0530] The results presented so far qualitatively indicate that

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[0533] FIG. 9 is a block diagram of a G α We present a graph demonstrating the performance of our method for mitigating errors, applied to multiple gates from the β,γ family. α 1000 gates from the ,β, and γ families were simulated on a classical computer.

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[0537] Two panels are shown in Figure 9. In both panels, the x-axis labeled "Index" represents the specific combination of parameters, i.e.

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[0539] Panel (a) shows that the QP decomposition has a blow-up speed very close to the optimal value of 2. The slight non-optimality is due to numerical inaccuracies in the linear programming involved in the computational algorithm. Panel (b) shows that the multitype decomposition also achieves better accuracy than the first-order decomposition.

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[0541] The advantage of the method according to the present disclosure is that it is possible to α =R ZZ It can be further seen by considering again the (α) family, that the error generator L b The noise model is completely general before , i.e., the assumption of single qubit dissipation in the gate is not assumed. To mitigate such a general noise model, a larger twiring group and a larger set of mitigation operations can be used compared to the simulations described above. In order to reduce the noise model as much as possible,

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[0547] The combination γ1 and γ2 is the commutator P ZZ γ3 includes the Pauli operators not included in P ZZ Nevertheless, all combinations of the three parameters are ZZIt corresponds to a superoperator that commutes with (α) and can therefore be thought of as acting before, between, or after the ideal gates.

[0548] All three combinations in Equation 14 correspond to two-qubit dissipation. γ3 can be generated by twiring of coherent errors, but γ1 and γ2 cannot. If we assume that γ3 is due only to twiring coherent errors, then γ_3 is given (for the leading order) by γ3=h XX h YY -h XY h YX

[0549] The sum of γ1 + γ2 determines the non-unitary error in the ZZ direction,

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[0551] Furthermore, as demonstrated by the above numerical simulations, R ZZ By adding (α') as a reduction operation, we obtain a QP norm close to the optimal

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[0553] FIG. 10 and the following discussion are intended to provide a brief, general description of an exemplary computing environment in which the disclosed technology may be implemented. Although not required, the disclosed technology is described in the general context of computer-executable instructions, such as program modules, executed by a personal computer (PC). Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Furthermore, the disclosed technology may be implemented in other computer system configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframe computers, etc. The disclosed technology may also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0554] Referring to FIG. 10, an exemplary system for implementing the disclosed technology includes a general-purpose (classical) computing device in the form of an exemplary conventional PC 1000 including one or more processing units 1010, a system memory 1020, and a system bus 1030 that couples various system components including the system memory 1020 to the one or more processing units 1010. The system bus 1030 can be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and / or a local bus using any of a variety of bus architectures. The exemplary system memory 1020 includes a read only memory (ROM) 1022 and a random-access memory (RAM) 1027. A basic input / output system (BIOS) 1025, containing the basic routines that help transfer information between elements within the PC 1000, is stored in the ROM 1022. As shown in FIG. 10, system memory 1020 may store computer-executable instructions for performing any of the disclosed techniques (e.g., sending instructions to a quantum computer to apply characterization gate sequences and adjacent gate sequences to a subset of quantum bits, measuring results, collecting frequencies, calculating model parameters) in respective memory portions (shown generally as executable software 1029 for performing any embodiment of the disclosed synthesis techniques).

[0555] The exemplary PC 1000 further includes one or more storage devices 1040, such as a hard disk drive for reading from and writing to a hard disk, a magnetic disk drive for reading from and writing to a removable magnetic disk, and / or an optical disk drive for reading from and writing to a removable optical disk (such as a CD-ROM or other optical medium). Such storage devices may be connected to the system bus 1030 by a hard disk drive interface, a magnetic disk drive interface, and / or an optical drive interface, respectively. The drives and their associated computer-readable media provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the PC 1000. In the exemplary operating environment, other types of computer-readable media capable of storing data accessible by a PC may also be used, such as magnetic cassettes, flash memory, digital video disks, CDs, DVDs, RAM, NVRAM, ROM, etc. As used herein, the terms storage, memory, and computer-readable media may not include or encompass the propagating carrier waves or signals themselves.

[0556] A number of program modules, including an operating system, one or more application programs, other program modules, and program data, may be stored in the storage device 1040. Storage of quantum measurement results and instructions for obtaining such measurements (and / or instructions for implementing any embodiment of the disclosed technology) may be stored in the storage device 1040. A user may enter commands and information into the PC 1000 through one or more input devices 1050, such as a keyboard and a pointing device such as a mouse. Other input devices may include a digital camera, microphone, joystick, game pad, satellite dish, scanner, and the like. These and other input devices are often connected to the one or more processing units 1010 through a serial port interface coupled to the system bus 1030, but may be connected by other interfaces such as a parallel port, game port, or universal serial bus (USB). A monitor 1080 or other type of display device is also connected to the system bus 1030 through an interface such as a video adapter. Other peripheral output devices 1060, such as speakers and a printer (not shown), may be included. In some cases, a user interface is displayed to allow the user to input circuits for synthesis and verify successful synthesis.

[0557] The PC 1000 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1090. In some examples, one or more network or communication connections 1070 are included. The remote computer 1090 may be another PC, a server, a router, a network PC, or a peer device or other common network node, and typically includes many or all of the elements described above with respect to the PC 1000, although only a memory storage device 1095 is illustrated in FIG. 10. The personal computer 1000 and / or the remote computer 1090 may be connected to local area networks (LANs) and wide area networks (WANs). Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets, and the Internet.

[0558] When used in a LAN networking environment, the PC 1000 is connected to the LAN via a network interface. When used in a WAN networking environment, the PC 1000 typically includes a modem or other means for establishing communications over the WAN, such as the Internet. In a networked environment, program modules depicted relative to the personal computer 1000, or portions thereof, may be stored in the remote memory storage device or other location on the LAN or WAN. The network connections shown are exemplary and other means of establishing a communications link between the computers may be used.

[0559] 11, an exemplary system for implementing the disclosed techniques includes a computing environment 1100, which includes one or more quantum processing units 1110 including one or more monitoring / measurement devices. The quantum processing units execute quantum circuits provided by classical processing units 1120. The quantum circuits are downloaded to the quantum processing units 1110 or used to program or configure the quantum processing units (e.g., via control lines (quantum buses) 1170). Procedures according to any of the disclosed embodiments (e.g., high-level descriptions of qubit patches and sets of quantum circuits applied to adjacent qubits) may be stored in memory 1130.

[0560] 11, a high-level description of the quantum software may be translated into a quantum circuit (e.g., a sequence of quantum gates, or layers of gates operating in parallel on different qubits). Such a high-level description may, in some cases, be stored on one or more external computers 1160 outside of the computing environment 1100 utilizing one or more memory and / or storage devices 1165, and then downloaded to the computing environment 1100 as needed via one or more communication connections 1140. The quantum circuit (according to any of the disclosed embodiments) is coupled to a quantum processor 1110.

[0561] The quantum processing unit may be one or more of, but is not limited to, the following: (a) a superconducting quantum computer, (b) an ion trap quantum computer, (c) a topological quantum computer, e.g., using Majorana zero modes, (d) a photonic quantum computer, or (e) a neutral atom quantum computer. A set of gates (e.g., using any of the disclosed embodiments) may be transmitted (or otherwise applied) to the quantum processing unit via control lines 1170 in controller 1150. In the illustrated example, the desired quantum computing process is implemented using one or more controllers 1150 that are specifically adapted to control a corresponding one of the quantum processors 1110. The classical processor 1120 may further interact with a measurement / monitoring device (e.g., readout device) 1180 to help control and implement the desired quantum computing process (e.g., by reading or measuring data results from the quantum processing unit when available, etc.).

[0562] Although the principles of the disclosed technology have been described and illustrated with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments may be modified in arrangement and detail without departing from such principles. For example, elements of the illustrated embodiments shown in software may be implemented in hardware and vice versa. Also, techniques from any example may be combined with techniques described in any one or more of the other examples. It will be understood that procedures and functions such as those described with reference to the illustrated examples may be implemented in a single hardware or software module, or separate modules may be provided. The above configurations are provided for convenient illustration, and other configurations may be used.

[0563] Thus, taking the language of the clauses into account, the present disclosure provides methods, systems, and methods that comply with, but are not limited to, the following clauses: Clause 1: A computer-implemented method for mitigating errors in a quantum circuit comprising at least one occurrence of a quantum logic operation G of a quantum processor, the method comprising: Set of base operations {B p}, the set of coefficients {c p} and calculate the set of basis operations {B p}, a quasi-probabilistic decomposition of the target version G0 of the quantum logical operation G

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Claims

1. 1. A computer-implemented method for mitigating errors in a quantum circuit comprising at least one occurrence of a quantum logic operation G of a quantum processor, the method comprising: A set of base operations {B ｐ } associated with the set of coefficients {c ｐ }, and calculate the set of basis operations {B ｐ }, the target version G of the quantum logical operation G ０ Quasi-probability decomposition of [0010] obtaining a i) the set of basis operations {B ｐ } forms a multitype basis constructed from elements of the quantum logic operations G and the set of reduction operations S; ii) the resolution is calculated to reach a resolution target based on at least one of a resolution accuracy target and a resolution sampling overhead target; Implementing the quasi-probability decomposition in the quantum processor to estimate an outcome of a target quantum circuit, the target version G of a quantum operation G being ０ permutes at least one occurrence of the quantum operation G.

2. The set of basis operations {B ｐ } is a multiple base operation type GS ｉ , S ｊ G.S. ｋ G.S. ｌ , S ｍ At least two base operation types selected from the S ｉ , . . . , S ｍ The method of claim 1 , wherein x is an element of a set S of reduction operations.

3. Implementing the quasi-probabilistic decomposition on the quantum processor comprises: i) for each of at least one occurrence of the quantum operation G in the quantum circuit, ｐ } based on the set of basis operations {B ｐ } to obtain at least one corresponding set of sampled operations, said sampling including weights [0025] According to the probability distribution defined by ｐ |c ｐ and ii) executing a set of sampled quantum circuits on the quantum processor, the set of sampled quantum circuits being determined by replacing at least one occurrence of G in the quantum circuit with one sampled operation of the corresponding set of sampled operations to obtain a sampled quantum circuit result, the replacement of at least one occurrence of G in the quantum circuit being performed by replacing each occurrence of G by a sample from the corresponding set of base operations; and iii) estimating the results of the target quantum circuit based on the sampled quantum circuit results.

4. The method further includes calculating the decomposition sampling overhead, the step of calculating the sampling overhead being based on the quasi-probability norm W=Σ ｐ |c ｐ The method of claim 1 , further comprising the step of calculating |

5. The target version G ０ The method of claim 1 , wherein:

6. The target version G ０ 2. The method of claim 1 , wherein:

7. The method of claim 1 , wherein ideal non-unitary quantum logic operations are excluded from the set S of reduced operations.

8. The S ｉ , . , S ｍ are set S １ , . . . , S ５ and the set S １ , . . . , S ５ At least one, preferably each, of ｎ 3. The method of claim 2 , comprising linearly independent operations of:

9. The method of claim 1 , wherein the set of reduced operations S comprises linearly dependent operations.

10. At least some of the operations in the set S of reduction operations ideally operate non-trivially on up to a predetermined number of quantum bits r, and each of the reduction operations included in the set S of reduction operations ideally operates non-trivially on up to the predetermined number of quantum bits r, and the set S １ , . . . , S ５ At least one, and preferably each, of [0030] The method of claim 1 , further comprising linearly independent operations of

11. The target version G of the quantum logical operation G ０ 2. The method of claim 1 , wherein x is a layer of gates that operate on non-overlapping sets of qubits.

12. The method of claim 1 , wherein the quantum logic operation G is twirl.

13. The target version G of the quantum logical operation G ０ comprises a non-Clifford gate, and the non-Clifford gate is ０ 13. The method of claim 12, wherein the gate is twirl using a gate interchangeable with.

14. The set of basis operations {B ｐ } includes two or more occurrences of a quantum logic operation G or includes two or more reduction operations selected from the set of reduction operations S. ｐ 2. The method of claim 1, further comprising: wherein the sub-circuits are shallow and have a depth less than a predetermined threshold.

15. a sub-circuit, the quantum logic operation G being given by a sequence of sub-operations [0045] and said sub-circuit B ｐ is zero or more sub-operations included in the sequence of sub-operations [0050] and zero or more operations in the set S of reduced operations.

16. 2. The method of claim 1, comprising optimizing a trade-off between decomposition accuracy and decomposition sampling overhead, the optimizing trade-off comprising optimizing the decomposition accuracy by solving a least squares problem and minimizing the sampling overhead by solving a linear programming problem.

17. The method of claim 1 , wherein the decomposition precision target comprises a decomposition precision that remains below a predetermined precision threshold ε, and the decomposition sampling overhead target comprises a decomposition sampling overhead that remains below a predetermined sampling overhead threshold η.

18. 4. The method of claim 3, wherein the estimating the outcome of the target quantum circuit comprises: calculating, for each sampled quantum circuit of the set of sampled quantum circuits, a corresponding sampled circuit signature equal to a sign of a product of the at least one coefficient corresponding to at least one sampled operation that replaces the at least one occurrence of G in the sampled quantum circuit; and wherein the estimating the outcome of the target quantum circuit comprises calculating an average of the sampled quantum circuit results, the sampled quantum circuit results being weighted by the corresponding sampled circuit signature and a quasi-probability norm W.

19. A non-transitory computer readable storage medium storing computer instructions, the computer instructions being used to cause a computer to perform the method of claim 1.

20. 1. A computer system comprising a quantum processor and a classical processor, the classical processor configured to execute the computer-executable components stored in a memory, the computer-executable components comprising: - A set of base operations {B ｐ } associated with the set of coefficients {c ｐ }, and calculate the set of basis operations {B ｐ }, the target version G of the quantum logical operation G ０ Quasi-probability decomposition of [006] obtaining a i) the set of basis operations {B ｐ } forms a multitype basis including at least two basis operation types constructed from elements of the quantum logic operation G and the set of reduced operations S; ii) a decomposition component, the decomposition being calculated to reach a decomposition target based on at least one of a decomposition accuracy target and a decomposition sampling overhead target; the target version G of the quantum operation G ０ and an implementation component that implements the quasi-probabilistic decomposition on the quantum processor to estimate an outcome of a target quantum circuit in which G replaces at least one occurrence of the quantum operation G.

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