Electro-optical device and electronic apparatus

Abstract

To provide an electro-optical device capable of suppressing temperature rise.SOLUTION: An electro-optical device includes: a pixel electrode 10a as a first pixel electrode and a pixel electrode 10b as a second pixel electrode adjacent to each other; a capacitor electrode 231 as a first light shielding layer provided between the pixel electrode 10a and the pixel electrode 10b in a plan view; and an interlayer insulation layer 20 as an insulation layer provided in a layer between the pixel electrode 10a and pixel electrode 10b and the capacitor electrode 231. The interlayer insulation layer 20 has a cavity 131 as a first cavity between the pixel electrode 10a and the pixel electrode 10b in a plan view.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to an electro-optical device and an electronic device equipped with the electro-optical device. [Background technology]

[0002] 2. Description of the Related Art A known conventional electro-optical device is described in Patent Document 1, for example. Patent document 1 describes a liquid crystal panel comprising a plurality of pixel electrodes and a light-shielding film formed along an area corresponding to the boundary between the pixel electrodes, the light-shielding film having a reflective surface that reflects a portion of the light incident from one of the first and second substrates. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-10122 A Summary of the Invention [Problem to be solved by the invention]

[0004] The light-shielding film is made of any one of titanium, chromium, tungsten, tantalum, molybdenum, palladium, aluminum, an alloy of these metals, and silicon. These light-shielding films reflect approximately 80 to 50 percent of the light that enters them, but the remaining 20 to 50 percent of the light is absorbed by the film, which poses the problem of causing the temperature of the LCD panel to rise. [Means for solving the problem]

[0005] An electro-optical device according to one embodiment of the present application comprises a first pixel electrode and a second pixel electrode adjacent to each other, a first light-shielding layer provided in a planar view between the first pixel electrode and the second pixel electrode, and an insulating layer provided in a layer between the first pixel electrode and the second pixel electrode and the first light-shielding layer, and in a planar view, the insulating layer has a first cavity between the first pixel electrode and the second pixel electrode.

[0006] An electronic device according to an aspect of the present application includes the electro-optical device described above. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of an electro-optical device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the electro-optical device taken along line II-II in FIG. [Diagram 3] FIG. 2 is an equivalent circuit diagram showing an electrical configuration of an element substrate. [Figure 4] FIG. 2 is an explanatory diagram showing a cross-sectional structure of a display area of ​​an element substrate. [Diagram 5] FIG. 2 is an explanatory diagram showing a planar structure of a display area of ​​an element substrate. [Figure 6] FIG. 2 is an explanatory diagram showing a planar structure of a display area of ​​an element substrate. [Figure 7] FIG. 2 is an explanatory diagram showing a planar structure of a display area of ​​an element substrate. [Figure 8] FIG. 2 is an explanatory diagram showing a planar structure of a display area of ​​an element substrate. [Figure 9] FIG. 2 is an explanatory diagram showing a planar structure of a display area of ​​an element substrate. [Figure 10] FIG. 2 is an explanatory diagram showing a planar structure of a display area of ​​an element substrate. [Figure 11] 11 is a cross-sectional view of the cavity and its surroundings taken along line XI-XI in FIG. 10 . [Figure 12] 4 is a flowchart showing a process for manufacturing a cavity. [Figure 13A] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 13B] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 13C] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 13D] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 14] FIG. 11 is a schematic diagram showing an example of an electronic device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the dimensions of the components may be shown on different scales in order to make the components easier to see. For ease of explanation, the following description will be made using the mutually orthogonal X-axis, Y-axis, and Z-axis as appropriate. A direction along the X-axis will be referred to as the X1 direction, and a direction opposite to the X1 direction will be referred to as the X2 direction. Similarly, a direction along the Y-axis will be referred to as the Y1 direction, and a direction opposite to the Y1 direction will be referred to as the Y2 direction. A direction along the Z-axis will be referred to as the Z1 direction, and a direction opposite to the Z1 direction will be referred to as the Z2 direction. In the following description, a view in the Z1 or Z2 direction will be referred to as a "planar view," and a view from a direction perpendicular to a cross section including the Z-axis will be referred to as a "cross-sectional view."

[0009] Furthermore, in the following description, for example, the expression "on the substrate" refers to a substrate that is disposed on the substrate, a substrate that is disposed on the substrate via another structure, or a substrate that is partially disposed on the substrate and partially disposed on the substrate via another structure. The expression "top surface of the substrate" refers to the surface of the substrate on the Z1 direction side.

[0010] 1. Embodiment 1 In this embodiment, a liquid crystal device will be described as an example of the electro-optical device. The liquid crystal device is an active-drive transmissive liquid crystal device having a TFT (Thin Film Transistor) as a switching element for each pixel. This liquid crystal device is used as a light modulation device in a projection display device, which will be described later. In this embodiment, the projection display device is an example of an electronic device.

[0011] 1.1. Overview of the structure of liquid crystal devices The structure of a liquid crystal device 300 according to this embodiment will be described with reference to Figures 1 and 2. Figure 1 shows a plan view of the liquid crystal device 300. Figure 2 shows a schematic cross-sectional configuration of the liquid crystal device 300 taken along line II-II in Figure 1.

[0012] 1 and 2, a liquid crystal device 300 includes a light-transmitting element substrate 100, a light-transmitting counter substrate 200, a frame-shaped seal member 8, and a liquid crystal layer Lc. Note that "light-transmitting" refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more.

[0013] The liquid crystal device 300 has a display area A1 for displaying an image, and a peripheral area A2 located on the outer periphery of the display area A1 in a plan view. The display area A1 is provided with a plurality of pixels P arranged in a matrix. Note that, although the liquid crystal device 300 and the display area A1 shown in Fig. 1 are rectangular in shape, they may be of another shape, for example, a circle.

[0014] As shown in FIG. 2, the element substrate 100 and the counter substrate 200 are disposed with a liquid crystal layer Lc therebetween. In this embodiment, the counter substrate 200 is disposed on the light incident side of the liquid crystal layer Lc, and the element substrate 100 is disposed on the light exit side of the liquid crystal layer Lc. Incident light IL incident on the counter substrate 200 is modulated by the liquid crystal layer Lc and is emitted from the element substrate 100 as modulated light ML.

[0015] The element substrate 100 includes a base 90 , a plurality of interlayer insulating layers including an interlayer insulating layer 82 , pixel electrodes 10 , and an alignment film 12 .

[0016] The base 90 is a flat plate having optical transparency and insulating properties. The base 90 is, for example, a glass substrate or a quartz substrate. Transistors, which will be described later, are disposed between the multiple interlayer insulating layers. The pixel electrode 10 is transparent. The pixel electrode 10 is made of ITO (Indium Tin Oxide). The pixel electrode 10 may be made of a transparent conductive material such as IZO (Indium Zinc Oxide) and FTO (Fluorine-doped tin oxide). The thickness direction of the pixel electrode 10 coincides with the Z1 direction or the Z2 direction. The alignment film 12 has light-transmitting and insulating properties. The alignment film 12 aligns the liquid crystal molecules of the liquid crystal layer Lc. Examples of materials for the alignment film 12 include silicon oxide (SiO2) and polyimide.

[0017] The counter substrate 200 includes a base 210 , an insulating layer 220 , a common electrode 230 , and an alignment film 240 . The substrate 210 is a flat plate having optical transparency and insulating properties, and is, for example, a glass substrate or a quartz substrate. The insulating layer 220 is transparent and insulating, and is made of an inorganic material such as silicon oxide.

[0018] The common electrode 230 is an electrode disposed opposite the pixel electrodes 10, and may be referred to as a counter electrode. The common electrode 230 includes a transparent conductive material such as ITO, IZO, or FTO. The common electrode 230 and the pixel electrodes 10 apply an electric field to the liquid crystal layer Lc. The alignment film 240 is light-transmitting and insulating.

[0019] The seal member 8 is disposed between the element substrate 100 and the opposing substrate 200. The seal member 8 is formed using an adhesive containing various hardening resins such as epoxy resin. The seal member 8 may contain a gap material made of an inorganic material such as glass.

[0020] The liquid crystal layer Lc is disposed within an area surrounded by the element substrate 100, the counter substrate 200, and the seal member 8. The liquid crystal layer Lc is an electro-optical layer whose optical characteristics change in response to an electric field generated by the pixel electrodes 10 and the common electrode 230. The liquid crystal layer Lc contains liquid crystal molecules having positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to an electric field applied to the liquid crystal layer Lc. The liquid crystal layer Lc modulates the incident light IL in response to the applied electric field.

[0021] As shown in FIG. 1, in a peripheral region A2 of an element substrate 100, a plurality of scanning line driving circuits 6, a data line driving circuit 7, and external terminals 9 are arranged. The external terminal 9 is a mounting terminal on which an external connection line such as an FPC (Flexible Printed Circuit) (not shown) is mounted. Various signals including an image signal, a synchronization signal, an inspection signal, a common potential, a power supply potential, etc. are supplied to the external terminal 9 from the outside via the external connection line.

[0022] 1.2.Electrical configuration of the element substrate FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 100. As shown in FIG. 3, a plurality of transistors 1, n scanning lines 3, m data lines 4, m capacitance lines 5a, n capacitance lines 5b, a pixel electrode 10, a capacitance element 2a, and a capacitance element 2b are provided in a display area A1 of a device substrate 100. n and m are each an integer of 2 or more.

[0023] The transistors 1 are provided corresponding to each intersection of the n scanning lines 3 and the m data lines 4. The pixel electrodes 10 are electrically connected to the drain regions of the transistors 1. Each of the n scanning lines 3 extends in the X1 direction, and the n scanning lines 3 are arranged at equal intervals in the Y1 direction. Each of the n scanning lines 3 is electrically connected to the gate electrode of the corresponding transistor 1. The n scanning lines 3 are electrically connected to a scanning line driving circuit 6 shown in FIG. The scanning line driving circuit 6 supplies scanning signals G1, G2, . . . , and Gn to the 1 to n scanning lines 3 in a line-sequential manner.

[0024] Each of the m data lines 4 extends in the Y1 direction, and the m data lines 4 are arranged at equal intervals in the X1 direction. Each of the m data lines 4 is electrically connected to the source regions of the corresponding transistors 1. The m data lines 4 are electrically connected to the data line driving circuit 7 shown in FIG. The data line driving circuit 7 supplies image signals E1, E2, . . . , and Em to the data lines 4, which number is 1 to m.

[0025] The n scanning lines 3 and the m data lines 4 are electrically insulated from each other and arranged in a lattice pattern in a plan view. An area surrounded by two adjacent scanning lines 3 and two adjacent data lines 4 corresponds to a pixel P.

[0026] The m capacitance lines 5a extend in the Y1 direction and are arranged at equal intervals in the X1 direction. The n capacitance lines 5b extend in the X1 direction and are arranged at equal intervals in the Y1 direction.

[0027] The capacitance lines 5a and 5b are electrically insulated from and spaced apart from the data lines 4 and the scanning lines 3. A fixed potential such as a common potential or a ground potential is supplied to the capacitance lines 5a and 5b via an external terminal 9.

[0028] One electrode of the capacitive element 2a is electrically connected to a capacitive line 5a, and one electrode of the capacitive element 2b is electrically connected to a capacitive line 5b. The other electrodes of the capacitive element 2 a and the capacitive element 2 b are electrically connected to the pixel electrode 10 and hold the potential of the image signal supplied to the pixel electrode 10 .

[0029] 1.3. Cross-sectional and planar structures of the display area of ​​the element substrate Fig. 4 is an explanatory diagram showing the cross-sectional structure of the display region A1 of the element substrate 100, and is a cross-sectional view showing the stacking relationship and electrical connection relationship of each layer. Fig. 5 to Fig. 10 are plan views showing the planar structure of the main layers. As shown in FIG. 4, in the display region A1, the element substrate 100 has a cross-sectional structure in which insulating or conductive functional layers or functional films are stacked on a base 90.

[0030] Fig. 5 is a plan view showing the planar structure from the base 90 to the interlayer insulating layer 76, in which the light-shielding layer 80, the semiconductor layer 70, the gate electrode 74, and the contact holes 71 and 73 are indicated by solid lines, and the contact hole 81 is indicated by a dashed line. In Figs. 5 to 10, the position of the pixel electrode 10 is indicated by a dashed line to show the positional relationship of each component in a plan view. The shape of the pixel electrode 10 is rectangular.

[0031] As shown in FIG. 4, a light-shielding layer 80 is disposed between the base 90 and the interlayer insulating layer 82 . As shown in FIG. 5, the light-shielding layer 80 is provided so as to overlap the gap between the adjacent pixel electrodes 10. The light-shielding layer 80 has portions extending in the X1 and X2 directions, and portions extending in the Y1 and Y2 directions and overlapping with the semiconductor layer 70. The light-shielding layer 80 constitutes the scanning lines 3.

[0032] The light-shielding layer 80 is formed of a conductive material having light-shielding properties. Examples of the conductive material having light-shielding properties include metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (AL), metal nitrides, and metal silicides. The same applies to the conductive material having light-shielding properties below. The conductive material having light-shielding properties is used for the wiring layer. In this embodiment, the scanning line 3 is the wiring layer closest to the base 90, in other words, the wiring layer at the bottom. The term "light-shielding properties" refers to a light-shielding property against visible light, and preferably means that the transmittance of visible light is less than 50%, and more preferably means that the transmittance is 10% or less.

[0033] The interlayer insulating layer 82 is transparent and insulating. The interlayer insulating layer 82 is made of an inorganic material such as silicon oxide (SiO2). Each of the following interlayer insulating layers is made of the same material as the interlayer insulating layer 82.

[0034] 4, the transistor 1 is provided on the interlayer insulating layer 82. As shown in Fig. 5, the transistor 1 is provided in the gap between adjacent pixel electrodes 10 so as to overlap the light-shielding layer 80.

[0035] As shown in FIG. 4, the transistor 1 includes a semiconductor layer 70 having an LDD (Lightly Doped Drain) structure, a gate electrode 74, and a gate insulating layer 72. The semiconductor layer 70 has a drain region 70d, an LDD region 70a, a channel region 70c, an LDD region 70b, and a source region 70s.

[0036] The channel region 70c is located in a central portion of the semiconductor layer 70. The LDD region 70b is located between the channel region 70c and the source region 70s. The LDD region 70a is located between the channel region 70c and the drain region 70d. The semiconductor layer 70 is, for example, polysilicon, and regions other than the channel region 70c are doped with impurities to enhance conductivity. The impurity concentrations in the LDD region 70b and the LDD region 70a are lower than the impurity concentrations in the source region 70s and the drain region 70d.

[0037] A gate electrode 74 is provided on the semiconductor layer 70 with a gate insulating layer 72 interposed therebetween. The gate electrode 74 overlaps the channel region 70c of the semiconductor layer 70. The gate electrode 74 is formed using, for example, polysilicon doped with impurities that enhance electrical conductivity. The gate electrode 74 may also be formed using a material having electrical conductivity, such as a metal, a metal silicide, or a metal compound.

[0038] The gate insulating layer 72 is made of silicon oxide formed by, for example, thermal oxidation or a CVD (Chemical Vapor Deposition) method. The gate electrode 74 and the light-shielding layer 80 are electrically connected via a contact hole 81. The contact hole 81 penetrates the gate insulating layer 72 and the interlayer insulating layer .

[0039] An interlayer insulating layer 76 is provided on the transistor 1 . A conductive layer 61 and relay layers 62 and 63 are provided on the interlayer insulating layer 76. The conductive layer 61 and the relay layers 62 and 63 are provided in the same layer, and are made of a light-shielding conductive material.

[0040] FIG. 6 is a plan view showing the planar structure of conductive layer 61 and relay layers 62, 63 provided on interlayer insulating layer 76, in which conductive layer 61, relay layers 62, 63, and contact holes 67, 68 are shown by solid lines, and contact holes 71, 73 provided in interlayer insulating layer 76 and semiconductor layer 70 provided in the underlying layer are shown by dashed lines.

[0041] The conductive layer 61 and the relay layers 62 and 63 are provided so as to overlap the gaps between the adjacent pixel electrodes 10, respectively. The conductive layer 61 has portions extending in the X1 and X2 directions, and portions protruding in the Y1 direction and in a diagonal direction of the pixel electrode 10 so as to overlap a central portion of the semiconductor layer 70. The conductive layer 61 constitutes a capacitance line 5b.

[0042] As shown in FIG. 4, the relay layer 62 is electrically connected to a drain region 70d of the semiconductor layer 70 via a contact hole 71 that penetrates the interlayer insulating layer 76. The relay layer 63 is electrically connected to a source region 70s of the semiconductor layer 70 via a contact hole 73 that penetrates the interlayer insulating layer 76.

[0043] On the interlayer insulating layer 76, the conductive layer 61, and the relay layers 62 and 63, an interlayer insulating layer 60, a capacitive element 2b, a capacitive insulating layer 65, and a relay layer 53 are provided. The capacitive element 2b has a capacitive electrode 64 and a capacitive electrode 54. The capacitive electrode 64, the capacitive electrode 54, and the relay layer 53 are each formed of a light-shielding conductive material. The capacitive electrode 54 and the relay layer 53 are provided in the same layer.

[0044] The capacitance insulating layer 65 is provided as a layer between the capacitance electrode 64 and the capacitance electrode 54. For the capacitance insulating layer 65, for example, a silicon compound such as a silicon oxide film or a silicon nitride film, or a dielectric layer having a high dielectric constant such as an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, or a zirconium oxide film can be used. The same applies to the capacitance insulating layer hereinafter.

[0045] FIG. 7 is a plan view showing the planar structure of the capacitive element 2b and relay layer 53, in which the relay layer 53, the capacitive electrode 54, and the contact holes 51 and 52 are indicated by solid lines, and the capacitive electrode 64, the contact holes 67 and 68, and the semiconductor layer 70 are indicated by dashed lines.

[0046] The capacitance electrode 64, the capacitance electrode 54, and the relay layer 53 are provided so as to overlap with the gaps between adjacent pixel electrodes 10. The capacitance electrode 64 and the capacitance electrode 54 each have a portion provided so as to protrude in the Y1 direction, the Y2 direction, and a corner portion of the pixel P, and are provided at a position overlapping with the center portion of the semiconductor layer 70.

[0047] As shown in FIG. 4, a portion of the capacitance electrode 64 is provided in a contact hole 66 provided in the interlayer insulating layer 60, and is electrically connected to the capacitance line 5b. The capacitance electrode 54 is electrically connected to the relay layer 62 through a contact hole 67 .

[0048] By providing the capacitive electrode 64 and the capacitive line 5b between the capacitive electrode 54 and the gate electrode 74, the capacitive electrode 54 and the gate electrode 74 are shielded by the capacitive electrode 64 and the capacitive line 5b, and electrical coupling between the capacitive electrode 54 and the gate electrode 74 is suppressed. Therefore, it is possible to suppress the scanning signal supplied to the gate electrode 74 from being superimposed as noise on the image signal via the capacitive electrode 54.

[0049] An interlayer insulating layer 50 is provided on the capacitance electrode 54, the relay layer 53, and the capacitance insulating layer 65, and a relay layer 41 and a conductive layer 42 are provided on the interlayer insulating layer 50. The relay layer 41 and the conductive layer 42 are provided in the same layer, and are each formed of a light-shielding conductive material.

[0050] FIG. 8 is a plan view showing the planar structure of relay layer 41 and conductive layer 42, in which relay layer 41, conductive layer 42, and contact hole 43 are indicated by solid lines, and contact holes 51, 52, and semiconductor layer 70 are indicated by dashed lines.

[0051] The relay layer 41 and the conductive layer 42 are provided so as to overlap the gap between the adjacent pixel electrodes 10, respectively. The conductive layer 42 extends in the Y1 and Y2 directions and overlaps with the semiconductor layer 70. The conductive layer 42 constitutes the data line 4.

[0052] 4, the relay layer 41 is electrically connected to the capacitance electrode 54 through a contact hole 51. The conductive layer 42 is electrically connected to the relay layer 53 through a contact hole 52.

[0053] An interlayer insulating layer 40 is provided on the relay layer 41, the conductive layer 42, and the interlayer insulating layer 50, and on the interlayer insulating layer 40, a conductive layer 44, an interlayer insulating layer 30, a capacitive element 2a, and a capacitive insulating layer 32 are provided.

[0054] The capacitive element 2a has a capacitive electrode 23 and a capacitive electrode 33. The capacitive electrodes 23 and 33 and the conductive layer 44 are each formed of a light-shielding conductive material. The capacitive electrode 23 is the wiring layer closest to the pixel electrode 10, in other words, the uppermost wiring layer. The capacitance insulating layer 32 is provided between the capacitance electrode 33 and the capacitance electrode 23 .

[0055] FIG. 9 is a plan view showing the planar structure of the capacitive electrode 23, the capacitive electrode 33, and the conductive layer 44, in which the capacitive electrode 23 and the contact hole 21 are indicated by solid lines, and the capacitive electrode 33, the conductive layer 44, the contact hole 43, and the semiconductor layer 70 are indicated by dashed lines.

[0056] The capacitance electrodes 23 and 33 and the conductive layer 44 are provided so as to overlap the gaps between the adjacent pixel electrodes 10, respectively. The conductive layer 44 extends in the Y1 and Y2 directions and overlaps the semiconductor layer 70. The conductive layer 44 also constitutes a capacitance line 5a.

[0057] The capacitance electrode 23 has a first light-shielding portion 23a, a second light-shielding portion 23b, and a third light-shielding portion 23c. The first light-shielding portion 23a is located at the center of the capacitance electrode 23, and is provided so as to extend in the Y1 direction, the Y2 direction, and to the corners of the pixel P. The first light-shielding portion 23a overlaps with the center portion of the semiconductor layer 70 and the contact hole 21. The second light-shielding portion 23b is a portion that protrudes in the Y2 direction from the first light-shielding portion 23a. The third light-shielding portion 23c is a portion that protrudes in the X2 direction from the first light-shielding portion 23a.

[0058] In this embodiment, the capacitance electrode 231 of the capacitance electrode 23 arranged between the pixel electrodes 10a and 10b is an example of a first light-shielding layer. The capacitance electrode 232 of the capacitance electrode 23 arranged between the pixel electrodes 10c and 10d and adjacent to the capacitance electrode 231 in the Y1 direction is an example of a second light-shielding layer. The capacitance electrode 233 of the capacitance electrode 23 arranged between the pixel electrodes 10b and 10c and adjacent to the capacitance electrode 231 in the X1 direction is an example of a third light-shielding layer. The Y2 direction is an example of a first direction, and the X2 direction is an example of a second direction.

[0059] The capacitance electrode 33 has a planar shape similar to that of the capacitance electrode 23 . As shown in FIG. 4, a portion of the capacitance electrode 33 is provided in a contact hole 31 provided in the interlayer insulating layer 30, and is electrically connected to the capacitance line 5a. The capacitance electrode 23 is electrically connected to the relay layer 41 through a contact hole 43. The capacitance electrode 23 is also electrically connected to the pixel electrode 10 through a contact hole 21. In this embodiment, a contact plug is provided in the contact hole 21 as a conductive member.

[0060] By providing the capacitance electrode 33 and the capacitance line 5a between the capacitance electrode 23 and the data line 4, the capacitance electrode 23 and the data line 4 are shielded by the capacitance electrode 33 and the capacitance line 5a, and electrical coupling between the capacitance electrode 23 and the data line 4 is suppressed. Therefore, it is possible to suppress the image signal of another pixel P supplied to the data line 4 from being superimposed as noise on the image signal via the capacitance electrode 23.

[0061] An interlayer insulating layer 20 is provided on the capacitive electrode 23 and the capacitive insulating layer 32 . The interlayer insulating layer 20 includes an insulating layer 20a and an insulating layer 20b. In this embodiment, the interlayer insulating layer 20 is an example of an insulating layer. The insulating layer 20a is an example of a first insulating layer. The insulating layer 20b is an example of a second insulating layer.

[0062] The insulating layer 20a has a groove 20s. An insulating layer 20b is provided on the insulating layer 20a including the inside of the groove 20s. The insulating layer 20b has a cavity 13 in the groove 20s. The cavity 13 is an empty space called a void formed in the insulating layer 20b, and the cavity 13 is filled with air or a vacuum.

[0063] In this embodiment, the insulating layer 20a is made of silicon oxide, and the insulating layer 20b is made of silicon oxynitride (SiON) or silicon nitride (SiNx). The refractive index of the cavity 13 is 1.0, and the refractive index of the insulating layer 20b is, for example, 1.6. Therefore, due to the difference in refractive index between the insulating layer 20b and the cavity 13, the cavity 13 can totally reflect the light that is about to enter the capacitance electrode 23. The insulating layer 20b may be made of silicon oxide, like the insulating layer 20a. However, by forming the insulating layer 20b from silicon oxynitride or silicon nitride, the refractive index difference between the cavity 13 and the insulating layer 20b can be made larger, making total reflection more likely to occur.

[0064] FIG. 10 is a plan view showing the planar structure of the cavity 13 and the capacitance electrode 23, in which the cavity 13 and the contact hole 21 are indicated by solid lines, and the capacitance electrode 23 is indicated by dashed lines. The cavity 13 and the capacitance electrode 23 are provided so as to overlap the gap between the adjacent pixel electrodes 10, respectively.

[0065] The cavity 13 has a first cavity portion 13a, a second cavity portion 13b, and a third cavity portion 13c. The first cavity 13a is located in the center of the cavity 13 and overlaps with the first light-shielding portion 23a of the capacitance electrode 23. The second cavity 13b is a portion that protrudes from the first cavity 13a in the Y1 direction and overlaps with the second light-shielding portion 23b of the capacitance electrode 232 adjacent to the capacitance electrode 231 in the Y1 direction. The third cavity 13c is a portion that protrudes from the first cavity 13a in the X1 direction and overlaps with the third light-shielding portion 23c of the capacitance electrode 233 adjacent to the capacitance electrode 231 in the X1 direction.

[0066] In this embodiment, the cavity 131 of the cavities 13 is an example of a first cavity, the cavity 132 is an example of a second cavity, and the cavity 133 is an example of a third cavity. The Y1 direction is an example of a third direction, and the X1 direction is an example of a fourth direction. The cavity 131 has a first cavity portion 13a disposed between pixel electrode 10a, pixel electrode 10b, pixel electrode 10c, and pixel electrode 10d, a second cavity portion 13b disposed between pixel electrode 10c and pixel electrode 10d, and a third cavity portion 13c disposed between pixel electrode 10b and pixel electrode 10c. The cavity 132 is adjacent to the cavity 131 in the Y2 direction. The cavity 133 is adjacent to the cavity 131 in the X2 direction.

[0067] The first cavity 13a has a shape that follows the outer edge of the first light-shielding portion 23a except for the portion where the contact hole 21 is provided. The first cavity 13a does not protrude in the Y2 direction. In other words, the first cavity 13a of the cavity 131 and the second cavity 13b of the cavity 132 are not continuous with each other. Similarly, the first cavity 13a of the cavity 131 and the third cavity 13c of the cavity 133 are not continuous with each other.

[0068] In this way, the cavity 13 has a portion where the cavity 13 is interrupted at the location where the contact hole 21 is provided. Therefore, a sufficient clearance can be provided between the contact hole 21 and the cavity 13, and the electrical connection between the pixel electrode 10 and the capacitance electrode 23 can be maintained in a good condition.

[0069] The capacitance electrode 23 overlaps three adjacent cavities 13 . For example, when attention is focused on the capacitance electrode 231 depicted near the center of FIG. 10, the first light-shielding portion 23a of the capacitance electrode 231 overlaps with the first cavity portion 13a of the cavity 131 depicted near the center of FIG. Further, the second light-shielding portion 23b of the capacitance electrode 231 overlaps with the second cavity portion 13b of the cavity 132 adjacent to the cavity 131 in the Y2 direction. Moreover, the third light-shielding portion 23c of the capacitance electrode 231 overlaps with the third cavity portion 13c of the cavity 133 adjacent to the cavity 131 in the X2 direction.

[0070] 1.4.Cross-sectional structure of the cavity FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10, and shows the cross-sectional structure around cavity 13. As shown in FIG.

[0071] As shown in FIG. 11, the cavity 13 is provided in the insulating layer 20b within the groove 20s of the insulating layer 20a. The cavity 13 is formed when the insulating layer 20b is formed on the insulating layer 20a including the inside of the groove 20s.

[0072] The cavity 13 has a cross-sectional shape called a teardrop shape, a water drop shape, or a bullet shape, in which the opening side of the groove 20s is narrowed. In order to make the cross-sectional shape of the cavity 13 into such a shape, it is preferable to make the aspect ratio of the groove 20s 2.0 or more. This aspect ratio is a value obtained by the inventors' experiments. In the inventors' experiments, it was found that by making the aspect ratio of the groove 20s 1.41 or more, the cavity 13 is formed in the groove 20s, and by making the aspect ratio of the groove 20s 2.0 or more, the cross-sectional shape of the cavity 13 can be made into a shape as shown in FIG. 11. The tip of the cavity 13 on the opening side of the groove 20s may protrude from inside the groove 20s.

[0073] The modulated light ML about to enter the capacitive electrode 23 is totally reflected by the cavity 13. This is due to the refractive index difference between the cavity 13 and the insulating layer 20b, as described above. Therefore, it is possible to suppress the modulated light ML from being absorbed by the capacitive electrode 23.

[0074] In this embodiment, the refractive index of the insulating layer 20a is 1.46, and the refractive index of the pixel electrode 10 is 2.1. The refractive index of the insulating layer 20b is 1.6, so that the insulating layer 20b has a refractive index between the pixel electrode 10 and the insulating layer 20a. In other words, the insulating layer 20b is an intermediate refractive index layer.

[0075] Therefore, the difference in refractive index between the cavity 13 and the insulating layer 20b can be made larger, and total reflection in the cavity 13 can be made to occur more easily. Furthermore, since light incident between the pixel electrodes 10 is totally reflected by the cavity 13, the brightness of the display screen can be improved. Furthermore, the refractive index difference between the pixel electrode 10 and the insulating layer 20a can be reduced, and therefore reflection at the interface between the pixel electrode 10 and the insulating layer 20b and / or the interface between the insulating layer 20b and the insulating layer 20a is suppressed, increasing the amount of transmitted light and improving the brightness of the display.

[0076] 1.5. Manufacturing method of the cavity Next, a method for manufacturing the cavity 13 will be described with reference to FIGS. 12 to 13D. Fig. 12 is a flow chart showing a method for manufacturing the cavity 13. Fig. 13A to Fig. 13D are cross-sectional views showing one embodiment of a process for manufacturing the cavity 13.

[0077] In step S1, as shown in FIG. 13A, an insulating layer 20a made of silicon oxide is formed on the capacitance electrode .

[0078] In step S2, as shown in Fig. 13B, grooves 20s are formed in insulating layer 20a. Grooves 20s are formed so that the aspect ratio, which is the ratio (L / D) of groove width W to groove depth L, is 2.0 or more.

[0079] When forming the groove 20s, it is preferable to prevent the capacitance electrode 23 from being exposed at the bottom of the groove 20s. If etching is performed until the capacitance electrode 23 is exposed at the bottom of the groove 20s, the capacitance electrode 23 acts as an etching stopper in the portion overlapping with the capacitance electrode 23 in a plan view, suppressing further etching, but etching proceeds in the portion where the capacitance electrode 23 is interrupted, resulting in a step at the bottom of the groove 20s.

[0080] In step S3, as shown in FIG. 13C, an insulating layer 20b made of silicon oxynitride or silicon nitride is formed by a PCVD (plasma chemical vapor deposition) method so as to fill the grooves 20s. This process forms a cavity 13 within the groove 20s.

[0081] In step S4, as shown in FIG. 13D, insulating layer 20b is planarized by CMP (Chemical Mechanical Polishing) to form interlayer insulating layer 20 made of insulating layer 20a and insulating layer 20b.

[0082] In step S5, the pixel electrodes 10 are formed. After providing contact holes 21 in interlayer insulating layer 20, contact plugs made of a conductive material are provided in contact holes 21. The contact plugs are made of tungsten. Since contact holes 21 are holes with a high aspect ratio, the difficulty of forming the contact plugs can be reduced by using tungsten as the material for the contact plugs. Thereafter, an ITO film is formed and patterned to form the pixel electrode 10.

[0083] As described above, the liquid crystal device 300 serving as an electro-optical device according to this embodiment has the following advantages. The liquid crystal device 300 of this embodiment includes a pixel electrode 10a as a first pixel electrode and a pixel electrode 10b as a second pixel electrode adjacent to each other, a capacitance electrode 231 as a first light-shielding layer provided between the pixel electrodes 10a and 10b in a planar view, and an interlayer insulating layer 20 as an insulating layer provided in a layer between the pixel electrodes 10a and 10b and the capacitance electrode 231, and in a planar view, the interlayer insulating layer 20 has a cavity 131 as a first cavity between the pixel electrodes 10a and 10b.

[0084] The interlayer insulating layer 20 thus provided between the pixel electrodes 10a, 10b and the capacitance electrode 231 has a cavity 131 as a first cavity between the pixel electrodes 10a and 10b adjacent to each other.

[0085] Therefore, light incident between the pixel electrodes 10a and 10b is totally reflected by the cavity 131 and is prevented from being absorbed by the capacitance electrode 231, so that an increase in temperature of the liquid crystal device 300 can be prevented. Furthermore, the light incident between the pixel electrodes 10a and 10b is totally reflected by the cavity 131, thereby improving the brightness of the display screen.

[0086] In the liquid crystal device 300 of this embodiment, the interlayer insulating layer 20 further has a contact hole 21 for electrically connecting the pixel electrode 10a and the capacitance electrode 231, and the contact hole 21 overlaps with the pixel electrode 10a and the capacitance electrode 231 in a planar view and is separated from the cavity 131.

[0087] Therefore, the cavity 131 can be disposed while maintaining good electrical connection between the pixel electrode 10a and the capacitance electrode 231.

[0088] In the liquid crystal device 300 of this embodiment, the interlayer insulating layer 20 further includes, in a planar view, an insulating layer 20a as a first insulating layer having a groove 20s overlapping between the pixel electrodes 10a and 10b, and an insulating layer 20b as a second insulating layer provided in the groove 20s and having a refractive index between the refractive index of the pixel electrode 10a and the refractive index of the insulating layer 20a, and a cavity 131 is provided in the groove 20s.

[0089] Therefore, the refractive index difference between the cavity 131 and the insulating layer 20b can be increased, and total reflection occurs more easily in the cavity 131. As a result, light absorption by the capacitive electrode 23 can be further suppressed, and an increase in temperature of the liquid crystal device 300 can be further suppressed. Furthermore, the refractive index difference between the pixel electrode 10 and the insulating layer 20a can be reduced, and light reflected at the interface between the pixel electrode 10 and the insulating layer 20b and / or the interface between the insulating layer 20b and the insulating layer 20a can be suppressed, resulting in a brighter display.

[0090] In the liquid crystal device 300 of this embodiment, the pixel electrodes 10a and 10b are made of ITO, the insulating layer 20a is made of SiO2, and the insulating layer 20b is made of SiON or SiNx.

[0091] Therefore, the refractive index difference between the cavity 131 and the insulating layer 20b can be increased, and total reflection occurs more easily in the cavity 131. As a result, light absorption by the capacitive electrode 23 can be further suppressed, and an increase in temperature of the liquid crystal device 300 can be further suppressed. Furthermore, the refractive index difference between the pixel electrode 10 and the insulating layer 20a can be reduced, thereby suppressing light reflection at the interface between the pixel electrode 10 and the insulating layer 20b and / or the interface between the insulating layer 20b and the insulating layer 20a, thereby enabling bright display.

[0092] In the liquid crystal device 300 of this embodiment, the aspect ratio of the grooves 20s is further set to 2 or more. Therefore, when the insulating layer 20b is formed, the cavity 131 can be formed in the groove 20s.

[0093] In the liquid crystal device 300 of this embodiment, the capacitive electrode 231 as a first light-shielding layer further has a first light-shielding portion 23a, a second light-shielding portion 23b protruding from the first light-shielding portion 23a along the Y2 direction as a first direction, and a third light-shielding portion 23c protruding from the first light-shielding portion 23a along the X2 direction as a second direction intersecting the Y2 direction, wherein the first light-shielding portion 23a overlaps with the cavity 131 as a first cavity in a planar view, the second light-shielding portion 23b overlaps with the cavity 132 as a second cavity adjacent to the cavity 131 in the Y2 direction in a planar view, and the third light-shielding portion 23c overlaps with the cavity 133 as a third cavity adjacent to the cavity 131 in the X2 direction in a planar view.

[0094] Therefore, the light traveling toward the capacitive electrode 23 can be totally reflected by the three cavities 131, 132, and 133.

[0095] In the liquid crystal device 300 of this embodiment, the cavity 131 as a first cavity further has a first cavity portion 13a, a second cavity portion 13b protruding from the first cavity portion 13a along the Y1 direction as a third direction, and a third cavity portion 13c protruding from the first cavity portion 13a along the X1 direction as a fourth direction intersecting the Y1 direction, where the first cavity portion 13a overlaps with the capacitive electrode 231 as a first light-shielding layer in a planar view, the second cavity portion 13b overlaps with the capacitive electrode 232 as a second light-shielding layer adjacent to the capacitive electrode 231 in the Y1 direction in a planar view, and the third cavity portion 13c overlaps with the capacitive electrode 233 as a third light-shielding layer adjacent to the capacitive electrode 231 in the X1 direction in a planar view.

[0096] Therefore, the light directed toward the capacitive electrodes 231 , 232 , and 233 can be totally reflected by the cavity 131 .

[0097] In the liquid crystal device 300 of this embodiment, the interlayer insulating layer 20 further includes a cavity 132 as a second cavity provided in the Y2 direction as a first direction of the cavity 131 as a first cavity, and a cavity 133 as a third cavity provided in the X2 direction as a second direction intersecting the Y2 direction of the cavity 131. The capacitance electrode 231 as a first light-shielding layer includes a first light-shielding portion 23a overlapping the cavity 131 in a plan view, a second light-shielding portion 23b protruding from the first light-shielding portion 23a along the Y2 direction and overlapping with the cavity 132 in a plan view, and a third light-shielding portion 23b protruding from the first light-shielding portion 23a along the X2 direction and overlapping with the cavity 132 in a plan view. , and a third light-shielding portion 23c overlapping the cavity 133, and the cavity 131 has a first cavity 13a overlapping the capacitive electrode 231 in a planar view, a second cavity 13b protruding from the first cavity 13a along the Y1 direction as a third direction opposite to the Y2 direction and overlapping with the capacitive electrode 232 as a second light-shielding layer adjacent to the capacitive electrode 231 in the Y1 direction in a planar view, and a third cavity 13c protruding from the first cavity 13a along the X1 direction as a fourth direction opposite to the X2 direction and overlapping with the capacitive electrode 233 as a third light-shielding layer adjacent to the capacitive electrode 231 in the X1 direction in a planar view.

[0098] Therefore, light traveling toward the capacitive electrode 231 can be totally reflected by the three cavities 131 , 132 , and 133 , and light traveling toward the capacitive electrodes 231 , 232 , and 233 can be totally reflected by the cavity 13 .

[0099] 2. Embodiment 2 FIG. 14 is a schematic diagram showing an example of an electronic device, and is a schematic diagram showing a schematic configuration of a projection type display device 1000 as the electronic device. The projection display device 1000 is, for example, a three-panel projector equipped with three of the above-mentioned liquid crystal devices 300. The liquid crystal device 300R corresponds to a red display color, the liquid crystal device 300G corresponds to a green display color, and the liquid crystal device 300B corresponds to a blue display color. The control unit 1005 includes, for example, a processor and a memory, and controls the operations of the liquid crystal devices 300R, 300G, and 300B.

[0100] The illumination optical system 1001 supplies a red component RL of light emitted from an illumination device 1002, which is a light source, to the liquid crystal device 300R, a green component GL to the liquid crystal device 300G, and a blue component BL to the liquid crystal device 300B. Each of the liquid crystal devices 300R, 300G, and 300B functions as a light modulation device that modulates the respective color lights RL, GL, and BL supplied from the illumination optical system 1001 in accordance with a display image. The projection optical system 1003 combines the light emitted from the liquid crystal device 300R, the liquid crystal device 300G, and the liquid crystal device 300B, and projects the combined light onto the screen 1004.

[0101] As described above, the projection display device 1000 serving as the electronic device of this embodiment includes the liquid crystal device 300 described above. Therefore, by employing the liquid crystal device 300 in which the temperature rise is suppressed, the performance of the projection display device 1000 can be improved.

[0102] The electronic device is not limited to the exemplified three-panel projector. For example, it may be a single-panel, two-panel, or projector equipped with four or more liquid crystal devices 300. The electronic device may also be a smartphone, a PDA (Personal Digital Assistant), a camera, a television, a car navigation device, a personal computer, a display, electronic paper, a calculator, a videophone, a POS (Point of Sale), a printer, a scanner, a copier, a video player, or a device equipped with a touch panel.

[0103] Although the preferred embodiment has been described above, the present invention is not limited to the above embodiment. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above embodiment, and any configuration can be added. [Explanation of symbols]

[0104] 1...transistor, 2a, 2b...capacitive element, 3...scanning line, 4...data line, 5a, 5b...capacitive line, 6...scanning line driving circuit, 7...data line driving circuit, 8...sealing member, 9...external terminal, 10, 10a, 10b, 10c, 10d...pixel electrode, 12...alignment film, 13, 131, 132, 133...cavity, 13a...first cavity portion, 13b...second cavity portion, 13c...third cavity portion, 20,30,40,50,60,76,82...interlayer insulating layer, 20a,20b...insulating layer, 20s...groove, 21,31,43,66,67,68,71,73,81...contact hole, 23,231,232,233,33,54,64...capacitor electrode, 23a...first light-shielding portion, 23b...second light-shielding portion, 23c...third light-shielding portion, 32...capacitor insulating layer, 41,53, 62, 63... relay layer, 42, 44, 61... conductive layer, 65... capacitance insulating layer, 70... semiconductor layer, 70a... LDD region, 70b... LDD region, 70c... channel region, 70d... drain region, 70s... source region, 72... gate insulating layer, 74... gate electrode, 80... light shielding layer, 90... base, 100... element substrate, 200... opposing substrate, 210... base, 220... insulating layer, 230...common electrode, 240...alignment film, 300, 300B, 300G, 300R...liquid crystal device, 1000...projection display device, 1001...illumination optical system, 1002...illumination device, 1003...projection optical system, 1004...screen, 1005...control unit, A1...display area, A2...peripheral area, E1...image signal, G1...scanning signal, IL...incident light, ML...modulated light, Lc...liquid crystal layer

Claims

1. a first pixel electrode and a second pixel electrode adjacent to each other; a first light-shielding layer provided between the first pixel electrode and the second pixel electrode in a plan view; an insulating layer provided between the first pixel electrode and the first light-shielding layer, and between the second pixel electrode and the first light-shielding layer; In a plan view, the insulating layer has a first cavity between the first pixel electrode and the second pixel electrode. Electro-optical device.

2. the insulating layer has a contact hole for electrically connecting the first pixel electrode and the first light-shielding layer; the contact hole overlaps with the first pixel electrode and the first light-shielding layer in a plan view and is separated from the first cavity; 2. The electro-optical device according to claim 1.

3. the insulating layer includes: a first insulating layer having a groove overlapping a gap between the first pixel electrode and the second pixel electrode in a plan view; and a second insulating layer provided in the groove and having a refractive index between a refractive index of the first pixel electrode and a refractive index of the first insulating layer; The first cavity is disposed within the groove.

2. The electro-optical device according to claim 1.

4. the first pixel electrode and the second pixel electrode are made of ITO, The first insulating layer is made of SiO 2 It consists of: The second insulating layer is made of SiON or SiNx.

4. The electro-optical device according to claim 3.

5. The aspect ratio of the groove is 2 or more.

4. The electro-optical device according to claim 3.

6. the first light-shielding layer has a first light-shielding portion, a second light-shielding portion protruding from the first light-shielding portion along a first direction, and a third light-shielding portion protruding from the first light-shielding portion along a second direction intersecting the first direction, the first light-shielding portion overlaps with the first cavity in a plan view, the second light-shielding portion overlaps with a second cavity adjacent to the first cavity in the first direction in a plan view, the third light-shielding portion overlaps with a third cavity adjacent to the first cavity in the second direction in a plan view; 2. The electro-optical device according to claim 1.

7. the first cavity has a first hollow portion, a second hollow portion protruding from the first hollow portion along a third direction, and a third hollow portion protruding from the first hollow portion along a fourth direction intersecting the third direction, the first cavity portion overlaps with the first light-shielding layer in a plan view, the second cavity portion overlaps with a second light-shielding layer adjacent to the first light-shielding layer in the third direction in a plan view, the third cavity portion overlaps with a third light-shielding layer adjacent to the first light-shielding layer in the fourth direction in a plan view; 2. The electro-optical device according to claim 1.

8. the insulating layer has a second cavity provided in a first direction of the first cavity and a third cavity provided in a second direction intersecting the first direction of the first cavity, the first light-shielding layer has a first light-shielding portion overlapping with the first cavity in a planar view, a second light-shielding portion protruding from the first light-shielding portion along the first direction and overlapping with the second cavity in a planar view, and a third light-shielding portion protruding from the first light-shielding portion along the second direction and overlapping with the third cavity in a planar view, the first cavity has a first hollow portion overlapping the first light-shielding layer in a plan view, a second hollow portion protruding from the first hollow portion along a third direction opposite to the first direction and overlapping with a second light-shielding layer adjacent to the first light-shielding layer in the third direction in a plan view, and a third hollow portion protruding from the first hollow portion along a fourth direction opposite to the second direction and overlapping with a third light-shielding layer adjacent to the first light-shielding layer in the fourth direction in a plan view.

2. The electro-optical device according to claim 1.

9. 9. An electronic device comprising the electro-optical device according to claim 1.

Images