Sensor device and manufacturing method thereof

Abstract

To suppress deterioration of electric characteristics of a transistor.SOLUTION: A method for manufacturing a sensor device includes: a process of forming a transistor on a substrate in a sensor area; a process of forming inter-layer insulation layers covering the transistor; a process of forming a first lower electrode electrically connected to the transistor on the interlayer insulation layers in the sensor area; a process of forming a plurality of first terminals respectively electrically connected to a plurality of electrodes other than an electrode electrically connected to the first lower electrode in the transistor on the interlayer insulation layers in a peripheral area; a process of forming a second terminal for polling processing on the interlayer insulation layers in the peripheral area; a process of forming a second lower electrode on the first lower electrode, the plurality of first terminals, and the second terminal; a process of forming a piezoelectric layer on the second lower electrode; a process of forming an upper electrode on the piezoelectric layer; and a process of applying a voltage between the second terminal and the upper electrode so as to execute polling processing of the piezoelectric layer.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to a sensor device and a manufacturing method thereof. [Background technology]

[0002] Sensors using organic piezoelectric materials such as P(VDF / TrFE) are currently in use. Organic piezoelectric materials can be applied by coating, can be produced in low-temperature processes, and can be easily made into films, so attempts are being made to apply them to flexible sensors for wearable devices and large-area sensors. Various applications are being considered for organic piezoelectric materials, such as biosensors for measuring pulse waves and myoelectric signals, tactile sensors, and pyroelectric sensors, making this a technology that is attracting attention.

[0003] Patent Document 1 proposes a pressure sensor that uses a thin film transistor (TFT) as a detection circuit for an organic piezoelectric element. Patent Document 2 realizes an organic piezoelectric sensor by bonding an organic piezoelectric film onto a TFT. In this way, by using a TFT in the detection circuit, two-dimensional sensing becomes possible by forming the element into an active matrix array. This is expected to further expand the range of applications, such as being able to capture the movement of the sensing target.

[0004] Poling is required to form a film of organic piezoelectric material on a TFT and have it function as a piezoelectric sensor. In poling, a high voltage (for example, an electric field of 100 V / μm or more) is applied to the organic piezoelectric film. However, the process of applying this high voltage causes electrical damage to the TFT, resulting in a significant decrease in the TFT's characteristics. Although the electrical damage to the TFT can be repaired by heat treatment, the spontaneous polarization of the organic piezoelectric film generated by the poling process disappears due to the heat, making it difficult to apply to piezoelectric sensors.

[0005] Another possible method is to perform a poling process on the organic piezoelectric film and then bond the organic piezoelectric film after the poling process onto the TFT with a conductive adhesive, anisotropic conductive film, etc. However, this manufacturing process makes it difficult to miniaturize the elements or increase the area of ​​the piezoelectric sensor. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2017-219336 A [Patent Document 2] Patent Publication No. 2021-27270 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention provides a sensor device capable of suppressing deterioration of the electrical characteristics of a transistor, and a method for manufacturing the same. [Means for solving the problem]

[0008] According to a first aspect of the present invention, there are provided a method for manufacturing a semiconductor device comprising the steps of: preparing a substrate having a sensor region in which unit sensors each including a piezoelectric element and a transistor are disposed, and a peripheral region in which a terminal portion is disposed; forming the transistor on the substrate in the sensor region; forming a first interlayer insulating layer in the sensor region and the peripheral region so as to cover the transistor; forming a first lower electrode electrically connected to the transistor on the first interlayer insulating layer in the sensor region; and forming a gate electrode, a source electrode, and a drain electrode of the transistor on the first interlayer insulating layer in the peripheral region, the first lower electrode being electrically connected to the transistor. A method for manufacturing a sensor device is provided, the method including the steps of: forming a plurality of first terminals each electrically connected to an electrode; forming a second terminal for a poling process on the first interlayer insulating layer in the peripheral region; forming a second lower electrode made of a material different from that of the first lower electrode on the first lower electrode, the plurality of first terminals, and the second terminal; forming a piezoelectric layer on the second lower electrode; forming an upper electrode on the piezoelectric layer; processing the upper electrode, the piezoelectric layer, and the second lower electrode to expose the second terminal; and applying a voltage between the second terminal and the upper electrode to perform a poling process on the piezoelectric layer.

[0009] According to a second aspect of the present invention, there is provided a method for manufacturing a sensor device according to the first aspect, further comprising a step of processing the upper electrode, the piezoelectric layer, and the second lower electrode to electrically isolate the second lower electrode, the plurality of first terminals, and the second terminal.

[0010] According to a third aspect of the present invention, there is provided a method for manufacturing a sensor device according to the second aspect, further comprising a step of forming a second interlayer insulating layer that covers the piezoelectric element consisting of the first lower electrode, the second lower electrode, the piezoelectric layer, and the upper electrode, and exposes the multiple first terminals.

[0011] According to a fourth aspect of the present invention, there is provided a method for manufacturing the sensor device according to the first aspect, wherein the second lower electrode is made of an organic conductive material.

[0012] According to a fifth aspect of the present invention, there is provided a method for manufacturing the sensor device according to the first aspect, wherein the first lower electrode is made of an inorganic conductive material.

[0013] According to a sixth aspect of the present invention, there is provided a method for manufacturing a sensor device according to the first aspect, wherein the piezoelectric layer is made of an organic piezoelectric material.

[0014] According to a seventh aspect of the present invention, there is provided a sensor device comprising: a substrate; a transistor provided on the substrate; an interlayer insulating layer provided on the transistor; and a piezoelectric element provided on the interlayer insulating layer and configured by sequentially stacking a first lower electrode, a second lower electrode, a piezoelectric layer, and an upper electrode, wherein the second lower electrode is made of a material different from that of the first lower electrode, the upper electrode, the piezoelectric layer, and the second lower electrode have the same planar shape, and the first lower electrode has a planar shape different from that of the upper electrode, the piezoelectric layer, and the second lower electrode. Effect of the Invention

[0015] According to the present invention, it is possible to provide a sensor device capable of suppressing deterioration of the electrical characteristics of a transistor, and a method for manufacturing the same. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a block diagram of a sensor device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram of the unit sensor shown in FIG. [Diagram 3] FIG. 3 is a circuit diagram showing another example of the configuration of the unit sensor. [Figure 4] FIG. 4 is a circuit diagram showing another example of the configuration of the unit sensor. [Diagram 5] FIG. 5 is a cross-sectional view of a unit sensor. [Figure 6] 6A to 6C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 7] 7A to 7C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 8] 8A to 8C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 9] 9A to 9C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 10] 10A to 10C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 11] 11A to 11C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 12] 12A to 12C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 13] 13A to 13C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 14] 14A to 14C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 15] 15A to 15C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 16] 16A to 16C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 17] 17A to 17C are cross-sectional views illustrating a manufacturing process of the sensor device. [Figure 18] 18A to 18C are cross-sectional views illustrating a manufacturing process of the sensor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, the embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. In addition, even when the same parts are shown between the drawings, the dimensional relationships and ratios of each may be different. In particular, the following embodiments are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not specified by the shape, structure, arrangement, etc. of the components. In the following description, elements having the same function and configuration are given the same reference numerals, and duplicated descriptions are omitted.

[0018] [1] Configuration of sensor device 1 Fig. 1 is a block diagram of a sensor device 1 according to an embodiment of the present invention. The X direction in Fig. 1 is a direction along one side of the sensor device 1, and the Y direction is a direction perpendicular to the X direction. The sensor device 1 includes a piezoelectric sensor array 2 and a terminal portion 3.

[0019] The piezoelectric sensor array 2 includes a plurality of unit sensors 10 arranged in a matrix. The piezoelectric sensor array 2 includes a plurality of gate lines GL each extending in the X direction and a plurality of signal lines SL each extending in the Y direction. The unit sensors 10 are arranged in the intersections of the gate lines GL and the signal lines SL. The unit sensors 10 are electrically connected to the corresponding gate lines GL and signal lines SL.

[0020] The multiple gate lines GL are connected to the terminal section 3 using multiple lead-out wirings. The multiple signal lines SL are connected to the terminal section 3 using multiple lead-out wirings. The terminal section 3 includes multiple terminals electrically connected to the multiple gate lines GL and the multiple signal lines SL, respectively. Using the terminal section 3, it is possible to supply voltages and signals to the multiple gate lines GL and the multiple signal lines SL. Furthermore, the terminal section 3 includes a polling process terminal 4. This is a terminal used during polling processing. Details of the polling process terminal 4 will be described later.

[0021] Each of the multiple unit sensors 10 includes a piezoelectric element 11 and a sensor circuit 12. The piezoelectric element 11 outputs a voltage in response to an applied pressure. The sensor circuit 12 is a detection circuit that detects the output voltage of the piezoelectric element 11, and operates in response to the output voltage of the piezoelectric element 11.

[0022] Fig. 2 is a circuit diagram of the unit sensor 10 shown in Fig. 1. Fig. 2 shows an example of the configuration of a back-gate type detection circuit. The sensor circuit 12 is composed of a transistor 12. Specifically, the transistor 12 is composed of a TFT (Thin Film Transistor), and is composed of an n-channel TFT.

[0023] The transistor 12 has a gate terminal G, a source terminal S, a drain terminal D, and a back gate terminal B. The gate terminal G of the transistor 12 is electrically connected to a gate line GL. The source terminal S of the transistor 12 is electrically connected to a terminal (ground terminal) to which a ground voltage Vss is supplied. The drain terminal D of the transistor 12 is electrically connected to a signal line SL. The back gate terminal B of the transistor 12 is electrically connected to one electrode of the piezoelectric element 11. The other electrode of the piezoelectric element 11 is electrically connected to a terminal to which a common voltage Vcom is supplied. The common voltage Vcom can be set appropriately.

[0024] The potential of the back gate terminal B of the transistor 12 changes according to the output voltage of the piezoelectric element 11. The threshold voltage of the transistor 12 changes according to the potential of the back gate terminal B. A predetermined selection signal is input to the gate line GL. The transistor 12 is controlled to be turned on / off according to the output voltage of the piezoelectric element 11. When the transistor 12 is turned on, a predetermined voltage is output to the signal line SL.

[0025] Fig. 3 is a circuit diagram showing another configuration example of the unit sensor 10. Fig. 3 shows a configuration example of a source-follower type detection circuit. The sensor circuit 12 is composed of a transistor 12, specifically, an n-channel TFT.

[0026] The transistor 12 has a gate terminal G, a source terminal S, and a drain terminal D. The gate terminal G of the transistor 12 is electrically connected to a gate line GL. The source terminal S of the transistor 12 is electrically connected to a signal line SL. The drain terminal D of the transistor 12 is electrically connected to one electrode of the piezoelectric element 11. The other electrode of the piezoelectric element 11 is electrically connected to a terminal to which a common voltage Vcom is supplied. The common voltage Vcom can be set appropriately. The transistor 12 outputs a predetermined voltage to the signal line SL in accordance with the output voltage of the piezoelectric element 11.

[0027] Fig. 4 is a circuit diagram showing another configuration example of the unit sensor 10. Fig. 4 shows a configuration example of a source-follower type detection circuit. The sensor circuit 12 is composed of two transistors 12-1 and 12-2. Specifically, the transistors 12-1 and 12-2 are composed of n-channel TFTs.

[0028] The transistors 12-1 and 12-2 have a gate terminal G, a source terminal S, and a drain terminal D. The gate terminal G of the transistor 12-1 is electrically connected to one electrode of the piezoelectric element 11. The other electrode of the piezoelectric element 11 is electrically connected to a terminal to which a common voltage Vcom is supplied. The common voltage Vcom can be set appropriately. The drain terminal D of the transistor 12-1 is electrically connected to a terminal (power supply terminal) to which a power supply voltage Vdd is supplied. The source terminal S of the transistor 12-1 is electrically connected to the drain terminal D of the transistor 12-2.

[0029] A gate terminal G of the transistor 12-2 is electrically connected to a gate line GL, and a source terminal S of the transistor 12-2 is electrically connected to a signal line SL.

[0030] The transistor 12-1 is controlled to be turned on / off in response to the output voltage of the piezoelectric element 11. The transistor 12-2 amplifies the source potential of the transistor 12-1 and outputs a predetermined voltage to the signal line SL.

[0031] 2 to 4, other sensors that operate in response to the output voltage of the piezoelectric element 11 may be used. In this embodiment, the back-gate type detection circuit shown in FIG. 2 will be described as an example of the unit sensor 10.

[0032] [2] Configuration of unit sensor 10 Next, a more detailed configuration of the unit sensor 10 will be described below.

[0033] The substrate 20 is made of an insulating material, such as a resin, for example, a polyurethane resin, a polyolefin resin, a polystyrene resin, or a polyester resin.

[0034] The transistor 12 is provided on the substrate 20. The transistor 12 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, ohmic contact layers 24 and 25, a source electrode 26, a drain electrode 27, and a backgate electrode 29.

[0035] A gate electrode 21 is provided on a substrate 20. For example, a molybdenum-niobium alloy (MoNb) is used as the gate electrode 21. A gate insulating film 22 is provided on the gate electrode 21. For example, a silicon nitride (SiN) is used as the gate insulating film 22.

[0036] A semiconductor layer 23 is provided on the gate insulating film 22 and above the gate electrode 21. The semiconductor layer 23 is made of, for example, amorphous silicon. Ohmic contact layers 24 and 25 are provided on the semiconductor layer 23 and spaced apart from each other. The ohmic contact layers 24 and 25 have the function of improving the electrical connection between the semiconductor layer and the electrodes. The ohmic contact layers 24 and 25 are n-type layers in which a high concentration of n-type impurities is introduced. + The ohmic contact layers 24 and 25 may be omitted.

[0037] A source electrode 26 is provided on the ohmic contact layer 24 so as to partially overlap the semiconductor layer 23. A drain electrode 27 is provided on the ohmic contact layer 25 so as to partially overlap the semiconductor layer 23. The source electrode 26 and the drain electrode 27 are made of, for example, a molybdenum-niobium alloy (MoNb).

[0038] An interlayer insulating layer 28 is provided on the source electrode 26 and the drain electrode 27. The interlayer insulating layer 28 may be made of, for example, silicon nitride (SiN).

[0039] A backgate electrode 29 is provided on the interlayer insulating layer 28. The backgate electrode 29 is disposed so as to overlap the semiconductor layer 23 in a plan view. The backgate electrode 29 is made of, for example, a transparent electrode, and is made of, for example, ITO (indium tin oxide).

[0040] An interlayer insulating layer 30 is provided on the back gate electrode 29. The interlayer insulating layer 30 may be made of, for example, silicon nitride (SiN).

[0041] A light-shielding layer 31 is provided on the interlayer insulating layer 30. The light-shielding layer 31 is configured to cover the entire semiconductor layer 23 in a plan view. The light-shielding layer 31 has a function of reducing light incident on the semiconductor layer 23. The light-shielding layer 31 is made of, for example, a molybdenum-niobium alloy (MoNb).

[0042] An interlayer insulating layer 32 is provided on the light-shielding layer 31. The interlayer insulating layer 32 may be made of, for example, silicon nitride (SiN).

[0043] The piezoelectric element 11 is provided on the interlayer insulating layer 32. The piezoelectric element 11 includes a first lower electrode 34, a second lower electrode 35, a piezoelectric layer 36, and an upper electrode 37. The planar shape of the piezoelectric element 11 is, for example, a rectangle.

[0044] A first lower electrode 34 is provided on the interlayer insulating layer 32. The first lower electrode 34 is made of, for example, an inorganic conductive material, for example, ITO.

[0045] A contact 33 that electrically connects the first lower electrode 34 and the backgate electrode 29 is provided in the interlayer insulating layers 30 and 32 .

[0046] A second lower electrode 35 is provided on the first lower electrode 34. The second lower electrode 35 is made of, for example, an organic conductive material, for example, PEDOT / PSS. PEDOT / PSS is a composite of poly(3,4-ethylenedioxythiophene) (PEDOT) and polystyrene sulfonate (PSS).

[0047] A piezoelectric layer 36 is provided on the second lower electrode 35. The piezoelectric layer 36 is made of, for example, an organic piezoelectric material. The piezoelectric layer 36 is made of, for example, a polymeric piezoelectric material such as polyvinylidene fluoride (PVDF), polyvinylidene fluoride / trifluoroethylene copolymer (P(VDF / TrFE)), or vinylidene cyanide / vinyl acetate copolymer (P(VDCN / VAc)). More preferably, the piezoelectric layer 36 is made of P(VDF / TrFE).

[0048] An upper electrode 37 is provided on the piezoelectric layer 36. The upper electrode 37 is made of, for example, a metal. For example, a molybdenum-niobium alloy (MoNb), chromium (Cr), or an alloy containing chromium (Cr) is used as the upper electrode 37.

[0049] An interlayer insulating layer 38 is provided on the upper electrode 37. The interlayer insulating layer 38 is made of, for example, an organic insulating material.

[0050] A wiring layer 39 electrically connected to the upper electrode 37 is provided on the interlayer insulating layer 38. The wiring layer 39 is a wiring layer for supplying a common voltage Vcom. The wiring layer 39 is extended to the terminal unit 3 and electrically connected to a terminal included in the terminal unit 3. The wiring layer 39 may be made of, for example, a molybdenum-niobium alloy (MoNb).

[0051] A protective layer 40 is provided on the wiring layer 39 and the interlayer insulating layer 38. The protective layer 40 is made of, for example, a resin.

[0052] [3] Manufacturing method of sensor device 1 Next, a manufacturing method of the sensor device 1 will be described with reference to the drawings. The sensor device 1 has an area where the piezoelectric sensor array 2 is arranged, and an area where the terminal parts 3 are arranged. The area where the piezoelectric sensor array 2 is arranged is called the sensor area 2A, and the area where the terminal parts 3 are arranged is called the peripheral area 3A. The sensor area 2A and the peripheral area 3A are provided on the same substrate 20. The drawings explaining the manufacturing process shown below show a part of the sensor area 2A and a part of the peripheral area 3A.

[0053] Fig. 6 is a cross-sectional view illustrating a manufacturing process of the sensor device 1. One unit sensor 10 is shown in the sensor area 2A. The separated cross-sectional portion on the right side of Fig. 6 shows the area of ​​the peripheral area 3A where the polling process terminals 4 are arranged.

[0054] As shown in Fig. 6, a transistor 12 is formed on a substrate 20. The configuration of the transistor 12 is the same as that of Fig. 5. The transistor 12 (specifically, the laminated structure from the gate electrode 21 to the light-shielding layer 31) can be formed using a known manufacturing method.

[0055] On the substrate 20, a lead-out wiring 41 is formed, which is electrically connected to the gate electrode 21 and extends to the terminal portion 3. The lead-out wiring 41 is formed simultaneously with the gate electrode 21. On the gate insulating film 22, a lead-out wiring 42 is formed, which is electrically connected to the drain electrode 27 and extends to the terminal portion 3. The lead-out wiring 42 is formed simultaneously with the drain electrode 27. Although not shown in the figure, on the gate insulating film 22, a lead-out wiring is formed, which is electrically connected to the source electrode 26 and extends to the terminal portion 3. This lead-out wiring is formed simultaneously with the source electrode 26.

[0056] Next, an interlayer insulating layer 32 that covers the transistor 12 is formed using a CVD (Chemical Vapor Deposition) method.

[0057] Next, openings 33A, 43A, and 44A are formed in the interlayer insulating layers 30 and 32 by photolithography. The openings 43A and 44A are arranged in the peripheral region 3A. The opening 33A exposes a part of the back gate electrode 29. The opening 43A exposes a part of the lead-out wiring 41. The opening 44A exposes a part of the lead-out wiring 42. Although not shown, an opening is also formed to expose a part of the lead-out wiring for the source electrode 26. In the example of FIG. 6, a contact portion formed simultaneously with the drain electrode 27 and a contact portion formed simultaneously with the back gate electrode 29 are formed in the lower part of the opening 43A. A contact portion formed simultaneously with the back gate electrode 29 is formed in the lower part of the opening 44A.

[0058] 7, the first lower electrode 34, the terminal for poling process 4, the terminals 45, 46, and the contacts 33, 43, 44 are formed on the interlayer insulating layer 32 by sputtering and photolithography. The terminal for poling process 4 and the terminals 45, 46 are disposed in the peripheral region 3A. The first lower electrode 34, the terminal for poling process 4, the terminals 45, 46, and the contacts 33, 43, 44 are made of the same material (e.g., ITO).

[0059] The contact 33 is formed in the opening 33A. The first lower electrode 34 is electrically connected to the back gate electrode 29 via the contact 33. The contact 43 is formed in the opening 43A. The terminal 45 is electrically connected to the lead-out wiring 41 via the contact 43. The contact 44 is formed in the opening 44A. The terminal 46 is electrically connected to the lead-out wiring 42 via the contact 44. Although not shown, a contact electrically connected to the lead-out wiring for the source electrode 26 and a ground terminal are also simultaneously formed in the process of FIG. 7.

[0060] The terminal 45 is electrically connected to the gate electrode 21. The terminal 45 is referred to as the first terminal. The terminal 46 is electrically connected to the drain electrode 27. The terminal 46 is referred to as the first terminal. A terminal electrically connected to the source electrode 26 is provided at the same level as the terminals 45, 46. The terminal electrically connected to the source electrode 26 is referred to as the first terminal. In other words, the multiple terminals electrically connected to the multiple electrodes of the transistor 12 other than the electrode electrically connected to the first lower electrode 34 (in this embodiment, the backgate electrode 29) are referred to as the first terminals. The poling process terminal 4 is referred to as the second terminal.

[0061] 8, an organic conductive layer 35A is formed on the interlayer insulating layer 32, the first lower electrode 34, the terminal for poling process 4, and the terminals 45, 46 by using a screen printing method. The organic conductive layer 35A is formed in the sensor region 2A and the peripheral region 3A. The organic conductive layer 35A is made of the same material (e.g., PEDOT / PSS) as the second lower electrode 35 of the piezoelectric element 11, and is a conductive layer that will become the second lower electrode 35 in a later process. The first lower electrode 34, the terminal for poling process 4, and the terminals 45, 46 are electrically connected by the organic conductive layer 35A. Although not shown, the source electrode 26 and the ground terminal are also electrically connected to the organic conductive layer 35A. That is, all electrodes (gate electrode, source electrode, drain electrode, and back gate electrode) of the transistor 12 are electrically connected to the organic conductive layer 35A.

[0062] 9, a piezoelectric layer 36A is formed on the organic conductive layer 35A by screen printing. The piezoelectric layer 36A is formed in the sensor region 2A and the peripheral region 3A. The piezoelectric layer 36A is made of the same material (e.g., P(VDF / TrFE)) as the piezoelectric layer 36 of the piezoelectric element 11, and will become the piezoelectric layer 36 in a later process.

[0063] 10, a conductive layer 37A is formed on the piezoelectric layer 36A by sputtering. The conductive layer 37A is formed in the sensor region 2A and the peripheral region 3A. The conductive layer 37A is made of the same material (e.g., MoNb) as the upper electrode 37 of the piezoelectric element 11, and will become the upper electrode 37 in a later process.

[0064] Subsequently, as shown in FIG. 11, the portion of the conductive layer 37A above the terminals for poling process 4 is removed by photolithography and etching.

[0065] 12, a hard mask 47 is used to protect areas other than the terminals 4 for poling treatment, and the piezoelectric layer 36A and the organic conductive layer 35A are ashed. This process exposes the terminals 4 for poling treatment. Instead of the hard mask 47, a resist mask may be formed on the conductive layer 37A. It is desirable to set the planar distance between the terminals 4 for poling treatment and the conductive layer 37A to 300 μm or more. This makes it possible to prevent a short circuit between the terminals 4 for poling treatment and the conductive layer 37A during the poling treatment described below.

[0066] Next, as shown in FIG. 13, a power source 48 is connected between the terminal 4 for poling and the conductive layer 37A, and an AC voltage is applied between the terminal 4 for poling and the conductive layer 37A. Then, a poling process is performed on the piezoelectric layer 36A. The poling process (also called a polarization process) is a process in which an electric field is applied from the outside to cause spontaneous polarization in a material. In the poling process, an AC voltage is applied so that the electric field is 100 V / μm or more. A DC voltage may be used for the poling process. The entire piezoelectric layer 36A is sandwiched between the organic conductive layer 35A and the conductive layer 37A, and the conductive layer 37A is electrically connected to the terminal 4 for poling. Therefore, a voltage can be applied to the entire piezoelectric layer 36A. By performing the poling process on the piezoelectric layer 36A, spontaneous polarization occurs in the piezoelectric layer 36A, and a large piezoelectricity is generated.

[0067] Here, the organic conductive layer 35A is electrically connected to the first lower electrode 34 and the terminals 45 and 46. As described above, the source electrode 26 and the ground terminal are also electrically connected to the organic conductive layer 35A. FIG. 13 shows a simplified view of the state in which the source electrode 26 and the organic conductive layer 35A are electrically connected. That is, the gate electrode, source electrode, drain electrode, and back gate electrode of the transistor 12 are short-circuited. Therefore, during the poling process, the gate electrode, source electrode, drain electrode, and back gate electrode of the transistor 12 are set to the same potential. This makes it possible to suppress the electrical influence of the high electric field of the poling process on the transistor 12.

[0068] When the transistor 12 does not have a back gate electrode (for example, the sensor circuit 12 in FIG. 3), the gate electrode, source electrode, and drain electrode of the transistor 12 are electrically connected to the organic conductive layer 35A. Specifically, of the gate electrode, source electrode, and drain electrode of the transistor 12, two electrodes other than the electrode electrically connected to the first lower electrode 34 of the piezoelectric element 11 are extended onto the interlayer insulating layer 32 in the peripheral region 3A, and two terminals electrically connected to the two electrodes are electrically connected to the organic conductive layer 35A.

[0069] Subsequently, as shown in FIG. 14, the conductive layer 37A is processed by photolithography and etching to form the upper electrode 37 of the piezoelectric element 11.

[0070] 15, the piezoelectric layer 36A and the organic conductive layer 35A are ashed using the upper electrode 37 as a mask. This forms the piezoelectric layer 36 of the piezoelectric element 11 and the second lower electrode 35. Furthermore, the gate electrode, source electrode, drain electrode, and back gate electrode of the transistor 12, the second lower electrode 35, and the poling process terminal 4 are electrically isolated from one another. Furthermore, in this process, the multiple piezoelectric elements 11 are electrically isolated from one another.

[0071] Here, the upper electrode 37 is used as a mask to process the piezoelectric layer 36 and the second lower electrode 35, so the upper electrode 37, the piezoelectric layer 36, and the second lower electrode 35 have the same planar shape. The first lower electrode 34 is processed in a process different from the process of processing the upper electrode 37, the piezoelectric layer 36, and the second lower electrode 35, so the planar shape of the first lower electrode 34 is different from the planar shapes of the upper electrode 37, the piezoelectric layer 36, and the second lower electrode 35. Specifically, the area of ​​the first lower electrode 34 is set to be larger than the areas of the upper electrode 37, the piezoelectric layer 36, and the second lower electrode 35.

[0072] 16, an interlayer insulating layer 38 covering the piezoelectric elements 11 and the poling process terminals 4 is formed by photolithography and etching. The interlayer insulating layer 38 is formed in the sensor region 2A and in a region of the peripheral region 3A where the poling process terminals 4 are disposed. Furthermore, an opening 38A exposing a part of the upper electrode 37 is formed in the interlayer insulating layer 38.

[0073] Subsequently, as shown in FIG. 17, a wiring layer 39 electrically connected to the upper electrode 37 is formed on the interlayer insulating layer 38 by using a sputtering method and a photolithography method.

[0074] 18, a protective layer 40 is formed by coating on the wiring layer 39 and the interlayer insulating layer 38. In this manner, the sensor device 1 according to this embodiment is manufactured.

[0075] [4] Effects of the embodiment According to this embodiment, during the poling process, the gate electrode, source electrode, drain electrode, and back gate electrode of the transistor 12 are short-circuited with the terminal 4 for poling process. In this state, a high voltage is applied between the terminal 4 for poling process and the conductive layer 37A (upper electrode 37). Therefore, during the poling process, the gate electrode, source electrode, drain electrode, and back gate electrode of the transistor 12 and the terminal 4 for poling process are set to the same potential. This makes it possible to suppress the electrical influence on the transistor 12 due to the high electric field of the poling process. Also, it is possible to suppress the deterioration of the electrical characteristics of the transistor 12.

[0076] It is also possible to perform poling processing on all the piezoelectric layers of the piezoelectric sensor array 2 at once.

[0077] Also, it is possible to form a unit sensor 10 in which a piezoelectric element 11 is stacked on a TFT as a transistor 12. Also, it is possible to form a plurality of unit sensors 10 arranged in a matrix. Furthermore, according to the manufacturing method of this embodiment, it is possible to miniaturize the unit sensors 10 and to increase the area of ​​the piezoelectric sensor array 2.

[0078] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made in the implementation stage without departing from the gist of the invention. In addition, the embodiments may be implemented in appropriate combination, and in that case, the combined effect can be obtained. Furthermore, the above-mentioned embodiment includes various inventions, and various inventions can be extracted by combinations selected from the multiple components disclosed. For example, if the problem can be solved and the effect can be obtained even if some components are deleted from all the components shown in the embodiment, the configuration from which the components are deleted can be extracted as an invention. [Explanation of symbols]

[0079] 1...sensor device, 2...piezoelectric sensor array, 2A...sensor area, 3...terminal portion, 3A...peripheral area, 4...terminal for poling process, 10...unit sensor, 11...piezoelectric element, 12...transistor, 20...substrate, 21...gate electrode, 22...gate insulating film, 23...semiconductor layer, 24, 25...ohmic contact layer, 26...source electrode, 27...drain electrode, 28, 30, 32, 38...interlayer insulating layer, 29...backgate electrode, 31...light-shielding layer, 33...contact, 33A...opening, 34...first lower electrode, 35...second lower electrode, 36...piezoelectric layer, 37...upper electrode, 38A...opening, 39...wiring layer, 40...protective layer, 41, 42...lead wiring, 43, 44...contact, 43A, 44A...opening, 45, 46...terminal, 47...hard mask, 48...power supply.

Claims

1. preparing a substrate having a sensor region in which unit sensors including a piezoelectric element and a transistor are arranged, and a peripheral region in which terminal portions are arranged; forming the transistor on the substrate in the sensor region; forming a first interlayer insulating layer in the sensor region and the peripheral region so as to cover the transistor; forming a first lower electrode on the first interlayer insulating layer in the sensor region, the first lower electrode being electrically connected to the transistor; forming a plurality of first terminals on the first interlayer insulating layer in the peripheral region, the first terminals being electrically connected to a plurality of electrodes among a gate electrode, a source electrode, and a drain electrode of the transistor other than the electrode electrically connected to the first lower electrode; forming a second terminal for a poling process on the first interlayer insulating layer in the peripheral region; forming a second lower electrode made of a material different from that of the first lower electrode on the first lower electrode, the plurality of first terminals, and the second terminal; forming a piezoelectric layer on the second lower electrode; forming an upper electrode on the piezoelectric layer; processing the upper electrode, the piezoelectric layer, and the second lower electrode to expose the second terminal; applying a voltage between the second terminal and the upper electrode to perform a poling process on the piezoelectric layer; A method for manufacturing a sensor device comprising the steps of:

2. The method further includes processing the upper electrode, the piezoelectric layer, and the second lower electrode to electrically isolate the second lower electrode, the first terminals, and the second terminal. A method for manufacturing the sensor device according to claim 1 .

3. The method further includes forming a second interlayer insulating layer that covers the piezoelectric element including the first lower electrode, the second lower electrode, the piezoelectric layer, and the upper electrode and exposes the first terminals. A method for manufacturing the sensor device according to claim 2.

4. The second lower electrode is made of an organic conductive material. A method for manufacturing the sensor device according to claim 1 .

5. The first lower electrode is made of an inorganic conductive material. A method for manufacturing the sensor device according to claim 1 .

6. The piezoelectric layer is made of an organic piezoelectric material. A method for manufacturing the sensor device according to claim 1 .

7. A substrate; A transistor provided on the substrate; an interlayer insulating layer provided on the transistor; a piezoelectric element provided on the interlayer insulating layer and configured by sequentially stacking a first lower electrode, a second lower electrode, a piezoelectric layer, and an upper electrode; Equipped with the second lower electrode is made of a material different from that of the first lower electrode, the upper electrode, the piezoelectric layer, and the second lower electrode have the same planar shape; The first lower electrode has a planar shape different from the planar shapes of the upper electrode, the piezoelectric layer, and the second lower electrode. Sensor device.

Images