Error correction management of memory system

Abstract

To provide a system, a method and a device including a computer readable medium for managing error correction of a memory system.SOLUTION: A memory system 100 includes a memory, and a device controller connected to the memory. The device controller reads out data from a data page of the memory, subjects the read-out data to an error correction code (ECC) test of a first phase on the basis of first ECC data associated with the data, and subjects a part of the read out data to an ECC test of a second phase on the basis of second ECC data, in response to determination that the read-out data does not pass the ECC test of the first phase. The first ECC data is stored in the data page together with the data. The second ECC data is associated with a part of the data corresponding to a part of the read-out data, and is stored in a redundant page different from the data page.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present disclosure is directed to memory systems, for example error correction in memory systems. [Background technology]

[0002] Once the memory cells of a data storage device (e.g., a memory system) have been programmed, data can be read from the memory cells by comparing the cell threshold voltage with one or more read voltages to sense the programming state of each memory cell. However, the cell threshold voltage may change due to one or more factors, such as read disturb or data retention, which may cause the sensed programming state to differ from the written programming state, resulting in a fail bit in the data read output. Summary of the Invention

[0003] This disclosure describes systems and techniques for managing error correction in memory systems, such as non-volatile memory (NVM) systems.

[0004] One aspect of the disclosure focuses on a memory system. The system includes a memory and a memory controller coupled to the memory and configured to: read data from a data page of the memory; perform a first phase of error correction code (ECC) testing on the read data based on first ECC data associated with the data, the first ECC data being stored with the data in the data page; and, in response to determining that the read data does not pass the first phase of ECC testing, perform a second phase of ECC testing on a portion of the read data based on second ECC data, where the second ECC data is associated with a portion of the data corresponding to the portion of the read data and is stored in a redundant page different from the data page. In some implementations, a size of the second ECC data is the same as a size of the first ECC data.

[0005] In some implementations, the data includes multiple portions including a portion of the data as a first portion of the data and a second portion of the data, and the read data includes multiple portions of the read data including the portion of the data read as the first portion of the read data and a second portion of the read data corresponding to the second portion of the data. The memory controller is configured to perform a first phase ECC test on the second portion of the read data and the corrected data of the first portion of the read data based on the first ECC data in response to determining that the first portion of the read data passes the second phase ECC test.

[0006] In some implementations, the memory controller is configured to output the corrected data of the second portion of the read data and the corrected data of the first portion of the read data as read data in response to determining that the second portion of the read data and the corrected data of the first portion of the read data pass the first phase ECC test.

[0007] In some implementations, the memory controller includes a redundant array of independent disks (RAID) circuit, and the memory controller is configured to perform error correction on the read data using the RAID circuit in response to determining that a portion of the read data does not pass the second phase ECC test. The RAID circuit may be configured to store redundant data for the data in one or more other memory devices external to the memory.

[0008] In some implementations, the memory controller includes an ECC decoder, and the memory controller is configured to perform the first phase ECC testing and the second phase ECC testing with the ECC decoder.

[0009] In some implementations, the memory controller is configured to, in response to determining that the read data does not pass the first phase ECC test, read second ECC data from the redundant page; and perform an ECC decode operation using the second ECC data on a combination of the portion of the read data and the plurality of predetermined values, where a total size of the portion of the read data and the plurality of predetermined values ​​is identical to a size of the read data.

[0010] In some implementations, the memory controller includes an ECC encoder configured to generate first ECC data based on the data; and generate second ECC data based on a portion of the data and a plurality of predetermined values.

[0011] In some implementations, the memory controller is configured to extract a portion of the data from the data page and store the portion of the data in a cache page; fill, via a processing unit or specific circuitry, the cache page with a plurality of predetermined values; and encode the portion of the data and the plurality of predetermined values ​​to generate the second ECC data.

[0012] In some implementations, the plurality of predetermined values ​​includes at least one of 0 or 1. In some implementations, the first ECC data includes ECC check bits generated for the data using an ECC encoder. In some implementations, a size of the portion of the data is half the size of the data.

[0013] In some implementations, the memory controller is configured to perform an ECC decoding operation on the read data based on the first ECC data; determine whether a number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold; determine that the read data passes the first phase ECC test if the number of error bits is less than the predetermined threshold; and determine that the read data does not pass the first phase ECC test if the number of error bits is the same as or greater than the predetermined threshold.

[0014] In some implementations, the memory controller is configured to perform an ECC decoding operation on the portion of the read data based on the second ECC data; determine whether a number of error bits in the portion of the read data after the ECC decoding operation is less than a predetermined threshold; determine that the portion of the read data passes the second phase ECC test if the number of error bits is less than the predetermined threshold; and determine that the portion of the read data does not pass the second phase ECC test if the number of error bits is the same as or greater than the predetermined threshold.

[0015] In some implementations, the redundant page includes ECC parity data associated with the second ECC data, and the memory controller is configured to perform an ECC decode operation on the second ECC data based on the ECC parity data to generate corrected second ECC data; and perform a second phase ECC test on a portion of the read data based on the corrected second ECC data.

[0016] In some implementations, the memory includes a plurality of data pages including the data page as a first data page, and the redundant page is different from each of the plurality of data pages, and the redundant page includes a plurality of second ECC data associated with a particular portion of page data in the plurality of data pages, the total size of the plurality of second ECC data not exceeding the size of the data.

[0017] In some implementations, a size of the page data of the particular portion in each of the plurality of data pages is identical, and the memory controller is configured to generate, for each of the plurality of data pages, respective first ECC data based on the page data in the data page and store the respective first ECC data in the data page; generate respective second ECC data based on the particular portion of the page data in the data page and the plurality of predetermined values, and store the respective second ECC data for the data page in the redundant page. A total size of the page data of the particular portion in the data page and the plurality of predetermined values ​​may be identical to the size of the page data in the data page.

[0018] In some implementations, the memory includes one or more memory chips each having a plurality of blocks, and the plurality of data pages are in a same block of one of the one or more memory chips, and the redundant page is in the same or a different block of said one of the one or more memory chips, or at least two of the plurality of data pages are in different blocks of one of the one or more memory chips, and the redundant page is in said one of the one or more memory chips, or a different one of the one or more memory chips, or at least two of the plurality of data pages are in different memory chips of the memory, and the redundant page is in the memory.

[0019] In some implementations, the memory system includes a first memory device including a memory and a memory controller; and a second memory device, the redundant page including a particular second ECC data associated with a particular data page in the second memory device.

[0020] In some implementations, the memory controller is configured to generate respective first ECC data based on respective page data of two or more data pages of the plurality of data pages and store the respective first ECC data in each of the two or more data pages; generate composite data based on particular portions of the two or more data pages, wherein a size of the composite data is identical to a size of each of the particular portions of the two or more data pages; generate corresponding second ECC data based on the composite data and a plurality of predetermined values, and store the corresponding second ECC data for the two or more data pages in a redundant page.

[0021] In some implementations, the memory controller is configured to generate the composite data by applying an XOR logical operation to certain portions of two or more data pages.

[0022] In some implementations, the memory controller is configured to: read first page data from a first data page of the two or more data pages; perform a first phase ECC test on the read first page data based on the first ECC data of each of the first data pages; in response to determining that the read first page data does not pass the first phase ECC test, read other page data from one or more other data pages of the two or more data pages; read corresponding second ECC data for the two or more data pages from a redundant page; and perform a second phase ECC test on the first data portion of the read first page data and the plurality of predetermined values ​​based on the corresponding second ECC data and the other page data from the one or more other data pages.

[0023] Another aspect of the disclosure is directed to a memory system including a memory and a memory controller coupled to the memory configured to generate first error correcting code (ECC) data based on data in a data page of the memory, store the first ECC data in the data page with the data, generate second ECC data based on a portion of the data in the data page, and store the second ECC data for the data page in a redundant page distinct from the data page.

[0024] In some implementations, the memory controller is configured to generate the second ECC data based on a portion of the data in the data page and the plurality of predetermined values. A total size of the portion of the data in the data page and the plurality of predetermined values ​​may be the same as a size of the data in the data page. A size of the second ECC data may be the same as a size of the first ECC data.

[0025] In some implementations, the memory controller is configured to read data from a data page of the memory; perform a first phase ECC test on the read data based on first ECC data in the data page; and, in response to determining that the read data does not pass the first phase ECC test, read second ECC data from a redundant page and perform a second phase ECC test on a portion of the read data corresponding to the portion of the data based on the second ECC data.

[0026] In some implementations, the memory includes a plurality of data pages including a data page, the redundant page being different from each of the plurality of data pages, and the memory controller is configured to generate respective first ECC data on respective page data of two or more data pages of the plurality of data pages and store the respective first ECC data together with the page data in each of the two or more data pages; generate composite data based on a particular portion of the page data of the two or more data pages, a size of the composite data being identical to a size of each of the particular portions of the page data of the two or more data pages; generate corresponding second ECC data based on the composite data, and store the corresponding second ECC data for the two or more data pages in the redundant page.

[0027] In some implementations, the memory controller is configured to generate the corresponding second ECC data based on the composite data and the plurality of predetermined values. In some implementations, the memory controller is configured to generate the composite data by applying an XOR logical operation to certain portions of the page data of the two or more data pages.

[0028] In some implementations, the memory controller is configured to: read first page data from a first data page of the two or more data pages; perform a first phase ECC test on the read first page data based on the first ECC data of each of the first data pages; in response to determining that the read first page data does not pass the first phase ECC test, read one or more other specific portions of the page data from one or more other data pages of the two or more data pages; read corresponding second ECC data for the two or more data pages from a redundant page; and perform a second phase ECC test on the first data portion of the read first page data and a plurality of predetermined values ​​based on the corresponding second ECC data and the one or more other specific portions of the page data from the one or more other data pages.

[0029] In some implementations, the memory controller is configured to perform a second phase ECC test on the first data portion of the read first page data and the plurality of predetermined values ​​based on corresponding second ECC data and one or more other specific portions of page data from one or more other data pages.

[0030] Another aspect of the disclosure is directed to a method that includes reading data from a data page of a memory; performing a first phase error correcting code (ECC) test on the read data based on first ECC data associated with the data, the first ECC data being stored in the data page with the data; and, in response to determining that the read data does not pass the first phase ECC test, performing a second phase ECC test on a portion of the read data based on second ECC data, where the second ECC data is associated with a portion of the data corresponding to the portion of the read data and is stored in a redundant page distinct from the data page.

[0031] In some implementations, the method further includes generating first ECC data based on the data in the data page and storing the first ECC data in the data page; and generating second ECC data based on a portion of the data in the data page and the plurality of predetermined values ​​and storing the second ECC data for the data page in the redundant page. A total size of the portion of the data in the data page and the plurality of predetermined values ​​may be the same as a size of the data in the data page.

[0032] Implementations of the above techniques include methods, systems, computer program products, and computer readable media. In one example, the method may be performed by a memory system including a memory and a memory controller coupled to the memory, and the method may include the above-mentioned operations performed by the memory controller and the memory, such as operations for managing error correction of the memory system. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above-mentioned operations. One such computer-readable medium stores instructions configured, when executed by the one or more processors, to cause the one or more processors to perform the above-mentioned operations.

[0033] The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0034] [Figure 1A] FIG. 1 is a schematic diagram of an example system with error correction capabilities.

[0035] [Figure 1B] FIG. 1 is a schematic diagram of an example memory chip.

[0036] [Diagram 2] 1 illustrates an example of generating multi-phase ECC data for error correction in a memory system.

[0037] [Diagram 3] 2 illustrates another example of generating multi-phase ECC data for error correction in a memory system.

[0038] [Figure 4A] 1 is a flowchart of an example process for generating multi-phase ECC data for error correction in a memory system.

[0039] [Figure 4B] 1 is a flow chart of an example process for managing error correction in a memory system.

[0040] Like reference numbers and designations in the various drawings indicate like elements. It should also be understood that the various exemplary implementations shown in the figures are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Frequent read operations may cause data stored in the memory to experience read disturbs, which may increase the threshold voltage due to the state of memory cells in the memory, e.g., an erased state and one or more programmed states. The read disturbs may cause fail bits (or erroneous bits) in the read output of the data. An error correction code (ECC) decoder may be configured to decode the data read from the memory to detect and correct any bit errors that may be present in the data up to the error correction capability of the ECC scheme.

[0042] RAID (Redundant Array of Independent Disks) is a data storage virtualization technology that combines multiple physical disk drive devices into one or more logical units for data redundancy, performance improvement, or both. Data is allocated to different disk drives in one of several schemes called RAID levels, depending on the level of redundancy and performance required. Different schemes or data allocation layouts are named by the word "RAID" followed by a number, for example, RAID0, RAID1, RAID2, ..., RAID9, or higher. Each scheme or RAID level provides a different balance between the primary goals of reliability, availability, performance, and capacity. RAID levels higher than RAID0 can provide protection against unrecoverable sector read errors as well as protection against complete physical drive failure.

[0043] Unlike ECC data, which is stored in the same page as user data, RAID redundancy data is stored on different physical disk drive devices. Thus, RAID can provide page-to-page or disk-to-disk RAID protection and recover ECC uncorrectable data as additional protection. However, page-to-page or disk-to-disk RAID protection requires reading every page for failed data, which takes much longer to recover the data than ECC.

[0044] Implementations of the present disclosure provide systems, methods, and techniques for managing error correction in a memory system, for example, using multi-phase ECC protection (or multi-phase ECC error correction). The techniques can enhance the ECC protection (or error correction) capabilities to recover data that is uncorrectable by standard ECC schemes. The techniques can achieve similar RAID functionality using the same ECC hardware (e.g., ECC encoder and decoder) without RAID circuitry and / or without modifying existing hardware configurations. The techniques can also be achieved using RAID circuitry or techniques for additional / further enhancement of data correction and protection.

[0045] In some implementations, for example, as discussed in further detail with respect to FIG. 2 and FIG. 4A, for a first phase ECC protection, an ECC encoder encodes data in each data page of the memory to generate first ECC data that is stored with the data in the data page; for a second phase ECC protection, the ECC encoder encodes a portion of the data (e.g., half of the data) with a predetermined value (e.g., 1 or 0) to generate second ECC data that is stored separately from the data in a redundant page. The redundant page can store the second ECC data for a portion of the data from multiple pages. Because the predetermined value is fixed, the second ECC data is only used to correct a portion of the data (e.g., half of the data), and therefore the second ECC data can provide a higher ECC capability than the first ECC data. As an example, if the portion of the data is half of the data and the second ECC data includes ECC check bits of the same length as the first ECC data, the second ECC data can have twice the ECC capability than the first ECC data.

[0046] In a read operation, for example, as discussed in further detail with respect to FIG. 4B, if the first ECC data in the data page cannot correct the data, for example, if the first phase ECC protection fails, the controller can retrieve (or extract) the second ECC data for the data page from the redundant page. Since the second ECC data has a higher ECC capability, the second ECC data can be used to correct a portion of the data. After the portion of the data is corrected, the corrected portion of the data can replace the portion of the data in the data, and then the first ECC data can be used to correct the remaining portion of the data. Since the size of the remaining portion of the data is smaller than the data, the first ECC data can have a higher ECC capability for the remaining portion of the data. Thus, the second phase ECC protection can recover the uncorrectable data of the first phase ECC protection. In the second phase ECC protection, only two pages (the data page and the redundant page) are read to implement the ECC protection. Compared to RAID techniques using inter-page RAID protection that require reading all pages (e.g., 8-128 pages) if the first phase ECC protection fails, the approach implemented herein provides faster speeds and faster response.

[0047] In some implementations, the second phase ECC protection utilizes RAID techniques to further improve performance. For example, when a large number of data pages need to be protected with a small number of available redundant pages, as discussed in further detail with respect to FIG. 3, the same second ECC data can be used to protect portions of the multiple data pages. The portions of the multiple data pages can be used to generate composite data using one or more logical / mathematical functions, such as XOR. The composite data can have the same size as each portion (e.g., half of a data page). The composite data can then be encoded to generate second ECC data that is stored in a redundant page. In that way, the redundant page can provide second phase ECC protection for more data pages. In a read operation, the multiple data pages for generating the composite data and the second ECC data are read for second phase ECC protection of any one of the multiple data pages.

[0048] This technique can be applied to different scenarios. In some implementations, the multiple data pages are in the same block of a memory chip, and the redundant page storing the second ECC data for the multiple data pages can be in the same block or a different block of the same memory chip. In some implementations, at least two of the multiple data pages are in different blocks of a memory chip, and the redundant page can be in a block of the memory chip or a different memory chip. In some implementations, at least two of the multiple data pages are in different memory chips of a memory device, and the redundant page can be in a memory chip of the memory device or a different memory device. In some implementations, at least two of the multiple data pages are in different memory devices, such as solid-state drives (SSDs) of a memory system, and the redundant page can be in one of the different memory devices or another memory device of the memory system. These techniques can be applied individually or in combination with RAID technology.

[0049] The technique can be applied to various types of semiconductor devices, volatile memory devices, or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, phase change memory (PCM) such as resistive random access memory (RRAM), phase change random access memory (PCRAM), spin transfer torque (STT) magnetoresistive random access memory (MRAM), among others. The technique can also be applied to charge trapping memory devices, such as silicon / oxide / nitride / oxide / silicon (SONOS) memory devices and floating gate memory devices. The technique can be applied to two-dimensional (2D) or three-dimensional (3D) memory devices. The technique can be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices such as two-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or penta-level cell (PLC) devices. Additionally or alternatively, the technique may be applied to various types of devices and systems, such as Secure Digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSD), embedded systems, among others.

[0050] 1A illustrates an example of a system 100 with error correction capabilities. System 100 includes a device 110 and a host device 120. Host device 120 includes a host controller 122, which may include at least one processor and at least one memory coupled to the at least one processor and storing programming instructions that the at least one processor executes to perform one or more corresponding operations.

[0051] In some implementations, device 110 is a storage device. For example, device 110 can be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid-state drive (SSD), or some other suitable storage. In some implementations, device 110 is a smartwatch, a digital camera, or a media player. In some implementations, device 110 is a client device coupled to host device 120. For example, device 110 is an SD card in a digital camera or media player that is host device 120.

[0052] In some implementations, the host device 120 is coupled to one or more devices 110 (e.g., SSDs). Each device 110 can include a device controller 112 and a memory 150. The memory 150 can include one or more memory chips 152, each coupled to a device controller 112. FIG. 1B illustrates an example configuration of a memory chip 152 that includes multiple blocks 154 (e.g., block 0, block 1, ..., block m-1, and block m). Each block can include the same number of pages 156 (e.g., page 0, page 1, ..., page n). Each page has a unique number within the block. Data is stored in the pages of a block according to the order of the unique numbers of the pages within the block. Each page can be read or written separately, and the pages within a block can be erased together.

[0053] The device controller 112 is a general-purpose microprocessor or an application-specific microcontroller. In some implementations, the device controller 112 is a memory controller for the device 110. In the following sections, various techniques are described based on an implementation in which the device controller 112 is a memory controller. However, the techniques described in the following sections are also applicable in implementations in which the device controller 112 is another type of controller that is different from a memory controller.

[0054] In some implementations, the device controller 112 includes a processor 113 and an embedded memory 114. The processor 113 is configured to execute instructions and process data. These instructions include firmware instructions and / or other program instructions stored in a secondary memory as firmware code and / or other program code, respectively. The data includes program data corresponding to the firmware and / or other programs executed by the processor, among other suitable data. In some implementations, the processor 113 is a general-purpose microprocessor or an application-specific microcontroller. The processor 113 is also referred to as a central processing unit (CPU).

[0055] The processor 113 accesses instructions and data from the internal memory 114. In some implementations, the internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some implementations, if the device 110 is an eMMC, an SD card, or a smart watch, the internal memory 114 is an SRAM. In some implementations, if the device 110 is a digital camera or a media player, the internal memory 114 is a DRAM.

[0056] 1A, the on-chip memory 114 is a cache memory included in the device controller 112. The on-chip memory 114 stores instruction code corresponding to instructions executed by the processor 113 and / or data required by the processor 113 during execution.

[0057] The device controller 112 transfers instruction code and / or data from the memory 150 to the embedded memory 114. In some implementations, the memory 150 is a storage device or non-volatile memory (NVM) configured for long-term storage of instructions and / or data, such as a NAND flash memory device, or some other suitable non-volatile memory device. In implementations where the memory 150 is a NAND flash memory, the device 110 is a flash memory device, such as a flash memory card, and the device controller 112 is a NAND flash controller. For example, in some implementations, if the device 110 is an eMMC or SD card, the memory 150 is a NAND flash; in some implementations, if the device 110 is a digital camera, the memory 150 is an SD card; in some implementations, if the device 110 is a media player, the memory 150 is a hard disk.

[0058] In some implementations, device controller 112 is configured to receive data and instructions from and send data to host device 120. Device controller 112 is further configured to send data and commands to and receive data from memory 150. For example, device controller 112 is configured to send data and write commands to instruct memory 150 to store the data at a specified address. As another example, device controller 112 is configured to receive a read request (or read command) from host device 120 and send a corresponding read command to memory 150 to read data from a specified address in memory 150.

[0059] 1A, the device controller 112 includes an ECC circuit 130. The ECC circuit 130 may include an ECC encoder 132 and an ECC decoder 134. In some implementations, the ECC circuit 130 may be disposed such that it is externally coupled to the device controller 112.

[0060] The ECC encoder 132 may be configured to receive data to be stored in the memory 150 and generate check bits, for example, by encoding the data using an ECC encoding scheme. The check bits may be referred to as ECC data. The ECC encoder 132 may include a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, or any combination thereof. The ECC decoder 134 may be configured to decode the data read from the memory 150 to detect and correct any bit errors that may be present in the data up to the error correction capability of the ECC scheme. The ECC decoder 134 may perform BCH decoding or LDPC decoding.

[0061] In some implementations, the ECC encoder 132 is configured to encode data of a predetermined length or size (e.g., 4KB) to generate ECC data of a predetermined size (e.g., 512B). The ECC decoder 134 is configured to decode data of a predetermined length or size (e.g., 4KB) using ECC data of a predetermined size (e.g., 512B). For data of the same size, ECC data of a larger size can provide higher error correction capability than ECC data of a smaller size. For ECC data of the same size, ECC data can provide higher error correction capability for data of a smaller size than data of a larger size. For example, a 4KB ECC encoder generates 512B ECC data. When an ECC encoder is used to encode 2KB data and 2KB of a predetermined (or fixed) value (e.g., 1 or 0) to generate 512B ECC data. When an ECC decoder decodes data using the ECC data, 512 B of ECC data generated based on 2 KB of data can provide higher error correction capability than 512 B of ECC data generated based on 4 KB of data. As discussed in further detail below, e.g., with respect to Figures 2, 3, and 4A-4B, the ECC encoder 132 and the ECC decoder 134 may be used to provide multi-phase ECC protection.

[0062] In some implementations, device controller 112 includes RAID circuitry (or RAID circuitry) 140 configured to protect data using RAID techniques. RAID circuitry 140 can allocate data across different disk drives in a RAID level, e.g., RAID0, RAID1, RAID2, ..., RAID9, or any combination thereof. RAID circuitry 140 can be configured to provide an additional phase of error protection if the multi-phase ECC protection using ECC circuitry 130 fails.

[0063] 2 illustrates an example 200 of generating multi-phase ECC data for error correction in a memory system. The memory system may include a memory device (e.g., device 110 of FIG. 1A) having a memory controller (e.g., device controller 112 of FIG. 1A) and a memory (e.g., memory 150 of FIG. 1A). The memory may include one or more memory chips (e.g., memory chip 152 of FIG. 1A-1B). Each memory chip includes multiple blocks (e.g., block 154 of FIG. 1B), each including multiple pages (e.g., page 156 of FIG. 1B).

[0064] For purposes of illustration, multi-phase ECC protection (or multi-phase ECC error correction) is implemented for a number of data pages (e.g., page 0 (202-0), page 1 (202-1), page 2 (202-2), page 3 (202-3), ..., page M-1 (202-(M-1))), which may be referred to generally and individually as data pages 202, where M is an integer equal to or greater than 1. In one specific example, M is 7. Each data page 202 stores respective user data 212 of the data page 202.

[0065] For the first phase ECC protection, an ECC encoder 220 (e.g., ECC encoder 132 of FIG. 1A) encodes the user data 212 of each of the multiple data pages 202, e.g., page 0 (202-0) shown in FIG. 2, to generate ECC data 222. As described above, the ECC encoder 220 may include a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, or any combination thereof. The ECC data 222 may include ECC check bits (or ECC protection bits) of the user data 212. The ECC data 222 may be stored in the same data page 202 as the user data 212, e.g., may be appended to the user data 212 of the data page 202.

[0066] The ECC encoder 220 is configured to encode data of a predetermined length or size to generate ECC data of a predetermined size. For example, the ECC encoder 220 may be a 4KB ECC encoder configured to encode data of a size of 4KB. The user data 212 may have a size of 4KB, and the ECC data 222 may have a size of 512B. In some examples, the data page 202 stores 16KB of user data. The ECC encoder 220 may encode the user data 212 every 4KB to generate corresponding ECC data 222 of a size of 512B, and store the corresponding ECC data 222 immediately adjacent to the user data 212 in the data page 202. The ECC encoder 220 may repeat four times to encode all 16KB of user data in the data page 202. The corresponding ECC data 222 may be referred to as first phase ECC data or first ECC data. It should be noted that the terms "first phase ECC data" and "first ECC data" may be used interchangeably in this disclosure.

[0067] 2, for second phase ECC protection, a controller (e.g., device controller 112 of FIG. 1A) may extract data portion 214 of user data 212 from data page 202 and place data portion 214 into cache page 230 as input for ECC encoder 220. Cache page 230 may be in a cache (or data buffer) of the controller (e.g., a cache in embedded memory 114 of FIG. 1A or a cache of ECC encoder 220).

[0068] 2, the controller fills the remaining space of the cache page 230 with fixed data 216 (e.g., a plurality of predetermined values) such that the combined size of the data portion 214 and the fixed data 216 fits (e.g., matches) the predetermined data size of the ECC encoder 220. The fixed data 216 may be filled into the cache page 230 by a processor of the controller (e.g., processor 113 of FIG. 1A) or specific circuitry within the controller configured to fill the data. The fixed data 216 may include at least one of 1, 0, or any fixed value.

[0069] In some examples, the ECC encoder 220 is a 4KB ECC encoder 220 and the user data 212 is 4KB. If the data portion 214 is half the user data 212, e.g., 2KB, then the size of the fixed data 216 filled into the cache page is 2KB. As such, the encoder 220 may still be used to encode the data of the cache page 230 (e.g., the data portion 214 and the predetermined value 216) to generate the ECC data 224. The ECC data 224 may have the same size as the ECC data 222 (e.g., 512B).

[0070] In comparison to the ECC data 222 for the user data 212, the ECC data 224 is for the data portion 214 and the fixed data 216. Because the fixed data 216 includes predetermined / fixed values ​​and has no error bits, all of the ECC data 224 may be used to decode and correct the data portion 214 (e.g., using an ECC decoder such as the ECC decoder 134 of FIG. 1A). Because the data portion 214 is a portion of the user data 212 and is smaller in size than the user data 212, if the ECC data 224 is the same size as the ECC data 222, the ECC data 224 may have a higher error correction capability for the data portion 214 than the ECC data 222 for the user data 212. For example, if the data portion 214 is half the user data 212 and the ECC data 224 is the same size as the ECC data 222, the ECC data 224 has twice the error correction capability of the ECC data 222.

[0071] The ECC data 224 may be referred to as second phase ECC data or second ECC data. It should be noted that the terms “second phase ECC data” and “second ECC data” may be used interchangeably in this disclosure. The second phase ECC data 224 may be used to correct the data portion 214 and the user data 212 if the first phase ECC data 222 cannot correct the user data 212. For example, after the data portion 214 is corrected with the second phase ECC data 224, the corrected data portion 214 may replace the data portion of the user data 212, and the first phase ECC data 222 may be used again to decode and correct the remaining portion of the user data 212 with the corrected data portion 214. In this way, the entire user data 212 may be corrected with the first phase ECC data 222 and the second phase ECC data 224.

[0072] In some implementations, the size of the data portion 214 is half the size of the user data 212. That is, the data portion 214 is 50% of the user data 212. The data portion can also be less than 50% of the user data 212 or more than 50% of the user data 212.

[0073] The fixed data 216 may be filled into the cache page 230 in any suitable manner. In some implementations, the fixed data 216 is located adjacent to the data portion 214 of the cache page 230. In some implementations, the value of the fixed data 216 (e.g., a 1 or a 0) is assigned or inserted between bits of the data portion 214. In some implementations, the fixed data 216 is split into two or more portions that are filled into different locations of the data portion 214.

[0074] The ECC data 224 may be stored in a redundant page 204 (e.g., page M), for example, as shown in FIG. 2. A controller (e.g., ECC encoder 220) may generate a respective ECC data 224 for each of the plurality of data pages 202. Thus, the redundant page 204 may store M ECC data 224 for the plurality of data pages 202. The redundant page 204 may have the same size as each of the plurality of data pages 202. The total size of the M ECC data 224 may not exceed the size of the redundant page 204. The redundant page 204 may be configured for M data pages 202. In some examples, M is equal to 7. In some implementations, the redundant page 204 may be optionally encoded, for example, by the ECC encoder 220, to generate unique ECC data 226, which may be stored in the redundant page 204 adjacent to the second ECC data 224. The ECC data 226 may optionally be used to correct erroneous bits in the redundant pages 204, for example, before deriving the second phase ECC data 224 for second phase ECC protection.

[0075] The redundant page 204 may be different from each of the plurality of data pages 202. In some implementations, the plurality of data pages 202 are in the same block of a memory chip, and the redundant page 204 may be in the same block or different blocks of the memory chip. In some implementations, at least two of the plurality of data pages 202 are in different blocks of a memory chip, and the redundant page 204 may be in the same memory chip or different memory chips of the same memory. In some implementations, at least two of the plurality of data pages 202 are in at least two memory chips of the same memory, and the redundant page 204 may be in a different memory chip than the at least two memory chips of the memory. In some implementations, at least two of the plurality of data pages 202 are in at least two memory devices (e.g., SSDs) of a memory system, and the redundant page 204 may be in a different memory device than the at least two memory devices of the memory system.

[0076] In some implementations, the controller includes a second ECC encoder that may be different from the ECC encoder 220. The second ECC encoder may be configured to encode data of the same size (e.g., 2KB) as the data portion 214. Accordingly, the controller may include a corresponding second ECC decoder configured to decode data of the same size (e.g., 2KB) as the data portion 214. It may not be necessary to add additional data (e.g., fixed data 216) to the cache page for the data portion 214. Instead, the data portion 214 may be used directly as an input for the second ECC encoder. In some examples, the ECC data generated by the second ECC encoder may have the same size as the ECC data 224 or the ECC data 222. In that way, the ECC data generated by the second ECC encoder may have a higher error correction capability than the ECC data 222 of the user data 212. The ECC data generated by the second ECC encoder may also be used as second-phase ECC data (or second ECC data) to provide second-phase protection if first-phase ECC protection using the first-phase ECC data 222 fails.

[0077] In some examples, the ECC data generated by the second ECC encoder can be a size greater than the size of the ECC data 222. In some examples, the ECC data generated by the second ECC encoder can be a size less than the size of the ECC data 222 but greater than a size threshold. For example, if the data portion 214 is half the size of the user data 212, the size threshold can be half the size of the ECC data 222.

[0078] 3 illustrates another example 300 of generating multi-phase ECC data for error correction in a memory system. Unlike the example 200 of FIG. 2, in which each data page has its own second-phase ECC data, the example 300 uses one or more logical and / or mathematical operations (e.g., XOR) on data portions of multiple data pages to obtain a single second-phase ECC data for multiple data pages. This can save space on redundant pages and / or reduce the number of redundant pages that store second-phase ECC data for multiple data pages for multi-phase ECC protection.

[0079] Similar to example 200 of FIG. 2, the memory system may include a memory device (e.g., device 110 of FIG. 1A) having a memory controller (e.g., device controller 112 of FIG. 1A) and a memory (e.g., memory 150 of FIG. 1A). The memory may include one or more memory chips (e.g., memory chip 152 of FIG. 1A-1B). Each memory chip includes multiple blocks (e.g., block 154 of FIG. 1B), each of which includes multiple pages (e.g., page 156 of FIG. 1B). The memory controller may include an ECC encoder 320 (e.g., ECC encoder 132 of FIG. 1A) and an ECC decoder (e.g., ECC decoder 134 of FIG. 1A).

[0080] For purposes of illustration, multi-phase ECC protection (or multi-phase ECC error correction) is implemented for multiple data pages (e.g., page 0 (302-0), page 1 (302-1), page 2 (302-2), page 3 (302-3), ..., page N-1 (302-(N-1))), which may be referred to generally and individually as data pages 302, where N is an integer equal to or greater than 2. In some examples, N is 15, 31, 63, 127, 255, or more.

[0081] The data pages 302 can be similar to or the same as the data pages 202 of Figure 2. Each data page 302 stores respective user data 312 for the data page 302. Similar to the example 200 of Figure 2, in first phase ECC protection, in the example 300, an ECC encoder 320 (e.g., ECC encoder 132 of Figure 1A or 220 of Figure 2) can generate respective first phase ECC data (or first ECC data) 322 for each user data 312 for the data page 302, and the first phase ECC data 322 can be stored in the data page 302 adjacent to the user data 312. For example, as shown in FIG. 3, page 0 (data page 302-0) stores user data 312-0 and first phase ECC data 322-0, page 1 (data page 302-1) stores user data 312-1 and first phase ECC data 322-1, page 2 (data page 302-2) stores user data 312-2 and first phase ECC data 322-2, page 3 (data page 302-3) stores user data 312-3 and first phase ECC data 322-3, ..., page N-1 (data page 302-(N-1)) stores user data 312-(N-1) and first phase ECC data 322-(N-1).

[0082] 2, where each data page 202 has its own second phase ECC data 224 in redundant page 204 (page M), in example 300, a single second phase ECC data for multiple data pages is placed in redundant page 304 (page N) using one or more logical or mathematical operations (e.g., XOR) on the data portions of the multiple data pages. The one or more logical or mathematical operations can be similar or the same as those used in RAID techniques.

[0083] For example, as shown in FIG. 3, data portion 314-0 of user data 312-0 in page 0 (data page 302-0) and data portion 314-1 of user data 312-1 in page 1 (data page 302-1), and optionally one or more other data portions of user data 312 in one or more other data pages 302, may be operated using an XOR operation 315 to generate composite data 316. The XOR operation 315 may be performed by a memory controller (e.g., an ECC encoder 320 or a specific logic gate or circuit) before encoding. The data portions 314-0, 314-1, ... may be generally referred to as data portions 314 and may also be individually referred to as data portions 314. The composite data 316 is the same size as each of the data portions 314. For example, if the data portions 314 have a size of 2KB, the composite data 316 also has a size of 2KB. In that way, the data portions 314 of the user data 312 of the multiple data pages 302 may be represented as a single composite data 316, which may be used to generate second phase ECC data 324 for the multiple data pages 302. The second phase ECC data 324 may be the same size as the first phase ECC data 322 (e.g., 512B).

[0084] In some implementations, similar to the example 200 of FIG. 2, in the example 300, the composite data 316 is stored in the cache page 330 as an input for the ECC encoder 320. The fixed data 318 may be filled into the cache page 330. The fixed data 318 may be similar to or the same as the fixed data 216 of FIG. 2. The fixed data 318 may include a number of predefined values ​​(e.g., 1 or 0). The combined size of the composite data 316 and the fixed data 318 is the same as the user data 312. In one specific example, each user data 312 has a size of 4KB, and each data portion 314 is half the size of the user data 312 (i.e., 2KB). Thus, the composite data 316 has a size of 2KB, and the fixed data 318 has a size of 2KB. In this manner, the ECC encoder 320 may be used to generate the first phase ECC data 322 and the second phase ECC data 324.

[0085] The multiple data pages 302 may be divided into multiple groups of data pages 302. Each group of data pages 302 may be associated with a respective second phase ECC data 324. The second phase ECC data 324 of each of the multiple groups may be stored in the redundant page 304. The total size of each of the second phase ECC data 324 may not exceed the size of the user data 312 or the space capacity of the redundant page 304. In some implementations, similar to the example 200 of FIG. 2, the second phase ECC data 324 stored in the redundant page 304 in the example 300 may be encoded, for example, by an ECC encoder 320 to generate ECC data 326 that is stored in the redundant page 304 with the second phase ECC data 324. During a read operation, ECC data 326 may optionally be used to correct bit errors in the second phase ECC data 324 stored in redundant page 304 before the second phase ECC data 324 is used for second phase ECC protection.

[0086] The number of the multiple data pages 302 may be an integer greater than 1, and the number of the multiple groups may be n, an integer greater than 1. In some examples, n may be 8 when the user data 312 has a size of 4KB and the second phase ECC data 324 each has a size of 512B.

[0087] In some examples, when the number of data pages 302 is 15 (e.g., N=15), there may be seven groups of two data pages 302 and one single data page 302. Each group is used to generate the composite data 316 and to generate the second phase ECC data 324 for that group, and the single data page 302 itself is used to generate the second phase ECC data 324 for the single data page 302. There are eight second phase ECC data 324 for the 15 data pages 302, which are stored in the redundant page 304. Thus, using an XOR operation, one redundant page can provide second phase ECC protection for the 15 data pages 302.

[0088] In some examples, when the number of data pages 302 is 31 (e.g., N=31), there may be seven groups of four data pages 302 and one group of three data pages 302. Each group is used to generate the composite data 316 and to generate the second phase ECC data 324 for that group. For the 31 data pages 302, there are still eight pieces of second phase ECC data 324 that are stored in the redundant page 304. Thus, using an XOR operation, one redundant page can provide second phase ECC protection for the 31 data pages 302.

[0089] In some examples, when the number of data pages 302 is 63 (e.g., N=63), there may be seven groups of eight data pages 302 and one group of seven data pages 302. Each group is used to generate the composite data 316 and to generate the second phase ECC data 324 for that group. There are eight second phase ECC data 324 for the 63 data pages 302 that are stored in the redundant page 304. Thus, using an XOR operation, one redundant page can provide second phase ECC protection for the 63 data pages 302.

[0090] Similar to the redundant page 204 of FIG. 2, the redundant page 304 may be different from each of the plurality of data pages 302. In some implementations, the plurality of data pages 302 are in the same block of a memory chip, and the redundant page 304 may be in the same block or different blocks of the memory chip. In some implementations, at least two of the plurality of data pages 302 are in different blocks of a memory chip, and the redundant page 304 may be in the same memory chip or different memory chips of the same memory. In some implementations, at least two of the plurality of data pages 302 are in at least two memory chips of the same memory, and the redundant page 304 may be in a different memory chip than the at least two memory chips of the memory. In some implementations, at least two of the plurality of data pages 302 are in at least two memory devices (e.g., SSDs) of a memory system, and the redundant page 304 may be in a different memory device than the at least two memory devices of the memory system.

[0091] FIG. 4A is a flow chart of an example process 400 for generating multi-phase ECC data for error correction in a memory system. The memory system may include a memory device (e.g., device 110 of FIG. 1A) having a memory controller (e.g., device controller 112 of FIG. 1A) and a memory (e.g., memory 150 of FIG. 1A). The memory may include one or more memory chips (e.g., memory chip 152 of FIG. 1A-1B). Each memory chip may include multiple blocks (e.g., block 154 of FIG. 1B), each of which includes multiple pages (e.g., page 156 of FIG. 1B). The memory controller may include an ECC encoder (e.g., ECC encoder 132 of FIG. 1A, 220 of FIG. 2, or 320 of FIG. 3) and an ECC decoder (e.g., ECC decoder 134 of FIG. 1A). The process 400 may be performed by the memory system (e.g., memory controller).

[0092] The memory system may receive data from a host device (e.g., host device 120 of FIG. 1A) and store the data in multiple data pages of the memory system. The memory system may provide data error protection for the stored data (e.g., multi-phase ECC protection as shown in FIG. 2 or FIG. 3, and optionally RAID data protection). The multiple data pages may be multiple data pages 202 of FIG. 2 or multiple data pages 302 of FIG. 3.

[0093] In step 402, first ECC data (or first phase ECC data) is generated based on data stored in each of the plurality of data pages and stored in the data page together with the data. The first ECC data may be generated by an ECC encoder. The data stored in each of the plurality of data pages may be user data 212 in FIG. 2 or user data 312 in FIG. 3. The first ECC data may be first ECC data 222 in FIG. 2 or first ECC data 322 in FIG. 3.

[0094] In step 404, second ECC data (or second phase ECC data) is generated based on a portion of the data stored in each of the multiple data pages and stored in a redundant page different from the data pages. The redundant page may be redundant page 204 of Figure 2 or redundant page 304 of Figure 3. The stored portion of data may be data portion 214 of Figure 2 or data portion 314 of Figure 3.

[0095] In some implementations, for example as shown in FIG. 2, the memory controller generates the second ECC data based on a portion of the data stored in the data page and a plurality of predetermined values ​​(e.g., fixed data 216 in FIG. 2). The plurality of predetermined values ​​may include at least one of 1 and 0. The portion of the stored data may be extracted and stored in a cache page (e.g., cache page 230 in FIG. 2). The portion may be half of the stored data. The plurality of predetermined values ​​may be filled into the cache page. A total size of the portion of the data stored in the data page and the plurality of predetermined values ​​is the same as the size of the data stored in the data page. An ECC encoder may encode data in the cache page to generate second ECC data for the data page. The second ECC data for the portion of the data stored in the data page may have the same size as the first ECC data for the data stored in the data page.

[0096] In some implementations, the multiple data pages are divided into multiple groups. Each group may include one or more data pages. For a group including two or more data pages, for example, as shown in FIG. 3, the page data of the specific portion of the two or more data pages may first be operated, for example, by an XOR operation, to generate composite data (e.g., composite data 316 in FIG. 3), and then the second ECC data (e.g., second ECC data 324 in FIG. 3) may be generated based on the composite data and multiple predetermined values ​​(e.g., fixed data 318 in FIG. 3). The term "page data" refers to the data stored in the data page. The second ECC data for the group may then be stored in a redundant page. The size of the composite data may be the same as the size of each of the specific portions of the page data of the two or more data pages. The total size of the composite data and the multiple predetermined values ​​is the same as the size of the page data in the data page. The second ECC data for the page data of the particular portion of the two or more data pages may have the same size as the first ECC data for each page data of the two or more data pages.

[0097] In some implementations, if the memory system includes a RAID circuit (e.g., RAID circuit 140 of FIG. 1A), the memory system can use the RAID circuit to protect the data, for example, by storing the data on multiple disk drive devices (e.g., memory chips) of the memory system.

[0098] In some implementations, the multiple data pages are in the same block of a memory chip of the memory, and the redundant page may be in the same block or a different block of the same memory chip. In some implementations, at least two of the multiple data pages are in different blocks of a memory chip of the memory, and the redundant page may be in the same memory chip or a different memory chip of the memory. In some implementations, at least two of the multiple data pages are in at least two memory chips of the memory, and the redundant page may be in a different memory chip than the at least two memory chips of the memory. In some implementations, at least two of the multiple data pages are in at least two memory devices (e.g., SSDs) of the memory system, and the redundant page may be in a different memory device than the at least two memory devices of the memory system.

[0099] FIG. 4B is a flow chart of an example process 450 for managing error correction in a memory system. The memory system can be similar to or the same as the memory system of FIG. 4A. The memory system can include a memory device (e.g., device 110 of FIG. 1A) having a memory controller (e.g., device controller 112 of FIG. 1A) and a memory (e.g., memory 150 of FIG. 1A). The memory can include one or more memory chips (e.g., memory chip 152 of FIG. 1A-FIG. 1B). Each memory chip includes multiple blocks (e.g., block 154 of FIG. 1B), each of which includes multiple pages (e.g., page 156 of FIG. 1B). The memory controller can include an ECC encoder (e.g., ECC encoder 132 of FIG. 1A, 220 of FIG. 2, or 320 of FIG. 3) and an ECC decoder (e.g., ECC decoder 134 of FIG. 1A). The process 450 can be performed by the memory system (e.g., memory controller).

[0100] The memory system may receive a request from a host device (e.g., host device 120 of FIG. 1A). The request may be a read request to read data stored in the memory system. As described above, the data may be stored in multiple data pages with multi-phase ECC protection.

[0101] In step 452, data (e.g., user data 212 of FIG. 2 or 312 of FIG. 3) is read from each of a plurality of data pages (e.g., data page 202 of FIG. 2 or 302 of FIG. 3). In step 454, a first phase ECC test is performed on the read data based on first ECC data associated with the data. The first ECC data is stored in the data page together with the data. The first ECC data may be first phase ECC data 222 of FIG. 2 or 322 of FIG. 3.

[0102] In some implementations, the memory controller performs a first phase ECC test by performing an ECC decoding operation on the read data based on the first ECC data, and determines whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold. If the number of error bits is less than the predetermined threshold, the memory controller determines that the read data passes the first phase ECC test. The memory controller can then output the read data as output data, for example, to a host device. If the number of error bits matches or is greater than the predetermined threshold, the memory controller determines that the read data does not pass the first phase ECC test.

[0103] In step 456, if the read data does not pass the first phase ECC test, a second phase ECC test is performed on the portion of the read data based on the second ECC data. The second ECC data is associated with a portion of data corresponding to the portion of the read data and is stored in a redundant page different from each of the multiple data pages. The second ECC data may be the second ECC data 224 in FIG. 2 or 324 in FIG. 3. The size of the second ECC data may be the same as the size of the first ECC data. The portion of data may be the data portion 214 in FIG. 2 or the data portion 314 in FIG. 3. The size of the portion of data may be half the size of the data. The redundant page may be the redundant page 204 in FIG. 2 or 304 in FIG. 3.

[0104] In some implementations, the memory controller performs a second phase ECC test by performing an ECC decoding operation (e.g., by an ECC decoder such as ECC decoder 134 of FIG. 1A) on the portion of the read data based on the second ECC data and determining whether the number of error bits in the portion of the read data after the ECC decoding operation is less than a predetermined threshold. The memory controller may use the same ECC decoder to perform the first phase ECC test and the second phase ECC test. If the number of error bits is less than the predetermined threshold, the memory controller determines that the portion of the read data passes the second phase ECC test. If the number of error bits matches or is greater than the predetermined threshold, the memory controller determines that the portion of the read data does not pass the second phase ECC test.

[0105] The data may include multiple portions including a portion of the data as a first portion of the data and a second portion (e.g., a remainder) of the data. The read data includes multiple portions of the read data including a portion of the data read as the first portion of the read data and a second portion of the read data corresponding to the second portion of the data. If the first portion of the read data passes the second phase ECC test, the memory controller may perform a first phase ECC test on the second portion of the read data and the corrected data of the first portion of the read data based on the first ECC data. If the second portion of the read data and the corrected data of the first portion of the read data pass the first phase ECC test, the memory controller may output the corrected data of the second portion of the read data and the corrected data of the first portion of the read data as read data of the data.

[0106] In some implementations, the memory controller includes a RAID circuit (e.g., RAID circuit 140 of FIG. 1A). If a portion of the read data fails the second phase ECC test, the memory controller can use the RAID circuit to perform error correction on the read data, for example, as a third phase of data protection.

[0107] In some implementations, in response to determining that the read data does not pass the first phase ECC test, the memory controller reads second ECC data from the redundant page and performs an ECC decode operation using the second ECC data on a combination of the portion of the read data and the plurality of predetermined values. A total size of the portion of the read data and the plurality of predetermined values ​​is the same as a size of the read data. The plurality of predetermined values ​​may be the same as the plurality of predetermined values ​​used to generate the second ECC data. The plurality of predetermined data may be fixed data 216 of FIG. 2 or fixed data 318 of FIG. 3. The plurality of predetermined values ​​may include at least one of 0 or 1.

[0108] In some implementations, the redundant page includes ECC parity data (e.g., ECC data 226 of FIG. 2 or 326 of FIG. 3) associated with the second ECC data. The memory controller can perform an ECC decode operation on the second ECC data based on the ECC parity data to generate corrected second ECC data, and perform a second phase ECC test on the portion of the read data based on the corrected second ECC data.

[0109] In some implementations, for example, as shown in FIG. 2 or FIG. 3, the redundant page includes a plurality of second ECC data associated with a particular portion of page data in a plurality of data pages. The total size of the plurality of second ECC data does not exceed the size of the data. The size of the particular portion of page data in each of the plurality of data pages may be the same.

[0110] In some implementations, as shown in FIG. 3, the multiple data pages are divided into multiple groups. Each group may include one or more data pages. For a group including two or more data pages, for example, as shown in FIG. 3, the page data of the specific portions of the two or more data pages may first be operated, for example, with an XOR operation, to generate composite data (e.g., composite data 316 in FIG. 3), and then the second ECC data (e.g., second ECC data 324 in FIG. 3) may be generated based on the composite data and multiple predetermined values ​​(e.g., fixed data 318 in FIG. 3). The second ECC data for the group may then be stored in a redundant page. The composite data may have the same size as the page data of each specific portion of the one or more data pages.

[0111] In some implementations, in a read operation, the memory controller reads first page data from a first data page of the two or more data pages (e.g., at step 452) and performs a first phase ECC test on the read first page data based on the first ECC data of each of the first data pages (e.g., at step 454). In response to determining that the read first page data does not pass the first phase ECC test, for example, at step 456, the memory controller reads other page data from one or more other data pages of the two or more data pages, reads corresponding second ECC data for the two or more data pages from a redundant page, and performs a second phase ECC test on the first data portion of the read first page data and a plurality of predetermined values ​​based on the corresponding second ECC data and the other page data from the one or more other data pages.

[0112] The plurality of predetermined values ​​are fixed data with no error bits. The ECC decoder can decode the composite data using the corresponding second ECC data, and the decoded composite data can be used in an inverse XOR operation with other page data from one or more other data pages to derive a first data portion of the first page data, which can be used to correct the first data portion of the read first page data. The corrected first data portion can be used to correct a remaining portion of the read first page data using the first ECC data for the first page data, as described above. Furthermore, after the read first page data in the first data page is corrected, the corrected first page data can be used to correct errors in the read page data of one or more other data pages.

[0113] The disclosed examples and other examples may be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer-readable medium for execution by or for controlling the operation of a data processing apparatus. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The term "data processing apparatus" encompasses all apparatus, devices, and machines that process data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. An apparatus may include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes a processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0114] A system may encompass all apparatus, devices, and machines that process data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may include code that creates an environment for the execution of the computer program in question, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0115] A computer program (also known as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form including components, subroutines, or other units suitable for use in a computing environment, as a stand-alone program or as a module. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., a file that stores one or more modules, subprograms, or portions of code). A computer program may be deployed for execution on one computer or on multiple computers, which may be located at one site or distributed across multiple sites and interconnected by a communication network.

[0116] The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows may also be performed by, and an apparatus may be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0117] Processors suitable for executing computer programs include, by way of example, both general-purpose and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Essential elements of a computer may include a processor for performing instructions, and one or more memory devices for storing instructions and data. Generally, a computer may also include one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data, or be operatively coupled to receive data therefrom, transfer data thereto, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all types of non-volatile memory, media, and memory devices, including, by way of example, semiconductor memory devices, such as EPROMs, EEPROMs, flash memory devices, and magnetic disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0118] Although many details may be described herein, these should not be construed as limitations on the scope of the claimed invention or what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of separate embodiments may be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although such features may be described above as operating in a particular combination, or even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination. Similarly, although the figures show operations in a particular order, this should not be understood as necessary for such operations to be performed in the particular order or sequence shown, or for all of the operations shown to be performed, to achieve desired results.

[0119] The disclosed examples and implementations are just a few. Variations, modifications, and improvements may be made to the described examples and implementations, as well as other implementations, based on the disclosure.

Claims

1. memory; and coupled to the memory; reading data from a data page of said memory; performing a first phase error correction code (ECC) test on the read data based on first ECC data associated with the data, the first ECC data being stored with the data in the data page; In response to determining that the read data does not pass the first phase ECC test, a second phase ECC test is performed on the portion of the read data based on second ECC data, where the second ECC data is associated with a portion of the data corresponding to the portion of the read data and is stored in a redundant page different from the data page. The memory controller is configured as follows: A memory system comprising:

2. the data includes a plurality of portions including the portion of the data as a first portion of the data and a second portion of the data, and the read data includes a plurality of portions of the read data including the portion of the read data as a first portion of the read data and a second portion of the read data corresponding to the second portion of the data; The memory controller, 2. The memory system of claim 1, configured to, in response to determining that the first portion of the read data passes the second phase ECC test, perform the first phase ECC test on the second portion of the read data and corrected data of the first portion of the read data based on the first ECC data.

3. the memory controller having RAID (Redundant Array of Independent Disks) circuitry; 3. The memory system of claim 1, wherein the memory controller is configured to, in response to determining that the portion of the read data does not pass the second phase ECC test, perform error correction on the read data using the RAID circuitry.

4. the memory controller having an ECC decoder; 3. The memory system of claim 1, wherein the memory controller is configured to perform the first phase ECC test and the second phase ECC test using the ECC decoder.

5. The memory controller, reading the second ECC data from the redundant page in response to determining that the read data does not pass the first phase ECC test; performing an ECC decode operation using the second ECC data on a combination of the portion of the read data and a plurality of predetermined values, where a total size of the portion of the read data and the plurality of predetermined values ​​is equal to a size of the read data.

3. The memory system according to claim 1, configured as follows:

6. The memory controller has an ECC encoder, the ECC encoder comprising: generating the first ECC data based on the data; generating the second ECC data based on the portion of the data and the plurality of predetermined values; 6. The memory system of claim 5, configured as follows:

7. 6. The memory system of claim 5, wherein the plurality of predetermined values ​​includes at least one of 0 or 1.

8. 3. The memory system of claim 1, wherein the size of the portion of data is half the size of the data.

9. The memory controller, performing an ECC decoding operation on the read data based on the first ECC data; determining whether a number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold; determining that the read data passes the first phase ECC test if the number of error bits is less than the predetermined threshold; If the number of error bits is equal to or greater than the predetermined threshold, it is determined that the read data does not pass the first phase ECC test.

3. The memory system according to claim 1, configured as follows:

10. the redundant page includes ECC parity data associated with the second ECC data; The memory controller, performing an ECC decode operation on the second ECC data based on the ECC parity data to generate corrected second ECC data; performing the second phase ECC test on the portion of the read data based on the corrected second ECC data; 3. The memory system according to claim 1, configured as follows:

11. the memory includes a plurality of data pages including the data page as a first data page, the redundant page being different from each of the plurality of data pages; 3. The memory system according to claim 1, wherein the redundant page includes a plurality of second ECC data associated with specific portions of page data in the plurality of data pages.

12. the size of the specific portion of page data in each of the plurality of data pages is the same; The memory controller, generating, for each of the plurality of data pages, respective first ECC data based on the page data in the data page, and storing the respective first ECC data in the data page; generating respective second ECC data based on the particular portion of the page data in the data page and a plurality of predetermined values; and storing the respective second ECC data for the data page in the redundant page. It is structured as follows:

12. The memory system of claim 11, wherein a total size of the page data of the particular portion in the data page and the plurality of predetermined values ​​is the same as a size of the page data in the data page.

13. the memory includes one or more memory chips, each having a plurality of blocks; the multiple data pages are in the same block of one of the one or more memory chips, and the redundant page is in the same or a different block of the one of the one or more memory chips; or at least two of the plurality of data pages are in different blocks of one of the one or more memory chips, and the redundant page is in the one of the one or more memory chips or in a different one of the one or more memory chips; or 12. The memory system of claim 11, wherein at least two of said plurality of data pages are in different memory chips of said memory, and said redundant page is in said memory.

14. The memory controller, generating respective first ECC data based on page data of each of two or more data pages of the plurality of data pages, and storing the respective first ECC data in each of the two or more data pages; generating composite data based on the particular portions of the two or more data pages, a size of the composite data being the same as a size of each of the particular portions of the two or more data pages; generating corresponding second ECC data based on the composite data and a plurality of predetermined values; and storing the corresponding second ECC data for the two or more data pages in the redundant page.

12. The memory system of claim 11 configured as follows:

15. The memory controller, reading a first page of data from a first data page of the two or more data pages; performing a first phase ECC test on the read first page data based on the respective first ECC data of the first data page; in response to determining that the first page data read does not pass the first phase ECC test, reading another page data from one or more other data pages of the two or more data pages; reading the corresponding second ECC data for the two or more data pages from the redundant page; performing a second phase ECC test on the first data portion of the read first page data and the plurality of predetermined values ​​based on the corresponding second ECC data and the other page data from the one or more other data pages; 15. The memory system of claim 14 configured as follows:

16. memory; and coupled to the memory; generating first error correction code (ECC) data based on data in a data page of the memory; storing the first ECC data in the data page together with the data; generating second ECC data based on a portion of the data in the data page; storing the second ECC data for the data page in a redundant page different from the data page; The memory controller is configured as follows: A memory system comprising:

17. The memory controller, configured to generate the second ECC data based on the portion of the data in the data page and a plurality of predetermined values; 17. The memory system of claim 16, wherein a combined size of said portion of data in said data page and said plurality of predetermined values ​​is the same as a size of said data in said data page.

18. The memory controller, reading the data from the data page of the memory; performing a first phase ECC test on the read data based on the first ECC data in the data page; In response to determining that the read data does not pass the first phase ECC test, reading the second ECC data from the redundant page and performing a second phase ECC test on a portion of the read data corresponding to the portion of the data based on the second ECC data.

18. The memory system according to claim 16 or 17, configured as follows.

19. the memory includes a plurality of data pages including the data page, the redundant page being different from each of the plurality of data pages; The memory controller, generating respective first ECC data on page data of each of two or more data pages of the plurality of data pages, and storing the respective first ECC data together with the page data in each of the two or more data pages; generating composite data based on the particular portions of the page data of the two or more data pages, a size of the composite data being the same as a size of each of the particular portions of the page data of the two or more data pages; generating corresponding second ECC data based on the composite data and storing the corresponding second ECC data for the two or more data pages in the redundant page; 18. The memory system according to claim 16 or 17, configured as follows.

20. The memory controller, reading a first page of data from a first data page of the two or more data pages; performing a first phase ECC test on the read first page data based on the respective first ECC data of the first data page; in response to determining that the first page data read does not pass the first phase ECC test, reading one or more other specific portions of page data from one or more other data pages of the two or more data pages; reading the corresponding second ECC data for the two or more data pages from the redundant page; performing a second phase ECC test on the first data portion of the read first page data and a plurality of predetermined values ​​based on the corresponding second ECC data and the one or more other specific portions of page data from the one or more other data pages; 20. The memory system of claim 19 configured as follows:

21. 1. A method for managing error correction in a memory system, comprising: reading data from a data page of the memory; performing a first phase error correction code (ECC) test on the read data based on first ECC data associated with the data, the first ECC data being stored with the data in the data page; and responsive to determining that the read data does not pass the first phase ECC test, performing a second phase ECC test on the portion of the read data based on second ECC data, the second ECC data being associated with a portion of the data corresponding to the portion of the read data and stored in a redundant page different from the data page. A method comprising:

22. moreover, generating the first ECC data based on the data in the data page and storing the first ECC data in the data page; and generating the second ECC data based on the portion of the data in the data page and a plurality of predetermined values ​​and storing the second ECC data for the data page in the redundant page; Equipped with 22. The method of claim 21, wherein a total size of the portion of data in the data page and the plurality of predetermined values ​​is the same as a size of the data in the data page.

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