Image pick-up device, control method, and computer program

Abstract

To provide an image pick-up device that can reduce peak power in collectively transferring electric charges to voltage holding units, while achieving a global electronic shutter.SOLUTION: An imaging apparatus A comprises: a photoelectric conversion unit PD; a plurality of pixels each having a charge holding unit FD storing electric charges generated in the photoelectric conversion unit PD; voltage holding units CN, CS that hold voltage signals according to the electric charges in the charge holding units FD; a source follower unit SF1 for transferring the voltage signals to the charge holding units FD; a current source I1 that drives the source follower unit SF1; and a current source control unit 20 that controls the current source I1. The electric charges generated in the photoelectric conversion unit PD are collectively transferred to the charge holding units FD. The current source control unit 20 sequentially connects the source follower unit SF1 and the current source I1 to each other to sequentially transfer the voltage signals according to the electric charges stored in the charge holding units FD to the voltage holding units CN, CS.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor capable of a global electronic shutter. Regarding. [Background technology]

[0002] For example, in a CMOS image sensor, the signal charge accumulation period (exposure period) between multiple pixels A so-called global electronic shutter has been proposed, which matches the time between the The shutter has a holding section that holds the signal for each pixel, and starts accumulation for all pixels at the same time. Upon completion, the charge is simultaneously transferred to the holding section.

[0003] The imaging device described in Patent Document 1 performs photoelectric conversion and charge-to-voltage conversion to output a voltage. and a plurality of voltage holding capacitors that hold the voltages output by each of the pixels. By using this, global electronic shutter operation is possible. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-108066 A [Patent Document 2] JP 2013-138406 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in Patent Document 1, when signals are transferred collectively from the photoelectric conversion unit to the voltage holding capacitor, In addition, the source follower current sources of all pixels operate simultaneously, resulting in a large peak power. There is a challenge to be overcome. On the other hand, in Patent Document 2, the charge-voltage conversion section (floating diffusion) is shared. This allows peak power to be reduced, but the global There is a problem with this, however, in that it will result in a loss of globalization.

[0006] The object of the present invention is to realize a global electronic shutter while transferring electric charges to a voltage holding section at once. The present invention provides an imaging element etc. capable of reducing peak power consumption during transmission. [Means for solving the problem]

[0007] In order to solve the above problem, an image sensor according to one embodiment of the present invention includes a photoelectric conversion unit and a plurality of pixels each having a charge storage section for storing charges generated in the photoelectric conversion section; a voltage holding unit for holding a voltage signal corresponding to the charge of the charge holding unit; a source follower section for transferring the signal to the holding section; and a current source for driving the source follower section. a current source control unit for controlling the current source, and the charge generated in the photoelectric conversion unit is The charge is transferred to the charge holding section all at once, and the current source control section transfers the charge to the source follower section and the charge The current sources are connected in sequence to generate the voltage signal according to the charge stored in the charge storage section. The data are transferred to the holding unit in sequence. Effect of the Invention

[0008] According to the present invention, a global electronic shutter is realized while simultaneously transferring electric charges to a voltage holding section. It is possible to provide an imaging element etc. capable of reducing peak power during transmission. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of the configuration of an imaging device A according to a first embodiment of the present invention. [Diagram 2] 2 is a schematic diagram showing an example of the configuration of a light receiving surface of a PD substrate 21 of an imaging element 2. FIG. [Diagram 3] 2 is a schematic diagram showing an example of the configuration of a non-light-receiving surface of a PD substrate 21 of an imaging element 2, as viewed from the light-receiving surface side. FIG. [Figure 4] 2 is a schematic diagram showing an example of the configuration of a laminated substrate 22 of an imaging element 2. FIG. [Diagram 5] 2 is an equivalent circuit diagram showing a configuration example of a PD 10, a pixel circuit 11, and a stacked circuit 12. FIG. [Figure 6] 4 is a timing chart showing an example of a driving method for the image sensor 2 according to the first embodiment. [Figure 7] 4 is a timing chart showing an example of a driving method for the image sensor 2 according to the first embodiment. [Figure 8] 4 is a timing chart showing an example of a driving method for the image sensor 2 according to the first embodiment. [Figure 9] 13 is a schematic diagram showing an example of the configuration of a non-light-receiving surface of a PD substrate 21 of an image sensor 2 in a second embodiment, as viewed from the light-receiving surface side. FIG. [Figure 10] 10 is a timing chart showing an example of a driving method for the image sensor 2 according to the second embodiment. [Figure 11] 10 is a timing chart showing an example of a driving method for the image sensor 2 according to the second embodiment. [Figure 12] 10 is a timing chart showing an example of a driving method for the image sensor 2 according to the second embodiment. [Figure 13] 13 is a schematic diagram showing an example of the configuration of a non-light receiving surface of a PD substrate 21 of an image sensor 2 in a third embodiment. FIG. [Figure 14] 13 is a schematic diagram showing an example of the configuration of a laminated substrate 22 of an imaging element 2 according to a third embodiment. FIG. [Figure 15] 10 is an equivalent circuit diagram showing an example of the configuration of a PD 10, a pixel circuit 11, and a stacked circuit 12 according to a third embodiment. [Figure 16] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the third embodiment. [Figure 17]13 is a timing chart showing an example of a driving method for the image sensor 2 according to the third embodiment. [Figure 18] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the third embodiment. [Figure 19] 11 is a timing chart showing an example of an operation when sequentially reading out the 0th row to the 5th row of the image sensor 2. [Figure 20] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the fourth embodiment. [Figure 21] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the fourth embodiment. [Figure 22] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the fourth embodiment. [Diagram 23] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the fourth embodiment. [Figure 24] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the fourth embodiment. [Diagram 25] 13 is a timing chart showing an example of a driving method for the image sensor 2 according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiment. In addition, the same members or elements are shown in the same figures. A single reference number is used, and duplicate descriptions are omitted or simplified.

[0011] First Embodiment [Imaging device, element] Fig. 1 is a diagram showing an example of the configuration of an image capture device A according to a first embodiment of the present invention. Some of the functional blocks shown in Fig. 1 are realized by causing a CPU or the like serving as a computer (not shown) included in the image capture device A to execute a computer program stored in a memory serving as a storage medium (not shown).

[0012] However, some or all of them may be realized by hardware. For the hardware, a dedicated circuit (ASIC) or a processor (reconfigurable processor, DSP) may be used. Furthermore, each functional block shown in Fig. 1 does not have to be built in the same housing, and may be configured by separate devices connected to each other via signal paths.

[0013] The imaging device A is applicable to digital still cameras, digital video cameras, car-mounted cameras, security cameras, smartphones, etc. The imaging device A includes an imaging optical system 1, an imaging element 2, a signal processing unit 3, a compression / decompression unit 4, a synchronization control unit 5, an operation unit 6, an image display unit 7, and an image recording unit 8.

[0014] The imaging optical system 1 includes a lens, a lens driving mechanism, a mechanical shutter mechanism, an aperture mechanism, etc. Among these, the movable parts are driven based on a control signal from a synchronization control unit 5.

[0015] The imaging element 2 is an XY address type CMOS (Complementary Metal Oxide Semiconductor) image sensor, and performs imaging operation in response to a control signal from a synchronization control unit 5. Furthermore, the imaging signal is digitized by an AD conversion circuit included in the imaging element 2, and is output as an image signal to a signal processing unit 3. A detailed configuration of the imaging element 2 will be described later.

[0016] The signal processing unit 3 performs image processing such as noise correction and white balance processing on the digitized image signal input from the imaging element 2 under the control of the synchronization control unit 5. The signal processing unit 3 also generates control information such as AF (Auto Focus) and AE (Auto Exposure). The image signal and control information subjected to image processing in the signal processing unit 3 are output to the synchronization control unit 5.

[0017] The compression / decompression unit 4 operates under the control of the synchronization control unit 5, and performs compression / encoding processing of image signals and decompression / decoding processing of encoded data of still images. It may also perform compression / encoding / decompression / decoding processing of moving images.

[0018] The synchronization control unit 5 is, for example, a microcontroller including a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), and the like.

[0019] The synchronization control unit 5 executes a computer program stored in a ROM or the like to comprehensively control each unit of this imaging device A. The operation unit 6 is composed of various operation members such as a shutter release button, and outputs a control signal according to an input operation by a user to the synchronization control unit 5. Examples of input operations by the user include setting a recording mode such as still images or videos, and exposure control (aperture, shutter speed, ISO sensitivity), etc.

[0020] The image display unit 7 supplies an image signal to a display device such as an LCD (Liquid Crystal Display) to display an image. The image recording unit 8 is connected to, for example, a portable recording medium and stores compressed and encoded image data files.

[0021] Next, the circuit configuration of the imaging element 2 will be described with reference to Fig. 2 to Fig. 5. Fig. 2 is a schematic diagram showing an example of the configuration of the light receiving surface of the PD substrate 21 of the imaging element 2. In Fig. 2, PD10(pq) represents a photodiode located in the pth row and qth column.

[0022] 2 shows an example of a pixel arrangement of 6 rows and 8 columns, but in reality, tens of millions of pixels are arranged in a two-dimensional matrix. The image sensor 2 includes a PD substrate 21 having a plurality of PDs 10. The PDs 10 function as photoelectric conversion units that generate electric charges in response to incident light.

[0023] 3 is a schematic diagram showing a configuration example of a non-light-receiving surface of the PD substrate 21 of the image sensor 2, as viewed from the light-receiving surface side. On this non-light-receiving surface, pixel circuits 11(pq) are two-dimensionally arranged in correspondence with the PDs 10(pq).

[0024] The PD 10 and the pixel circuit 11 are collectively called a pixel. That is, each pixel includes a PD 10(pq) and a pixel circuit 11(pq). The voltage signal output from the pixel circuit 11(pq) can be transferred to the laminated substrate 22 via the electrical contact CONT for each pixel.

[0025] The contact CONT is connected to the vertical scanning circuit 20 on the laminated substrate 22, and outputs a control signal to the PD 10 and the like on the PD substrate 21. This makes it possible to realize a global electronic shutter operation, which will be described later.

[0026] For example, the PD substrate 21 is an N-type silicon substrate, and the PD 10 is an N-type semiconductor region, which accumulates electrons of electron-hole pairs generated when light is received. The driving timing will be described in detail after the explanation of the equivalent circuit diagram including the pixel circuit 11.

[0027] 4 is a schematic diagram showing a configuration example of the laminated substrate 22 of the imaging element 2. In the laminated substrate 22, laminated circuits 12(pq) connected to the respective pixel circuits 11(pq) of the PD substrate 21 are arranged two-dimensionally.

[0028] The stacked circuit 12(pq) and the pixel circuit 11(pq) are connected at each contact CONT, and the voltage signal output from the pixel circuit 11(pq) can be transferred to the corresponding stacked circuit 12(pq) for all pixels at once and stored. The stored voltage signal (pixel signal) is transmitted row by row via the vertical output line VLq0 by the vertical scanning circuit 20 for scanning the stacked circuit 12(pq) to the AD conversion circuit ADq0 as an AD conversion unit, where it is AD converted.

[0029] The AD converted digital signals are output in column sequence by the horizontal scanning circuit 30 via the horizontal output line HL to the output section 50. The output section 50 includes a known parallel-serial conversion means (P / S conversion means).

[0030] The output section 50 sequentially converts the digital imaging signals transferred to the horizontal output line HL into a high-speed serial transmission format such as LVDS (Low Voltage Differential Signaling), and outputs the converted signals. Correction processing for point defects, etc. may also be included.

[0031] The timing generating circuit 40 generates pulse signals for controlling the vertical scanning circuit 20, the AD conversion circuit ADq0, and the horizontal scanning circuit 30, respectively.

[0032] In the imaging device A, each column has one vertical output line VLq0, which is shared by all rows in the same column. Each column also has one AD conversion circuit ADq0. To increase the signal readout speed, each column can have two or more vertical output lines and AD conversion circuits.

[0033] The AD conversion circuit ADq0 is supplied with the vertical output line VLq0 and a reference signal RAMP that varies in proportion to time. The structure for accumulating voltage signals in the stacked circuit 12(pq) will be described later with reference to an equivalent circuit diagram, together with the PD 10(pq) and the pixel circuit 11(pq).

[0034] 5 is an equivalent circuit diagram showing a configuration example of the PD10, the pixel circuit 11, and the stacked circuit 12. In the PD10(pq) and the pixel circuit 11(pq), the charge generated in the PD10 is transferred to a floating diffusion (FD) via a transfer transistor TX. The FD has a floating capacitance and functions as a charge storage unit that accumulates the charge generated in the PD10.

[0035] The amplifier transistor SF1 functions as a source follower. The amplifier transistor SF1 also constitutes a source follower circuit consisting of an FD and a current source I1. The reset transistor RES1 resets the FD with a predetermined voltage VDD. The selection transistor SEL1 is connected to the source of the amplifier transistor SF1.

[0036] A current source switch ISW is connected between the sources of the current sources I1 and SEL1. The transfer transistor TX, reset transistor RES1, selection transistor SEL1, and current source switch ISW can be controlled to be turned on and off by the vertical scanning circuit 20 via pulses PTX, PRES1, PSEL1, and PISW, respectively.

[0037] Of these transistors, the gates of RES1, TX, and ISW can each be controlled by the vertical scanning circuit 20. Read operations such as charge transfer and resetting of the PD 10, and current control of the source follower circuit are performed by switching the current source I1.

[0038] The vertical scanning circuit 20 functions as a current source control section that controls the current source I1. Furthermore, the source of the selection transistor SEL1 is connected to the laminated circuit 12(pq) via a contact CONT.

[0039] The stacked circuit 12(pq) includes two voltage holding capacitances CN and CS that store the voltage signals of the pixel circuits 11(pq). The voltage holding capacitances CN and CS function as voltage holding units. The larger the capacitance of the voltage holding capacitances CN and CS, the smaller the kTC noise that accompanies the reset operation can be.

[0040] PD and voltage holding capacitances CN and CS are provided for each pixel. The voltage holding capacitance CN holds a voltage signal (hereinafter referred to as an N signal) corresponding to the charge of the FD of the pixel circuit 11 (pq) after the reset is released. The voltage holding capacitance CS holds the voltage of the FD (hereinafter referred to as an S signal) that has decreased according to the signal charge of the PD 10.

[0041] These voltage holding capacitors CN and CS may be capacitive elements with an expanded equal surface area using a trench structure. Also, high capacitance elements formed between lines in a portion using a high dielectric constant material between wiring layers of the laminated substrate 22 may be used. Furthermore, the transistor gate oxide film of the laminated substrate 22 may be used in part.

[0042] The two voltage holding capacitors CN and CS are provided with memory write transistors MWN and MWS that write voltage signals to them. The voltage holding capacitors CN and CS are connected to the gate of an amplifier transistor SF2, and form a source follower circuit consisting of a current source I2. The amplifier transistor SF2 functions as a source follower section.

[0043] The reset transistor RES2 resets the voltage holding capacitors CN and CS with a predetermined voltage VDD. The selection transistor SEL2 is connected to the source of SF2 and selectively transmits a voltage signal to the vertical output line VLq0.

[0044] These memory write transistors MWN and MWS, reset transistor RES2, and selection transistor SEL2 can be controlled to be turned on and off by the vertical scanning circuit 20 via pulses PMWN, PMWS, PRES2, and PSEL2, respectively. Therefore, read operations such as transfer and reset of voltage signals can be controlled by these pulses.

[0045] [Imaging method] Next, a description will be given of a method for driving the image sensor 2. In the first embodiment, driving is performed that can reduce the peak power of the image sensor 2 while maintaining global characteristics.

[0046] FIG. 19 is a timing chart showing an example of an operation when the 0th row to the 5th row of the image sensor 2 are sequentially read out.

[0047] From time t1900 to time t1901, the FDs and voltage holding capacitances CS and CN of all pixels are reset. From time t1901 to time t1902, the N signals stored in each FD are written sequentially to the corresponding voltage holding capacitances CN from row 0 to row 5. From time t1902 to time t1903, the charges stored in each PD 10 are transferred to the corresponding FDs of all pixels at once.

[0048] From time t1903 to time t1904 is a period during which the voltages (S signals) of each FD are written to the corresponding voltage holding capacitances CS from row 0 to row 5. From time t1904 to time t1905 is a period during which the N signals and S signals respectively held in the voltage holding capacitances CN and CS are AD converted and read out sequentially from row 0.

[0049] 19, the period from time t1901 to time t1902 and the period from time t1903 to time t1904 are characterized in that they are shorter than the period from time t1904 to time t1905. The AD conversion performed from time t1904 to time t1905 requires a predetermined operation period, and requires a corresponding amount of time in row sequence.

[0050] On the other hand, the periods from t1901 to t1902 and from t1903 to t1904, which are the periods during which writing occurs from the FD to the voltage holding capacitances CN and CS, are voltage stabilization periods, and since the voltage path to the voltage holding capacitances CN and CS provided in each pixel is very short, it is possible to shorten this period, and therefore the charge holding period in the FD can be shortened.

[0051] Fig. 6 to Fig. 8 are timing charts showing a driving method according to the first embodiment of the image sensor 2. Fig. 6 is a timing chart for the pixels in the first and second rows, Fig. 7 is a timing chart for the pixels in the third and fourth rows, and Fig. 8 is a timing chart for the pixels in the fifth and sixth rows.

[0052] Each pulse is applied to the gate of each transistor, turning the transistor ON at Hi (High) and OFF at Lo (Low). The parentheses in the pulse name correspond to the row number in the schematic diagram mentioned above.

[0053] From time t602 to time t623, a global electronic shutter operation is performed in which voltage signals corresponding to the signal charges of each pixel of the first frame are transferred to the corresponding multilayer circuits 12 of the multilayer substrate 22 simultaneously for all pixels.

[0054] Furthermore, the period from time t624 to time t632 is a sequential read-out scanning period for the laminated circuit 12(0q) in the first row of the laminated substrate 22 to the laminated circuit 12(5q) in the sixth row.

[0055] First, from time t600 to time t601, PRES1 (0 to 5), PRES2 (0 to 5), PMWS (0 to 5), and PWMN (0 to 5) are set to Hi, and FD and the voltage holding capacitances CS and CN are reset.

[0056] At time t602, PISW(0) is set to Hi, and the current source I1 for the pixels in the first row is connected to the source side of SEL1.

[0057] Next, at time t603, PSEL1(0) and PMWN(0) are set to Hi, and at time t604, PWMN(0) is set to Lo, so that the N signal is written to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the FD reset is released. Then, PSEL1(0) is set to Lo, and at time t605, PISW(0) is set to Lo, disconnecting the first row current source I1 and SEL1.

[0058] Next, at time t606, PISW(1) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1. Next, at time t607, PSEL1(1) and PMWN(1) are set to Hi, and at time t608, PWMN(1) is set to Lo, so that the N signal is written to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the reset of the FD is released.

[0059] Then, PSEL1(1) is set to Lo, and at time t609, PISW(1) is set to Lo to disconnect the second row current source I1 and SEL1. Thereafter, similarly, from time t610 to time t611, the N signals of the third row to the sixth row are sequentially written to the voltage holding capacitance CN of the stacked circuit 12(pq).

[0060] Next, at time t612, PTX (0 to 5) goes to Hi, and at time t613, PTX (0 to 5) goes to Lo, whereby the charges accumulated in the PD 10 are transferred to the FD for all pixels at once.

[0061] Next, at time t614, PISW(0) is set to Hi, and the current source I1 for the pixels in the first row is connected to the source side of SEL1.

[0062] Next, at time t615, PSEL1(0) and PMWS(0) are set to Hi, and at time t616, PWMS(0) is set to Lo, so that the voltage (S signal) of the FD in the first row that has changed in accordance with the signal charge of PD10 is written to the voltage holding capacitance CS.

[0063] Then, PSEL1(0) is set to Lo, and at time t617, PISW(0) is set to Lo, disconnecting the current source I1 and SEL1 in the first row.

[0064] Next, at time t618, PISW(1) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1.

[0065] Next, at time t619, PSEL1(1) and PWMN(1) are set to Hi, and at time t620, PWMN(1) is set to Lo, thereby writing the voltage (S signal) of the FD in the second row to the voltage holding capacitance CS.

[0066] Then, PSEL1(1) is set to Lo, and at time t621, PISW(1) is set to Lo, disconnecting the current source I1 in the second row from the source side of SEL1 and SEL1.

[0067] Similarly, from time t622 to time t623, the S signals in the third to sixth rows are sequentially written to the voltage holding capacitances CS of the stacked circuits 12(pq).

[0068] In this way, by sequentially transferring the voltage signals (pixel signals) transferred collectively to the FD to the voltage holding capacitances CS, it is possible to suppress the peak current flowing through the amplification transistor SF1 while maintaining globality.

[0069] From time t624 to t626, signals from the first row are read out. That is, by the vertical scanning circuit 20, PSEL2(0) for the first row is set to Hi from time t624 to time t626, and PMWN(0) for the first row is set to Hi from time t624 to time t625. As a result, the N signal for the first row is transferred to the AD conversion circuit ADq0 via the vertical output line VLq0, and the signals for eight pixels in the first row are AD converted.

[0070] Furthermore, from time t625 to time t626, PMWS(0) for the first row goes Hi, so that the S signal for the first row is transferred to the AD conversion circuit ADq0 via the vertical output line VLq0, and the signals for eight pixels in the first row are AD converted.

[0071] At time t627, the vertical scanning circuit 20 starts scanning the second row, and PSEL2(1) of the second row goes Hi until time t629.

[0072] From time t627 to time t628, PMWN(1) of the second row becomes Hi, so that the N signal of the second row is transferred to the AD conversion circuit ADq0 via the vertical output line VLq0, and the signals of 8 pixels of the second row are AD converted.

[0073] Furthermore, from time t628 to time t629, PMWS(1) for the second row goes Hi, so that the S signal for the second row is transferred to the AD conversion circuit ADq0 via the vertical output line VLq0, and the signals for eight pixels in the second row are AD converted.

[0074] Thereafter, similarly for each row, the N signal is transferred via the vertical output line VLq0 to the AD conversion circuit ADq0, the N signal is AD converted, and then the N signal is transferred via the vertical output line VLq0 to the AD conversion circuit ADq0, and the operation of AD conversion of the S signal is repeated.

[0075] Then, readout of the sixth row begins at time t630 when PSEL2(5) for the sixth row becomes Hi, and when AD conversion operation of S signals for eight pixels in the sixth row is completed at time t632, readout scanning of all pixels is completed.

[0076] Here, the period from time t602 to time t611, during which the N signal is sequentially written from the FD to the voltage holding capacitance CN, corresponds to the period from time t1901 to time t1902 shown in Fig. 19. Also, the period from time t614 to time t615, during which the S signal is sequentially written from the FD to the voltage holding capacitance CS, corresponds to the period from time t1903 to time t1904 shown in Fig. 19.

[0077] Furthermore, the period from time t624 to time t632, during which the voltage signals, N signals, and S signals are AD converted and sequentially read out, corresponds to time t1904 to time t1905 shown in Fig. 19. In this manner, after the charges of multiple pixels are transferred to the voltage holding capacitances CN and CS serving as voltage holding units, the voltage signals held in the voltage holding units are sequentially converted into digital signals by the AD conversion unit.

[0078] As described above, the image pickup device A transfers the charges accumulated in the PD 10 to the FD in a lump, and transfers the charges from the FD to the voltage holding capacitors CN and CS in sequence for each row while maintaining globality. In other words, the amplifying transistor SF1, which is the source follower section, and the current source I1 are sequentially connected.

[0079] This makes it possible to reduce the peak power of the image sensor 2 compared to when all pixels are transferred to the voltage holding capacitances CN and CS at the same time. Also, in the first embodiment, by shortening the charge holding time in the FD, it is possible to reduce image quality degradation due to noise generated in the FD and image quality degradation due to PLS (Parasitc Light Sensitivity) and the like.

[0080] The imaging element 2 uses an FD for holding electric charges generated by the PD 10. However, the imaging element 2 can operate in the same way even if it has a memory capacity (electric charge holding unit) in addition to the FD. Also, the imaging element 2 does not need to provide a laminated circuit 12 (pq) on the laminated substrate 22 in addition to the PD substrate 21.

[0081] The image sensor 2 may include a multilayer circuit 12(pq) on the PD substrate 21 in the vicinity of the pixel circuit 11(pq). However, providing the multilayer circuit 12(pq) on the multilayer substrate 22 is advantageous in that stray light is less likely to enter the voltage holding capacitances CN and CS.

[0082] In order to reduce the voltage drop (signal effect) caused by charges generated by stray light, it is preferable to make the voltage holding capacitances CN and CS as large as possible compared to the capacitance of the FD section of the PD substrate 21. In order to increase the voltage holding capacitance of the voltage holding capacitances CN and CS, it is advantageous to provide the laminated circuit 12(pq) on the laminated substrate 22.

[0083] <Second embodiment> [Imaging device] In the second embodiment, the charges accumulated in the PD 10 are transferred to the FD in a lump, and the charges are transferred from the FD to the voltage holding capacitances CN and CS in sequence for each region (block unit) while maintaining globality. This reduces the peak power of the image sensor 2. The description of the same configuration as the first embodiment will be omitted.

[0084] 9 is a schematic diagram showing an example of the configuration of the non-light receiving surface of the PD substrate 21 of the image sensor 2, as viewed from the light receiving surface side. On this non-light receiving surface, pixel circuits 11(pq) are arranged two-dimensionally, and are divided into regions every two rows. The 0th and 1st rows are region 1, the 2nd and 3rd rows are region 2, and the 4th and 5th rows are region 3. The vertical scanning circuit 20 is configured to control region 1, region 2, and region 3, respectively.

[0085] [Imaging method] Next, a method for driving the image sensor 2 will be described. Figures 10 to 12 are timing charts showing an example of a method for driving the image sensor 2 according to the second embodiment. Figure 10 is a timing chart for pixels in region 1 (first and second rows), Figure 11 is a timing chart for pixels in region 2 (third and fourth rows), and Figure 12 is a timing chart for pixels in region 3 (fifth and sixth rows).

[0086] Each pulse is applied to the gate of each transistor, turning the transistor ON at Hi (High) and OFF at Lo (Low). The parentheses in the pulse name correspond to the row number in the schematic diagram mentioned above.

[0087] From time t802 to time t820, a global electronic shutter operation is performed in which a voltage signal corresponding to the signal charge of each pixel of the first frame is transferred to the corresponding multilayer circuit 12 of the multilayer substrate 22 simultaneously for all pixels.

[0088] Furthermore, the period from time t821 to time t826 is a sequential readout scanning period for the laminated circuit 12(0q) in the first row of the laminated substrate 22 to the laminated circuit 12(5q) in the sixth row.

[0089] First, from time t800 to time t801, PRES1 (0 to 5), PRES2 (0 to 5), PMWS (0 to 5), and PWMN (0 to 5) are set to Hi, and FD and the voltage holding capacitances CS and CN are reset.

[0090] At time t802, PISW(0, 2, 4) is set to Hi, and current source I1 for each of the pixels in the first row of region 1, the first row of region 2, and the first row of region 3 is connected to the source side of SEL1.

[0091] Next, at time t803, PSEL1(0,2,4) and PWMN(0,2,4) are set to Hi, and at time t804, PWMN(0,2,4) is set to Lo. As a result, an N signal is written to the voltage holding capacitance CN of the stacked circuit 12(pq) as a voltage after the reset of the FD for each of the pixels in the first row of region 1, the first row of region 2, and the first row of region 3.

[0092] Then, PSEL1(0,2,4) is set to Lo, and at time t805, PISW(0,2,4) is set to Lo, disconnecting current sources I1 and SEL1 for the pixels in the first row of region 1, the first row of region 2, and the first row of region 3.

[0093] Next, at time t806, PISW(1, 3, 5) is set to Hi, and current source I1 for the pixels in the second row of region 1, the second row of region 2, and the second row of region 3 is connected to the source side of SEL1.

[0094] Next, at time t807, PSEL1(1,3,5) and PWMN(1,3,5) are set to Hi, and at time t808, PWMN(1,3,5) is set to Lo. As a result, an N signal is written to the voltage holding capacitance CN of the stacked circuit 12(pq) as a voltage after the reset of FD for each of the pixels in the second row of region 1, the second row of region 2, and the second row of region 3.

[0095] Then, PSEL1(1,3,5) is set to Lo, and at time t809, PISW(1,3,5) is set to Lo, disconnecting current sources I1 and SEL1 for the pixels in the second row of region 1, the second row of region 2, and the second row of region 3.

[0096] Next, at time t810, PTX (0 to 5) goes to Hi, and at time t811, PTX (0 to 5) goes to Lo, whereby the charges accumulated in the PD 10 are transferred to the FD for all pixels at once.

[0097] Next, at time t812, PISW(0,2,4) is set to Hi, and current source I1 for the pixels in the first row of region 1, the first row of region 2, and the first row of region 3 is connected to the source side of SEL1.

[0098] Next, at time t813, PSEL1(0,2,4) and PMWS(0,2,4) are set to Hi, and at time t814, PWMS(0,2,4) is set to Lo. As a result, the FD voltages (S signals) for the pixels in the first row of region 1, the first row of region 2, and the first row of region 3, which have changed in accordance with the signal charge of PD10, are written to the voltage holding capacitance CS.

[0099] Then, PSEL1(0,2,4) is set to Lo, and at time t815, PISW(0,2,4) is set to Lo, disconnecting current sources I1 and SEL1 for the pixels in the first row of region 1, the first row of region 2, and the first row of region 3.

[0100] Next, at time t816, PISW(1, 3, 5) is set to Hi, and current source I1 for the pixels in the first row of region 1, the first row of region 2, and the first row of region 3 is connected to the source side of SEL1. Next, at time t819, PSEL1(1, 3, 5) and PMWN(1) are set to Hi, and at time t820, PWMN(1, 3, 5) is set to Lo.

[0101] As a result, the FD voltages (S signals) for the pixels in the second row of region 1, the second row of region 2, and the second row of region 3 are written to the voltage holding capacitances CS. Then, PSEL1(1, 3, 5) is set to Lo, and at time t821, PISW(1, 3, 5) is set to Lo, disconnecting current sources I1 and SEL1 for the pixels in the second row of region 1, the second row of region 2, and the second row of region 3.

[0102] From time t821 to time t823, signals in the first row are read out. From time t821 to time t826, the readout operation for each row is performed in sequence, including the transfer of N signals to vertical output lines and AD conversion of the N signals, and the transfer of S signals and AD conversion of the S signals. This operation is similar to the operation from time t624 to time t632 in the first embodiment, and therefore will not be described.

[0103] In the second embodiment, the image pickup device A transfers the electric charges accumulated in the PD 10 to the FD all at once, and then transfers the electric charges from the FD to the voltage holding capacitances CN and CS in sequence for each predetermined region while maintaining globality. This makes it possible to reduce the peak power of the image pickup device A by half, compared to when all pixels are transferred to the voltage holding capacitances CN and CS at the same time.

[0104] In addition, compared to the configuration in the first embodiment, since the charge is transferred from the FD to the voltage holding capacitances CN and CS for each row in the region in sequence, it is possible to shorten the readout time. Also, since the charge holding time in the FD is shortened, deterioration of image quality is suppressed.

[0105] In the first and second embodiments, the voltages are sequentially transferred from the FD to the voltage holding capacitors CN and CS for each row of the arranged pixels. However, the present invention is not limited to this, and it is also possible to sequentially transfer the voltages for each pixel or for each color filter (not shown) (i.e., for each color), and the same effect can be obtained.

[0106] In the first and second embodiments, the vertical output line VLq0 of the laminated circuit 12 is a common wiring for each column of each region. However, the present invention is not limited to this, and a vertical output line and an AD conversion circuit may be provided for each region.

[0107] <Third embodiment> [Imaging device] In the third embodiment, a charge storage capacitor MEM is provided to store the charge of the pixel, and an amplifying transistor SF1 (source follower section) is shared by multiple pixels. The peak power flowing through SF is suppressed while maintaining globality. The description of the same configuration as the first and second embodiments is omitted.

[0108] 13 is a schematic diagram showing an example of the configuration of the non-light receiving surface of the PD substrate 21 of the image sensor 2 in the third embodiment, as viewed from the light receiving surface side. The pixel circuit 11(pq) has a charge holding capacitance MEM for each pixel. The charge holding capacitance MEM functions as a charge holding section different from the FD.

[0109] In addition, the reset transistor RES1, the amplifying transistor SF1, the selection transistor SEL1, the current source switch ISW, the current source I1, and the contact CONT are shared by the FD and the two vertical pixels.

[0110] A voltage signal output from the pixel circuit 11(pq) can be sequentially transferred to a laminated substrate 22 (described later) via one contact CONT shared by two vertical pixels. The contact CONT is connected to the vertical scanning circuit 20 of the laminated substrate 22, and a global electronic shutter operation can be realized by outputting a control signal to the PD etc. on the PD substrate 21 as well.

[0111] 14 is a schematic diagram showing an example of the configuration of the laminated substrate 22 of the image sensor 2 according to the third embodiment. The laminated circuits 12(pq) are arranged in a two-dimensional matrix in correspondence with the pixel circuits 11(pq) of the PD substrate 21. The pixel circuits 11(pq) are connected to one contact CONT for every two vertical pixels, and the voltage signals output from the pixel circuits 11(pq) are sequentially transferred to the laminated circuits 12(pq) for the two vertical pixels of interest.

[0112] The accumulated voltage signals (pixel signals) are transmitted row-sequentially to the AD conversion circuit ADq0 via the vertical output line VLq0 by the vertical scanning circuit 20 that scans the stacked circuit 12, and are AD-converted. The AD-converted digital signals are output column-sequentially by the horizontal scanning circuit 30 to the output section 50 via the horizontal output line HL.

[0113] The output unit 50 includes a known parallel-serial conversion means (P / S conversion means) and sequentially converts the digital imaging signals transferred to the horizontal output line HL into a high-speed serial transmission format such as LVDS, and outputs the converted signals. In addition, the output unit 50 may include correction processing for point defects, etc.

[0114] In the imaging device A, each column has one vertical output line VLq0, which is shared by all rows in the same column. Each column also has one AD conversion circuit ADq0. The vertical output line VLq0 and a reference signal RAMP that varies in proportion to time are input to the AD conversion circuit ADq0.

[0115] The structure for accumulating voltage signals in the stacked circuit 12(pq) will be described later using an equivalent circuit diagram, together with the PD 10(pq) and the pixel circuit 11(pq). In addition, a timing generating circuit 40 generates predetermined drive timings that the vertical scanning circuit 20 provides to the stacked circuit 12(pq) in row sequence, control of the AD conversion circuit ADq0, and horizontal scanning timing.

[0116] 15 is an equivalent circuit diagram showing a configuration example of PD 10, pixel circuit 11, and stacked circuit 12 according to the third embodiment. PD 10(00), PD10(10), pixel circuits 11(00), 11(10), vertical two-pixel shared portion, and stacked circuits 12(00), 12(10) for two vertical pixels are shown.

[0117] In the PD10(pq) and the pixel circuit 11(pq), a charge storage capacitance MEM and a transfer transistor TE that transfers the charge generated in the PD10 to the FD via a transfer transistor TX are provided for each pixel.

[0118] The two vertical pixels, pixel circuit 11(00) and pixel circuit 11(10), share the FD, reset transistor RES1, amplification transistor SF1, selection transistor SEL1, current source switch ISW, and current source I1. The electrical contact CONT that connects pixel circuit 11 and stacked circuit 12 is also shared by the two vertical pixels.

[0119] Using these shared portions, the charge accumulated in the pixel PD10(00) is transferred to the charge storage capacitance MEM of the pixel circuit 11(00), and then transferred to the FD of the vertical two-pixel shared portion.Then, the charge is sequentially transferred to the stack circuit 12(00) via the amplification transistor (source follower portion) SF1 and the contact CONT.

[0120] In addition, the stacked circuit 12(pq) is provided with a transfer transistor TM for each pixel to transfer a voltage signal (pixel signal) to the voltage holding capacitances CS and CN. These transfer transistors TE and TM can be controlled by the vertical scanning circuit 20 via PTE and PTM, respectively.

[0121] [Imaging method] Next, a driving method of the image sensor 2 according to the third embodiment will be described. Figures 16 to 18 are timing charts showing an example of the driving method of the image sensor 2 according to the third embodiment. Figure 16 is a timing chart for pixels in the first and second rows, Figure 17 is a timing chart for pixels in the third and fourth rows, and Figure 18 is a timing chart for pixels in the fifth and sixth rows.

[0122] Each pulse is applied to the gate of each transistor, turning the transistor ON at Hi (High) and OFF at Lo (Low). The parentheses in the pulse name correspond to the row number in the schematic diagram mentioned above.

[0123] Since the selection transistor SEL1 and the current source switch ISW are shared by two pixels, the respective pulses PSEL1 and PISW are expressed as follows.

[0124] The pulses shared between the first and second rows are PSEL1(01) and PISW(01). The pulses shared between the third and fourth rows are PSEL1(23) and PISW(23). The pulses shared between the fifth and sixth rows are PSEL1(45) and PISW(45).

[0125] From time t1202 to time t1225, a global electronic shutter operation is performed in which a voltage signal corresponding to the signal charge of each pixel of the first frame is transferred simultaneously to the corresponding laminated circuit 12 of the laminated substrate for all pixels.

[0126] Furthermore, the period from time t1225 to time t1231 is a sequential readout scanning period for the laminated circuit 12(0q) in the first row to the laminated circuit 12(5q) in the sixth row of the laminated substrate.

[0127] First, from time t1200 to time t1201, PRES1 (01, 23, 45), PTE (0 to 5), PTM (0 to 5), PRES2 (0 to 5), PMWS (0 to 5), and PWMN (0 to 5) are set to Hi. This resets the charge holding capacitances MEM and FD, and the voltage holding capacitances CS and CN.

[0128] At time t1202, PTX (0 to 5) is set to Hi, and at time t1203, PTX (0 to 5) is set to Lo, whereby the charges accumulated in the PDs 10 are transferred to the charge storage capacitors MEM for all pixels at once. Subsequently, at time t1204, PISW(01, 23, 45) is set to Hi, and the current source I1 is connected to the source side of SEL1.

[0129] Next, at time t1205, PSEL1 (01, 23, 45) is set to Hin, and reading of the first pixel to be read out of the two shared pixels is started. Next, at time t1206, PTM (0, 2, 4) becomes Hi, at time t1207, PMWN (0, 2, 4) becomes Hi, and at time t1208, PMWN (0, 2, 4) becomes Lo.

[0130] By this operation, the N signal is written to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after reset release of the FD in the 1st, 3rd, and 5th rows. Then, at time t1209, PTE(0, 2, 4) and PMWS(0, 2, 4) become Hi, and at time t1210, PTE(0, 2, 4) and PMWS(0, 2, 4) become Lo.

[0131] Through this operation, the charges stored in the charge storage capacitors MEM in the first, third, and fifth rows are transferred to the FD, and the voltage of the FD (signal S) that fluctuates according to the signal charge is written to the voltage storage capacitor CS.

[0132] At time t1211 after the transfer is completed, PTM(0, 2, 4) is set to Lo, and at time t1212 after the reading of the 1st, 3rd, and 5th rows is completed, PSEL1(01, 23, 45) is set to Lo. Subsequently, at time t1213, PISW(01, 23, 45) is set to Lo, and the current source I1 is disconnected from the source side of SEL1 and SEL1.

[0133] Next, the operation proceeds to read out the pixel that will be read later out of the two shared pixels. At time t1214, PRES1 (01, 23, 45) is set to Hi, and at time t1215, PRES1 (01, 23, 45) is set to Lo. This resets the charge stored in FD. Next, at time t1216, PISW (01, 23, 45) is set to Hi, and current source I1 is connected to the source side of SEL1.

[0134] Next, at time t1217, PSEL1 (01, 23, 45) is set to Hi, and reading of the pixel that will be read later out of the two shared pixels is started. Next, at time t1218, PTM (1, 3, 5) is set to Hi, at time t1219, PMWN (1, 3, 5) is set to Hi, and at time t1220, PMWN (1, 3, 5) is set to Lo.

[0135] By this operation, the N signal is written to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after reset release of the FD in the 2nd, 4th, and 6th rows. Next, at time t1221, PTE(1, 3, 5) and PMWS(1, 3, 5) become Hi, and at time t1222, PTE(1, 3, 5) and PMWS(1, 3, 5) become Lo.

[0136] Through this operation, the charges stored in the charge storage capacitors MEM in the second, fourth, and sixth rows are transferred to the FD, and the voltage of the FD (S signal) that fluctuates according to the signal charge is written to the voltage storage capacitor CS.

[0137] At time t1223 after the transfer is completed, PTM(1, 3, 5) is set to Lo, and at time t1224 after the reading of the 2nd, 4th, and 6th rows is completed, PSEL1(01, 23, 45) is set to Lo. Subsequently, at time t1225, PISW(01, 23, 45) is set to Lo, and the current source I1 is disconnected from the source side of SEL1 and SEL1.

[0138] From time t1226 to time t1228, the signal readout of the first row is performed. From time t1226 to time t1231, in relation to the readout operation of each row, the transfer of the N signal to the vertical output line and the AD conversion of the N signal, and the transfer of the S signal and the AD conversion of the S signal are performed sequentially for each row.

[0139] This operation is similar to the operation from time t624 to time t632 in the first embodiment, and therefore a description thereof will be omitted.

[0140] In the third embodiment, the imaging device A transfers the electric charge accumulated in the PD10 in one go to a charge holding capacitance MEM that is different from the FD, thereby maintaining globality and sharing the transfer section from the FD to the voltage holding capacitances CN and CS among multiple pixels.

[0141] This makes it possible to reduce the peak power consumption of the imaging device A by half, while downsizing the circuit configuration, compared to when all pixels of the imaging device A simultaneously transfer voltages to the voltage holding capacitors CN and CS.

[0142] In the third embodiment, the amplification transistor (source follower unit) SF1 is shared by two pixels. This is not limiting, and the source follower unit may be shared by multiple pixels. In the third embodiment, the first, third, and fifth rows and the second, fourth, and sixth rows are simultaneously read out with respect to the transfer from the FD to the voltage holding capacitance CS.

[0143] Alternatively, for example, rows 1, 3, and 5 may be read out first in row sequence, and then rows 2, 4, and 6 may be read out in row sequence. This will increase the read time, but it is also possible to further reduce peak power consumption.

[0144] <Fourth embodiment> [Imaging device] In the fourth embodiment, in the configuration of the first embodiment, a driving method is used that shortens the period during which the charge is held by the FD. This makes it possible to reduce the peak power of the image sensor 2 while also reducing image quality degradation. Note that the description of the same configuration as the first embodiment is omitted.

[0145] [Imaging method] Next, a description will be given of a driving method according to the fourth embodiment of the image sensor 2. Fig. 20 to Fig. 25 are timing charts showing an example of a driving method according to the fourth embodiment of the image sensor 2, and Fig. 20 to Fig. 25 are timing charts for the pixels in the first to sixth rows, respectively.

[0146] Each pulse is applied to the gate of each transistor, turning the transistor ON at Hi (High) and OFF at Lo (Low). The parentheses in the pulse name correspond to the row number in the schematic diagram mentioned above.

[0147] From time t2002 to time t2021, a global electronic shutter operation is performed in which a voltage signal corresponding to the signal charge of each pixel of the first frame is transferred to the corresponding multilayer circuit 12 of the multilayer substrate 22 simultaneously for all pixels.

[0148] Furthermore, the period from time t2022 to time t2031 is a sequential read-out scanning period for the laminated circuit 12(0q) in the first row of the laminated substrate 22 to the laminated circuit 12(5q) in the sixth row.

[0149] First, from time t2000 to time t2001, PRES1 (0 to 5), PRES2 (0 to 5), PMWS (0 to 5), and PWMN (0 to 5) are set to Hi, and FD and the voltage holding capacitances CS and CN are reset.

[0150] At time t2002, PISW(0) is set to Hi, and the current source I1 for the pixels in the first row is connected to the source side of SEL1.

[0151] Furthermore, at time t2003, PSEL1(0) and PMWN(0) are set to Hi, and at time t2004, PWMN(0) is set to Lo, thereby writing the N signal to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the reset release of the FD.

[0152] Then, PSEL1(0) is set to Lo, and at time t2005, PISW(0) is set to Lo, disconnecting the current source I1 and SEL1 in the first row.

[0153] Next, as the operation for the second row, at time t2003, PISW(1) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1.

[0154] Next, at time t2004, PSEL1(1) and PMWN(1) are set to Hi, and at time t2005, PWMN(1) is set to Lo, thereby writing the N signal to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the reset release of the FD.

[0155] Then, PSEL1(1) is set to Lo, and at time t2006, PISW(1) is set to Lo, disconnecting the current source I1 and SEL1 in the second row.

[0156] Next, as the operation for the third row, at time t2004, PISW(2) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1.

[0157] Next, at time t2005, PSEL1(2) and PWMN(2) are set to Hi, and at time t2006, PWMN(2) is set to Lo, thereby writing the N signal to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the reset release of the FD.

[0158] Then, PSEL1(2) is set to Lo, and at time t2007, PISW(2) is set to Lo, disconnecting the current source I1 and SEL1 in the third row.

[0159] Next, as the operation for the fourth row, at time t2005, PISW(3) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1.

[0160] Next, at time t2006, PSEL1(3) and PWMN(3) are set to Hi, and at time t2007, PWMN(3) is set to Lo, thereby writing the N signal to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the reset release of the FD.

[0161] Then, PSEL1(3) is set to Lo, and at time t2008, PISW(3) is set to Lo, disconnecting the current source I1 and SEL1 in the fourth row.

[0162] Next, as the operation for the fifth row, at time t2006, PISW(4) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1.

[0163] Next, at time t2007, PSEL1(4) and PWMN(4) are set to Hi, and at time t2008, PWMN(4) is set to Lo, thereby writing the N signal to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the reset release of the FD.

[0164] Then, PSEL1(4) is set to Lo, and at time t2009, PISW(4) is set to Lo, disconnecting the current source I1 and SEL1 in the fifth row.

[0165] Next, as the operation for the sixth row, at time t2007, PISW(5) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1.

[0166] Next, at time t2008, PSEL1(5) and PWMN(5) are set to Hi, and at time t2009, PWMN(5) is set to Lo, thereby writing the N signal to the voltage holding capacitance CN of the stacked circuit 12(pq) as the voltage after the reset release of the FD.

[0167] Then, PSEL1(5) is set to Lo, and at time t20010, PISW(5) is set to Lo, disconnecting the current source I1 and SEL1 in the sixth row.

[0168] In this way, when transferring the N signal to the voltage holding capacitance CN for each row, by overlapping some of the control periods, it is possible to shorten the period in which transfer for all rows is completed.

[0169] That is, for example, if the charge accumulated in the charge holding unit in the first row after the reset of the FD is released is defined as the first charge, the first transfer period in which a voltage signal (N signal) corresponding to the first charge is transferred to the voltage holding unit is from t2002 to t2005.

[0170] If the charge stored in the charge holding unit in the second row after the reset of the FD is released is defined as the second charge, the second transfer period in which a voltage signal corresponding to the second charge is transferred to the voltage holding unit is from t2003 to t2006. Thus, in this embodiment, the second transfer period starts before the first transfer period is completed.

[0171] Next, at time t2011, PTX (0 to 5) goes to Hi, and at time t2012, PTX (0 to 5) goes to Lo, whereby the charges accumulated in the PD 10 are transferred to the FD for all pixels at once.

[0172] Next, at time t2013, PISW(0) is set to Hi, and the current source I1 for the pixels in the first row is connected to the source side of SEL1. Next, at time t2014, PSEL1(0) and PMWS(0) are set to Hi, and at time t2015, PWMS(0) is set to Lo, so that the voltage (S signal) of the FD in the first row that has changed according to the signal charge of PD10 is written to the voltage holding capacitance CS.

[0173] Then, PSEL1(0) is set to Lo, and at time t2016, PISW(0) is set to Lo, disconnecting the current source I1 and SEL1 in the first row.

[0174] Next, as the operation for the second row, at time t2014, PISW(1) is set to Hi, and the current source I1 for the pixels in the second row is connected to the source side of SEL1.

[0175] Next, at time t2015, PSEL1(1) and PWMN(1) are set to Hi, and at time t2016, PWMN(1) is set to Lo, thereby writing the voltage (S signal) of the FD in the second row to the voltage holding capacitance CS.

[0176] Then, PSEL1(1) is set to Lo, and at time t2017, PISW(1) is set to Lo, disconnecting the current source I1 in the second row from the source side of SEL1 and SEL1.

[0177] Next, as the operation for the third row, at time t2015, PISW(2) is set to Hi, and the current source I1 for the pixels in the third row is connected to the source side of SEL1.

[0178] Next, at time t2016, PSEL1(2) and PWMN(2) are set to Hi, and at time t2017, PWMN(2) is set to Lo, thereby writing the voltage (S signal) of the FD in the third row to the voltage holding capacitance CS.

[0179] Then, PSEL1(2) is set to Lo, and at time t2018, PISW(2) is set to Lo, disconnecting the current source I1 in the third row from the source side of SEL1 and SEL1.

[0180] Next, as the operation for the fourth row, at time t2016, PISW(3) is set to Hi, and the current source I1 for the pixels in the fourth row is connected to the source side of SEL1.

[0181] Next, at time t2017, PSEL1(3) and PWMN(3) are set to Hi, and at time t2018, PWMN(3) is set to Lo, thereby writing the voltage (S signal) of the FD in the fourth row to the voltage holding capacitance CS.

[0182] Then, PSEL1(3) is set to Lo, and at time t2019, PISW(3) is set to Lo, disconnecting the current source I1 in the fourth row from the source side of SEL1 and SEL1.

[0183] Next, as the operation for the fifth row, at time t2017, PISW(4) is set to Hi, and the current source I1 for the pixels in the fifth row is connected to the source side of SEL1.

[0184] Next, at time t2018, PSEL1(4) and PWMN(4) are set to Hi, and at time t2019, PWMN(4) is set to Lo, thereby writing the voltage (S signal) of the FD in the fifth row to the voltage holding capacitance CS.

[0185] Then, PSEL1(4) is set to Lo, and at time t2020, PISW(4) is set to Lo, disconnecting the current source I1 in the fifth row from the source side of SEL1 and SEL1.

[0186] Next, as the operation for the sixth row, at time t2018, PISW(5) is set to Hi, and the current source I1 for the pixels in the sixth row is connected to the source side of SEL1.

[0187] Next, at time t2019, PSEL1(5) and PWMN(5) are set to Hi, and at time t2020, PWMN(5) is set to Lo, thereby writing the voltage (S signal) of the FD in the sixth row to the voltage holding capacitance CS.

[0188] Then, PSEL1(5) is set to Lo, and at time t2021, PISW(5) is set to Lo, disconnecting the current source I1 in the sixth row from the source side of SEL1 and SEL1.

[0189] In this way, when the S signal is transferred to the voltage holding capacitance CS for each row, by overlapping some of the control periods, it is possible to shorten the period required to complete the transfer for all rows.

[0190] That is, for example, if the signal charge stored in the charge holding section in the first row is the first charge, the first transfer period in which a voltage signal (S signal) corresponding to the first charge is transferred to the voltage holding section is from t2013 to t2016.

[0191] If the charge accumulated in the charge holding unit in the second row after the reset of the FD is released is the second charge, then the second transfer period in which a voltage signal (S signal) corresponding to the second charge is transferred to the voltage holding unit is from t2014 to t2017. In this way, the second transfer period for the S signal also starts before the first transfer period is completed.

[0192] In this manner, in the fourth embodiment, it is possible to suppress the peak current flowing through the amplifying transistor SF1 while maintaining global characteristics, and further to prevent deterioration of image quality.

[0193] Next, from time t2022 to time t2024, signals in the first row are read out. From time t2022 to time t2031, in relation to the readout operation for each row, the transfer of N signals to the vertical output lines and AD conversion of the N signals, and the transfer of S signals and AD conversion of the S signals are sequentially performed for each row. This operation is similar to the operation from time t624 to time t632 in the first embodiment, and therefore a description thereof will be omitted.

[0194] In this way, in the fourth embodiment, when the charges transferred in a lump to the FD are transferred from the FD to the voltage holding unit, the row-by-row control is partially overlapped in order to shorten the transfer period from the FD to the voltage holding unit.

[0195] As described above, in the fourth embodiment, it is possible to reduce the peak power of the image sensor 2 while maintaining globality, and by partially overlapping row-by-row control, it is possible to further shorten the charge retention period in the FD, thereby making it possible to prevent deterioration of image quality more than in the first embodiment.

[0196] The disclosure of this embodiment includes the following configurations of an imaging device and the like.

[0197] (Configuration 1) an image sensor comprising: a photoelectric conversion unit; a plurality of pixels each having a charge holding unit that accumulates charge generated in the photoelectric conversion unit; a voltage holding unit that holds a voltage signal corresponding to the charge of the charge holding unit; a source follower unit for transferring the voltage signal to the voltage holding unit; a current source that drives the source follower unit; and a current source control unit that controls the current source, wherein charges generated in the photoelectric conversion unit are transferred all at once to the charge holding unit, and the current source control unit sequentially connects the source follower units and the current source to sequentially transfer the voltage signal corresponding to the charge accumulated in the charge holding unit to the voltage holding unit.

[0198] (Configuration 2) The image sensor according to configuration 1, wherein the voltage holding unit is provided for each of the pixels.

[0199] (Configuration 3) 3. The imaging element of configuration 1 or 2, wherein the voltage signal corresponding to the charge accumulated in the charge holding portion is transferred sequentially for each row in a matrix arrangement of the pixels.

[0200] (Configuration 4) The imaging element according to any one of configurations 1 to 3, wherein the voltage signal corresponding to the charge accumulated in the charge holding portion is transferred sequentially for each predetermined region in a matrix arrangement of the pixels.

[0201] (Configuration 5) An imaging element according to any one of configurations 1 to 4, wherein the source follower section is shared by a plurality of the pixels.

[0202] (Configuration 6) The imaging element according to any one of configurations 1 to 5, further comprising an AD conversion unit that converts the voltage signals into digital signals, the AD conversion unit sequentially converting the voltage signals held in the voltage holding unit into the digital signals.

[0203] (Configuration 7) 7. The imaging element of any one of configurations 1 to 6, characterized in that a first transfer period in which the voltage signal corresponding to a first charge accumulated in the charge holding section is transferred to the voltage holding section, and a second transfer period in which the voltage signal corresponding to a second charge accumulated in the charge holding section is transferred to the voltage holding section, and the second transfer period is started before the first transfer period is completed.

[0204] (method) A control method for controlling an imaging element comprising: a photoelectric conversion unit; a plurality of pixels each having a charge holding unit that accumulates charge generated in the photoelectric conversion unit; a voltage holding unit that holds a voltage signal corresponding to the charge of the charge holding unit; a source follower unit for transferring the voltage signal to the voltage holding unit; a current source that drives the source follower unit; and a current source control unit that controls the current source, the control method comprising the steps of: transferring the charge generated in the photoelectric conversion unit to the charge holding unit all at once; sequentially connecting the source follower unit and the current source; and sequentially transferring the voltage signal corresponding to the charge accumulated in the charge holding unit to the voltage holding unit.

[0205] (Computer Program) A computer program for controlling each part of the imaging element of any one of configurations 1 to 7 by a computer.

[0206] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention. [Explanation of symbols]

[0207] A: Imaging device 2: Image sensor 10: PD (photoelectric conversion unit) 11: Pixel circuit 12: Multilayer circuit 20: Vertical scanning circuit (current source control section) 21: PD board 22:Laminated substrate FD: Floating diffusion (charge retention section) MEM: Charge retention capacitor (charge retention part) SF1, SF2: Amplification transistor (source follower section) CONT: Contact CN, CS: Voltage holding capacitance (voltage holding section) I1,I2: Current source

Claims

1. A photoelectric conversion unit; a plurality of pixels each having a charge storage unit that stores charges generated in the photoelectric conversion unit; a voltage holding unit that holds a voltage signal corresponding to the charge of the charge holding unit; a source follower unit for transferring the voltage signal to the voltage holding unit; A current source that drives the source follower section; a current source control unit for controlling the current source; Equipped with The charges generated in the photoelectric conversion unit are transferred to the charge storage unit in a lump. The current source control unit sequentially connects the source follower unit and the current source to sequentially transfer the voltage signal corresponding to the charge stored in the charge holding unit to the voltage holding unit.

2. The image sensor according to claim 1 , wherein the voltage holding section is provided for each of the pixels.

3. The image sensor according to claim 1 , wherein the voltage signal corresponding to the charge stored in the charge holding portion is transferred sequentially for each row in a matrix arrangement of the pixels.

4. The image sensor according to claim 1 , wherein the voltage signal corresponding to the charge stored in the charge holding portion is transferred sequentially for each predetermined region in the matrix arrangement of the pixels.

5. The image sensor according to claim 1 , wherein the source follower section is shared by a plurality of the pixels.

6. an AD conversion unit for converting the voltage signal into a digital signal; 2. The image sensor according to claim 1, wherein the AD conversion section sequentially converts the voltage signals held in the voltage holding section into the digital signals.

7. a first transfer period in which the voltage signal corresponding to the first charge stored in the charge storage unit is transferred to the voltage storage unit; a second transfer period in which the voltage signal corresponding to the second charge stored in the charge storage section is transferred to the voltage storage section; and 2. The image sensor according to claim 1, wherein the second transfer period starts before the first transfer period is completed.

8. A photoelectric conversion unit; a plurality of pixels each having a charge storage unit that stores charges generated in the photoelectric conversion unit; a voltage holding unit that holds a voltage signal corresponding to the charge of the charge holding unit; a source follower unit for transferring the voltage signal to the voltage holding unit; A current source that drives the source follower section; a current source control unit for controlling the current source; A control method for controlling an imaging element comprising: The charges generated in the photoelectric conversion unit are transferred to the charge storage unit in a lump; a control method for sequentially connecting the source follower unit and the current source to sequentially transfer the voltage signal corresponding to the charge stored in the charge storage unit to the voltage storage unit.

9. A computer program for controlling each unit of the imaging device according to any one of claims 1 to 7 by a computer.

Images