FRONT SIDE OHMIC CONTACT FORMATION FOR SiC DEVICE
The method of forming schottky and ohmic contacts using a single metal layer with a laser annealing process addresses the complexity and cost issues of conventional SiC power device manufacturing by reducing direct metal removal, enhancing reliability and efficiency.
Patent Information
- Application Number
- JP2024095088
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-06-26
- Filing Date
- 2024-06-12
- Publication Date
- 2025-01-28
AI Technical Summary
Conventional methods for forming ohmic contacts in silicon carbide (SiC) power devices require complex processes involving high-temperature annealing and direct removal of metal deposits, which can damage the device and increase production costs and complexity.
A method involving a single metal layer with a laser annealing process to form both schottky and ohmic contacts, using a reflective barrier layer to prevent direct contact removal, reducing the risk of damage and simplifying the manufacturing process.
This approach enhances the reliability and reduces manufacturing costs by eliminating the need for direct metal removal, thereby improving the efficiency and consistency of SiC power device production.
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Figure 2025013749000001_ABST
Abstract
Description
[Technical field]
[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Patent Application No. 18 / 341,147, filed June 26, 2023, the entire contents of which are incorporated herein by reference.
[0002] Exemplary embodiments of the present disclosure relate generally to the field of silicon carbide (SiC) power devices, and more particularly to surface ohmic contact formation for SiC power devices. [Background technology]
[0003] Applicant has recognized many of the technical challenges and difficulties associated with SiC devices, such as SiC power devices, and through applied effort, ingenuity, and innovation, Applicant has solved the problems associated with manufacturing SiC power devices by developing the solutions embodied in the present disclosure, which are described in detail below. Summary of the Invention
[0004] Various embodiments described herein relate to systems, apparatus, articles, and methods for the manufacture and use of SiC power devices.
[0005] In some embodiments, a method includes providing a semiconductor substrate including a first side and a second side, the semiconductor substrate comprising a silicon carbide (SiC) material; forming a first metal layer on the first side of the semiconductor substrate to form a Schottky contact; forming a second metal layer on the first metal layer to form a reflective barrier layer over the Schottky contact; removing one or more portions of the second metal layer to expose a first portion of the first metal layer; and forming one or more silicide portions on the first metal layer by a laser annealing process to form one or more ohmic contacts in the Schottky contact.
[0006] In some embodiments, the first metal layer forms one or more ohmic and Schottky contacts in the p+ region.
[0007] In some embodiments, the method further includes forming a dielectric layer on the first side of the semiconductor substrate subsequent to forming the one or more silicide portions on the first metal layer, the dielectric layer may cover the semiconductor substrate, the first metal layer, and the second metal layer.
[0008] In some embodiments, the method includes placing a dielectric layer mask over one or more peripheral dielectric portions of the dielectric layer, etching the interior dielectric portion from the dielectric layer to expose the second metal layer and one or more silicide portions on the first metal layer, and removing the dielectric layer mask.
[0009] In some embodiments, the method includes forming a surface metal layer over a first side of a semiconductor substrate, a dielectric layer, a first metal layer, and a second metal layer, disposing a surface metal layer mask over an interior portion of the surface metal layer, etching a peripheral surface metal portion from the surface metal layer to expose the dielectric layer, and removing the surface metal layer mask.
[0010] In some embodiments, the method includes forming a passivation layer over the dielectric layer and the surface metal layer, disposing a passivation layer mask over a peripheral portion of the passivation layer, etching the interior passivation layer portion from the passivation layer to expose the surface metal layer, and removing the passivation layer mask.
[0011] In some embodiments, removing one or more portions of the second metal layer includes disposing a patterned mask over the second metal layer. The patterned mask may expose one or more portions of the second metal layer. The method may include etching the second metal layer through the patterned mask to remove one or more portions of the second metal layer and removing the patterned mask.
[0012] In some embodiments, the method includes forming one or more silicide portions on the first metal layer followed by removing one or more peripheral portions of the first metal layer and the second metal layer to expose at least a portion of the semiconductor substrate.
[0013] In some embodiments, removing one or more peripheral portions of the first metal layer includes placing an internal mask over the second metal layer, the internal mask exposing one or more peripheral portions of the second metal layer, and etching the second metal layer and the first metal layer around the internal mask to remove the one or more peripheral portions of the second metal layer and the first metal layer.
[0014] In some embodiments, the semiconductor substrate includes one or more anode implants, and the one or more silicide portions on the first metal layer correspond to the one or more anode implants.
[0015] In some embodiments, the method includes forming one or more anode implants in the first side of the semiconductor substrate.
[0016] In some embodiments, the first side of the semiconductor substrate includes an epitaxial drift layer and the second side of the semiconductor substrate includes a doped SiC substrate.
[0017] In some embodiments, the method includes forming a back ohmic contact on a second side of the semiconductor substrate and forming a back metal layer over the back ohmic contact.
[0018] In some embodiments, the first metallic layer comprises a nickel-based material.
[0019] In some embodiments, the second metallic layer comprises an aluminum-based material.
[0020] In some embodiments, a silicon carbide (SiC) power device includes a semiconductor substrate having a first side and a second side; a first metal layer disposed on the first side of the semiconductor substrate, a first portion of the first metal layer forming one or more ohmic contacts and a second portion of the first metal layer forming a Schottky contact; and a second metal layer disposed on the second portion of the first metal layer.
[0021] In some embodiments, the first side of the semiconductor substrate includes an epitaxial drift layer.
[0022] In some embodiments, the second side of the semiconductor substrate comprises a doped SiC substrate.
[0023] In some embodiments, the first metallic layer comprises a nickel material.
[0024] In some embodiments, the second metal layer comprises an aluminum material.
[0025] The above summary has been provided merely for the purpose of summarizing some exemplary embodiments to provide a basic understanding of some aspects of the present disclosure. As such, it will be understood that the above-described embodiments are merely examples and should not be construed to narrow the scope or spirit of the present disclosure in any way. It will also be understood that the scope of the present disclosure encompasses many potential embodiments in addition to those summarized herein, some of which are further described below. [Brief description of the drawings]
[0026] Having thus described in general terms certain exemplary embodiments of the present disclosure, reference is now made to the accompanying drawings, which are not necessarily drawn to scale.
[0027] [Figure 1] 1 illustrates an exemplary computing entity in accordance with one or more embodiments of the present disclosure. [Figure 2A] 1 illustrates an exemplary SiC power device in accordance with one or more embodiments of the present disclosure. [Figure 2B] 1 illustrates an exemplary SiC power device in accordance with one or more embodiments of the present disclosure. [Figure 3A] 1 illustrates exemplary stages for manufacturing a SiC device according to one or more embodiments of the present disclosure. [Figure 3B] 1 illustrates exemplary stages for manufacturing a SiC device according to one or more embodiments of the present disclosure. [Figure 3C] 1 illustrates exemplary stages for manufacturing a SiC device according to one or more embodiments of the present disclosure. [Figure 3D] 1 illustrates exemplary stages for manufacturing a SiC device according to one or more embodiments of the present disclosure. [Figure 4] 1 shows a flowchart of an exemplary method for manufacturing a SiC device in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0028] Embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are illustrated. Indeed, various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.
[0029] Various exemplary embodiments of the present disclosure are directed to improved SiC devices, as well as systems, apparatus, articles, and methods for fabricating the improved SiC devices. The present disclosure describes, in some examples, methods for achieving surface ohmic contacts for SiC merged pin Schottky (MPS) devices, among other SiC devices, that improve upon conventional techniques for fabricating SiC devices.
[0030] Conventionally, complex process flows are required to achieve ohmic contact formation on p+ and / or n+ regions of SiC devices. Ohmic contact formation may require (i) metal deposition, such as nickel or other conductive material, (ii) annealing temperatures approaching 1000° C. to induce a reaction between the metal deposition and SiC (e.g., to form silicide, titanium silicide, etc.), and (iii) removal of portions of the metal deposition in direct contact with the SiC surface. Selective removal of portions of the metal deposition may be complex and, in part due to the complexity, unreliable and error prone, yet critical to the functionality of the SiC device. Thus, conventional techniques for manufacturing SiC devices face technical challenges that reduce their reliability while increasing failure rates and the cost and expense of manufacturing.
[0031] To address these technical challenges, some embodiments of the present disclosure provide an improved SiC formation that includes a single layer of metal to achieve both Schottky and Ohmic contacts. The Schottky and Ohmic contacts can be achieved through a laser annealing process by shielding the single layer of metal with a patterned second metal layer. Each layer may not be sacrificial and may be part of the active area of the SiC device, thereby reducing the risk of damaging the SiC device by removing a metal layer that is in direct contact with the SiC surface. In some embodiments of the present disclosure, the technique includes providing a semiconductor substrate having a first side and a second side, forming a first metal layer on the first side of the semiconductor substrate to form a Schottky contact, forming a second metal layer on the first metal layer to form a reflective barrier layer covering the Schottky contact, removing one or more portions of the second metal layer to expose a first portion of the first metal layer, and forming one or more silicide portions (e.g., titanium silicide, etc.) on the first metal layer by a laser annealing process to form one or more ohmic contacts in the Schottky contact. By doing so, the exemplary technique of the present disclosure addresses technical challenges for SiC devices by eliminating the need to remove metal deposits in direct contact with the SiC surface. In this manner, various embodiments of the present disclosure prevent damage to SiC devices during fabrication while reducing manufacturing costs, efficiency, and reliability.
[0032] It should be readily understood that the embodiments of the systems, apparatus, and methods described herein may be configured in a variety of additional and alternative ways in addition to those explicitly described herein.
[0033] 1 illustrates an exemplary computing system 100 in accordance with one or more embodiments of the present disclosure. In general, computing system, computer, system, device, entity, and / or similar terms used interchangeably herein may refer to, for example, one or more computers, computing entities, desktops, mobile phones, tablets, notebooks, laptops, distributed systems, kiosks, input terminals, servers or server networks, blades, gateways, switches, processing devices, processing entities, set-top boxes, relays, routers, network access points, base stations, etc., and / or any combination of devices or entities adapted to perform the functions, operations, and / or processes described herein. Such functions, operations, and / or processes may include, for example, transmitting, receiving, operating on, processing, displaying, storing, determining, creating / generating, monitoring, evaluating, comparing, and / or similar terms used interchangeably herein. In an embodiment, these functions, operations, and / or processes may be performed on data, content, information, and / or similar terms used interchangeably herein.
[0034] Computing system 100 may include computing device 110 and / or one or more computing entities 120 communicatively coupled to computing device 110 using one or more wired and / or wireless communication techniques. Computing device 110 may include any computing device including, for example, one or more servers, computing platforms, and / or the like specifically configured to perform one or more steps / operations of one or more manufacturing techniques described herein. In some embodiments, computing device 110 may include and / or be associated with one or more mobile device(s), desktop computer(s), laptop(s), server(s), cloud computing platform(s), and / or the like. In some exemplary embodiments, computing device 110 may be configured to receive and / or provide power conversion instructions, data, and / or the like to and from one or more computing entities 120 to perform one or more steps / operations of one or more manufacturing techniques described herein.
[0035] In some embodiments, the computing device 110 includes, is integrated with, and / or is otherwise associated with one or more computing entities 120. The one or more computing entities 120 may include one or more semiconductor manufacturing devices, such as one or more reactive etching devices 114 (e.g., ion etching devices, chemical etching devices, physical etching devices, etc.), one or more laser annealing machines 112 (e.g., ultraviolet lasers, fiber lasers, carbon dioxide lasers, etc.), chemical, physical, atomic and / or the like deposition devices (e.g., plasma enhanced chemical vapor deposition (PECVD), sputter vapor deposition, thermal evaporation, arc vapor deposition, etc.). For example, the computing device 110 may be configured to receive and / or provide one or more manufacturing instructions between one or more components of the one or more computing entities 120. The computing entities 120 may include and / or be associated with one or more manufacturing systems configured to perform one or more manufacturing operations, for example, to manufacture SiC and / or other power devices. The one or more manufacturing systems may be configured to manufacture one or more SiC power devices (e.g., MOSFETs, diodes, IGBTs, etc.) for use with, for example, one or more converters, inverters, power supplies, battery chargers, motor control systems, and / or the like.
[0036] Computing device 110 may include or communicate with one or more processing elements 102 (also referred to as processors, processing circuits, digital circuits, and / or similar terms used interchangeably herein) that communicate with other elements within computing device 110, for example, via a bus. As will be appreciated, processing element 102 may be embodied in a number of different ways.
[0037] For example, the processing element 102 may be embodied as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, co-processing entities, application specific instruction set processors (ASIPs), microcontrollers, and / or controllers. Additionally, the processing element 102 may be embodied as one or more other processing devices or circuits. The term circuitry may refer to an entirely hardware embodiment or a combination of hardware and computer program products. Thus, the processing element 102 may be embodied as an integrated circuit, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, a digital circuit, and / or the like.
[0038] It will thus be appreciated that processing element 102 may be configured for a particular application or may be configured to execute instructions stored on a volatile or non-volatile medium or accessible to processing element 102. Thus, whether configured by hardware or a computer program product, or a combination thereof, processing element 102, when configured accordingly, may be capable of performing steps or operations according to embodiments of the present disclosure.
[0039] In one embodiment, the computing device 110 may further include or communicate with one or more memory elements 104. The one or more memory elements 104 may include non-volatile and / or volatile media. The memory elements 104 may include, for example, non-volatile media (also referred to as non-volatile storage, memory, memory storage, memory circuits, and / or similar terms used interchangeably herein). In one embodiment, the non-volatile storage or memory may include one or more non-volatile storage or memory media, including, but not limited to, a hard disk, a ROM, a PROM, an EPROM, an EEPROM, a flash memory, an MMC, an SD memory card, a memory stick, a CBRAM, a PRAM, a FeRAM, a NVRAM, a MRAM, a RRAM, a SONOS, an FJG RAM, a Millipede memory, a racetrack memory, and / or the like.
[0040] As will be appreciated, a non-volatile storage or memory medium may store databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like. The terms database, database instance, database management system, and / or similar terms used interchangeably herein may refer to a collection of records or data stored in a computer-readable storage medium using one or more database models, such as a hierarchical database model, a network model, a relational model, an entity-relationship model, an object model, a document model, a semantic model, a graph model, and / or the like.
[0041] Additionally or alternatively, memory element 104 may include volatile memory. For example, computing device 110 may further include or communicate with volatile media (also referred to as volatile storage memory, memory storage, memory circuitry, and / or similar terms used interchangeably herein). In one embodiment, volatile storage or memory may include one or more volatile storage or memory media, including, but not limited to, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, registered memory, and / or the like.
[0042] As will be appreciated, the volatile storage or memory medium may be used to store at least a portion of, for example, databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like being executed by the processing elements 102. Thus, the databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like may be used to control certain aspects of the operation of the computing device 110 with the aid of the processing elements 102 and the operating system.
[0043] As shown, in one embodiment, computing device 110 may also include one or more communication interfaces 108 for communicating with various computing entities, including computing entity 120, such as by communicating data, content, information, and / or similar terms used interchangeably herein, which may be transmitted, received, operated on, processed, displayed, stored, and / or the like. One or more communication interfaces 108 may include, for example, one or more wired peripherals (e.g., fiber interfaces, Ethernet ports, and / or the like), antennas, transmitters, receivers, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), modulators, demodulators, and / or the like. Such communications may be performed using a wired data transmission protocol, such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Data Over Cable Service Interface Specification (DOCSIS), or any other wired transmission protocol.Similarly, the computing device 110 may be configured to support any of the following wireless technologies: General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution Data Optimized (EVDO), High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), IEEE 802.9 (Wi-Fi), Wi-Fi It may be configured to communicate over a wireless external communications network using any of a variety of protocols, such as Direct, 802.16 (WiMAX), ultra-wideband (UWB), infrared (IR) protocols, NFC protocols such as NFC-A, NFC-B, NFC-F, Wibree, Bluetooth protocols, wireless universal serial bus (USB) protocols, and / or any other wireless protocols.
[0044] Computing device 110 may include input / output circuitry for communicating with one or more users. The input / output circuitry may include, for example, one or more user interfaces for providing and / or receiving information from one or more users of computing device 110. The input / output interfaces may include one or more tactile interfaces (e.g., keypads, touch screens, etc.), one or more audio interfaces (e.g., microphones, speakers, etc.), visual interfaces (e.g., display devices, etc.), and / or the like. The input / output circuitry may be configured to receive user input from a user of computing device 110 via one or more of the user interfaces and to provide data to the user via one or more of the user interfaces.
[0045] Exemplary embodiments of the present disclosure describe improved SiC power device structures that can be manufactured using improved manufacturing techniques that eliminate the need to remove metal materials in contact with the SiC surface, which reduces manufacturing complexity and risk of damage, among other advantages described herein.
[0046] 2A illustrates an example SiC power device 200 according to one or more embodiments of the present disclosure. The SiC power device 200 may be manufactured using one or more of the improved manufacturing techniques of the present disclosure. The SiC power device 200 or the SiC power device 200 may include a semiconductor device having multiple material layers.
[0047] In some embodiments, the SiC power device 200 includes a semiconductor substrate 202. The semiconductor substrate 202 may include a SiC material. The SiC material may extend laterally along a base surface 224. In some examples, the SiC material may include a wide band gap semiconductor material. The semiconductor substrate 202 may include a first side and a second side. The first side may include an epitaxial drift layer 204. The second side may include a doped SiC substrate 206. The doped SiC substrate 206 may be doped with one or more combinations of aluminum, boron, gallium, and / or the like, for example, to produce a P-type SiC power device. Additionally or alternatively, the doped SiC substrate 206 may be doped with one or more combinations of nitrogen, phosphorous, and / or the like to produce an N-type SiC power device.
[0048] In some embodiments, the semiconductor substrate 202 includes one or more anode implants 214. The anode implants 214 may be disposed in the epitaxial drift layer 204. In some examples, the anode implants 214 may extend vertically from a surface of the epitaxial drift layer 204 toward the base surface 224. In some examples, the anode implants may include epitaxially grown guard rings.
[0049] In some embodiments, the SiC power device 200 includes a first metal layer 208 and / or a second metal layer 212. The first metal layer 208 may be disposed on a first side of the semiconductor substrate 202. For example, the first metal layer 208 may be disposed on a surface of the epitaxial drift layer 204. The first metal layer 208 may be disposed directly on the surface of the epitaxial drift layer 204. In some examples, the first metal layer 208 may cover an anode implant. The first metal layer 208 may extend laterally along the surface 226 of the epitaxial drift layer 204, for example. The first metal layer may comprise an electrically and / or thermally conductive metal such as nickel material (chemical symbol Ni), gold (chemical symbol Au), germanium (chemical symbol Ge), tin (chemical symbol Sn), indium tin oxide, titanium (chemical symbol Ti), molybdenum (chemical symbol Mo), tungsten (chemical symbol W), titanium nitride (chemical symbol TiN), molybdenum nitride (chemical symbol MoN), tungsten nitride (chemical symbol WN), and / or the like.
[0050] In some embodiments, the first metal layer 208 forms one or more ohmic contacts 210 and / or Schottky contacts for the SiC power device 200. For example, a single first metal layer 208 may form both an ohmic contact 210 and a Schottky contact. The first metal layer 208 may form one or more ohmic contacts 210 and a Schottky contact in the same plane (e.g., surface 226). By way of example, one or more ohmic contacts 210 and a Schottky contact may be formed in a p+ region of the SiC device (e.g., to prevent shorting behavior during bias application, etc.).
[0051] For example, a first portion of the first metal layer 208 may form one or more ohmic contacts 210 and / or a second portion of the first metal layer 208 may form a Schottky contact. In some examples, the one or more ohmic contacts may include one or more silicide portions (e.g., titanium silicide, etc.) on the first metal layer 208. The one or more silicide portions may correspond to one or more anode implants 214. For example, the silicide portions may be disposed directly on one or more of the anode implants 214.
[0052] In some embodiments, the second metal layer 212 is disposed on the first metal layer 208. For example, the second metal layer 212 may be disposed directly on the first metal layer 208. The second metal layer 212 may extend laterally along the barrier surface 228 above the first metal layer 208, for example. In some examples, the second metal layer 212 may include one or more cutouts that expose one or more portions of the first metal layer 208. For example, the second metal layer 212 may be disposed on a second portion of the first metal layer 208, exposing a first portion of the first metal layer 208 (e.g., ohmic contact 210). The second metal layer may include a reflective metal such as an aluminum material (chemical symbol Al) and / or the like. As described herein, the second metal layer 212 may act as a barrier layer during fabrication of the SiC power device 200. The second metal layer 212 may not be a sacrificial layer and may be part of the active area of the SiC power device 200 .
[0053] In some embodiments, the SiC power device 200 includes a surface metal layer 216 and / or a passivation layer 218. The surface metal layer 216 may include any type of metal layer, including, by way of example, aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, tantalum, and / or the like. The surface metal layer 216 may be disposed on the first metal layer 208 and / or the second metal layer 212. For example, the surface metal layer 216 may directly cover the exposed portions of the second metal layer 212 and the first metal layer 208 (e.g., the ohmic contacts 210). The passivation layer 218 may include any type of insulating material, such as an oxide, a nitride, and / or the like. The passivation layer 218 may be disposed on a first side of the semiconductor substrate 202. For example, the passivation layer 218 may directly cover the exposed surface portion of the epitaxial drift layer 204.
[0054] In some embodiments, the SiC power device 200 includes a backside ohmic contact 220 and / or a backside metal layer 222. The backside ohmic contact 220 may extend laterally along a backside surface 230 on a surface of the second side (e.g., doped SiC substrate 206) of the semiconductor workpiece 202. The backside ohmic contact 220 may include any electrically and / or thermally conductive metal, including, by way of example, nickel (chemical symbol Ni), gold (chemical symbol Au), germanium (chemical symbol Ge), tin (chemical symbol Sn), indium tin oxide, and / or the like. The backside metal layer 222 may extend laterally along a second plane 232 on the surface of the backside ohmic contact 220. The backside metal layer 222 may include any type of metal layer, including, by way of example, aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, tantalum, and / or the like.
[0055] 2B illustrates another exemplary SiC power device 250 according to one or more embodiments of the present disclosure. The SiC power device 250 may be fabricated using one or more of the improved fabrication techniques of the present disclosure. The SiC power device 250 may include a semiconductor device having multiple material layers, including some of the metal layers described herein with reference to the SiC power device 250. In some examples, the SiC power device 250 may include a SiC power device with a field plate edge termination. For example, the SiC power device 250. For example, in addition to the metal, SiC, and / or passivation layers of the SiC power device 200, the SiC power device 250 may include one or more dielectric layers 252. The dielectric layer 252 may cover one or more peripheral portions of the semiconductor substrate 202. For example, the dielectric layer 252 may separate the semiconductor substrate 202 from the passivation layer 218 and the surface metal layer 216.
[0056] The SiC power devices 200 and 250 may be manufactured using improved semiconductor fabrication techniques, some of which are described in further detail with reference to Figures 3A-3D.
[0057] 3A illustrates an exemplary first stage of a manufacturing process 300 for fabricating a SiC device according to one or more embodiments of the present disclosure. The first stage may include a first manufacturing operation 302. During the first manufacturing operation 302, a semiconductor substrate 202 may be provided. The semiconductor substrate 202 may include a first side 202A and a second side 202B. The semiconductor substrate 202 may include a SiC material. In some examples, the first side 202A may include an epitaxial drift layer 204 and the second side 202B may include a doped SiC substrate 206. During the first manufacturing operation 302, an anode mask 304 may be disposed over the first side 202A of the semiconductor substrate 202. The anode mask 304 may include a patterned mask having one or more cutouts for one or more anode implants. An anode implant operation may be applied through the anode mask 304 to form one or more anode implants in the epitaxial drift layer 204 of the semiconductor substrate 202 .
[0058] The first stage may include a second fabrication operation 306. During the second fabrication operation 306, the anode mask 304 may be removed from a surface of the first side 202A of the semiconductor substrate 202. The first stage may include a third fabrication operation 308, which may form one or more anode implants 214 in the first side 202A of the semiconductor substrate 202 (e.g., the epitaxial drift layer 204). In some examples, the third fabrication operation 308 may include dopant activation. The dopant activation may include a high temperature anneal (e.g., about 1600 C, etc.).
[0059] The first stage may include a fourth manufacturing operation 310. During the fourth manufacturing operation 310, a first metal layer 208 may be formed on the first side 202A of the semiconductor substrate 202 to form a Schottky contact. The first metal layer 208 may be formed using one or more metal deposition techniques, such as one or more laser metal deposition, direct metal deposition, cold spray metal deposition, and / or the like. In some examples, the first metal layer may include a titanium-based material and / or any other electrically and / or thermally conductive metal (e.g., nickel-based, etc.).
[0060] The first stage may include a fifth fabrication operation 312. During the fifth fabrication operation 312, a second metal layer 212 may be formed over the first metal layer 208 to form a reflective barrier layer over the Schottky contact. The second metal layer 212 may be formed using one or more metal deposition techniques described herein. In some examples, the second metal layer may include an aluminum-based material and / or any other reflective metal.
[0061] The first stage may include a sixth manufacturing operation 314. During the sixth manufacturing operation 314, a patterned mask 316 may be disposed over the second metal layer 212. The patterned mask 316 may expose one or more portions 318 of the second metal layer 212.
[0062] Referring to FIG. 3B, FIG. 3B illustrates an exemplary second stage of a manufacturing process 300 for producing a SiC device in accordance with one or more embodiments of the present disclosure.
[0063] The second stage may include a seventh manufacturing operation 320. During the seventh manufacturing operation 320, one or more exposed portions of the second metal layer 212 may be removed to expose the first portion 322 of the first metal layer 208. In some examples, one or more exposed portions of the second metal layer 212 may be etched to expose the first portion 322 of the first metal layer 208. For example, the second metal layer 212 may be etched through a patterned mask 316 to remove one or more portions of the second metal layer 212 to expose the first portion 322 of the first metal layer 208. The second metal layer 212 may be etched using one or more etching techniques such as chemical etching, mechanical etching, wet etching, dry etching, and / or the like. The second stage may include an eighth manufacturing operation 321, in which the patterned mask 316 may be removed from the second metal layer 212.
[0064] The second stage may include a ninth manufacturing operation 324. During the ninth manufacturing operation 324, one or more silicide portions (e.g., titanium silicide, etc.) may be formed on the first metal layer 208 to form one or more ohmic contacts 210 in the Schottky contact. In some examples, the one or more silicide portions may be formed through a laser annealing process. The laser annealing process may include, for example, applying a laser annealing machine 112 to the first metal layer 208 through a reflective layer of the second metal layer 212. In this manner, the first metal layer 208 may form one or more ohmic contacts 210 and / or Schottky contacts in the same plane. In some examples, the one or more silicide portions on the first metal layer 208 may correspond to one or more anode implants 214. For example, each silicide portion may be aligned with at least one of the one or more anode implants 214. In this manner, ohmic contacts 210 and / or Schottky contacts may be formed on the p+ regions of the SiC device to ensure proper turn-on of the PN junction when high currents are required.
[0065] The second stage may include a tenth manufacturing operation 326. During the tenth manufacturing operation 326, an interior mask 328 may be disposed over the second metal layer 212. The interior mask 328 may expose one or more peripheral portions 330 of the second metal layer 212 while covering interior portions of the second metal layer 212 and the first metal layer 208, including the ohmic contacts 210.
[0066] The second stage may include an eleventh manufacturing operation 332. During the eleventh manufacturing operation 332, following forming one or more silicide portions on the first metal layer 208, one or more peripheral portions 330 of the first metal layer 208 and the second metal layer 212 may be removed to expose at least a portion of the semiconductor substrate 202. For example, the second metal layer 212 and / or the first metal layer 208 may be etched around the interior mask 328 to remove one or more peripheral portions 330 of the second metal layer 212 and / or the first metal layer 208. The first and second metal layers may be etched using any etching process, such as those described herein. The second stage may include a twelfth manufacturing operation 334, during which the interior mask 328 may be removed to expose an interior portion of the second metal layer 212 and the first metal layer 208, including the ohmic contact 210.
[0067] Referring to FIG. 3C, FIG. 3C illustrates an exemplary third stage of a manufacturing process 300 for producing a SiC device in accordance with one or more embodiments of the present disclosure.
[0068] The third phase may include a thirteenth manufacturing operation 336. During the thirteenth manufacturing operation 336, following the formation of one or more silicide portions on the first metal layer 208, a dielectric layer 338 may be formed on the first side 202A of the semiconductor substrate 202. The dielectric layer 338 may cover the semiconductor substrate 202, the first metal layer 208, and / or the second metal layer 212.
[0069] The third stage may include a fourteenth manufacturing operation 340. During the fourteenth manufacturing operation 340, a dielectric layer mask 344 may be disposed over one or more peripheral dielectric portions 342 of the dielectric layer 338. During a fifteenth manufacturing operation 346, an interior dielectric portion may be etched from the dielectric layer 338 to expose the second metal layer 212 and / or one or more silicide portions (e.g., ohmic contacts 210) on the first metal layer 208. During a sixteenth operation 348, the dielectric layer mask 344 may be removed to expose the peripheral dielectric portions 342 of the dielectric layer 338.
[0070] The third stage may include a seventeenth manufacturing operation 350. During the seventeenth manufacturing operation 350, a surface metal layer 352 may be formed on the first side 202A of the semiconductor workpiece 202, the dielectric layer 338, the first metal layer 208, and / or the second metal layer 212. The third stage may include an eighteenth manufacturing operation 354, in which a surface metal layer mask 356 may be disposed on an interior portion of the surface metal layer 352.
[0071] Referring to FIG. 3D, FIG. 3D illustrates an exemplary fourth stage of a manufacturing process 300 for producing a SiC device in accordance with one or more embodiments of the present disclosure.
[0072] The fourth stage may include a nineteenth manufacturing operation 358. During the nineteenth manufacturing operation 358, a peripheral surface metal portion may be removed from the surface metal layer 352 to expose the dielectric layer 338. For example, the peripheral surface metal portion may be etched around the surface metal layer mask 356 to remove the peripheral surface metal portion from the surface metal layer 352 and expose the dielectric layer 338. The fourth stage may include a twentieth manufacturing operation 360, in which the surface metal layer mask 356 may be removed to expose the surface metal layer 352.
[0073] The fourth stage may include a twenty-first manufacturing operation 362. During the twenty-first manufacturing operation 362, a passivation layer 364 may be formed on the dielectric layer 338 and the surface metal layer 352. By way of example, the passivation layer may include an oxide and / or nitride layer formed by performing one or more plasma enhanced chemical vapor deposition and / or any other deposition techniques. The fourth stage may include a twenty-second manufacturing operation 366. During the twenty-second manufacturing operation 366, a passivation layer mask 368 may be disposed on a peripheral portion of the passivation layer 364. The fourth stage may include a twenty-third manufacturing operation 370. During the twenty-third manufacturing operation 370, an inner passivation layer portion may be removed (e.g., etched, etc.) from the passivation layer 364 to expose the surface metal layer 352. The fourth stage may include a twenty-fourth manufacturing operation 372. During a twenty-fourth manufacturing operation 372, the passivation layer mask 368 may be removed to expose the passivation layer 364. Additionally, or alternatively, during the twenty-fourth manufacturing operation 372, a backside ohmic contact 374 may be formed on the second side 202B of the semiconductor workpiece 202. In some examples, a backside metal layer 376 may be formed on the backside ohmic contact 374.
[0074] 4 illustrates a flowchart of an exemplary method 400 for manufacturing SiC devices according to one or more embodiments of the present disclosure. The flowchart illustrates a technique for overcoming various limitations of conventional SiC manufacturing processes for manufacturing SiC power devices. The technique may be implemented by one or more computing devices, entities, and / or systems described herein. For example, through various steps / operations of the method 400, a computing device, such as the computing apparatus 110 described herein, may implement (e.g., via one or more control instructions to one or more computing entities 120) a technique for overcoming various limitations of conventional SiC manufacturing processes by maximizing surge peak forward current (IFSM) durability of merged pin Schottky diodes in silicon carbide, minimizing and simplifying the manufacturing process flow, and avoiding metal scrap due to nickel silicide protrusions and nickel residues, among other advantages.
[0075] 4 shows an illustrative example method 400. Although the example method 400 shows a particular sequence of steps / actions, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated steps / actions may be performed in parallel or in a different sequence that does not substantially affect the functionality of the method 400. In other examples, different components of an example device or system implementing the method 400 may perform functions substantially simultaneously or in a particular sequence.
[0076] According to some examples, method 400 includes, at step / action 402, providing a semiconductor substrate. For example, method 400 may include providing a semiconductor substrate including a first side and a second side. The semiconductor substrate may include a silicon carbide material.
[0077] According to some examples, method 400 includes forming a first metal layer at step / act 404. For example, method 400 may include forming a first metal layer on a first side of a semiconductor substrate to form a Schottky contact.
[0078] According to some examples, method 400 includes forming a second metal layer over the first metal layer at step / act 406. For example, method 400 may include forming the second metal layer over the first metal layer to form a reflective barrier layer over the Schottky contact.
[0079] According to some examples, the method 400 includes, at step / operation 408, removing a portion of the second metal layer to expose the first metal layer. For example, the method 400 may include removing one or more portions of the second metal layer to expose a first portion of the first metal layer. In some examples, the method 400 may include placing a patterned mask over the second metal layer. The patterned mask may expose one or more portions of the second metal layer. The method 400 may include etching the second metal layer through the patterned mask to remove one or more portions of the second metal layer and then removing the patterned mask.
[0080] According to some examples, the method 400 includes, at step / operation 410, applying a laser annealing process to form a silicide portion on the first metal layer. For example, the method 400 may include forming one or more silicide portions on the first metal layer by a laser annealing process to form one or more ohmic contacts in the Schottky contact. In some examples, the first metal layer forms one or more ohmic contacts and Schottky contacts in the same plane. For example, one or more ohmic contacts and Schottky contacts may be formed in a p+ region of the SiC device to prevent shorting behavior during bias application.
[0081] In some embodiments, following forming one or more silicide portions on the first metal layer, the method 400 may include removing one or more peripheral portions of the first metal layer and the second metal layer to expose at least a portion of the semiconductor substrate. In some examples, the method 400 may include placing an internal mask over the second metal layer. The internal mask may expose one or more peripheral portions of the second metal layer. The method 400 may include etching the second metal layer and the first metal layer around the internal mask to remove one or more peripheral portions of the second metal layer and the first metal layer, and then removing the internal mask.
[0082] According to some examples, the method 400 includes forming a dielectric layer at step / action 412. For example, the method 400 may include forming a dielectric layer on a first side of the semiconductor substrate following forming one or more silicide portions on the first metal layer. The dielectric layer may cover the semiconductor substrate, the first metal layer, and the second metal layer. In some examples, the method 400 may include disposing a dielectric layer mask over the one or more peripheral dielectric portions of the dielectric layer. The method may include etching an interior dielectric portion from the dielectric layer to expose the second metal layer and the one or more silicide portions on the first metal layer, and then removing the dielectric layer mask.
[0083] According to some examples, the method 400 includes forming a surface metal layer at step / action 414. For example, the method 400 may include forming a surface metal layer over a first side of a semiconductor substrate, a dielectric layer, a first metal layer, and a second metal layer. In some examples, the method 400 may include disposing a surface metal layer mask over an interior portion of the surface metal layer. The method 400 may include etching a peripheral surface metal portion from the surface metal layer to expose the dielectric layer and removing the surface metal layer mask.
[0084] According to some examples, the method 400 includes forming a passivation layer at step / operation 416. For example, the method 400 may include forming a passivation layer over the dielectric layer and the surface metal layer. In some examples, the method 400 may include disposing a passivation layer mask over a peripheral portion of the passivation layer. The method 400 may include etching the interior passivation layer portion from the passivation layer to expose the surface metal layer and then removing the passivation layer mask.
[0085] In some examples, the method 400 may include forming a backside ohmic contact on the second side of the semiconductor substrate and then forming a backside metal layer over the backside ohmic contact. conclusion
[0086] Many modifications and other embodiments of the disclosures described herein will occur to one skilled in the art to which these disclosures pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. It should be understood that the figures show only certain components of the apparatus and systems described herein, but that various other components may be used in conjunction with the systems. It should be understood, therefore, that the disclosure is not to be limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, the steps in the methods described above may not necessarily be performed in the order shown in the accompanying drawings, and in some cases, one or more of the steps shown may be performed substantially simultaneously, or additional steps may be included. Although specific terms have been employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
[0087] Although various embodiments according to the principles disclosed herein have been shown and described above, modifications thereof may be made by those skilled in the art without departing from the spirit and teachings of the present disclosure. The embodiments described herein are merely representative and are not intended to be limiting. Many variations, combinations, and modifications are possible and are within the scope of the present disclosure. Although the disclosed embodiments are primarily directed to SiC power devices and techniques for manufacturing SiC power devices, those skilled in the art may recognize that such principles may be applied to any semiconductor device. Alternative embodiments resulting from combining, integrating, and / or omitting features of the embodiment(s) are also within the scope of the present disclosure. Thus, the scope of protection is not limited by the description set forth above.
[0088] Additionally, the section headings used herein are provided for consistency with the suggestions under 37 CFR 1.77 or to otherwise provide organizational guidance, and are not intended to limit or characterize the disclosure(s) set forth in any claim that may issue from this disclosure.
[0089] Use of broader terms such as "comprises," "includes," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting essentially of," and "comprised substantially of." Use of terms such as "optionally," "may," "might," and "possibly" with respect to any element of an embodiment means that the element is not required or that the element is required, with both alternatives being within the scope of the embodiment. Also, references to examples are provided merely for illustrative purposes and are not intended to be exclusive.
[0090] Although this detailed description has described several embodiments of the present disclosure, the appended claims encompass other embodiments of the present disclosure that differ from the described embodiments, according to various modifications and improvements. For example, the appended claims may encompass any form of semiconductor manufacturing.
[0091] In the appended claims, unless the specific term "means for" or "step for" is used in a given claim,
Claims
1. providing a semiconductor substrate comprising a first side and a second side, the semiconductor substrate comprising a silicon carbide (SiC) material; forming a first metal layer on a first side of the semiconductor substrate to form a Schottky contact; forming a second metal layer over the first metal layer to form a reflective barrier layer overlying the Schottky contact; removing one or more portions of the second metal layer to expose a first portion of the first metal layer; forming one or more silicide portions on the first metal layer by a laser annealing process to form one or more ohmic contacts within the Schottky contact; A method comprising:
2. The method of claim 1 , wherein the first metal layer forms the one or more ohmic contacts and the Schottky contact in a p+ region.
3. 3. The method of claim 1, further comprising forming a dielectric layer on the first side of the semiconductor substrate subsequent to forming the one or more silicide portions on the first metal layer, the dielectric layer covering the semiconductor substrate, the first metal layer, and the second metal layer.
4. disposing a dielectric layer mask over one or more peripheral dielectric portions of the dielectric layer; etching an interior dielectric portion from the dielectric layer to expose the second metal layer and the one or more silicide portions on the first metal layer; removing the dielectric layer mask; The method of claim 3 further comprising:
5. forming a surface metal layer over the first side of the semiconductor substrate, the dielectric layer, the first metal layer, and the second metal layer; disposing a surface metal layer mask over an interior portion of the surface metal layer; etching a peripheral surface metal portion from the surface metal layer to expose the dielectric layer; removing the front metal layer mask; The method of claim 4 further comprising:
6. forming a passivation layer over the dielectric layer and the surface metal layer; disposing a passivation layer mask over a peripheral portion of the passivation layer; etching an inner passivation layer portion from the passivation layer to expose the surface metal layer; removing the passivation layer mask; The method of claim 5 further comprising:
7. removing the one or more portions of the second metal layer; disposing a patterned mask over the second metal layer, the patterned mask exposing the one or more portions of the second metal layer; Etching the second metal layer through the patterned mask to remove the one or more portions of the second metal layer; removing the patterned mask; and The method of claim 1 or 2, comprising:
8. 3. The method of claim 1, further comprising, following forming the one or more silicide portions on the first metal layer, removing peripheral portions of one or more of the first metal layer and the second metal layer to expose at least a portion of the semiconductor body.
9. removing the one or more peripheral portions of the first metal layer; disposing an interior mask over the second metal layer, the interior mask exposing the one or more peripheral portions of the second metal layer; Etching the second metal layer and the first metal layer around the interior mask to remove the one or more peripheral portions of the second metal layer and the first metal layer; removing the inner mask; The method of claim 1 or 2, comprising:
10. 3. The method of claim 1, wherein the semiconductor substrate includes one or more anode implants, and the one or more silicide portions on the first metal layer correspond to the one or more anode implants.
11. The method of claim 10 , further comprising forming the one or more anode implants in the first side of the semiconductor substrate.
12. 3. The method of claim 1, wherein the first side of the semiconductor body comprises an epitaxial drift layer and the second side of the semiconductor body comprises a doped SiC substrate.
13. forming a backside ohmic contact on the second side of the semiconductor substrate; forming a back metal layer on the back ohmic contact; The method of claim 12 further comprising:
14. The method of claim 1 , wherein the first metal layer comprises a nickel-based material.
15. The method of claim 1 , wherein the second metal layer comprises an aluminum-based material.
16. 1. A silicon carbide (SiC) device, comprising: a semiconductor substrate having a first side and a second side; a first metal layer disposed on the first side of the semiconductor substrate, a first portion of the first metal layer forming one or more ohmic contacts and a second portion of the first metal layer forming a Schottky contact, the one or more contacts and the Schottky contact being formed in a p+ region of the SiC device; a second metal layer disposed on the second portion of the first metal layer; and A SiC device comprising:
17. The SiC device of claim 16 , wherein the first side of the semiconductor substrate includes an epitaxial drift layer.
18. 18. The SiC device of claim 16 or 17, wherein the second side of the semiconductor substrate comprises a doped SiC substrate.
19. The SiC device of claim 16 or 17, wherein the first metal layer comprises a nickel material.
20. The SiC device of claim 16 or 17, wherein the second metal layer comprises an aluminum material.