Method to improve profile control during selective etching of silicon nitride spacer

Abstract

To provide a cycle atomic layer etching method for spacer patterning in semiconductor applications.SOLUTION: An etching method includes a step 1 of exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) and forming a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer. The HFC has a formula CxHyFz, and is a saturated or unsaturated, linear or cyclic HFC. The method also includes a step 2 of exposing the polymer layer deposited on the SiN layer to a plasma of inert gas, and removing, by the plasma of inert gas, the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on an etch front. The step 1 and the step 2 are repeated until the SiN layer on the etch front is selectively removed, thereby forming a vertically straight SiN spacer comprising the SiN layer on the sidewall of the structure.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Patent Application No. 16 / 265,782, filed February 1, 2019, which is incorporated by reference in its entirety for all purposes.

[0002] A cyclic atomic layer etching (ALE) method for spacer patterning in semiconductor applications is disclosed. In particular, a cyclic ALE process for forming vertically straight silicon nitride (SiN) spacers using hydrofluorocarbon (HFC) gases is disclosed. The HFC gases of the present disclosure are saturated or unsaturated, linear or cyclic, and have the formula C for selective plasma etching of SiN. x H y F z (wherein x=2 to 5, and y>z). [Background technology]

[0003] The continuing downscaling of semiconductor devices brings increasing challenges to the semiconductor manufacturing process. At technology nodes below 14 nm, one of the most critical steps is the spacer etch. This requires a completely anisotropic etch (no critical dimension (CD) loss) without damaging or consuming the exposed material, such as silicon or silicon oxide. This is typically done by plasma etching using fluorocarbon-based chemistries. However, with the increasing aspect ratios associated with the most advanced technology nodes, traditional etch processes can no longer reach etch specifications such as shape control (e.g. footing and surface roughness), intact underlayers, and CD control.

[0004] In industry, the standard etching process used for SiN etching is HFCs combined with oxidizers and / or noble gases, such as CH3F combined with an oxidizer (e.g., O2), a noble gas (e.g., Ar or He), and possibly additional gases (e.g., CH4, CF4) containing F or O. However, the tradeoff between etch selectivity, shape control, and damage to the underlying layers is difficult to manage. Previous patents on SiN etching claim selectively etching SiN spacers using different HFCs, but without quantifiable information on shape control.

[0005] Chang et al., U.S. Patent Application Publication No. 20130105916A1, discloses a method for producing a SiN film using an HFC plasma. x Anisotropic etching of SiN of various thicknesses was performed. x A highly selective nitride etch process is disclosed that involves forming an HFC polymer on SiO2, SiO, and Si. The process comprises forming a saturated or unsaturated, linear or cyclic HFC of the formula C x H y F z where x=3-6, y>z, and HFCs having the formula: x However, Chang et al. does not disclose any consideration of shape control, such as footing control. The etching process disclosed by Chang et al. is not a cyclic process.

[0006] Suzuki et al., U.S. Patent Application Publication No. 20110068086A1, discloses x H y F z A method for plasma etching on flat wafers is disclosed, which involves plasma etching a target using linear or cyclic HFCs with only saturated molecules of the formula: (where x=3-5, y>z). More specifically, Suzuki et al. report the use of certain HFCs under plasma conditions on flat wafers, rather than patterned wafers containing semiconductor structures, to etch a target containing SiN. xdiscloses selective etching of SiO2. As shown in the Examples, Suzuki et al. used 2,2-difluoro-n-butane to etch SiN and SiO flat wafers.

[0007] U.S. Patent No. 8,501,630 to Metz et al. or U.S. Patent Application Publication No. 20120077347A1 discloses a plasma etching method for selectively etching a substrate. The plasma etching process uses a process composition having a process gas containing C, H, and F and an additive gas that does not contain oxygen. The process gas includes CH3F, CHF3, CH2F2, or any combination of two or more thereof. The plasma etching process disclosed by Metz et al. is not a cyclic process.

[0008] Kajiwara, US Patent Application Publication No. 20010005634A1, discloses a dry etching method for forming contact holes by highly selective etching of SiN over SiO2 using CH2F2 as the etching gas.

[0009] US Patent Publication No. 20130105996 to Brink et al. discloses a low energy etch process for a nitrogen-containing dielectric layer included in a stack including, from bottom up, a nitrogen-containing dielectric layer formed on a substrate, a dielectric material layer at an interconnect level, and a hard mask layer. x H y F z (x=3-6, y>z) was used for plasma etching. Brink et al. did not mention the selectivity to Si or SiO2.

[0010] US Patent Publication No. 20140273292A1 to Posseme et al. discloses a method of forming a SiN spacer, including depositing a SiN layer on an exposed silicon-containing layer and an at least partially formed gate stack disposed on a substrate; modifying a portion of the SiN layer by exposing the SiN layer to a substantially fluorine-free hydrogen or helium-containing plasma; and removing the modified portion of the SiN layer by performing a wet cleaning process to form a SiN spacer. In one embodiment, Posseme et al. disclose that the SiN layer is etched using an HFC-containing gas, such as CH2F2, CH4, or CHF3.

[0011] Gupta et al., US Patent Publication No. 20150270140A1, discloses atomic layer or cyclic plasma etching chemistries and processes for etching films including Si, Ti, Ta, W, Al, Pd, Ir, Co, Fe, B, Cu, Ni, Pt, Ru, Mn, Mg, Cr, Au, alloys thereof, oxides thereof, nitrides thereof, and combinations thereof. Examples include etching Fe and Pd using Cl2 and ethanol (EtOH), and etching Ni, Co, Pd, or Fe using Cl2 and acetylacetonate (Acac).

[0012] US Patent Publication No. 20160293438 A1 to Zhou et al. discloses a cyclic spacer etch process with improved feature control, but the method is based on NF3 / NH3 plasma rather than HFC gases.

[0013] WO 2018 / 044713 A1 to Sherpa et al. discloses a method for sub-atomic layer etching of SiN that includes a first step of a process gas containing H and optional noble gases (H2, or H2 and Ar); and a second step of a process gas containing N, F, O, and optional noble gas elements (NF3, O2, and Ar).

[0014] In U.S. Pat. No. 9,318,343 B2 to Ranjan et al. x H y F z A method for improving etch selectivity during SiN spacer etching is disclosed, which includes a cyclic process of etching and oxidizing SiN spacers and silicon (such as polysilicon) using a process gas containing an HFC gas represented by (x, y, and z are non-zero). The HFC disclosed in Renjan et al. is CH3F. Ranjan et al. does not address spacer geometry, such as the footing or surface roughness of the spacer. Summary of the Invention [Problem to be solved by the invention]

[0015] It is a challenge to find new and novel etching components applicable to improve the shape control for etching silicon-containing spacers such as SiN spacers, since their application for etching silicon-containing spacers must meet the requirements of etching profile such as low or no footing, low or no fluoride formation, smooth spacer surface after etching, etc. Therefore, there is a need to provide such etching components to meet these requirements. [Means for solving the problem]

[0016] i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC being a compound of formula C x H y F zwhere x=2-5, y>z, and is a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to an inert gas plasma and removing the polymer layer deposited on the SiN layer at the etch front and the modified surface of the SiN layer by the inert gas plasma; and iii) repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming vertically straight SiN spacers with SiN layer covering the sidewalls of the structure.

[0017] i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC being a compound of formula C x H y F z Also disclosed is a cyclic etching method for forming vertically straight SiN spacers, comprising the steps of: (i) exposing a polymer layer deposited on the SiN layer to an inert gas plasma, and removing the polymer layer deposited on the SiN layer at the etch front and the modified surface of the SiN layer by the inert gas plasma; and (ii) repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming vertically straight SiN spacers with a SiN layer covering the sidewalls of the structure.

[0018] i) exposing a SiN layer covering a gate stack on a substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) selected from the group consisting of C2H5F and C3H7F to form a polymer layer deposited on the SiN layer that modifies the SiN layer surface; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas and removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer at the etch front with the inert gas plasma; and iii) repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming a vertically straight SiN gate spacer with a SiN layer covering the sidewalls of the gate stack. Also disclosed is a cyclic etching method for forming vertically straight SiN gate spacers, comprising repeating the steps of:

[0019] Any of the disclosed methods may include one or more of the following aspects: After step i), pumping the reaction chamber to a vacuum; purging the reaction chamber with N2; Pumping the reaction chamber to a vacuum; and introducing an inert gas into the reaction chamber to generate a plasma of the inert gas; Further comprising; After step ii), pumping the reaction chamber to a vacuum; purging the reaction chamber with N2; Pumping the reaction chamber to a vacuum; and introducing the HFC into a reaction chamber to generate a plasma of the HFC; Further comprising; Exposing the SiN layer to a plasma of a mixture of HFC and inert gas; At least a large part of the SiN layer on the sidewalls of the gate stack is not removed; · Less than 10% of the thickness of the SiN layer on the sidewalls of the gate stack is removed; · Less than 5% of the thickness of the SiN layer on the sidewalls of the gate stack is removed; Less than 1% of the thickness of the SiN layer on the sidewalls of the gate stack is removed; · There is no measurable reduction in the thickness of the SiN layer on the sidewalls of the gate stack; The inert gas is selected from N2, Ar, Kr, or Xe; · The inert gas is Ar; · HFC is C2H5F; · HFC is C3H7F; the substrate comprises a silicon-containing material; The substrate is silicon; · The structure is a gate stack; ·HFC plasma interacts with SiN to form C-rich polymers (C:F>1); ·C-rich polymer is a polymer layer deposited on top of a SiN layer; · HFC selectively etches the SiN layer on the structure; · HFC selectively etches the SiN layer on the substrate; · Infinite selectivity of SiN for structures; · Infinite selectivity of SiN for gate stacks; · Infinite selectivity of SiN over p-Si, SiO, SiON, and SiCN; · ALE overetch recipe is applied; ·ALE overetch recipes range from approximately 10% ALE overetch to approximately 200% ALE overetch; ·ALE overetch recipes range from approximately 50% ALE overetch to approximately 200% ALE overetch; · Introduce HFC gas into the reaction chamber at a flow rate ranging from about 1 sccm to about 10 slm; · Introduce HFC gas into the reaction chamber at a flow rate ranging from about 1 sccm to about 100 sccm; · Introduce an inert gas into the reaction chamber at a flow rate ranging from about 1 sccm to about 10 slm; · Introduce an inert gas into the reaction chamber at a flow rate ranging from about 10 sccm to about 200 sccm; · the reaction chamber has a pressure in the range of about 1 mTorr to about 50 Torr; · the reaction chamber has a pressure in the range of about 1 mTorr to about 10 Torr; · the reaction chamber has a pressure in the range of about 300 mTorr to about 1 Torr; The substrate temperature in the chamber is in the range of about -110°C to about 2000°C; The substrate temperature in the chamber is in the range of about -20°C to about 1000°C; The substrate temperature in the chamber is in the range of about 25°C to about 700°C; The substrate temperature in the chamber is in the range of about 25°C to about 500°C; The substrate temperature in the chamber is in the range of about 25°C to about 50°C; The temperature of the reaction chamber walls is in the range of about 25°C to about 100°C; · Plasma treatment time varies from 0.01 seconds to 10000 seconds; · Plasma treatment time varies from 1 to 30 seconds; ·N2 purge time varies from 1 second to 10000 seconds; ·N2 purge time varies from 10 to 60 seconds; Almost no footing is formed at each corner between the SiN spacer and the substrate; Little or no excess material remaining adjacent to the SiN layer and substrate; Vertically straight SiN spacers and no fluoride residues on the etch front; · The surface roughness of the vertically straight SiN spacer surface and the etch front surface after cycle etching is improved compared with that before cycle etching; · Removal of the polymer layer with ion bombardment process; further comprising the step of adding an oxygen-containing gas; and The oxygen-containing gas is selected from the group consisting of O2, O3, CO, CO2, NO, NO2, N2O, SO2, COS, H2O, and combinations thereof.

[0020] formula C x H y F z Also disclosed is an HFC etching gas having the formula: (wherein x=2 to 5, y>z). The HFC etching gas of the present disclosure includes one or more of the following aspects: · The HFC is a saturated or unsaturated, linear or cyclic HFC; ·Having a purity greater than about 99% by volume; ·Having a purity greater than about 99.9% by volume; Contains less than 1% by volume of trace gas impurities; · Trace gas impurities include water; · Trace gas impurities include CO2; Trace gas impurities include N2; and · The moisture content of HFC etching gas is less than 20 ppmw.

[0021] Notation and Nomenclature The following detailed description and claims utilize a number of abbreviations, symbols, and terms that are commonly known in the art, including:

[0022] As used herein, the indefinite articles "a" or "an" mean one or more.

[0023] As used herein, in the text or claims, "about" or "approximately" or "approximately" means ±10% of the stated value.

[0024] As used herein, "room temperature" in the text and claims means about 20°C to about 25°C.

[0025] The term "wafer" or "patterned wafer" refers to a wafer having a silicon-containing film stack on a substrate and a patterned hard mask layer on the silicon-containing film stack formed for pattern etching.

[0026] The term "substrate" refers to one or more materials on which a process is performed. A substrate may refer to a wafer having one or more materials on which a process is performed. A substrate may be any suitable wafer used in the manufacture of semiconductor, photovoltaic, flat panel, or LCD-TFT devices. A substrate may also have one or more layers of different materials already deposited thereon from a previous manufacturing step. For example, a wafer may include a silicon layer (e.g., crystalline, amorphous, porous, etc.), a silicon-containing layer (e.g., SiO2, SiN, SiON, SiCOH, etc.), a metal-containing layer (e.g., copper, cobalt, ruthenium, tungsten, platinum, palladium, nickel, ruthenium, gold, etc.), or a combination thereof. Furthermore, a substrate may be flat or patterned. A substrate may be a photoresist film patterned with an organic material. The substrate may include a layer of oxide (e.g., ZrO2-based material, HfO2-based material, TiO2-based material, rare earth oxide-based material, ternary oxide-based material, etc.) used as a dielectric material in MEMS, 3D NAND, MIM, DRAM, or FeRam device applications, or a nitride-based film (e.g., TaN, TiN, NbN) used as an electrode. Those skilled in the art will recognize that the term "film" or "layer" as used herein refers to a thickness of any material disposed or extending over a surface, which may be a trench or line. Throughout this specification and claims, the wafer and associated layers thereon are referred to as the substrate.

[0027] The terms "pattern etch" or "patterned etch" refer to etching a non-planar structure, such as a stack of silicon-containing films underneath a patterned hardmask layer.

[0028] The term "etch" or "etching" as used herein refers to isotropic and / or anisotropic etching processes. Isotropic etching processes involve a chemical reaction between an etching compound and a substrate, resulting in the removal of a portion of material on the substrate. This type of etching process includes chemical dry etching, gas phase chemical etching, thermal dry etching, and the like. Isotropic etching processes create lateral or horizontal etch features in the substrate. Isotropic etching processes create recesses or horizontal recesses on the sidewalls of preformed apertures in the substrate. Anisotropic etching processes remove only material perpendicular to the surface of the substrate, resulting in accurate transfer of the mask pattern. The dry etching process may be a plasma etching process. Plasma is any gas in which a significant percentage of the atoms or molecules are ionized. The plasma may be a capacitively coupled plasma (CCP) generated by a CCP system that essentially consists of two metal electrodes spaced a small distance apart, placed in a reactor. A typical CCP system is driven by a single radio frequency (RF) power source. One of the two electrodes is connected to the power source and the other is grounded. When an electric field is generated between the electrodes, atoms ionize and release electrons. Electrons in the gas are accelerated by the RF field and can collide to directly or indirectly ionize the gas, producing secondary electrons. The plasma may be an inductively coupled plasma (ICP) or a transformer coupled plasma (TCP), which is generated by an ICP system energized by electromagnetic induction, i.e., an electric current generated by a time-varying magnetic field. An ICP discharge can be as fast as 10 15 cm -3The ICP discharge has a relatively high electron density of the order of 1000 nm. As a result, ICP discharges have a wide range of applications where a high density plasma (HDP) is required. Another advantage of ICP discharges is that there is relatively little contamination, since the electrodes are completely outside the reaction chamber. Plasma etching processes produce etch features that are perpendicular to the substrate. Plasma etching processes produce apertures, trenches, channel holes, gate trenches, stepped contacts, capacitor holes, contact holes, etc. that are perpendicular to the substrate.

[0029] The term "100% etch" refers to the ALE process etching a material completely through its thickness. The term "overetch" means that the ALE process continues even after etching through the material. For example, in the method of the present disclosure, if an ALE recipe has an etch rate of 1 nm / cycle for the SiN layer and the SiN layer has a thickness of 10 nm, 10 cycles are required to completely etch through the 10 nm thick SiN. This means 100% etching. If more than 10 etch cycles are set to etch the SiN layer, the ALE is "overetched". For example, if 15 etch cycles are set to etch the SiN layer, the etch process is 50% overetched. If 20 etch cycles are set to etch the SiN layer, the etch process is 100% overetched.

[0030] The term "deposit" refers to a series of processes in which atomic or molecular level materials are deposited on a wafer surface or substrate from a gaseous state (vapor) to a solid state as a thin layer. A chemical reaction is involved in the process that occurs after the creation of a plasma of reacting gases. The plasma may be the CCP mentioned above, which is usually formed by a radio frequency (RF) (alternating current (AC)) or direct current (DC) discharge between two electrodes, filling the space between them with a reacting gas. Deposition methods may include atomic layer deposition (ALD) and chemical vapor deposition (CVD).

[0031] The term "mask" refers to a layer that resists etching. A hard mask layer can be placed over a layer to be etched.

[0032] The term "aspect ratio" refers to the ratio of the height of a trench (or aperture) to the width of the trench (or diameter of the aperture).

[0033] The term "selectivity" refers to the ratio of the etch rate of one material to the etch rate of another material. The terms "selective etching" or "selectively etching" refer to etching one material more than another, in other words, having an etch selectivity between two materials that is greater or less than 1:1.

[0034] It should be noted that, as used herein, the terms "film" and "layer" may be used interchangeably. It is understood that a film may correspond to or relate to a layer, and a layer may refer to a film. Furthermore, one of ordinary skill in the art will appreciate that the terms "film" or "layer" as used herein refer to a thickness of any material disposed on or extending over a surface, which may range from as large as an entire wafer to as small as a trench or line.

[0035] Also, in this specification, the terms "etching compound" and "etching gas" may be used interchangeably when the etching compound is in a gaseous state at room temperature and ambient pressure. It is understood that an etching compound may correspond to or be related to an etching gas, and an etching gas may refer to an etching compound.

[0036] Standard abbreviations for elements from the Periodic Table of the Elements are used herein. It should be understood that elements may be referred to by these abbreviations (e.g., Si refers to silicon, N refers to nitrogen, O refers to oxygen, C refers to carbon, H refers to hydrogen, F refers to fluorine, etc.).

[0037] Unique CAS Registry Numbers assigned by the Chemical Abstract Service (or "CAS") are provided to identify the particular molecules disclosed.

[0038] It should be noted that silicon-containing films, such as SiN and SiO, are described throughout this specification and claims without regard to their appropriate stoichiometry. Silicon-containing films include pure silicon (Si) layers, such as crystalline Si, polysilicon (p-Si or polycrystalline silicon), or amorphous silicon; silicon nitride (Si k N l ) layer; or silicon oxide (Si n O m ) layer; or a mixture thereof, where k, l, m, and n are in the range of 0.1 to 6, inclusive. Preferably, the silicon nitride is a SiN layer, where k and I are in the range of 0.5 to 1.5, respectively. k N l More preferably, the silicon nitride is Si3N4. In the following description, SiN is Si k N l It may be used to represent a silicon-containing layer. Preferably, silicon oxide is a Si n O mMore preferably, the silicon oxide is SiO2. In the following description of this specification, SiO means Si n O m It may be used to describe a silicon-containing layer. The silicon-containing film may also be a silicon oxide-based dielectric material, such as an organic-based or silicon oxide-based low-k dielectric material, such as Applied Materials, Inc.'s Black Diamond II or III material, which has the formula SiOCH. The silicon-containing film may be a Si-containing layer, where a, b, and c are in the range of 0.1 to 6. a O b N c The silicon-containing film may also include dopants such as B, C, P, As, and / or Ge.

[0039] Ranges may be expressed herein as from about one particular value and / or to about another particular value, When such a range is expressed, it should be understood that another embodiment is from the one particular value and / or to the other particular value, along with all combinations within said ranges.

[0040] References herein to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification do not necessarily all refer to the same embodiment, and alternative or alternate embodiments are not necessarily mutually exclusive of other embodiments. The same applies to the term "implementation."

[0041] For a fuller understanding of the nature and objects of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which like elements are designated with the same or similar reference numerals, and in which: [Brief description of the drawings]

[0042] [Figure 1a]1 shows a cross-sectional side view of an exemplary pattern formed in the art to create SiN spacers on an underlying substrate. [Figure 1b] FIG. 2 is a cross-sectional side view of an exemplary SiN spacer on an underlying substrate, illustrating an ideal etching result for the SiN spacer in the art. [Figure 1c] FIG. 2 shows a cross-sectional side view of an exemplary SiN spacer on an underlying substrate with an actual spacer etch process in the art that results in a footing at the bottom of the spacer. [Diagram 2] 1 illustrates the process flow per cycle of the cyclic ALE process of the present disclosure. [Diagram 3] 1 is a graph of etch thickness versus ALE cycles using CH3F. [Figure 4] 1 is a graph of etch thickness versus ALE cycles using C2H5F. [Diagram 5] 1 is a graph of etch thickness versus ALE cycles using C3H7F. [Figure 6a] 13 shows EDS mapping of SiN spacer after ALE with 100% etched sidewall and 100% over-etched sidewall using C2H5F, respectively - horizontal scan of sidewall. [Figure 6b] 4 shows EDS line scans using atoms of a SiN spacer after ALE with 100% etched sidewalls and 100% over-etched sidewalls using C2H5F, respectively - vertical scan of the spacer bottom. [Figure 7] Showing sequential etching of SiN spacers using C2H5F: EDS mapping (left) and EDS line scan (right). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] A method is disclosed for improving shape control for forming silicon nitride (SiN) spacers on Si-containing substrates with high selectivity in semiconductor applications. The disclosed method utilizes a cyclic atomic layer etching (ALE) process using a plasma of an HFC and a plasma of a noble gas to selectively etch a SiN layer on a structure that is covered with a SiN layer and / or an underlying Si-containing layer (e.g., a substrate). In this specification, the structure may be a gate or a gate stack.

[0044] The disclosed method has significantly improved shape control for forming SiN spacers. Important features of the formed SiN spacers include high selectivity of SiN to underlying Si-containing layers such as poly-Si (or Si) and SiO2. Important features of the formed SiN spacers also include no chemical damage to the underlying Si-containing layers even when overetch recipes are used, little or no excess material adjacent to the SiN layer and substrate, little or no footing on the bottom edge of the spacer, and no F residue on the sidewalls of the spacer.

[0045] In semiconductor applications, a spacer is a layer of material deposited by CVD or ALD on a structure such as a gate or gate stack to separate the gate contact from the source and drain contacts in a metal oxide semiconductor field effect transistor (MOSFET). The material may be SiN, etc. The spacer passivates the sidewalls of the gate stack. The disclosed method can be applied to any type of spacer in semiconductor applications, including gate spacers, patterning spacers with self-aligned double patterning (SADP) spacers and self-aligned quadruple patterning (SAQP) spacers, etc. In this specification, the gate stack can be a digital switch, a random access memory (RAM), an amplifier, a biosensor based on a field effect transistor (BioFET), a DNA field effect transistor (DNAFET), a ferroelectric, a magnetic, an electrolytic, etc. More specifically, the gate stack can be a flash memory such as 3D NAND or NOR, a high-k gate stack including silicon-oxide-nitride-oxide-silicon (SONOS), a strain interface including global and local strain, a ferroelectric gate stack, an electrolytic interface, etc.

[0046] 1a-1c show exemplary cross-sectional side views of the formation of an exemplary SiN spacer on an underlying substrate. FIG. 1a shows, but is not limited to, a trench pattern formed to fabricate a SiN spacer. SiN-coated structures 10 and 12 are formed on top of a substrate 102. Multiple SiN-coated structures can be formed on top of the substrate 102, but only two structures 10 and 20 are shown. The substrate 102 may be a FinFET (Fin Field Effect Transistor) substrate composed of Si-containing materials such as Si, poly-Si, SiO2, etc. Number 104 represents a layer of SiN that coats a structure 106 on the substrate 102. The structure 106, also referred to in the art as a pillar, may be a gate stack coated by a SiN layer 104. In an ideal situation, the SiN layer horizontally covering the etch front, the top of the structure 106 or the top of the pillars, and the top of the substrate 102 or the bottom of the trench, should be removed, resulting in vertically straight and uniform SiN sidewalls on the structure 106 with little or no footing at the bottom corners. Herein, "a1" and "a2" represent the thickness of the SiN layer on the sidewall 104 at different heights of the structure or gate stack. The height of "a1" can be, for example, about one-third of the total height of the structure 106 below the top of the pillar and closer to the top of the pillar, and "a2" can be about one-third of the total height of the structure 106 above the substrate 102 and closer to the substrate 102. Because the structure 106 below the SiN layer 104 can be curved at the bottom adjacent to the substrate 102 (not shown), the value of "a2" can be smaller than the value of "a1" with a vertically straight SiN spacer. "b" and "c" represent the thickness of the SiN layer at the top of the structure 106 and the top of the substrate 102, respectively. Herein, "b" and "c" are the thicknesses of the etch front. Additionally, "c" can represent the removal thickness of the substrate 102 after removing the SiN layer. In this case, "c" can be a negative value. As shown in FIG. 1b, an ideal SiN spacer etch result is shown, which forms vertically straight and uniform SiN sidewall 204 coverage on the structure 206 and removes the SiN layer at the etch front that horizontally covers the top of the structure 206 and the top of the substrate 202. However, in practical spacer etch processes, excess material often remains adjacent to the SiN layer and the substrate, creating a footing 308 at the bottom of the spacer, as shown in FIG. 1c. In this specification, the horizontal length "d" of the footing 308 adjacent to the substrate 302 is defined to represent the size of the footing.

[0047] The disclosed cyclic ALE process for controlling the etched shape of SiN spacers formed on Si-containing substrates overcomes the footing defect in manufacturing SiN spacers. The disclosed cyclic ALE process for controlling the etched shape of SiN spacers formed on Si-containing substrates also produces vertically straight spacers without tapering in manufacturing SiN spacers. The disclosed cyclic ALE process includes a surface modification or deposition step and a surface removal or etching step in one ALE cycle. During the surface modification step, a thin layer of polymer that modifies the surface of the SiN layer (see FIG. 1a, SiN layer 104) is deposited on the surface of the SiN layer in a reaction chamber. The thin layer of polymer is formed by a plasma of HFC gas or a plasma of a gas mixture of HFC gas and an inert gas (such as N2, Ar, Kr, Xe, preferably Ar). The HFC gas reacts with the material SiN at the surface of the SiN layer to form a thin layer of polymer, which is a C-rich polymer (C:F>1), also called modified surface layer at the surface of the SiN layer, where chemical bonds are formed in the intermediate layer between the thin layer of polymer and the surface of the SiN layer. In the surface removal step, the modified surface layer is etched or removed by a plasma of pure inert gas (e.g. Ar), which is highly volatile and can be pumped out of the chamber, by high energy ion bombardment to sputter the modified surface layer. After the surface removal step, the surface modification step is repeated to form a cycle ALE process. In the cycle ALE, an ALE overetch recipe can be applied to further remove the SiN layer at the etch front due to the infinite selectivity of SiN to the structure or gate stack. The ALE overetch recipe can range from about 10% ALE overetch to about 200% ALE overetch, preferably from about 50% ALE overetch to about 200% ALE overetch. These processes can be cycled, allowing for gradual removal of material, which enhances pattern fidelity and minimizes SiN spacer footing.Between the surface modification step and the surface removal step, or after the deposition step and the etching step, an N2 purge step is applied, which includes a vacuum pump step to pump HFC gases out of the reaction chamber before the N2 purge step, and a vacuum pump step to pump N2 out of the reaction chamber after the N2 purge step.

[0048] An ideal cyclic ALE process is based on a self-limiting reaction. This means that the etchant reacts only with the available surface sites on the substrate while keeping the remaining layers intact. The ALE process conditions can be optimized by tracking the self-limiting nature of the reactants in terms of flow rate and exposure time. To avoid synergistic reactions, a constant N2 purge was used at the end of each step to remove excess etchant from the system.

[0049] 2, in one cycle of the ALE process of the present disclosure, a plasma etch gas formed from a gas mixture of HFC gas and Ar deposits a thin layer of polymer on the surface of the SiN layer in the reaction chamber in step 1. The thin layer of polymer is then etched or removed by a plasma of a pure inert gas (e.g., Ar) in step 2. After each step, the reaction chamber undergoes a pump / N2 purge / pump process that includes pumping the reaction chamber to a vacuum, filling the reaction chamber with N2 for purging, and pumping the reaction chamber to a vacuum again before proceeding to the next step.

[0050] The disclosed cyclic ALE method can be used to selectively etch SiN using the formula C x H y F zThe method may include using saturated or unsaturated, linear or cyclic HFC gases with (x=2-5, y>z). The HFC plasma interacts with the SiN to form a C-rich polymer (C:F>1), which is deposited on the SiN layer to form a polymer layer. The HFC gases of the present disclosure can be mixed with an inert gas in the plasma chamber to selectively etch not only the polymer layer but also a single atomic layer of the SiN layer. Thus, the SiN spacer is formed with improved shape control, such as high selectivity, minimized footing, limited fluorine generation, and a smooth surface of the SiN spacer. The inert gas can be Ar, Kr, and Xe. Preferably, it is Ar.

[0051] The HFC gases of the present disclosure for forming a polymer layer on a SiN layer may include the following HFC gases: fluoroethane CHF (CAS#353-36-6) and 1-fluoropropane CHF (CAS#460-13-9). These HFC gases are used to deposit a polymer layer on a SiN layer by mixing with an inert gas in a plasma chamber. To modify the surface of the SiN layer, an intermediate layer is formed between the polymer layer and the SiN layer. Then, a plasma of an inert gas such as Ar selectively removes not only the polymer layer but also the intermediate layer. This corresponds to removing a single atomic layer of the SiN layer. In this way, the SiN spacer is formed with improved shape control, such as high selectivity, minimized footing, limited fluorine generation, and a smooth surface of the SiN spacer. The inert gas may be Ar, Kr, and Xe. Ar is preferred.

[0052] The HFC gas disclosed in this disclosure is free of the major impurities N2, CO x , S.O. x , HO, etc., are removed to provide a purity of greater than 99% v / v, and preferably greater than 99.9% v / v.

[0053] The HFC gases of the present disclosure contain less than 1% by volume of trace gas impurities, including less than 150 ppm by volume of impurity gases such as N2 and / or H2O and / or CO2. Preferably, the water content of the plasma etching gas is less than 20 ppmw by weight. Purified products can be produced by distillation and / or by passing the gas or liquid through a suitable adsorbent such as a 4 Å molecular sieve.

[0054] The cyclic ALE method of the present disclosure includes providing a plasma processing chamber having a substrate disposed therein, such as, but not limited to, a reactive ion etch (RIE), capacitively coupled plasma (CCP) using single or multiple frequency RF sources, inductively coupled plasma (ICP), electron cyclotron resonance (ECR), microwave plasma reactor, remote plasma reactor, pulsed plasma reactor, or other type of etching system capable of selectively removing portions of a silicon-containing film or generating activated species. The chamber may be any enclosure or chamber within the device in which the etching process takes place, such as any chamber or enclosure used for plasma etching of the prior art. A preferred chamber is a CCP chamber.

[0055] Those skilled in the art will recognize that different plasma reaction chamber designs provide different electronic temperature control. Suitable commercially available plasma reaction chambers include, but are not limited to, Applied Materials' magnetically enhanced reactive ion etcher sold under the trademark eMAX™, or Lam Research's family of dual CCP reactive ion etcher dielectric etch products sold under the trademark 2300® Flex™. The RF power in these may be pulsed to control the plasma characteristics, which further improves the etch performance (selectivity and damage).

[0056] To eliminate or reduce the thickness of polymer deposition, an oxygen-containing gas can be introduced into the reaction chamber. The oxygen-containing gas includes, but is not limited to, oxidizers such as O2, O3, CO, CO2, NO, NO2, N2O, SO2, COS, H2O, and combinations thereof. The addition of oxygen or an oxygen-containing gas to the plasma chemistry is known to increase the F / C ratio of plasma species and reduce polymer formation (see, for example, U.S. Patent No. 6,387,287 to Hung et al.). The HFC gas and oxygen-containing gas of the present disclosure can be mixed together before being introduced into the reaction chamber.

[0057] Alternatively, the oxygen-containing gas is introduced into the chamber continuously and the HFC gas of the present disclosure is introduced into the chamber in pulses, the oxygen-containing gas comprising from about 0.01% to about 99.99% by volume of the mixture introduced into the chamber.

[0058] In the cyclic ALE method of the present disclosure, the plasma treatment time can vary from 0.01 seconds to 10000 seconds, preferably 1 second to 30 seconds. The N2 purge time can vary from 1 second to 10000 seconds, preferably 10 seconds to 60 seconds.

[0059] The temperature and pressure in the reaction chamber are maintained at suitable conditions for the silicon-containing film to react with the activated etching gas. For example, the pressure in the chamber can be maintained at about 1 mTorr to about 50 Torr, preferably about 1 mTorr to about 10 Torr, more preferably about 300 mTorr to about 1 Torr, as required by the etching parameters. Similarly, the substrate temperature in the chamber can range from about -110°C to about 2000°C, preferably about -70°C to about 1500°C, more preferably about -20°C to about 1000°C, even more preferably about 25°C to about 700°C, even more preferably about 25°C to about 500°C, even more preferably about 25°C to about 50°C. The temperature of the chamber walls can range from about 25°C to about 100°C depending on the processing requirements.

[0060] In one embodiment, the HFC gases of the present disclosure are introduced into a reaction chamber containing a substrate having a structure such as a gate stack with a coated SiN layer formed thereon. The gases can be introduced into the chamber at a flow rate ranging from about 1 sccm to about 10 slm, preferably from 1 sccm to 100 sccm. The inert gas can be introduced into the chamber at a flow rate ranging from about 1 sccm to about 10 slm, preferably from 10 sccm to 200 sccm. One skilled in the art will recognize that the flow rates may vary from tool to tool.

[0061] The disclosed cyclic etching method includes the steps of: i) placing a patterned substrate on a substrate holder in a plasma processing chamber or reaction chamber, the patterned substrate having a SiN layer covering at least one structure on the substrate, the structure being a gate. ii) introducing an HFC gas or a mixture of an HFC gas and an inert gas into a reaction chamber to generate a plasma therein, wherein upon generation of the plasma, the plasma deposits a polymer layer on the SiN layer that modifies the SiN surface, and the HFC gas is a compound of formula C. x H y F z(x=2-5, y>z), saturated or unsaturated, linear or cyclic HFC gas, and the inert gas is N2, Ar, Kr, Xe, preferably Ar; iii) pumping the HFC gas or a mixture of HFC gas and inert gas out of the reaction chamber until the reaction chamber reaches high vacuum; iv) purging the reaction chamber with N2; v) pumping the reaction chamber back to high vacuum, i.e. pumping N2 out of the reaction chamber until the reaction chamber reaches high vacuum; vi) introducing an inert gas into the reaction chamber to generate a plasma of the inert gas; vii) exposing the polymer layer deposited on the SiN layer to the plasma of the inert gas. The method further includes the steps of: a plasma of inert gas removes the polymer layer deposited on the SiN layer at the etch front and the modified surface of the SiN layer at the etch front by ion bombardment; vii) pumping the reaction chamber to a high vacuum, i.e., pumping the inert gas out of the reaction chamber until the reaction chamber reaches a high vacuum; viii) purging the reaction chamber with N2; ix) pumping the reaction chamber to a high vacuum; and x) repeating steps ii) to ix) until the SiN layer at the etch front is selectively removed, thereby forming substantially vertically straight SiN spacers including the SiN layer on the sidewalls of the gate stack. An overetch recipe can be applied here, for example, from 50% overetch to 200% overetch.

[0062] In the ideal case, the ion bombardment process removes only the modified surface of the polymer layer and the SiN layer at the etch front, i.e., the SiN layer at the top of the pillar and the bottom of the trench, while the SiN layer at the sidewall remains unchanged. In practice, the thickness of the SiN layer at the sidewall may vary slightly due to slight deviations and / or structures with curved bottoms. The cycle etching method of the present disclosure provides that at least a large portion of the SiN layer on the sidewall of the gate stack is not removed. Preferably, less than 10% of the thickness of the SiN layer on the sidewall of the gate stack is removed, especially the SiN layer close to the bottom of the structure. More preferably, less than 5% of the thickness of the SiN layer on the sidewall of the gate stack is removed. Even more preferably, less than 1% of the thickness of the SiN layer on the sidewall of the gate stack is removed. Even more preferably, no measurable reduction in the thickness of the SiN layer on the sidewall of the gate stack occurs.

[0063] Compared to conventional SiN spacer etching processes, the disclosed cyclic ALE process using the disclosed HFC gases can reduce SiN footing at the bottom edge of the spacer by more than 70% from the following examples while maintaining chemical integrity without causing significant surface roughness or chemical contamination (e.g., F residue) to the underlying material. More specifically, the disclosed cyclic ALE process using C2H5F produces no fluoride residue at the bottom and sidewalls of the trench. Here, no fluoride residue means that less than about 0.05%, preferably less than 0.03%, of fluoride residue remains at the bottom and sidewalls of the trench. The disclosed cyclic ALE process using the disclosed HFC gases also produces a smooth surface of the SiN spacer. EXAMPLES

[0064] The following non-limiting examples are provided to further illustrate embodiments of the present invention, however, these examples are not intended to be exhaustive or to limit the scope of the invention disclosed herein.

[0065] The following examples are carried out using a CCP plasma chamber with variable conditions for each step. The plasma power, pressure, gas flow rate, reaction time, etc. were very well controlled. The pressure range was 300 mTorr to 1 Torr. The temperature range was 25°C to 50°C. The gas flow rate of CH3F, C2H5F, or C3H7F was varied from 1 sccm to 10 sccm. The rare gas flow rate was varied from 10 sccm to 200 sccm. The rare gas used was Ar. The RF plasma power ranged from 50 W to 100 W. The plasma treatment time or reaction time was varied from 1 second to 30 seconds. The N2 purge time was varied from 10 seconds to 60 seconds. N2, CO x , C x H y F z , S.O. x By removing major impurities such as HO, the desired purity of CHF or C2H5F or C3H7F was >99.9%.

[0066] The sample used in the following examples was a patterned spacer wafer as shown in FIG. 1a, and the substrate was a Si substrate.

[0067] The Ellipsometer was a JAWololam Co. M-2000. The SEM (Scanning Electron Microscope) for imaging the patterned structures was a JOEL JSM-7500SEM. The XPS for characterizing the surfaces was a Kratos XPS-Supra Model. The AFM (Atomic Force Microscope) for probing the surfaces was a Park NX10 AFM. The TEM (Transmission Electron Microscope) for imaging the patterned structures was a FEI Tecnai Osiris operating at 200 kV in bright field (BF) TEM mode and high resolution (HR) TEM mode. FEG / TEM was used. EDS (electron diffusion spectroscopy) was acquired on a Bruker QuantaxEDS system.

[0068] Example 1 CH3F cycle ALE process The CH3F cycle ALE process was performed under optimized ALE conditions. Referring to FIG. 2, the etching gas was CH3F. The deposition step (step 1) with CH3F was performed at RF power 75 W, pressure 300 mTorr, Ar gas flow rate 100 sccm, and CH3F flow rate 5 sccm. The reaction time of the deposition step was 4 seconds. The removal step (step 2) was performed at RF power 50 W, pressure 500 mTorr, Ar gas flow rate 100 sccm, no CH3F, and reaction time 30 seconds. The pump / N2 purge / pump process between step 1 and step 2 and vice versa was 90 seconds. FIG. 3 shows the etched thickness versus ALE cycle for CH3F. With the increase of ALE cycle, the etch thickness of SiN becomes deeper, the selectivity of SiN to p-Si, SiO, and SiON becomes higher, and the selectivity of SiN to SiCN can remain unchanged. The etch thickness of SiN per cycle using CH3F with various ALE cycles is listed in Table 1.

[0069] [Table 1]

[0070] Example 2 C2H5F cycle ALE process The C2H5F cycle ALE process was carried out under optimized ALE conditions. See Figure 2. In Fig. 4, the etching gas was C2H5F. The deposition step (step 1) with C2H5F was performed with RF power of 75 W, pressure of 300 mTorr, Ar gas flow rate of 100 sccm, and C2H5F flow rate of 5 sccm. The reaction time of the deposition step was 4 seconds. The removal step (step 2) was performed with RF power of 50 W, pressure of 500 mTorr, Ar gas flow rate of 100 sccm, and no C2H5F, and reaction time of 35 seconds. The time for the pump / N2 purge / pump process between step 1 and step 2 and vice versa was 90 seconds. Fig. 4 shows the etched thickness versus ALE cycle for C2H5F. With increasing ALE cycle, the etch thickness of SiN increased linearly, and no etching occurred to p-Si, SiO, and SiON. The results of the C2H5F cycle ALE process show very high selectivity of SiN to p-Si, SiO, SiON, and SiCN, almost infinite selectivity.

[0071] Compared with the cyclic ALE process using CH3F, C2H5F gas exhibits higher etch selectivity of SiN over p-Si, SiO, SiON, and SiCN, and a lower etch rate, resulting in a smaller amount etched per cycle. The etch thickness of SiN per cycle using C2H5F in various ALE cycles is listed in Table 1.

[0072] Example 3 C3H7F cycle ALE process The C3H7F cycle ALE process was performed under optimized ALE conditions. Referring to Figure 2, the etching gas was C3H7F. The deposition step (step 1) with C3H7F was performed at RF power 75 W, pressure 300 mTorr, Ar gas flow rate 100 sccm, and C3H7F flow rate 5 sccm. The reaction time of the deposition step was 4 seconds. The removal step (step 2) was performed at RF power 50 W, pressure 500 mTorr, Ar gas flow rate 100 sccm, without C3H7F, and reaction time 40 seconds. The time of the pump / N2 purge / pump process between step 1 and step 2 and vice versa was 150 seconds. Figure 5 shows the etched thickness versus ALE cycle for C3H7F. The amount of etched thickness increased linearly with the number of ALE cycles, with an etch rate of 2.0-2.4 nm / cycle. Infinite etch selectivity of SiN over other materials can also be obtained under optimized conditions. The etch thickness of SiN per cycle using C3H7F in different ALE cycles is listed in Table 1.

[0073] Example 4 SEM of cyclic ALE of SiN spacer patterned wafers using CH3F and C2H5F With reference to FIG. 1a, the dimensions of the SiN spacer patterned wafer before etching are as follows: "a" is 34 nm; "b" is 34 nm; "c" is 34 nm. The substrate 102 is a Si substrate. The main factors of concern after etching are damage to the Si substrate, sidewall deposition, footing at the corner between the spacer and the substrate, fluoride residues on the SiN layer and the substrate or etch front, surface roughness of the SiN layer and the substrate or etch front, etc. Table 2 lists the etch front thickness after cyclic ALE of SiN spacers with CH3F and C2H5F in various cyclic ALE modes, such as 50% etch, 100% etch, 100% overetch, and 200% overetch. It is noted that the optimized results of ALE 100% etch and ALE 100% overetch with C2H5F are shown, showing little or no footing formed at the bottom of the spacer.

[0074] [Table 2]

[0075] Example 5 TEM of Cyclic ALE of SiN Spacer Patterned Wafers Using C2H5F The ALE 100% etch and 100% overetch with C2H5F shown in Example 4 were further examined by TEM.

[0076] With reference to FIG. 1a, the dimensions of the SiN spacer patterned wafer before etching are as follows: "a" is 34 nm; "b" is 34 nm; and "c" is 34 nm. The substrate 102 is a Si substrate. Samples for TEM were prepared using an in situ focused ion beam (FIB) lift-out technique on an FEI Strata400 dual beam FIB / SEM. Samples were capped with protective carbon and e-Pt / I-Pt before milling. The thickness of the TEM lamella was about 100 nm. Samples were imaged in bright field (BF) and high resolution (HR) TEM modes with an FEI Tecnai Osiris FEG / TEM operating at 200 kV. TEM results for cyclic ALE using C2H5F are listed in Table 3.

[0077] For the ALE-100% etch, no overetching occurred, the SiN on the top of the pillar was not completely etched, and the left (L) and right (R) thicknesses of the sidewall SiN layer ("a2", approximately one third of the total height of the gate stack close to the substrate) were 32.6 nm and 32.3 nm, respectively, with left and right footings ("d") of 6.6 nm and 8.2 nm. The thickness of the sidewall SiN layer ("a2") was reduced by approximately 5%. In contrast, for the ALE-100% overetch, the SiN on the top of the pillar was completely etched, and the left and right thicknesses of the sidewall SiN layer ("a2") were 30.4 and 31.1 nm, respectively, with left and right footings of 6.0 nm and 3.9 nm. The thickness of the SiN layer on the sidewall ("a2") was reduced by approximately 9.5%. Thus, less than 10% of the thickness of the SiN layer on the sidewall of the gate stack is removed. The reduction in thickness (a2) of the SiN layer on the sidewalls may be due to curvature of the structure or gate stack adjacent to the substrate, which causes the inner curvature of the SiN layer adjacent to the structure or gate stack. The reduction in thickness (a2) of the SiN layer on the sidewalls may also be due to small deviations.

[0078] The Si recess refers to the amount of Si substrate thickness that was etched. The Si recess was measured 10 nm away from the bottom edge of the SiN sidewall in the left and right directions. In the ALE-100% etching, no overetching occurred, and the left and right Si recesses were 1.446 nm, respectively. and 1.285 nm. In contrast, for ALE-100% overetch, the left and right Si recesses were 4.096 nm and 4.194 nm, respectively.

[0079] The surface roughness of the SiN spacer after ALE with 100% etching and 100% overetching using C2H5F includes the surface roughness of the pillar top (T) and the surface roughness of the trench bottom (B). Table 3 also includes the surface roughness results. With 100% ALE etching, a 2-3 atomic layer level (a1) SiN layer remained on the pillar top (positive value). This means that the SiN layer on the pillar top was not completely removed. In this case, the interface between the SiN layer and the pillar top was smooth and flat, which corresponds to the surface roughness without etching. The trench bottom etched with ALE-100% etching also shows that a 2-3 atomic layer level SiN layer remained on the trench bottom. With ALE-100% overetching, both the pillar top and the trench bottom were etched at a 2-3 atomic layer level (negative value).

[0080] [Table 3]

[0081] Example 6 EDS of Cycle ALE of SiN Spacer Patterned Wafers Using C2H5F Figure 6a shows EDS mapping of SiN spacer after ALE with 100% etched sidewall and 100% over-etched sidewall, respectively, using C2H5F (horizontal scan of sidewall). 100% etch results in no over-etch and no F residue on the sidewall. 100% over-etch also results in no F residue on the sidewall.

[0082] Figure 6b shows EDS line scans using atoms of a SiN spacer after cycle ALE with 100% etched sidewalls and 100% overetched sidewalls, respectively, using C2H5F (vertical scan of spacer bottom). 100% etch leaves no F residue on the sidewall. 100% overetch leaves no F residue on the sidewall.

[0083] Example 7 Cycle ALE vs. Continuous Etching Using C2H5F Table 4 shows a comparison between the sequential etching and the cycle ALE. The results show that in the sequential etching process, the Si recess is 2.9 nm; a polymer layer is formed on the sidewall; and the footing is 16.2 nm at the left corner and 15.3 nm at the right corner. Meanwhile, in the cycle ALE process, the results show that the Si recess is 4.1-4.2 nm; a minimal polymer layer is formed on the sidewall; and the footing is 6.0 nm at the left and 3.9 nm at the right. Compared to the sequential etching, the cycle ALE process reduces the footing by about 75%. Thus, the Si recess and surface roughness are all improved in the cycle ALE process, which is an advantage over the cycle ALE process in etching the SiN spacer using C2H5F. Little or no footing is formed as compared to a continuous etching process that uses a continuous etching process. As used herein, little or no footing may be defined by "d"≦about 6 nm.

[0084] [Table 4]

[0085] Figure 7 shows the sequential etching of SiN spacers using C2H5F: EDS mapping (left) and EDS line scan (right). The sequential etching clearly showed F residues on the sidewalls (~22-36 nm) and bottom of the trench (~36-58 nm), whereas Figures 6a and 6b showed no F residues.

[0086] The measured percentage of fluoride residue remaining on the trench bottom and sidewalls after cyclic ALE and continuous etching, respectively, is listed in Table 5. The cyclic ALE process mode left very little fluoride on the trench bottom and sidewalls, while the continuous etching method produced fluoride residue on the trench bottom and sidewalls.

[0087] Thus, the cyclic ALE process mode with C2H5F produces no fluoride residues and reduces residual etchant on the etch front and sidewall surfaces. The cyclic ALE process mode with C2H5F minimizes SiN footing and causes little or no damage to the top of the SiN spacers.

[0088] [Table 5]

[0089] Example 8 Surface Roughness of SiN Flat Wafers Using C2H5F in Cycle ALE Surface roughness - The RMS of a thin film of SiN on a flat wafer was measured by AFM before and after cyclic ALE with C2H5F. Before cyclic ALE with C2H5F, RMS (root mean square) = 2.9 nm. After cyclic ALE with C2H5F, RMS = 1.1 nm. Thus, a smaller RMS was achieved after cyclic ALE with C2H5F. This is due to the improved surface smoothing effect of ALE with C2H5F. The results are shown.

[0090] In summary, the disclosed cycle ALE of SiN spacers using disclosed HFCs such as C2H5F and C3H7F can minimize SiN footing (e.g., about 75% reduction in footing compared to continuous etching), generate no F residues on the pillar tops, trench bottoms, and sidewalls, and have no chemical contamination and reduced surface roughness after the cycle ALE process. The disclosed cycle ALE of SiN spacers using disclosed HFCs such as C2H5F and C3H7F improves etch profile control with high selectivity for etching SiN spacers formed on Si-containing substrates in semiconductor applications.

[0091] It will be understood that many additional changes in the details, materials, steps, and arrangements of parts described and illustrated herein to explain the nature of the invention may be made by those skilled in the art within the principles and scope of the invention as set forth in the appended claims. Accordingly, it is not intended that the invention be limited to the specific embodiments in the examples given above and / or in the accompanying drawings.

[0092] Although embodiments of the present invention have been shown and described, modifications thereof may be made by those skilled in the art without departing from the spirit or teachings of the present invention. The embodiments described herein are illustrative only and not limiting. Many variations and modifications of the compositions and methods are possible and are within the scope of the present invention. Thus, the scope of protection is not limited to the embodiments described herein, but is limited only by the following claims, which scope is intended to include all equivalents of the subject matter of the claims.

Claims

1. 1. A cycle etching method comprising the steps of: i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC being a compound represented by the formula C ｘ H ｙ F ｚ where x=2-5, y>z, and is a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, and removing the polymer layer deposited on the SiN layer at an etch front and the modified surface of the SiN layer by the plasma of the inert gas; and iii) repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming vertically straight SiN spacers with the SiN layer covering the sidewalls of the structure; A cyclic etching method, wherein the HFC plasma in step i), the inert gas plasma in step ii), or both, are pulsed plasmas.

2. After step i), pumping the reaction chamber to a vacuum; The reaction chamber is filled with N ２ purging with; pumping the reaction chamber to a vacuum; and introducing the inert gas into the reaction chamber to generate the plasma of the inert gas; and After step ii), pumping the reaction chamber to a vacuum; The reaction chamber is filled with N ２ purging with; pumping the reaction chamber to a vacuum; and introducing said HFC into said reaction chamber to generate a plasma of said HFC; The cyclic etching method of claim 1 further comprising:

3. 2. The cyclic etching method of claim 1, wherein a single or multiple frequency RF source is used to generate the pulsed plasma of the HFC in step i) and to generate the plasma of the inert gas in step ii), respectively.

4. The hydrofluorocarbon (HFC) is ２ , O ３ , CO, CO ２ , NO, NO ２ , N ２ O, S.O. ２ , C.O.S., H. ２ 4. The cyclic etching method of claim 1, wherein the oxygen-containing gas is selected from the group consisting of oxygen, nitrogen, oxygen, oxygen, oxygen-containing gas ...

5. The inert gas is N ２ 4. The cycle etching method according to claim 1, wherein the gas is selected from the group consisting of Ar, Kr and Xe.

6. The HFC is ２ H ５ F or C ３ H ７ The cyclic etching method according to any one of claims 1 to 3, wherein F is

7. The cyclic etching method of any one of claims 1 to 3, wherein the HFC selectively etches the SiN layer on the structure.

8. A footing is provided at each corner between the vertically straight SiN spacer and the substrate. The cyclic etching method according to any one of claims 1 to 3, wherein no burrs are formed.

9. A cycle etching method for forming vertically straight SiN spacers, comprising the steps of: i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of a mixture of a hydrofluorocarbon (HFC) and an oxygen-containing gas to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC being a compound represented by the formula C ｘ H ｙ F ｚ where x=2-5, y>z, and the oxygen-containing gas is a saturated or unsaturated, linear or cyclic HFC, ２ , O ３ , CO, CO ２ , NO, NO ２ , N ２ O, S.O. ２ , C.O.S., H. ２ O, and combinations thereof; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, and removing the polymer layer deposited on the SiN layer at an etch front and the modified surface of the SiN layer by the plasma of the inert gas; and iii) repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming vertically straight SiN spacers with the SiN layer covering the sidewalls of the structure; Including, The cyclic etching method, wherein the plasma of the mixture in step i), the plasma of the inert gas in step ii), or both, are pulsed plasmas.

10. 10. The cyclic etching method of claim 9, wherein a single or multiple frequency RF source is used to generate the pulsed plasma of the mixture in step i) and to generate the plasma of the inert gas in step ii), respectively.

11. The HFC selectively etches the SiN layer on the structure. ２ H ５ F or C ３ H ７ 11. The cyclic etching method according to claim 9 or 10, wherein F is

12. 11. The cyclic etching method of claim 9 or 10, wherein no footing is formed at each corner between the vertically straight SiN spacers and the substrate.

13. A cycle etching method for forming vertically straight SiN gate spacers, comprising the steps of: i) removing a SiN layer covering a gate stack on a substrate in a reaction chamber by C ２ H ５ F and C ３ H ７ and F to form a polymer layer deposited on the SiN layer that modifies the SiN layer surface; ii) exposing the polymer layer deposited on the SiN layer to a plasma of Ar, where the plasma of Ar removes the polymer layer deposited on the SiN layer at an etch front and the modified surface of the SiN layer; and iii) repeating steps i) and ii) until the SiN layer at the etch front is selectively removed, thereby forming vertically straight SiN gate spacers with the SiN layer covering the sidewalls of the gate stack; Including, A cyclic etching method, wherein the HFC plasma in step i), the Ar plasma in step ii), or both, are pulsed plasmas.

14. The generation of the pulsed plasma of the mixture in the step i) and the generation of the Ar plasma in the step ii) are each performed using a single or multiple frequency RF source. The cyclic etching method of claim 13, wherein:

15. The cyclic etching method according to any one of claims 13 to 14, wherein no footing is formed at each corner between the vertically straight SiN gate spacer and the substrate.

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