Support for 8-bit floating point operand in arithmetic architecture

Abstract

To provide a hardware for calculation using a 8-bit floating point operand.SOLUTION: A processing system 100 has a decoder for decoding fetched instructions. The decoded instructions are matrix instructions for use in using a 8-bit floating point operand to carry out parallel dot product operation. The system has a controller for scheduling the decoded instructions. The controller provides the 8-bit floating point operand with the input data in accordance with a 8-bit floating point data format designated by the decoded instructions. The system further has a systolic dot product circuit using a systolic layer to execute the decoded instructions. Each of the systolic layers has one or more sets each having a multiplier, a shifter and an adder which are connected to one another. Each set of the multiplier, the shifter and the adder generates a dot product of the 8-bit floating point operand.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001]

[0001] This invention relates generally to data processing, and more particularly to supporting 8-bit floating-point format operands in computing architectures. [Background technology]

[0002]

[0002] Modern parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed function computation units to process the graphics data; however, more recently, portions of graphics processors have been made programmable, allowing such processors to support a wider range of operations for processing vertex and fragment data.

[0003]

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel through different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple data (SIMD) or single instruction, multiple threads (SIMT) architectures are designed to maximize the amount of parallelism in the graphics pipeline. In a SIMD architecture, a computer with multiple processing elements attempts to perform the same operation on multiple data points simultaneously. In a SIMT architecture, a group of parallel threads attempts to synchronize and execute program instructions together as often as possible to increase processing efficiency.

[0004]

[0004] Graphics processors are frequently used for applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these fields have enabled ML models to utilize lower precision arithmetic for training neural networks. Traditional training platforms support floating-point 16 (FP16) and brain floating-point 16 (bfloat16 or BF16) data formats in high-performance systolic array implementations. Recently, they have been built to help train deep neural networks using lower precision data formats, such as 8-bit data formats. However, traditional systems do not provide hardware support for performing operations using 8-bit floating-point format operands. [Brief description of the drawings]

[0005]

[0005] In order to allow the above features of the present embodiment to be understood in detail, a more detailed description of the presently briefly summarized embodiment will be made by referring to the embodiment, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments and therefore should not be construed as limiting the scope thereof.

[0006]

[0006] [Figure 1] FIG. 1 is a block diagram of a processing system.

[0007] [Figure 2A] A computing system and a graphics processor are shown. [Figure 2B] A computing system and a graphics processor are shown. [Figure 2C] A computing system and a graphics processor are shown. [Figure 2D] A computing system and a graphics processor are shown.

[0008] [Figure 3A]1 shows a block diagram of an additional graphics processor and compute accelerator architecture. [Figure 3B] 1 shows a block diagram of an additional graphics processor and compute accelerator architecture. [Figure 3C] 1 shows a block diagram of an additional graphics processor and compute accelerator architecture.

[0009] [Figure 4] 1 is a block diagram of a graphics processing engine of a graphics processor. [Figure 5A] 1 illustrates the thread execution logic used in a graphics processor core, including an array of processing elements. [Figure 5B] The present invention illustrates a thread execution logic including an array of processing elements used in a graphics processor core. [Figure 6] 1 illustrates an additional execution unit. [Figure 7] 1 is a block diagram illustrating a graphics processor instruction format. [Figure 8] 1 is a block diagram of an additional graphics processor architecture. [Figure 9A] 2 shows the graphics processor command format and command sequence. [Figure 9B] 1 shows a graphics processor command format and command sequence. [Figure 10] 1 illustrates an exemplary graphics software architecture for a data processing system. [Figure 11A] 1 is a block diagram illustrating an IP core development system. [Figure 11B] 1 illustrates a cross-sectional side view of an integrated circuit package assembly. [Figure 11C]A package assembly is shown that includes multiple units of hardware logic chiplets connected to a substrate (e.g., a base die). [Figure 11D] FIG. 1 shows a package assembly including replaceable chiplets. [Figure 12] 1 is a block diagram illustrating an exemplary system on a chip integrated circuit. [Figure 13A] FIG. 1 is a block diagram illustrating an exemplary graphics processor for use within a SoC. [Figure 13B] 1 is a block diagram illustrating an exemplary graphics processor for use within an SoC. [Figure 14] 1 is a block diagram of a data processing system according to an embodiment. [Figure 15] FIG. 2 is a block diagram illustrating the Brain Float 8 (BFLOAT8 or BF8) binary format according to an embodiment. [Figure 16] 1 is a block diagram illustrating systolic DP 8-bit FP format operations performed by an instruction pipeline according to an embodiment. [Figure 17A] FIG. 2 is a block diagram illustrating a systolic array circuit for performing a systolic dot product on 8-bit floating-point format input operands according to an embodiment. [Figure 17B] 1 is a block diagram illustrating a systolic array circuit that performs a systolic dot product on 8-bit floating-point format input operands according to an embodiment. [Figure 18A] 1 illustrates an instruction that may be executed by a systolic array circuit according to an embodiment described herein. [Figure 18B] 1 illustrates a program code compilation process according to an embodiment. [Figure 19]1 is a flow chart illustrating an embodiment of a method for executing a systolic dot-product-accumulate instruction with respect to input operands in 8-bit floating-point format. [Figure 20] 1 is a flow chart illustrating an embodiment of a method for systolic dot product accumulation for input operands in 8-bit floating point format. [Figure 21] 1 is a block diagram illustrating an 8-bit FP format conversion operation performed by an instruction pipeline according to an embodiment. [Figure 22A] 1 illustrates instructions that may be executed by a processing unit according to embodiments described herein. [Figure 22B] 1 illustrates a program code compilation process according to an embodiment. [Figure 23] 1 is a flow chart illustrating an embodiment of a method for executing an instruction to convert floating point data to 8-bit floating point format data. [Figure 24] 1 is a flow chart illustrating an embodiment of a method for converting floating point data to 8-bit floating point format data. [Diagram 25] 1 is a block diagram illustrating an 8-bit FP format conversion with probabilistic rounding operations performed by an instruction pipeline according to an embodiment. [Figure 26] 1 is a block diagram illustrating fixed-point addition of a sign-magnitude representation of a mantissa and a random number according to an embodiment. [Figure 27A] 1 illustrates instructions that may be executed by a processing unit according to embodiments described herein. [Figure 27B] 1 illustrates a program code compilation process according to an embodiment. [Figure 28] 1 is a flow chart illustrating an embodiment of a method for executing instructions to perform efficient probabilistic rounding on floating-point values. [Figure 29] 1 is a flow chart illustrating an embodiment of a method for performing efficient probabilistic rounding on floating-point values. [Diagram 30] 1 is a block diagram illustrating two 8-bit floating-point formats using different binary encodings and exponent biases according to an embodiment. [Diagram 31] 1 is a block diagram illustrating systolic operations in a hybrid 8-bit FP format performed by an instruction pipeline according to an embodiment. [Diagram 32] 1 is a block diagram illustrating a hybrid FMA unit of a systolic array circuit for performing hybrid floating-point and stochastic operations according to an embodiment. [Figure 33A] 1 illustrates an instruction that may be executed by a systolic array circuit according to an embodiment described herein. [Figure 33B] 1 illustrates a program code compilation process according to an embodiment. [Diagram 34] 1 is a flow chart illustrating an embodiment of a method for executing an instruction of a hybrid floating point systolic operation. [Diagram 35] 1 is a flow chart illustrating an embodiment of a method for hybrid floating-point systolic operations. [Diagram 36] 1 is a block diagram illustrating mixed-mode 8-bit FP format operations performed by an instruction pipeline according to an embodiment. [Figure 37] 1 illustrates an exemplary schematic diagram of a hardware circuit for performing a mixed-mode MAC operation using at least one 8-bit FP format operand according to an embodiment. [Figure 38A] 1 illustrates a set of instructions executable by a processing unit according to embodiments described herein. [Figure 38B] 1 illustrates a program code compilation process according to an embodiment. [Figure 39] 13 is a flow chart illustrating an embodiment of a method for executing an instruction to perform mixed-mode operations with 8-bit floating-point format operands. [Diagram 40] 1 is a flow chart illustrating an embodiment of a method for performing mixed-mode operations using 8-bit floating-point format operands. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007]

[0054] A graphics processing unit (GPU) is communicatively coupled to a host / processor core, for example to accelerate graphics operations, machine learning operations, pattern analysis operations, and / or various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated on the same package or chip as the cores, or may be communicatively coupled to the cores on an internal processor bus / interconnect (i.e., internal to the package or chip). Regardless of how the GPU is connected, the processor cores can assign work to the GPU in the form of a set of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0008]

[0055] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the embodiments.

[0009] System Overview

[0056] 1 is a block diagram of a processing system 100 according to an embodiment. System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices, such as those in Internet of Things (IoT) devices that utilize wired or wireless connections to local or wide area networks.

[0010]

[0057] In one embodiment, the system 100 may include, be coupled to, or be integrated into a server-based gaming platform; a gaming console, including a game and media console; a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, the system 100 is part of a mobile Internet-connected device, such as a mobile phone, a smart phone, a tablet computing device, or a laptop with a small internal storage capacity. The processing system 100 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device; smart eyewear or clothing enhanced with augmented reality (AR) or virtual reality (VR) capabilities to provide visual, auditory, or tactile output to supplement a real-world visual, auditory, or tactile experience, or to provide other text, audio, graphic, video, holographic images or video, or tactile feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. In some embodiments, processing system 100 includes or is part of a television or set-top box device. In one embodiment, system 100 can include, be coupled to, or be integrated into an autonomous vehicle, such as a bus, a tractor trailer, an automobile, a motor or electric bicycle, an airplane or glider (or any combination thereof). The autonomous vehicle can use system 100 to process the sensed environment around the vehicle.

[0058] In some embodiments, the one or more processors 102 each include one or more processor cores 107 for processing instructions that, when executed, perform operations for system or user software. In embodiments herein, a processor may be referred to as a dedicated hardware circuit for efficiently processing commands / instructions and may be referred to as a processor circuit. In some embodiments, at least one of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate Complex Instruction Set Arithmetic (CISC), Reduced Instruction Set Arithmetic (RISC), or Very Long Instruction Word (VLIW) operations. The one or more processor cores 107 may process different instruction sets 109 that may include instructions to facilitate emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as a digital signal processor (DSP).

[0011]

[0059] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared within the processor core 107 using known cache coherency techniques. A register file 106 may additionally be included in the processor 102 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0012]

[0060] In some embodiments, the one or more processors 102 are coupled to one or more interface buses 110 to carry communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. The interface bus 110, in one embodiment, may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In one embodiment, the processor 102 includes an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connectivity to I / O devices over a local I / O bus.

[0013]

[0061] The memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device having suitable performance to act as process memory. In one embodiment, the memory device 120 may operate as a system memory for the system 100 to store data 122 and instructions 121 for use when the one or more processors 102 execute applications or processes. The memory controller 116 also couples to an optional external graphics processor 118 that may communicate with one or more graphics processors 108 in the processor 102 and perform graphics and media operations. In some embodiments, graphics, media, and / or computational operations may be assisted by an accelerator 112, which is a co-processor that may be configured to perform a specialized set of graphics, media, or computational operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or computational operations. In one embodiment, accelerator 112 is a ray tracing accelerator that may be used to perform ray tracing operations in coordination with graphics processor 108. In one embodiment, external accelerator 119 may be used in place of or in coordination with accelerator 112.

[0014]

[0062] In some embodiments, a display device 111 may be connected to the processor 102. The display device 111 may be one or more internal display devices, such as those in a mobile electronic device, a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 111 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0015]

[0063] In some embodiments, the platform controller hub 130 allows peripherals to connect to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). The network controller 134 may enable network connectivity to a wired network. In some embodiments, a high performance network controller (not shown) is coupled to the interface bus 110. The audio controller 146, in one embodiment, is a multi-channel high definition audio controller. In one embodiment, the system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.The platform controller hub 130 may also be connected to one or more universal serial bus (USB) controllers 142 to which input devices such as a keyboard and mouse combination 143, a camera 144, or other USB input devices may be connected.

[0016]

[0064] It will be understood that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured differently may be used. For example, instances of platform controller hub 130 and memory controller 116 may be integrated into a separate external graphics processor, such as external graphics processor 118. In one embodiment, platform controller hub 130 and / or memory controller 116 may be external to one or more processors 102. For example, system 100 may include external memory controller 116 and platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 102.

[0017]

[0065] For example, the circuit board (sled) on which components such as the CPU, memory, and other components are placed is designed for increased thermal characteristics. In some examples, processing components such as the processor are placed on the top side of the sled, while memory vicinity such as DIMMs are placed on the bottom side of the sled. As a result of the increased airflow provided by this design, the components can operate at higher frequencies and power levels than in a typical system, thereby improving performance. Additionally, the sled is configured to mate hand-in-hand with power and data communication cables in the rack, thereby enhancing the ability to quickly remove, upgrade, reinstall, and / or replace the sled. Similarly, the individual components placed on the sled, such as the processor, accelerator, memory, and data storage drives, are configured to be easily upgraded due to the increased spacing between each other. In an exemplary embodiment, the components further include hardware authentication features to prove their authenticity.

[0018]

[0066] Data centers can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and Omni-Path. The threads can be coupled to switches via fiber optics, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Cat5, Cat5e, Cat6, etc.). Due to the high bandwidth, low latency interconnect and network architecture, data centers can pool resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network, and / or artificial intelligence accelerators, etc.), and physically disaggregated data storage drives, when in use, and provide them to computational resources (e.g., processors) as needed, allowing the computational resources to access the pooled resources as if they were local.

[0019]

[0067] A power supply or power source can provide voltage and / or current to system 100 or any component or system described herein. In one example, the power source includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar power) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging via the proximity of a charging field. In one example, the power source can include an internal battery, an AC power source, a motion-based power source, a solar power source, or a fuel cell power source.

[0068] 2A-2D illustrate a computing system and graphics processor provided by embodiments described herein. Elements of FIG. 2A-2D having the same reference number (or name) as elements in any other figure of the present application may operate or function in any manner similar to that described elsewhere in the present application, but are not limited to such.

[0020]

[0069] 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Processor 200 includes and can include additional cores up to additional core 202N, represented by a dashed box. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and the shared cache unit 206 represent a cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), and other cache levels, where the highest level of cache before external memory is classified as an LLC. In some embodiments, cache coherence logic maintains coherency between the various cache units 206 and 204A-204N.

[0021]

[0070] In some embodiments, processor 200 may include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

[0022]

[0071] In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multi-threading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A-202N during multi-threaded processing. The system agent core 210 may further include a power control unit (PCU) that includes logic and components for coordinating the power state of the processor cores 202A-202N and the graphics processor 208.

[0023]

[0072] In some embodiments, processor 200 additionally includes a graphics processor 208 to perform graphics processing operations. In some embodiments, graphics processor 208 couples to a set of shared cache units 206, including one or more integrated memory controllers 214, and a system agent core 210. In some embodiments, system agent core 210 also includes a display controller 211 that drives the graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within graphics processor 208.

[0024]

[0073] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of processor 200. However, other interconnect units may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including those known in the art. In some embodiments, graphics processor 208 couples to ring interconnect 212 via I / O link 213.

[0025]

[0074] The exemplary I / O link 213 represents at least one of several types of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 may use the embedded memory module 218 as a shared, last-level cache.

[0026]

[0075] In some embodiments, the processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 202A-202N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively high power consumption are combined with one or more power cores having a lower power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of computational capabilities. Additionally, the processor 200 may be implemented as one or more chips or SoC integrated circuits having the illustrated components, in addition to other components.

[0027]

[0076] FIG. 2B is a block diagram of hardware logic of a graphics processor core 219 according to some embodiments described herein. Elements of FIG. 2B having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, including, but not limited to, the manner described elsewhere herein. The graphics processor core 219 may be one or more graphics cores, sometimes referred to as a core slice, in a modular graphics processor. The graphics processor core 219 is an example of a graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 may include a fixed function block 230 coupled with multiple sub-cores 221A-221F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0028]

[0077] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231 that may be shared by all sub-cores in graphics processor core 219, e.g., in a lower performance and / or lower power graphics processor implementation. In various embodiments, geometry / fixed function pipeline 231 includes a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer (e.g., unified return buffer 418 of FIG. 4, described below), a 3D fixed function pipeline (e.g., 3D pipeline 312 of FIGS. 3A and 4).

[0029]

[0078] In one embodiment, the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores in the system on a chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that can be configured to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and preemption. The media pipeline 234 (e.g., media pipeline 316 of FIGS. 3A and 4) includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multi-media data, including image and video data. The media pipeline 234 performs media operations via requests for computation or sampling logic in the sub-cores 221-221F.

[0030]

[0079] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with general purpose application processor cores and / or other components in the SoC, including memory hierarchy elements such as shared last level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 232 also enables communication with fixed function devices in the SoC, such as a camera imaging pipeline, and enables and / or implements the use of global memory atomics that may be shared between a CPU and the graphics processor core 219 in the SoC. The SoC interface 232 may also implement power management controls for the graphics processor core 219 and enable an interface between the clock domain of the graphics core 219 and other clock domains in the SoC. In one embodiment, the SoC interface 232 enables receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. Commands and instructions can be dispatched to the media pipeline 234 if media operations are to be performed, or to the geometry and fixed function pipelines (e.g., to the geometry and fixed function pipeline 231, the geometry and fixed function pipeline 237) if graphics processing operations are to be performed.

[0031]

[0080] The graphics microcontroller 233 can be configured to perform various scheduling and management tasks for the graphics processor core 219. In one embodiment, the graphics microcontroller 233 can perform graphics and / or compute workload scheduling on various graphics parallel engines in the execution unit (EU) arrays 222A-222F, 224A-224F in the sub-cores 221A-221F. In this scheduling model, host software running on a CPU core of the SoC including the graphics processor core 219 can submit a workload to one of a number of graphics processor doorbells which initiates a scheduling operation on the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to a command streamer, preempting existing workloads running on the engines, monitoring the progress of the workload, and notifying the host software when the workload is completed. In one embodiment, graphics microcontroller 233 may also facilitate low power or idle states for graphics processor core 219 and may provide graphics processor core 219 with the ability to save and restore registers within graphics processor core 219 across low power state transitions independent of the system's operating system and / or graphics driver software.

[0032]

[0081] Graphics processor core 219 may have up to N modular sub-cores, which may be more or less than the illustrated sub-cores 221A-221F. For each set of N sub-cores, graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipeline 237, and additional fixed function logic 238 for various graphics acceleration and computational processing. Shared function logic 235 may include logic units related to shared function logic 420 of FIG. 4 (e.g., sampler, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics processor core 219. Shared and / or cache memory 236 may be a last level cache for the set of N sub-cores 221A-221F in graphics processor core 219 and may function as a shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 237 may be included in place of geometry / fixed function pipeline 231 in fixed function block 230 and may include the same or similar logical units.

[0033]

[0082] In one embodiment, graphics processor core 219 includes additional fixed function logic 238, which may include various fixed function acceleration logic used by graphics processor core 219. In one embodiment, additional fixed function logic 238 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline in geometry / fixed function pipeline 238, 231, and a cull pipeline, which is an additional geometry pipeline that may be included in additional fixed function logic 238. In one embodiment, the cull pipeline is a trimmed-down version of the full geometry pipeline. The full pipeline and the cull pipeline may run different instances of the same application, with each instance having a separate context. Position-only shading may hide long cull runs of discarded triangles, potentially allowing shading to complete sooner. For example, in one embodiment, the cull pipeline logic in additional fixed function logic 238 can execute position shaders in parallel with the main application, and generally produces critical results faster than the full pipeline because the cull pipeline fetches and shades only the position attributes of vertices without rasterizing and rendering the pixels to the frame buffer. The cull pipeline can use the critical results produced to compute visibility information for all triangles, whether those triangles are culled or not. The full pipeline (which in this example may be referred to as a reproduction pipeline) can use the visibility information to skip culled triangles in order to occlude only visible triangles that are ultimately passed to the rasterization stage.

[0034]

[0083] In one embodiment, the additional fixed function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations that include optimizations for machine learning training or inference.

[0035]

[0084] Contained within each graphics sub-core 221A-221F is a set of execution resources that can be used to perform graphics, media, and computational operations as requested by the graphics pipeline, media pipeline, or shader programs. The graphics sub-cores 221A-221F include a number of EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD / IC) logic 223A-223F, 3D (e.g., texture) samplers 225A-225F, media samplers 206A-206F, shader processors 227A-227F, and shared local memories (SLMs) 228A-228F. The EU arrays 222A-222F, 224A-224F each include multiple execution units, which are general purpose graphics processing units capable of executing floating point and integer / fixed point logic operations, including graphics, media, or computation shader programs, in service of graphics, media, or computation operations. The TD / IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units in the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. The 3D samplers 225A-225F can load textures or other 3D graphics related data into memory. The 3D samplers can load texture data differently based on the configured sample state and the texture format associated with a given texture. The media samplers 206A-206F can perform a similar load operation based on the type and format associated with the media data. In one embodiment, each graphics sub-core 221A-221F may alternatively include a unified 3D and media sampler. Threads executing in execution units within each sub-core 221A-221F may use shared local memory 228A-228F within each sub-core, allowing threads executing within a thread group to execute using a common pool of on-chip memory.

[0036]

[0085] 2C illustrates a graphics processing unit (GPU) 239 that includes a dedicated set of graphics processing resources arranged into multi-core groups 240A-240N. Although details of only a single multi-core group 240A are provided, it will be understood that the other multi-core groups 240B-240N may include the same or similar sets of graphics processing resources.

[0037]

[0086] As shown, multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 243, 244, 245. A set of register files 242 store operand values ​​used by cores 243, 244, 245 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0038]

[0087] One or more combined level 1 (L1) cache and shared memory units 247 store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multi-core group 240A. One or more texture units 247 may also be used to perform texturing operations, such as texture mapping and sampling. A level 2 (L2) cache 253, shared by all or a subset of the multi-core groups 240A-240N, stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 253 may be shared across multiple multi-core groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to memory 249, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0039]

[0088] Input / output (I / O) circuitry 250 couples GPU 239 to one or more input / output devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple I / O devices 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 directly couple I / O devices 252 to system memory 249. In one embodiment, IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, I / O devices 252, CPU 246, and GPU 239 may share the same virtual address space.

[0040]

[0089] In some implementations, IOMMU 251 supports virtualization, where it may manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., in system memory 249). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped in a context switch (e.g., so that a new context is provided for accessing the associated set of page tables). Although not shown in FIG. 2C, each of cores 243, 244, 245 and / or multi-core groups 240A-240N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical, guest physical to guest virtual, and guest virtual to host physical translations.

[0041]

[0090] In one embodiment, CPU 246, GPU 239, and I / O devices 252 are integrated into a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 includes GDDR6 memory that shares the same virtual address space with other physical system-level memory, although the principles underlying the invention are not limited to this particular implementation.

[0042]

[0091] In one embodiment, tensor core 244 includes multiple execution units specifically designed to perform matrix operations, which are fundamental mathematical operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations can be used for neural network training and inference. Tensor core 244 can perform matrix operations using a variety of operand precisions, including single precision floating point (e.g., 32 bits), half precision floating point (e.g., 16 bits), integer word (16 bits), byte (8 bits), and half byte (4 bits). In one embodiment, the neural network implementation extracts features for each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0043]

[0092] In a deep learning implementation, parallel matrix multiplication operations may be scheduled for execution on tensor cores 244. Training neural networks, in particular, requires a significant number of matrix dot product operations. To process the inner product formulation of N×N×N matrix multiplication, tensor cores 244 may include at least N dot product processing elements. Before the matrix multiplication begins, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded each of the N cycles. There are N dot products processed per cycle.

[0044]

[0093] Matrix elements may be stored in different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8), 4-bit half-bytes (e.g., INT4), etc. Different precision modes may be specified for tensor cores 244 to ensure that the most efficient precision is used for various workloads (e.g., inference workloads that can tolerate quantization to bytes and half-bytes).

[0045]

[0094] In one embodiment, ray tracing core 245 accelerates ray tracing computations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, ray tracing core 245 includes ray traverse / intersection circuitry for performing ray traversal using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed by the BVH volume. Ray tracing core 245 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar configuration). In one embodiment, ray tracing core 245 performs traversal and intersection operations in coordination with the image denoising techniques described herein, at least some of which may be performed in tensor core 244. For example, in one embodiment, tensor core 244 implements a deep learning neural network to perform denoising of frames generated by ray tracing core 245. However, the CPU 246, the graphics core 243, and / or the ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0046]

[0095] Additionally, as discussed above, a distributed approach to denoising may be used in situations where the GPU 239 is in a computing device coupled to other computing devices via a network or high speed interconnect, in which the interconnected computing devices share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0047]

[0096] In one embodiment, the ray tracing core 245 handles all BVH traversals and ray-primitive intersections, preventing the graphics core 243 from becoming overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuitry for performing bounding box tests (e.g., traversal operations) and a second set of specialized circuitry for performing ray-triangle intersection tests (e.g., intersecting rays that cross). Thus, in one embodiment, the multi-core group 240A can simply initiate ray probes, and the ray tracing core 245 independently performs ray traversals and intersections and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or compute other work while the ray tracing core 245 performs the traversal and intersection operations.

[0048]

[0097] In one embodiment, each ray tracing core 245 includes a traversal unit for performing BVH test operations and an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit," "no hit," or "multi-hit" response and provides it to the appropriate thread. Between traversal and intersection operations, the execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed to perform other forms of graphics work.

[0049]

[0098] In one particular embodiment described below, a hybrid rasterization / ray tracing approach is used in which work is distributed between the graphics core 243 and the ray tracing core 245.

[0050]

[0099] In one embodiment, ray tracing core 245 (and / or other cores 243, 244) includes hardware support for Microsoft's DirectX Ray Tracing (DXR), including the DispatchRays command, and a ray tracing instruction set such as ray generation, nearest hit, any hit, and miss shaders, which allows for the assignment of a set of shaders and textures for each object. Another ray tracing platform that may be supported by ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, the underlying principles of the present embodiments are not limited to any particular ray tracing ISA.

[0051]

[0100] In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions / functions for ray generation, nearest hit, any hit, ray-primitive intersection, primitive and hierarchy related bounding box construction, misses, visits, and exceptions. More specifically, one embodiment includes ray tracing instructions for performing the following functions:

[0101] ray generation - Ray generation commands can be executed for each pixel, sample, or other user-defined work allocation.

[0052]

[0102] Nearest Hits - A nearest hit command can be executed to find the nearest intersection point of a ray with a primitive in the scene.

[0053]

[0103] Any hit - The any hit command identifies multiple intersection points between rays and primitives in the scene, and potentially identifies a new closest intersection point.

[0054]

[0104] Intersection - The intersection commands perform ray-primitive intersection tests and output the results.

[0055]

[0105] Primitive-related bounding box construction - This command builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0056]

[0106] Miss - Indicates that the ray misses all geometry in the scene, or a specific area of ​​the scene.

[0057]

[0107] Visit - Indicates the child volume that the ray will traverse.

[0058]

[0107] exception - Contains different types of exception handling (called for different error conditions)

[0109] FIG. 2D is a block diagram of a general purpose graphics processing unit (GPGPU) 270 that can be configured as a graphics processor and / or computer accelerator according to embodiments described herein. The GPGPU 270 can be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, the memory 271 is a system memory that may be shared with one or more CPUs 246, and the memory 272 is a device memory dedicated to the GPGPU 270. In one embodiment, components within the GPGPU 270 and the device memory 272 may be mapped to memory addresses accessible to one or more CPUs 246. Access to the memories 271 and 272 can be facilitated by a memory controller 268. In one embodiment, the memory controller 268 can include an internal direct memory access (DMA) controller 269 or logic to perform operations that would otherwise be performed by the DMA controller.

[0059]

[0110] The GPGPU 270 includes a number of cache memories, including an L2 cache 253, an L1 cache 254, an instruction cache 255, and a shared memory 256, at least some of which may be partitioned as cache memories. The GPGPU 270 also includes a number of computational units 260A-260N. Each computational unit 260A-260N includes a set of vector registers 261, scalar registers 262, a vector logic unit 263, and a scalar logic unit 264. The computational units 260A-260N may also include a local shared memory 265 and a program counter 266. The computational units 260A-260N may be coupled with a constant cache 267, which may be used to store constant data, which is data that does not change during the execution of a kernel or shader program running on the GPGPU 270. In one embodiment, constant cache 267 is a scalar data cache, and cached data can be fetched directly into scalar registers 262 .

[0060]

[0111] During operation, one or more CPU(s) 246 can write commands to registers or memory in GPGPU 270 that are mapped to an accessible address space. Command processor 257 can read commands from registers or memory and determine how these commands are processed in GPGPU 270. Thread dispatcher 258 can then dispatch threads to compute units 260A-260N to execute these commands. Each compute unit 260A-260N can execute threads independently of the other compute units. Additionally, each compute unit 260A-260N can be independently configured for conditional computation and can conditionally output computation results to memory. Command processor 257 can interrupt one or more CPUs 246 when a submitted command is completed.

[0061]

[0112] 3A-3C show block diagrams of additional graphics processor and compute accelerator architectures provided by embodiments described herein. Elements of FIG. 3A-3C having the same reference numbers (or names) as elements of any other figure of this application may operate or function in a similar manner as described elsewhere in this application, but are not limited to such.

[0062]

[0113] 3A is a block diagram of a graphics processor 300, which may be, but is not limited to, a separate graphics processing unit or a graphics processor integrated with multiple processing cores or other semiconductor devices such as memory devices or network interfaces. In some embodiments, the graphics processor communicates through a memory-mapped I / O interface to registers on the graphics processor and with commands located in the processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0063]

[0114] In some embodiments, graphics processor 300 also includes a display controller 302 that drives display output data to a display device 318. Display controller 302 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. Display device 318 can be an internal or external display device. In one embodiment, display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 that encodes, decodes, or transcodes media to, from, or between one or more media encoding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9, ​​and the Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG and Motion JPEG (MJPEG).

[0064]

[0115] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some implementations, GPE 310 is a computation engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0065]

[0116] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D processing such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable & fixed function elements that perform various tasks within the element and / or generate execution threads in 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media processing, embodiments of GPE 310 also include a media pipeline 316 that is used specifically to perform media processing such as video post-processing and image enhancement.

[0066]

[0117] In some embodiments, the media pipeline 316 includes fixed function or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, on behalf of or in lieu of the video codec engine 306. In some embodiments, the media pipeline 316 additionally includes a thread generation unit that generates threads for execution in the 3D / media subsystem 315. The generated threads perform operations for the media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0067]

[0118] In some embodiments, the 3D / Media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / Media subsystem 315, which includes thread dispatch logic for arbitrating the various requests and dispatching them to available thread execution resources. The execution resources include an array of graphics execution units for processing the 3D and media threads. In some embodiments, the 3D / Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0068]

[0119] FIG. 3B illustrates a graphics processor 320 having a tiled architecture according to an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A in graphics engine tiles 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D can be graphics double data rate (GDDR) memory. The memory devices 326A-326D, in one embodiment, are high bandwidth memory (HBM) modules that may be on a die with their respective graphics engine tiles 310A-310D. In one embodiment, the memory devices 326A-326D are stacked memory devices that may be stacked on top of their respective graphics engine tiles 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D resides on a separate chiplet that is coupled to a base die or base substrate, as described in further detail in Figures 11B-11D.

[0069]

[0120] The graphics processor 320 may be configured with a non-uniform memory access (NUMA) system in which memory devices 326A-326D are coupled to associated graphics engine tiles 310A-310D. A given memory device may be accessed by graphics engine tiles other than the tile to which it is directly connected. However, access latency to memory devices 326A-326D will be lowest when accessing the local tile. In one embodiment, a cache coherent NUMA (ccNUMA) system uses tile interconnects 323A-323F to enable communication between cache controllers in the graphics engine tiles 310A-310D to maintain a consistent memory image when multiple caches store the same memory location.

[0070]

[0121] The graphics processing engine cluster 322 may be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 may enable communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 may be used to move data to, from, in, and between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 may also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable connection to an external display device 318. The graphics processor may also be configured as a graphics or compute accelerator. In an accelerator configuration, the display controller 302 and the display device 318 may be omitted.

[0071]

[0122] Graphics processor 320 may connect to a host system via host interface 328. Host interface 328 may enable communication between graphics processor 320, system memory, and / or other system components. Host interface 328 may be, for example, a PCI Express bus or other type of host system interface.

[0072]

[0123] FIG. 3C illustrates a computation accelerator 330 according to an embodiment described herein. The computation accelerator 330 may include an architecture similar to the graphics processor 320 of FIG. 3B and is optimized for computation acceleration. The computation engine cluster 332 may include a set of computation engine tiles 340A-340D that include execution logic optimized for parallel or vector-based general-purpose computation. In some embodiments, the computation engine tiles 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the computation engine tiles 340A-340D may include logic for performing media acceleration. The computation engine tiles 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and memory interconnects 325A-325D may be of similar technology to the graphics processor 320 or may be different. The graphics compute engine tiles 340A-340D may also be interconnected via a set of tile interconnects 323A-323F, which may be connected to and / or interconnected by the fabric interconnect 324. In one embodiment, the compute accelerator 330 includes a large L3 cache 336, which may be configured as a device-wide cache. The compute accelerator 330 may also be connected to a host processor and memory via a host interface 328, in a manner similar to the graphics processor 320 of FIG. 3B.

[0073] Graphics Processing Engine

[0124] FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A and may represent the graphics engine tiles 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as elements of any other figure herein may operate or function in a similar manner as described elsewhere in this application, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are shown. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, in at least one embodiment, separate media and / or image processors are coupled to the GPE 410.

[0074]

[0125] In some embodiments, the GPE 410 is coupled to or includes a command streamer 403 that provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 is coupled to a memory, which may be one or more of a system memory or an internal cache memory and a shared cache memory. In some embodiments, the command streamer 403 receives commands from the memory and sends the commands to the 3D pipeline 312 and / or the media pipeline 316. The commands are directives that are fetched from a ring buffer that stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. The commands for the 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometric data for the 3D pipeline 312, and / or image data and memory objects for the media pipeline 316. 3D pipeline 312 and media pipeline 316 process commands and data by executing operations on logic within the respective pipelines or by dispatching one or more execution threads to graphics core array 414. In one embodiment, graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core 415A, graphics core 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources including general purpose and graphics-specific execution logic for performing graphics and computational processing, as well as fixed function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0075]

[0126] In various embodiments, the 3D pipeline 312 may include fixed function & programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. The multipurpose execution logic (e.g., execution units) within the graphics cores 415A-414B of the graphics core array 414 includes support for various 3D API shader languages ​​and is capable of running multiple concurrent threads of execution associated with multiple shaders.

[0076]

[0127] In some embodiments, the graphics core array 414 includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution units include general purpose logic that is programmable to perform parallel general purpose computations in addition to graphics computations. The general purpose logic may perform computations in parallel or in conjunction with general purpose logic in the processor core 107 of FIG. 1 or cores 202A-202N such as those in FIG. 2A.

[0077]

[0128] Output data generated by threads executing on graphics core array 414 may output data to memory in unified return buffers (URBs) 418. URBs 418 may store data for multiple threads. In some embodiments, URBs 418 may be used to transmit data between different threads executing on graphics core array 414. In some embodiments, URBs 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic in shared function logic 420.

[0078]

[0129] In some implementations, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment, the execution resources are dynamically scalable, such that execution resources may be enabled or disabled.

[0079]

[0130] The graphics core array 414 couples to shared function logic 420 that includes multiple resources shared among the graphics cores in the graphics core array. The shared functions in the shared function logic 420 are hardware logic units that provide specialized complementary functions to the graphics core array 414. In various embodiments, the shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 in the shared function logic 420.

[0080]

[0131] Shared functionality is implemented at least when the demand for a given specialized functionality is insufficient for inclusion within the graphics core array 414. Instead, a single instance of that specialized functionality is implemented as a stand-alone entity within the shared functionality logic 420 and shared among the execution resources within the graphics core array 414. The exact set of functionality shared among and included within the graphics core array 414 varies from embodiment to embodiment. In some embodiments, certain shared functionality within the shared functionality logic 420 that is used extensively by the graphics core array 414 may be included within the shared functionality logic 416 within the graphics core array 414. In various embodiments, the shared functionality logic 416 within the graphics core array 414 may include some or all of the logic within the shared functionality logic 420. In one embodiment, all logic elements within the shared functionality logic 420 may be duplicated within the shared functionality logic 416 of the graphics core array 414. In one embodiment, the shared function logic 420 is omitted in favor of the shared function logic 416 in the graphics core array 414.

[0081] Execution Unit

[0132] 5A-5B illustrate thread execution logic 500 including an array of processing elements for use in a graphics processor core, according to embodiments described herein. Elements in FIG. 5A-5B having the same reference numbers (or names) as elements in other figures of the present application may operate or function in a manner similar to that described elsewhere in the present application, but are not limited to such. FIG. 5A-5B illustrates an overview of thread execution logic 500 that may represent the hardware logic shown in each of sub-cores 221A-221F of FIG. 2B. FIG. 5A represents an execution unit in a general-purpose graphics processor, while FIG. 5B represents an execution unit that may be used in a computer accelerator.

[0082]

[0133] 5A, in some embodiments, the thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit including multiple execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array is capable of dynamically scaling by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D, through 508N-1 and 508N) based on the computational requirements of a workload. In one embodiment, the included components are interconnected via an interconnect structure that links each of the components. In some embodiments, the thread execution logic 500 includes one or more connections to memory, such as system memory or cache memory, via one or more of the instruction cache 506, data port 514, sampler 510, and execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a stand-alone programmable general-purpose computing unit capable of executing multiple simultaneous hardware / threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

[0083]

[0134] In some embodiments, the execution units 508A-508N are primarily used to execute shader programs. The shader processor 502 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 504. In one embodiment, the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution units within the execution units 508A-508N. For example, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 504 can also handle run-time thread creation requests from the executing shader programs.

[0084]

[0135] In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct3D and OpenGL) execute with minimal translation. The execution units support vertex and geometric processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, allowing for an efficient execution environment when multi-threaded operation faces higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock against a pipeline capable of performing integer, single and double precision floating point operations, SIMD branching capability, logical operations, transcendental operations, and other operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units 508A-508N causes the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources may be allocated to processing other threads. For example, during the delay associated with a vertex shader operation, the execution unit may execute operations for a pixel shader, fragment shader, or another type of shader program (including a vertex shader). Various embodiments may apply to the use of execution through the use of single instruction multiple threads (SIMT) as an alternative to or in addition to using SIMD. References to SIMD cores or operations may also apply to SIMT or SIMD in combination with SIMT.

[0085]

[0136] Each of the execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size", or number of channels, of the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 508A-508N support integer and floating point data types.

[0086]

[0137] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit processes the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 54-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double-Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (Byte (B) size data elements). However, different vector widths and register sizes are possible.

[0087]

[0138] In one embodiment, one or more execution units may be combined into a fused execution unit 509A-509N with thread control logic (507A-507N) common to the fused EUs. Multiple EUs may be fused into an EU group. Each EU in a fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group may vary depending on the embodiment. Additionally, various SIMD widths may be implemented per EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, a second EU 508B, and thread control logic 507A common to the first EU 508A and the second EU 508B. Thread control logic 507A controls the threads executing in fused graphics execution unit 509A and allows each EU in fused execution units 509A-509N to execute using a common instruction pointer register.

[0088]

[0139] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 for caching thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included for caching thread data during thread execution. Threads executing on the execution logic 500 may also store explicitly managed data in the shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D processing and media sampling for media processing. In some embodiments, the sampler 510 includes specialized texture or media sampling functions for processing texture or media data during the sampling process before providing the sampled data to the execution units.

[0089]

[0140] During execution, the graphics and media pipeline sends thread start requests to the thread execution logic 500 via thread creation and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 502 is invoked to further compute output information and write the results to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates values ​​for various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 502 then executes application programming interface (API) supplied pixel or fragment shader programs. To execute the shader programs, the shader processor 502 dispatches threads to the execution units (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses texture sampling logic in the sampler 510 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data calculate pixel color data for each geometric piece or eliminate one or more pixels from further processing.

[0090]

[0141] In some embodiments, the data port 514 provides a memory access mechanism for the thread execution logic 500 and outputs processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, the data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) for caching data for memory access via the data port.

[0091]

[0142] In one embodiment, the execution logic 500 may also include a ray tracer 505 capable of providing ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be similar to or different from the ray tracing instruction set supported by the ray tracing core 245 of FIG. 2C.

[0092]

[0143] 5B illustrates exemplary internal details of an execution unit 508 according to an embodiment. The graphics execution unit 508 may include an instruction fetch unit 537, a general purpose register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and in one embodiment, a set of dedicated integer SIMD ALUs 535. The GRF 524 and ARF 526 include a set of general purpose register files and architectural register files associated with each concurrent hardware thread that may be active in the graphics execution unit 508. In one embodiment, per-thread architectural state is maintained in the ARF 526, and data used during thread execution is stored in the GRF 524. The execution state of each thread, including an instruction pointer for each thread, may be held in thread-specific registers in the ARF 526.

[0093]

[0144] In one embodiment, the GSU 508 has an architecture that is a combination of simultaneous multithreading (SMT) and finely interleaved multithreading (IMT). The architecture has a modular organization that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where the execution unit resources are divided across the logic used to execute multiple simultaneous threads. The number of logical threads that can be executed by the GSU 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0094]

[0145] In one embodiment, the graphics execution unit 508 can issue multiple instructions together, each of which may be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instruction to one of the send unit 530, the branch unit 532, or the SIMD FPU 534 for execution. Each execution thread can access 128 general purpose registers in the GRF 524, each of which can store 32 bytes and is accessible as a SIMD 8 element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4K bytes in the GRF 524, although embodiments are not so limited and other embodiments may provide greater or lesser register resources. In one embodiment, the graphics execution unit 508 is divided into seven hardware threads capable of independently executing computations, although the number of threads per execution unit may vary depending on the embodiment. For example, in one embodiment, up to 16 hardware threads are supported. In an embodiment where seven threads may access 4K bytes, the GRF524 can store a total of 28K bytes. If 16 threads can access 4K bytes, the GRF524 can store a total of 64K bytes. Flexible addressing modes allow registers to be addressed together, effectively building wider registers or representing strided rectangular block data structures.

[0095]

[0146] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched by "send" instructions executed by a message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD diversity and eventual convergence.

[0096]

[0147] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPUs) 534 to perform floating point operations. In one embodiment, the FPU(s) 534 also support integer operations. In one embodiment, the FPUs 534 can perform up to M 32-bit floating point (or integer) SIMD operations, or up to 2M 16-bit integer or 16-bit floating point SIMD operations. In one embodiment, at least one of the FPUs provides extended math capabilities supporting high throughput transcendental math functions and double precision 54-bit floating point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present and may be specially optimized to perform operations related to machine learning operations.

[0097]

[0148] In one embodiment, an array of multiple instances of the graphics execution unit 508 can be instantiated in a graphics sub-core grouping (e.g., sub-slice). For scalability, the product architecture can select the exact number of execution units per sub-core group. In one embodiment, the execution unit 508 can execute instructions across multiple execution channels. In a further embodiment, each thread executing in the graphics execution unit 508 executes on a different channel.

[0098]

[0149] FIG. 6 illustrates an additional execution unit 600 according to one embodiment. The execution unit 600 may be a computationally optimized execution unit for use in the compute engine tiles 340A-340D, such as those in FIG. 3C, but is not so limited. Variations of the execution unit 600 may also be used in the graphics engine tiles 310A-310D, as shown in FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604 (also referred to herein as a decoder). The execution unit 600 further includes a register file 606 that stores registers that can be allocated to hardware threads within the execution unit. The execution unit 600 additionally includes a send unit 607 and a branch unit 608. In one embodiment, sending unit 607 and branching unit 608 may operate similarly to sending unit 530 and branching unit 532 of graphics execution unit 508 in FIG. 5B.

[0099]

[0150] Execution unit 600 also includes a computation unit 610 that includes multiple different types of functional units. In one embodiment, computation unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. The integer and floating point operations may be performed simultaneously. Computation unit 610 may also include a systolic array 612 and a math unit 613. Systolic array 612 includes a wide W and deep D network of data processing units that can be used to perform vector or other data parallel operations in a systolic manner. In one embodiment, systolic array 612 can be configured to perform matrix operations such as matrix dot product operations. In one embodiment, systolic array 612 supports 8-bit and 4-bit integer operations in addition to 16-bit floating point operations. In one embodiment, systolic array 612 can be configured to accelerate machine learning operations. In such an embodiment, systolic array 612 may be configured to support the bfloat 16-bit floating point format. In one embodiment, math unit 613 may be included to perform a particular subset of mathematical operations in a more efficient and lower power manner than ALU unit 611. Math unit 613 may include a variation of math logic found in the shared functional logic of a graphics processing engine provided by other embodiments (e.g., math logic 422 of shared functional logic 420 of FIG. 4). In one embodiment, math unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0100]

[0151] The thread control unit 601 includes logic to control the execution of threads in the execution units. The thread control unit 601 may include thread arbitration logic to start, stop, and preempt the execution of threads in the execution units 600. The thread state unit 602 may be used to store thread states for threads assigned to execute in the execution units 600. Storing thread states in the execution units 600 allows for rapid preemption of threads if they become blocked or idle. The instruction fetch / prefetch unit 603 may fetch instructions from an instruction cache of a higher level of execution logic (e.g., instruction cache 506 such as in FIG. 5A). The instruction fetch / prefetch unit 603 may also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of currently executing threads. The instruction decode unit 604 may be used to decode instructions to be executed by the compute units. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder to decode complex instructions into micro-operational components.

[0101]

[0152] The execution unit 600 additionally includes a register file 606 that can be used by the hardware threads executing on the execution unit 600. The registers in the register file 606 can be divided across logic used to execute multiple simultaneous threads within the compute units 610 of the execution unit 600. The number of logical threads that may be executed by the graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file 606 can vary depending on the embodiment based on the number of hardware threads supported. In one embodiment, register renaming can be used to dynamically allocate registers to hardware threads.

[0102]

[0153] 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid lined boxes indicate components that are typically included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated are macro-instructions, in that they are instructions that are supplied to the execution units as the instructions are processed, as opposed to micro-operations that result from instruction decode.

[0103]

[0154] In some embodiments, the graphics processor execution units natively support instructions in the 128-bit instruction format 710. A 64-bit compact instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are limited in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, the instructions are compacted in part using a set of index values ​​in the index field 713. The execution unit hardware looks up a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 710. Other sizes and formats of instructions are possible.

[0104]

[0155] For each format, the instruction opcode 712 defines the operation that the execution unit performs. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture or picture element. By default, the execution unit executes each instruction across all data channels of an operand. In some embodiments, the instruction control field 714 allows control of certain execution options such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710, the exec-size field 716 limits the number of data channels that are executed in parallel. In some embodiments, the exec-size field 716 is not available for use with the 64-bit compact instruction format 730.

[0105]

[0156] Some execution unit instructions have up to three operands, including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions where one of the destinations is implied. Data processing instructions may have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be a direct (e.g., hard-coded) value passed by the instruction.

[0106]

[0157] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether a direct register addressing mode or an indirect register addressing mode is used. When a direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0107]

[0158] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies an access mode and / or address mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte aligned addresses for all source and destination operands.

[0108]

[0159] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. If the direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. If the indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address immediate field in the instruction and the address register value.

[0109]

[0160] In some embodiments, instructions are grouped based on opcode 712 bit fields to simplify opcode decode 740. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, the move and logical opcode group 742 includes data movement and logical instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logical group 742 shares five most significant bits (MSBs), where move (mov) instructions are of the form 0000xxxxb and logical instructions are of the form 0001xxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxxb (e.g., 0x20). Other instruction group 746 includes a mix of instructions including synchronization instructions (e.g., wait, send) in the format of 0011xxxxb (e.g., 0x30). Parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply) in the format of 0100xxxxb (e.g., 0x40). Parallel math group 748 performs arithmetic operations in parallel across data channels. Vector math group 750 includes arithmetic instructions (e.g., dp4) in the format of 0101xxxxb (e.g., 0x50). Vector math group performs operations such as dot product calculations of vector operands. The illustrated opcode decode 740, in one embodiment, can be used to determine which portion of the execution unit is used to execute the decoded instruction. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0110] Graphics Pipeline

[0161] Figure 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as elements of any other figure in this application may operate or function in a similar manner as described elsewhere in this application, but are not limited to such.

[0111]

[0162] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 800 through a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803, which provides instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0112]

[0163] In some embodiments, command streamer 803 directs the operation of vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides vertex data to vertex shader 807, which performs coordinate space transformation and lighting operations for each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

[0113]

[0164] In some embodiments, the execution units 852A-852B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, the execution units 852A-852B have an attached L1 cache 851 that is unique to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0114]

[0165] In some embodiments, the geometry pipeline 820 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operations. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 813 operates at the direction of the hull shader 811 and includes special purpose logic for generating a set of detailed geometric objects based on a coarse geometric model provided as input to the geometry pipeline 820. In some embodiments, the tessellation components (e.g., the hull shader 811, the tessellator 813, and the domain shader 817) can be bypassed when tessellation is not used. The tessellation components can operate based on data received from the vertex shader 807.

[0115]

[0166] In some embodiments, a complete geometric object can be processed by the geometry shader 819 by one or more threads dispatched to the execution units 852A-852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. The geometry shader 819 receives input from the vertex shader 807 when tessellation is disabled. In some embodiments, the geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0116]

[0167] Prior to rasterization, a clipper 829 processes the vertex data. The clipper 829 may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some implementations, a rasterizer and depth test component 873 in the rendering output pipeline 870 dispatches pixel shaders to convert the geometric objects into a pixel-by-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access unrasterized vertex data via the stream output unit 823.

[0117]

[0168] Graphics processor 800 includes an interconnect bus, interconnect fabric, or other integrated connection mechanism that allows data and messages to be transferred between the major components of the processor. In some embodiments, execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via data port 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, sampler 854, caches 851, 858, and execution units 852A-852B each have a separate memory access path. In one embodiment, texture cache 858 may also be configured as a sampler cache.

[0118]

[0169] In some implementations, the rendering output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a window / mask unit for performing fixed function triangle and line rasterization. An associated rendering cache 878 and depth cache 879 are also available in some embodiments. A pixel processing component 877 performs pixel-based processing on the data, although in some instances pixel processing associated with 2D processing (e.g., bit-block image transfer with blending) is performed by the 2D engine 841 or is replaced by the display controller 843 at display time using overlay display planes. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing sharing of data without using main system memory.

[0119]

[0170] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command streamer 803. In some embodiments, the media pipeline 830 includes individual command streamers. In some embodiments, the video front end 834 processes the media commands before sending the commands to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function that generates threads for dispatch by the thread dispatcher 831 to the thread execution logic 850.

[0120]

[0171] In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples to the graphics processor via ring interconnect 802, or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 includes dedicated logic capable of operating independently from the 3D pipeline. In some embodiments, display controller 843 couples to a display device (not shown), which may be a system integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0121]

[0172] In some embodiments, the geometry pipeline 820 and the media pipeline 830 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and computation APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines may also be supported, provided that a mapping from the pipeline of the future API to the pipeline of the graphics processor is possible.

[0122] Graphics Pipeline Programming

[0173] FIG. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. FIG. 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. The solid lined boxes in FIG. 9A indicate components that are typically included in a graphics command, while the dashed lines indicate components that are optional or that are only included in a subset of the graphics commands. The example graphics processor command format 900 of FIG. 9A includes data fields to identify a client 902, a command operation code (opcode) 904, and data for the command 906. A sub-opcode 905 and a command size 908 are also included in some commands.

[0123]

[0174] In some embodiments, the client 902 specifies a client unit of the graphics device that will process the command data. In some embodiments, the graphics processor command parser inspects the client field of each command to condition further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. When a command is received by a client unit, the client unit reads the opcode 904 and, if any, the sub-opcode 905 to determine the operation to perform. The client unit executes the command using the information in the data field 906. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command opcode. In some embodiments, the commands are aligned in multiples of double words. Other command formats may be used.

[0124]

[0175] The flow chart of Figure 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as the embodiment is not limited to these particular commands or this command sequence. Furthermore, commands may be issued as a batch of commands within the command sequence such that the graphics processor processes the sequence of commands at least partially concurrently.

[0125]

[0176] In some embodiments, a graphics processor command sequence 910 begins with a pipeline flush command 912, which causes any active graphics pipelines to complete any commands currently outstanding for that pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. The pipeline flush is executed to cause the active graphics pipelines to complete any outstanding commands. In response to the pipeline flush, the graphics processor's command parser pauses command processing until the active drawing engines complete outstanding operations and the associated read cache is invalidated. Optionally, any data in the rendering cache that is marked as "dirty" can be flushed to memory. In some embodiments, the pipeline flush command 912 can be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0126]

[0177] In some embodiments, the pipeline select command 913 is used when a command sequence explicitly switches between pipelines with the graphics processor. In some embodiments, the pipeline select command 913 is used only once in an execution context prior to issuing a pipeline command unless the context issues commands to both pipelines. In some embodiments, the pipeline flush command 912 is used immediately prior to pipeline switching via the pipeline select command 913.

[0127]

[0178] In some embodiments, pipeline control commands 914 are used to configure the graphics pipeline for operations and to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 set the pipeline state for an active pipeline. In one embodiment, pipeline control commands 914 are used to clear data from one or more cache memories in an active pipeline before processing a batch of commands and for pipeline synchronization.

[0128]

[0179] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for each pipeline to write data to. Some pipeline operations use the allocation, selection, or configuration of one or more return buffers to which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and for cross-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0129]

[0180] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on a pipeline decision 920, the command sequence is aligned to either the 3D pipeline 922 beginning with a 3D pipeline state 930, or the media pipeline 924 beginning with a media pipeline state 940.

[0130]

[0181] Commands for setting the 3D pipeline state 930 include set 3D state commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that should be set before the corresponding 3D primitive command is processed. The values ​​of these commands are determined at least in part based on the particular 3D API being used. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if those elements are not being used.

[0131]

[0182] In some embodiments, the 3D Primitive 932 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D Primitive 932 command are forwarded to a vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D Primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D Primitive 932 command is used to perform vertex operations on the 3D primitives by a vertex shader. To process the vertex shader, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0132]

[0183] In some embodiments, the 3D pipeline 922 is triggered by an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered by a 'go' or 'kick' command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence with the graphics pipeline. The 3D pipeline performs geometric operations on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel backend operations may be included for these operations.

[0133]

[0184] In some embodiments, the graphics processor command sequence 910 follows the path of the media pipeline 924 when performing media operations. In general, the specific use and manner of programming the media pipeline 924 depends on the media or computation being performed. Certain media decode operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may be bypassed and media decoding may be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computation shader programs that are not explicitly related to rendering graphics primitives.

[0134]

[0185] In some embodiments, the media pipeline 924 is configured similarly to the 3D pipeline 922. A set of commands to set the media pipeline state 940 are dispatched or placed in the command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data to configure the media pipeline elements used to process the media objects. This includes data to configure the video decode and video encode logic in the media pipeline, such as the encode or decode format. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.

[0135]

[0186] In some embodiments, the media object command 942 provides a pointer to a media object for processing by the media pipeline. The media object contains a memory buffer that contains the video data to be processed. In some embodiments, all media pipeline state should be "valid" before issuing the media object command 942. Once the pipeline state is set and the media object command 942 is queued, the media pipeline 924 is triggered by an execute command 944 or an equivalent execution event (e.g., a register write). The output from the media pipeline 924 can then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, the GPGPU operations are set up and executed in a similar manner to the media operations.

[0136] Graphics Software Architecture

[0187] 10 illustrates an exemplary graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute within the system memory 1050 of the data processing system.

[0137]

[0188] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language such as Direct3D's High-level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 that are defined by vertex data.

[0138]

[0189] In some embodiments, the operating system 1020 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX®-like operating system, or an open source UNIX®-like operating system using a variant of the Linux® kernel. The operating system 1020 may support a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. If the Direct3D API is used, the operating system 1020 uses a front-end shader compiler 1024 to compile the HLSL shader instructions 1012 into a lower level shader language. The compilation may be a just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, the high level shaders are compiled into low level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate format, such as a version of Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0139]

[0190] In some embodiments, the user mode graphics driver 1026 includes a back end shader compiler 1027 for converting the shader instructions 1012 into a hardware specific representation. If the OpenGL API is used, the shader instructions 1012 in the GLSL high level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 communicates with the kernel mode graphics driver 1029 using operating system kernel mode functions 1028. In some embodiments, the kernel mode graphics driver 1029 communicates with the graphics processor 1032 for dispatching commands and instructions.

[0140] IP Core Implementation

[0191] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions that represent various logic within a processor. In some implementations, the machine-readable medium is also referred to herein as a computer-readable medium, or a non-transitory computer-readable medium. When read by a machine, the instructions can cause the machine to configure logic to perform the techniques described herein. Such representations, known as "IP cores," are reusable logic units for integrated circuits that can be stored in a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model can be provided to various consumers or manufacturing facilities, which load the hardware model into a manufacturing machine that produces the integrated circuit. The integrated circuit can be manufactured such that the circuit performs the operations described in connection with any of the embodiments described herein.

[0141]

[0192] FIG. 11A is a block diagram illustrating an IP core development system 1100 that can be used to fabricate an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 may be used to create modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 1130 can generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and / or timing simulation. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is implemented with the modeled digital signals. In addition to the RTL design 1115, lower level designs at the logic level or transistor level may be generated, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0142]

[0193] The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which may be in a hardware description language (HDL), or some other representation of the physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 1140 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design may be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0143]

[0194] 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 coupled to a substrate 1180. The logic 1172, 1174 may be implemented, at least in part, in hardware of configurable logic or fixed function logic and may include any one or more portions of a processor core, graphics processor, or other accelerator device described herein. Each unit of logic 1172, 1174 may be implemented in a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include, but is not limited to, interconnects such as bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some implementations, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0144]

[0195] In some embodiments, the units of logic 1172, 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a high density interconnect structure that provides paths for electrical signals. The bridge 1182 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing features may be formed in the bridge substrate to provide chip-to-chip connections between the logic 1172, 1174.

[0196] Although two units of logic 1172, 1174 and a bridge 1182 are shown, the embodiments described herein may include more or less logic units on one or more dies. If the logic is included on a single die, bridge 1182 may be omitted, such that one or more dies can be connected by zero or more bridges. Alternatively, multiple dies or logic units can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected to each other in other possible configurations, including three-dimensional configurations.

[0145]

[0197] FIG. 11C illustrates a package assembly 1190 including multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., a base die). Graphics processing units, parallel processors, and / or computational accelerators as described herein can be composed of multiple silicon chiplets that are fabricated separately. In this context, a chiplet is an at least partially packaged integrated circuit that includes individual logic units that can be assembled into a larger package with other chiplets. A diverse set of chiplets with different IP core logic can be assembled into a single device. Furthermore, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein allow interconnection and communication between various forms of IP within a GPU. IP cores can be fabricated using various process technologies and configured during fabrication, which avoids the complexity of concentrating multiple IPs, especially on a large SoC with multiple flavors of IP, in the same fabrication process. Having multiple process technologies available improves time to market and provides a cost-effective way to create multiple product SKUs. In addition, the de-aggregated IP is independently power-gated; components not used in a given workload can be powered off, reducing overall power consumption.

[0146]

[0198] The hardware logic chiplets may include special purpose hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 may be implemented, at least in part, in configurable logic or fixed function logic hardware and may include any one or more portions of the processor cores, graphics processors, parallel processors, or other accelerator devices described herein. The memory chiplets 1175 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0147]

[0199] Each chiplet may be fabricated as an individual semiconductor die and coupled to substrate 1180 via interconnect structures 1173. Interconnect structures 1173 may be configured to route electrical signals between the various chiplets and logic in substrate 1180. Interconnect structures 1173 may include interconnects such as, but are not limited to, bumps or pillars. In some embodiments, interconnect structures 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic, I / O, and memory chiplets.

[0148]

[0200] In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1190 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 for routing electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0149]

[0201] In some embodiments, the logic or I / O chiplets 1174 and the memory chiplets 1175 can be electrically coupled through a bridge 1187 configured to route electrical signals between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 can be a high density interconnect structure that provides a route for the electrical signals. The bridge 1187 can include a bridge substrate that is constructed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide chip-to-chip connections between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 can also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 1187 can be an embedded multi-die interconnect bridge (EMIB) in some embodiments. In some embodiments, the bridge 1187 can simply be a direct connection from one chiplet to another.

[0150]

[0202] The substrate 1180 can include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. A fabric 1185 can be embedded within the substrate 1180 to enable communication between the various logic chiplets and the logic 1191, 1193 within the substrate 1180. In one embodiment, the I / O 1191, fabric 1185, cache, bridges, and other hardware logic 1193 can be integrated into a base die that is stacked on top of the substrate 1180. The fabric 1185 can be a network on chip interconnects or another form of packet switching fabric that switches data packets between components of a package assembly.

[0151]

[0203] In various embodiments, package assembly 1190 can include fewer or more components and chiplets interconnected by fabric 1185 or one or more bridges 1187. Chiplets in package assembly 1190 can be arranged in a 3D or 2.5D format. In general, bridge structures 1187 can be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. Fabric 1185 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, in-substrate cache memory 1192 can function as a global cache for package assembly 1190, part of a distributed global cache, or a dedicated cache for fabric 1185.

[0152]

[0204] FIG. 11D illustrates a package assembly 1194 including a replaceable chiplet 1195, according to one embodiment. The replaceable chiplet 1195 can be assembled into a standardized slot on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to other bridge interconnects described herein, such as an EMIB. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. The I / O and logic chiplets can communicate via an interconnect fabric. Each of the base chiplets can support one or more slots in a standardized format for one of logic or I / O or memory / cache.

[0153]

[0205] In one embodiment, the SRAM and power distribution circuitry can be fabricated in one or more of the base chiplets 1196, 1198, which can be fabricated using a different process technology relative to the replaceable chiplet 1195 that is stacked on top of the base chiplet. For example, the base chiplets 1196, 1198 can be fabricated using a larger process technology and the replaceable chiplets can be fabricated using a smaller process technology. One or more of the replaceable chiplets 1195 can be memory (e.g., DRAM) chiplets. Various memory densities can be selected for the package assembly 1194 based on the target power and / or performance for the product that uses the package assembly 1194. Furthermore, logic chiplets with a variety of functional units can be selected at assembly time based on the target power and / or performance for the product. Furthermore, chiplets containing different types of IP logic cores can be inserted into the replaceable chiplet slots, allowing for hybrid processor designs where different technology IP blocks can be mixed and matched.

[0154] System example for chip integrated circuit

[0206] 12-13B illustrate example integrated circuits and associated graphics processors that may be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0155]

[0207] 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that can be manufactured using one or more IP cores according to one embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., a CPU) and at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller 1236. 2 S / I 2 The integrated circuit may further include peripheral or bus logic including a C controller 1240. Additionally, the integrated circuit may include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI®) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including a flash memory and a flash memory controller. Memory interfacing may be provided through a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits further include an embedded security engine 1270.

[0156]

[0208] 13A-13B are block diagrams illustrating an example graphics processor for use in an SoC, according to an embodiment described herein. FIG. 13A illustrates an example graphics processor 1310 of a system on a chip integrated circuit that can be manufactured using one or more IP cores, according to an embodiment. FIG. 13B illustrates an additional example graphics processor 1340 of a system on a chip integrated circuit that can be manufactured using one or more IP cores, according to an embodiment. The graphics processor 1310 of FIG. 13A is an example of a low power graphics processor core. The graphics processor 1340 of FIG. 13B is an example of a high performance graphics processor core. Each of the graphics processors 1310, 1340 can be a variation of the graphics processor 1210 of FIG. 12.

[0157]

[0209] As shown in FIG. 13A, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors (e.g., 1315A, 1315B, 1315C, 1315D, 1315N-1, and 1315N). The graphics processor 1310 is capable of executing different shader programs with separate logic such that the vertex processor 1305 is optimized to perform operations on vertex shader programs, while one or more fragment processor(s) 1315A-1315N perform fragment (e.g., pixel) shader operations on fragment or pixel shader programs. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processor(s) 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on a display device. In one embodiment, the fragment processors 1315A-1315N are optimized to execute fragment shader programs, as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs, as provided in the Direct3D API.

[0158]

[0210] The graphics processor 1310 further includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual-to-physical address mapping for the graphics processor 1310, including the vertex processor 1305 and / or fragment processors 1315A-1315N, which can reference vertices or image / texture data stored in memory in addition to vertices or image / texture data stored in one or more caches 1325A-1325B. In one embodiment, the one or more MMUs 1320A-1320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 of Figure 12, such that each processor 1205-1220 may participate in a shared or unified virtual memory system. One or more circuit interconnects 1330A-1330B may enable the graphics processor 1310 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection, according to an embodiment.

[0159]

[0211] As shown in FIG. 13B, the graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the graphics processor 1310 of FIG. 13A. The graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N) that provide a unified shader core architecture in which a single core or type or cores can execute all types of programmable shader code, including shader program code implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores presented may vary depending on the embodiment and implementation. Additionally, graphics processor 1340 includes an inter-core task manager 1345 that functions as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A-1355N, and a tile unit 1358 that accelerates tile processing for tile-based rendering, where rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize internal cache usage.

[0160]

[0212] In some embodiments, a processing resource refers to a processing element (e.g., a GPGPU core, a ray tracing core, a tensor core, an execution resource, an execution unit (EU), a stream processor, a streaming multiprocessor (SM), a graphics multiprocessor) associated with a graphics processor or graphics processor structure (e.g., a parallel processing unit, a graphics processing engine, a multi-core group, a compute unit, a compute unit of a graphics core) within a GPU as described herein. For example, a processing resource may be one of a GPGPU core or a tensor / ray tracing core of a graphics multiprocessor; a ray tracing core, a tensor core or a GPGPU core of a graphics multiprocessor; an execution resource of a graphics multiprocessor; one of a GFX core, a tensor core or a ray tracing core of a multi-core group; one of a vector logic unit or a scalar logic unit of a compute unit; an EU array or an execution unit having an EU array; an execution unit of execution logic; and / or an execution unit. A processing resource may also be, for example, a graphics processing engine, a processing cluster, a GPGPU, a graphics processing engine, a graphics processing engine cluster, and / or execution resources within a graphics processing engine. A processing resource may also be a processing resource within a graphics processor, a graphics processor, and / or a graphics processor.

[0161]

[0213] Support for 8-bit floating-point format operands in the computing architecture Parallel computing is a type of computing in which many calculations or processes are performed simultaneously. Parallel computing can come in various forms, including, but not limited to, SIMD or SIMT. SIMD describes a computer with multiple processing elements performing the same operation on multiple data points simultaneously. In one example, Figures 5A-5B above refer to SIMD and its implementation in a typical processor in terms of EUs, FPUs, and ALUs. In a typical SIMD machine, data is packaged into registers, each of which contains an array of channels. An instruction operates on data found in channel n of a register along with data found in the same channel in another register. SIMD machines are advantageous in areas where a single instruction sequence can be applied to large amounts of data simultaneously. For example, in one embodiment, a graphics processor (e.g., GPGPU, GPU, etc.) can be used to perform SIMD vector operations using computational shader programs.

[0162]

[0214] Various embodiments may also be applied to use cases of execution using single instruction multiple threads (SIMT) as an alternative to or in addition to using SIMD. References to SIMD cores or operations may also be applicable to SIMT and SIMD in combination with SIMT. The following description is described with respect to SIMD machines. However, the embodiments herein are not limited solely to application in a SIMD context, but may also be applied to other parallel computing paradigms, such as SIMT. For ease of discussion and explanation, the following description generally focuses on SIMD implementations. However, the embodiments may be similarly applied to SIMT machines without modification to the techniques and methods described. For SIMT machines, instructions may be provided to a systolic array and executed in a SIMT machine following a similar pattern described below. Other types of parallel computing machines may also utilize the embodiments herein.

[0163]

[0215] Various embodiments may implement a GPGPU with matrix acceleration circuitry, which may be utilized for accelerating machine learning (ML) operations.

[0164]

[0216] FIG. 14 is a block diagram of a data processing system 1400 according to an embodiment. Various embodiments discussed herein may be implemented in a system such as the data processing system 1400. The data processing system 1400 is a heterogeneous processing system having a processor 1402, a unified memory 1410, and a GPGPU 1420 including machine learning acceleration logic. The processor 1402 and the GPGPU 1420 may be any processor and GPGPU / parallel processor described herein. The processor 1402 may execute instructions for a compiler 1415 stored in the system memory 1412. The compiler 1415 runs on the processor 1402 to compile source code 1414A into compiled code 1414B. The compiled code 1414B may include instructions that may be executed by the processor 1402 and / or instructions that may be executed by the GPGPU 1420. During compilation, the compiler 1415 may perform operations to insert metadata, including hints regarding the level of data parallelism present in the compiled code 1414B and / or hints regarding data locality associated with threads dispatched based on the compiled code 1414B. The compiler 1415 may include information utilized to perform such operations, or may perform operations with the assistance of a runtime library 1416. The runtime library 1416 may also assist the compiler 1415 in compiling the source code 1414A, and may also include instructions that are linked at runtime with the compiled code 1414B to assist in execution of the compiled instructions on the GPGPU 1420.

[0165]

[0217] Unified memory 1410 represents a unified address space that can be accessed by processor 1402 and GPGPU 1420. The unified memory can include system memory 1412 and GPGPU memory 1418. GPGPU memory 1418 is memory within the address space of GPGPU 1420 and can include some or all of system memory 1412. In one embodiment, GPGPU memory 1418 can also include at least a portion of any memory dedicated for use by GPGPU 1420. In one embodiment, compiled code 1414B stored in system memory 1412 can be mapped into GPGPU memory 1418 for access by GPGPU 1420.

[0166]

[0218] The GPGPU 1420 includes a number of computation blocks 1424A-1424N, which may include one or more of the various computation units or execution elements described herein. In one embodiment, the GPGPU 1420 further includes a matrix accelerator 1423, which may include one or more special function computation units designed to accelerate a subset of matrix operations (e.g., dot products (or inner products)). The GPGPU 1420 may also include a set of resources that may be shared by the computation blocks 1424A-1424N and the matrix accelerator 1423, including, but not limited to, a set of registers 1425, a power and performance module 1426, and a cache 1427. In one embodiment, the registers 1425 include directly and indirectly accessible registers, where the indirectly accessible registers are optimized for use by the matrix accelerator 1423. The power & performance module 1426 can be configured to adjust the clock frequency and power allocation of the computation blocks 1424A-1424N to power gate idle components in the computation blocks 1424A-1424N. In various embodiments, the cache 1427 can include an instruction cache and / or a lower level data cache. The GPGPU 1420 can further include an L3 data cache 1430, which can be used to cache data accessed from the unified memory 1410 by the computation elements in the matrix accelerator 1423 and / or the computation blocks 1424A-1424N. In one embodiment, the L3 data cache 1430 includes a shared local memory 1432 that can be shared by the computation elements in the computation blocks 1424A-1424N and the matrix accelerator 1423.

[0167]

[0219] In one embodiment, the GPGPU 1420 includes instruction handling logic, such as a fetch & decode unit 1421 (also referred to herein as a decoder, as in decoder 1421), and a scheduler controller 1422. The fetch & decode unit 1421 includes a fetch & decode unit that fetches and decodes instructions for execution by one or more of the computation blocks 1424A-1424N or the matrix accelerator 1423. Instructions can be scheduled to appropriate functional units within the computation blocks 1424A-1424N or to the matrix accelerator via the scheduler controller 1422. In one embodiment, the scheduler controller 1422 is an ASIC that can be configured to perform advanced scheduling operations. In one embodiment, the scheduler controller 1422 is a microcontroller or a low energy-per-instruction processing core that can execute scheduler instructions loaded from a firmware module.

[0220] In one embodiment, some functions performed by the computational blocks 1424A-1424N can be scheduled directly or offloaded to the matrix accelerator 1423. In various embodiments, the matrix accelerator 1423 includes processing element logic configured to efficiently perform matrix computation operations such as multiply-and-add operations and dot-product operations used by 3D graphics or computational shader programs. In one embodiment, the matrix accelerator 1423 can be configured to accelerate operations used by machine learning frameworks. In one embodiment, the matrix accelerator 1423 is an application specific integrated circuit explicitly configured to perform a specific set of parallel matrix multiplication and / or addition operations. In one embodiment, the matrix accelerator 1423 is a field programmable gate array (FPGA) that provides fixed function logic that can be updated between workloads. The set of matrix operations that can be performed by the matrix accelerator 1423 can be limited in relation to the operations that can be performed by the computational blocks 1424A-1424N. However, the matrix accelerator 1423 can perform these operations with significantly higher throughput for the computation blocks 1424A-1424N.

[0168]

[0221] In an embodiment, the data processing system 1400 of FIG. 14 may be utilized for applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these fields have enabled ML models to benefit from lower precision arithmetic to train neural networks. Conventional training platforms support IEEE-754 floating point 16 (FP16) and brain floating point 16 (bfloat16 or BF16) data formats in high performance systolic array implementations. However, recent advances have been made to support training of deep neural networks using lower precision data formats, such as 8-bit floating point data formats. One such 8-bit floating point data format is bfloat8 or BF8. BF8 has a binary format of one sign bit, five exponent bits, and two mantissa bits. In some cases, utilizing the BF8 format can provide up to a 2x improvement in neural network training throughput compared to FP16 or BF16 implementations. However, conventional systems do not provide hardware support for performing operations using 8-bit floating-point operands, such as BF8 operands.

[0169]

[0222] The present embodiment addresses the above-mentioned shortcomings by providing support for 8-bit floating-point format operands in a computing architecture. In one embodiment, the 8-bit floating-point format described herein is the BF8 format. The embodiment introduces various techniques for supporting 8-bit floating-point format operands in a computing architecture. One of the embodiment techniques is systolic dot product accumulate on 8-bit floating-point format input operands. Another embodiment technique is converting floating-point data to or from 8-bit floating-point format data. Another embodiment technique is performing efficient stochastic rounding on floating-point format data values. Another embodiment technique is hybrid floating-point systolic operations. A further embodiment technique is performing mixed-mode operations on 8-bit floating-point format operands. The technology of the embodiment of the present invention will be described in further detail below.

[0170] Systolic dot-product-accumulation for 8-bit floating-point input operands

[0223] An embodiment provides a systolic dot-product accumulate on 8-bit floating-point format input operands.

[0171]

[0224] As mentioned above, conventional training platforms support IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. These data formats are also supported in the systolic array dot-product accumulate (DPAS) engine. As mentioned above, deep neural networks can be trained using 8-bit floating-point data formats (BFLOAT8 or BF8, binary format = 1s-5e-2m). BFLOAT8 can provide up to a two-fold improvement in training throughput compared to FP16 and BFLOAT16 implementations. However, there are no existing solutions that support systolic dot-product operations using the BFLOAT8 numeric format.

[0172]

[0225] Embodiments provide an extension to a DPAS (dot product accumulate systolic) engine to support the BF8 data format. An implementation provides an instruction to perform a matrix dot product on three input operands c += a*b, where a and b matrices are of BF data type. Additionally, embodiments provide hardware circuitry to fetch, decode, and execute the instruction. In some implementations, the accumulated representation of the dot product can be returned in either 32-bit (FP32) or 16-bit (FP16, BF16) floating point format. Embodiments provide the technical advantages of increasing systolic operation density and throughput, reducing data movement costs (because BF8 utilizes half the bandwidth and cache / register space compared to 16-bit data formats), and accelerating training by enabling mixed-precision BFLOAT8 training.

[0173]

[0226] An embodiment provides a DPAS instruction to support dot product and accumulate operations on input arguments presented in an 8-bit floating point (e.g., BF8) data format. FIG. 15 is a block diagram illustrating a BFLOAT8 (BF8) binary format 1500 according to an embodiment. The BF8 binary format 1500 is represented by sign 1510, exponent 1520, and mantissa 1530 bits. The sign bit 1510 is 1 bit, the exponent 1520 is 5 bits, and the mantissa 1530 is 2 bits. The 5-bit exponent 1520 uses 15 offset values ​​that can represent normal floating point values ​​between 6.1e-05 and 5.7344e+04. The BF8 binary format 1500 also supports subnormal values ​​that extend the dynamic range downwards to a minimum representable value of 1.5e-05.

[0174]

[0227] 16 is a block diagram illustrating a systolic DP 8-bit FP format operation 1610 performed by an instruction pipeline 1600 according to an embodiment. The instruction pipeline 1600 can be configured to perform a systolic DP 8-bit format operation 1610, such as, but not limited to, a dot product operation. The dot product of two vectors is a scalar value equal to the sum of the products of corresponding components of the vectors. The dot product can be calculated as shown in Equation (1) below.

[0175]

number

[0228] The dot product may be used in convolution operations of neural networks such as convolutional neural networks (CNNs). An instruction pipeline 1600 used to accelerate hardware instructions may include an instruction fetch & decode unit 1421 that may fetch and decode the hardware instructions, and a controller unit 1620 (such as scheduler controller 1422) that may schedule the decoded instructions to one or more execution units in the computation blocks 1424A-1424N (collectively referred to as computation blocks 1424) and / or the matrix accelerator 1423. The instruction pipeline 1600 may also include a selection circuit 1630, such as a collection of multiplexers (muxes), to route input data to the computation blocks 1424 and / or the matrix accelerator 1423 according to the 8-bit FP format encoded in the hardware instruction of the systolic DP 8-bit format operation 1610.

[0176]

[0229] In one embodiment, the hardware instructions can be scheduled to the computation block 1424 and offloaded to the matrix accelerator 1423. One or more hardware instructions and associated data for performing the systolic DP 8-bit FP format computation 1610 can be stored in the memory 1650. The output of the hardware instructions can also be stored in the memory 1650. The memory 1650 can be any memory described herein, including the system memory 1412, the GPGPU memory 1418, or one or more cache memories 1427, 1430, as in FIG. 14. In some embodiments, the memory 1650 can be one or more register files.

[0177]

[0230] In one embodiment, the matrix accelerator 1423 can execute one or more hardware instructions to perform the systolic DP 8-bit format operations 1610 using the systolic array circuitry 1640. The systolic array circuitry 1640 can include a combination of programmable and fixed function hardware that can be configured to perform dot product operations. The functional units within the computation block 1424 can also be configured to perform dot product operations, and the systolic array circuitry 1640 can be configured to perform a limited subset of dot product operations with a significantly higher throughput for the computation block 1424.

[0178]

[0231] In this embodiment, a DPAS instruction is provided to perform a systolic dot product & accumulate operation on 8-bit floating-point format (e.g., BF8) source operands from a register file, accumulate the results in a selected precision (fp32, fp16, bf16), and write the final output back to the register file. This DPAS instruction for performing a systolic DP 8-bit format operation 1610 accepts three input operands to operate c += a*b, where the 'a' and 'b' operands are of an 8-bit FP type such as BF8. Some of the supported combinations of input and output operands are listed below:

[0179]

number

[0232] DPAS is a multiply-accumulate operation in a systolic pipeline with BFLOAT8 inputs (src1 × src2). Each fused multiply-accumulate (FMA) stage in the systolic pipeline represents a 32-bit SIMD channel in the systolic array circuit 1640 and performs a DPAS operation on four input elements (e.g., dp4a operation) from src1 and src2, respectively. dst and src0 accept IEEE 754 float or half-float operands, and src0 contains the accumulated output from the preceding DPAS iteration in the systolic array. Embodiments may utilize any iteration of the block normalization technique, including, but not limited to, dp4a, dp2a (block=2), dp8a (block=8), dp32a (block=32), etc. Each block normalization technique is associated with its own advantages (e.g., improved area efficiency) and disadvantages (e.g., loss of precision). The particular block normalization technique implemented may be based on the particular application being used.

[0180]

[0233] The 'sdepth' parameter represents the systolic depth of the operation, which means that a series of these 'sdepth' operations are performed on successive registers in priority. The output of each stage is maintained with 32-bit precision to be the accumulated input to the next systolic stage. The dst and src0 arguments can accept IEEE-754 float, half-float and bfloat16 data types, and the previously accumulated results are passed to the instruction via the source register (src0). The final accumulated output is converted to the destination data format and written to the destination register (dst). The 'rcount' parameter is the number of iterations of the operation, which means that 'rcount' number of dpas instructions are generated, dst and src0 are the registers to be advanced sequentially, src1 remains the same, and src2 is advanced by 32 elements.

[0181]

[0234] In an embodiment, the accumulator operand 'c' can be FP32, FP16, or BF16. The systolic array circuit 1640 hardware should support subnormal values ​​(i.e., DAZ=0) on the input. In an embodiment, the input subnormal values ​​can be up-converted and grid-normalized before they are fed to the first stage of the systolic array circuit 1640.

[0182]

[0235] In some implementations, partial sums passed through input argument 'c' can be accumulated at the end of the systolic chain to minimize precision loss due to internal normalization and addition operations. This accumulation of the accumulator input argument ('c') at the end of the systolic chain is called "late accumulate". The internal sums at each stage of the systolic array are accumulated and rounded to FP32 values ​​using round-to-nearest. In some embodiments, the accumulation of the accumulator input argument ('c') can occur at the first stage of the systolic chain or at any intermediate stage of the systolic chain.

[0183]

[0236] FIG. 17A is a block diagram illustrating a systolic array circuit 1700 for performing a systolic dot product accumulate for 8-bit floating point format input operands according to an embodiment. In one embodiment, the systolic dot product accumulate for 8-bit floating point format input operands shown in FIG. 17A is an exemplary dp4a operation. In one implementation, the systolic array circuit 1700 is identical to the systolic array circuit 1640 described with respect to FIG. 16. The systolic array circuit 1700 may include a combination of programmable & fixed function hardware that may be configured to perform a dot product operation. Other variations and combinations of the circuits and elements of the systolic array circuit 1700 may be implemented and are not limited to those described herein. FIG. 17A provides an example architecture of the systolic array circuit 1700, and other architectures may be implemented to perform a systolic dot product accumulate for 8-bit floating point format input operand operations as discussed herein.

[0184]

[0237] Each FMA unit in the systolic array circuit 1700 performs a vector dot product operation (e.g., a four-element vector dot product operation (dp4a)) on four pairs of BF8 input values ​​from the src1 and src2 registers. In one embodiment, each FMA unit includes a combination of a multiplier 1710a-1710d and a shifter 1715b-1715d pair, as well as an adder 1720. A third input register, src0, contains the partial accumulated sum from the preceding dot product iteration. Multiple such FMA units concatenated together in a systolic array can perform DPAS operations, as described further below. A systolic array implementation can chain these individual FMA units in any order possible to make an efficient design, and the order of accumulation does not matter.

[0185]

[0238] In the present embodiment, the systolic array circuit 1700 should support subnormal values ​​for BF8 inputs (e.g., DAZ=0). This can be achieved by extending the exponents of the inputs and normalizing the subnormal input values ​​on the grid. Multiplication can be performed, for example, using 4-bit multipliers 1710a-1710d and 1730a-1730d without loss of precision. The outputs of multipliers 1710a-1710d and 1730a-1730d can be normalized using shifters such as 32-bit shifters 1715a-1715e and 1735a-1735e after each multiplier. Although the shifters 1715a-1715e, 1735a-1735e are shown as 32-bit shifters, in the present embodiment, the shifters 1715a-1715e, 1735a-1735e can be of any precision. For example, in cases where a block normalization arithmetic with a large block size of 32 is used, the shifters 1715a-1715e, 1735a-1735e can be as large as 48 bits. Thus, while the 32-bit shifters 1715a-1715e, 1735a-1735e are shown for illustrative purposes, the embodiments are not limited to a particular 32-bit shifter size, and the shifters 1715a-1715e, 1735a-1735e can be of any precision.

[0186]

[0239] The normalized products output from shifters 1715a-1715e, 1735a-1735e are added together in adders, such as 5-way FP32 adders 1720, 1740, and rounded using nearest neighbor rounding to generate the FP32 output. In some embodiments, the 5-way FP32 adder may be an N-way adder tree (N is configurable) based on the block size selected for normalization. In embodiments, any subnormal values ​​in each subsequent FP32 intermediate result (e.g., in adders 1720, 1740) are flushed to zero.

[0187]

[0240] As previously mentioned, the systolic array circuit 1700 may implement post-accumulation. For post-accumulation, src0 is accumulated at the end of the systolic chain in a final adder, such as FP32 adder 1750. Thus, the 'c' value for the first stage (e.g., 'depth 0') of the systolic array circuit 1700 is zero. Post-accumulation prevents loss of numerical precision in the accumulated output and may provide improved performance at workload level accuracy. As previously mentioned, in some embodiments, accumulation of the accumulator input argument ('c') may occur at the first stage of the systolic chain or at any intermediate stage of the systolic chain.

[0188]

[0241] The final output after post-accumulation (e.g., dest(FP32) 1752) is rounded to the destination precision by adder 1750 using round to nearest even (RNE). Implementations of the systolic array circuit 1700 can support multiple output formats, including FP32, FP16, and BF16, to name a few. In some embodiments, subnormal values ​​in the final output of adder 1750 are flushed to zero if the output is FP32 or BF16. In some embodiments, subnormal values ​​are supported in FP16 output.

[0189]

[0242] FIG. 17B is a block diagram illustrating a systolic array circuit 1755 for performing a contraction dot product accumulate on 8-bit floating point format input operands according to an embodiment. In one embodiment, the systolic dot product accumulate on 8-bit floating point format input operands illustrated in FIG. 17B is an exemplary dp2a operation, which is a two-element vector dot product operation. In one implementation, the systolic array circuit 1755 is identical to the systolic array circuit 1640 described with respect to FIG. 16. The systolic array circuit 1755 may include a combination of programmable & fixed function hardware that can be configured to perform a dot product operation. Other variations and combinations of the circuits and elements of the systolic array circuit 1755 may be implemented and are not limited to those shown herein. FIG. 17B provides an example architecture of the systolic array circuit 1755, and other architectures may be implemented to perform a systolic dot product accumulate on 8-bit floating point format input operand operation as discussed herein.

[0190]

[0243] Each FMA unit in the systolic array circuit 1755 performs a vector dot product operation (e.g., a two-element vector dot product operation (dp2a)) on four pairs of BF8 input values ​​from the src1 and src2 registers. In one embodiment, each FMA unit includes a combination of re-bias & normalization circuits 1760a-1760h, multipliers 1770a-1770d, and adders 1780a-b, 1785a-b. A third input register, src0, contains the partial accumulated sum from the preceding dot product iteration. Multiple such FMA units concatenated together in a systolic array can perform DPAS operations, as described further below. A systolic array implementation can chain these individual FMA units in any order possible to make an efficient design, and the order of accumulation does not matter.

[0191]

[0244] In this embodiment, the systolic array circuit 1755 should support subnormal values ​​for BF8 inputs (e.g., DAZ=0). This can be achieved by expanding the input exponents and normalizing the subnormal input values ​​on the grid. The rebiasing & normalization circuits 1760a-1760h can convert both the incoming operands (src1(BF8) and src2(BF8)) to a common binary format (e.g., FP32) that can accommodate both the 8-bit FP format and its subnormal values ​​(e.g., DAZ=0).

[0192]

[0245] The multiplications can be performed, for example, using FP32 multipliers 1770a-1770d without loss of precision. The outputs of multipliers 1710a-1710d can be added together in an addition tree (e.g., an N-way addition tree based on a selected block size), such as the addition tree provided by FP32 adders 1780a, 1780b and FP32 adders 1785a, 1785b, and rounded using round-to-nearest (RNE) to generate the FP32 output. In an embodiment, any subnormal values ​​in each subsequent FP32 intermediate result (e.g., in adders 1780a-b, 1785a-b) are flushed to zero.

[0193]

[0246] As mentioned above, the systolic array circuit 1755 can implement post-accumulation. For post-accumulation, src0 is accumulated at the end of the systolic chain in the final addition tree as provided by the FP32 adders 1790, 1795. Thus, the 'c' value for the first stage (e.g., 'depth 0') of the systolic array circuit 1755 is zero. Post-accumulation prevents loss of numerical precision in the accumulated output and can provide improved performance at workload level accuracy. As mentioned above, in some embodiments, accumulation of the accumulator input argument ('c') can occur at the first stage of the systolic chain or at any intermediate stage of the systolic chain.

[0194]

[0247] The final output after post-accumulation (e.g., dest(FP32) 1792) is rounded to the destination precision by adder 1795 using round-to-nearest even (RNE). The implementation of the systolic array circuitry 1755 can support multiple output formats, including FP32, FP16, and BF16, to name a few. In some embodiments, subnormal values ​​in the final output of adder 1795 are flushed to zero if the output is FP32 or BF16. In some embodiments, subnormal values ​​are supported in FP16 output.

[0195]

[0248] The following is an example of pseudocode for implementing a systolic dot-product-accumulate for an 8-bit floating-point format input operand (eg, a BF8 operand) according to an embodiment.

[0196]

number

[0249] FIG. 18A illustrates a dot product with accumulate instruction 1800 that may be executed by a systolic array circuit according to an embodiment described herein. FIG. 18A illustrates fields of a dot product with accumulate instruction that may be executed by a systolic matrix logic provided by an embodiment operating on 8-bit floating-point format input operands. FIG. 18A illustrates fields of a dot product with accumulate instruction 1800 that, when executed, causes the systolic matrix accelerator to perform a dot product with accumulation on an 8-bit floating-point format input operand (e.g., a BF8 operand). In one embodiment, the instruction 1800 includes an opcode field 1802, a systolic depth 1804 (sdepth), a repeat count 1806 (rcount), and operand fields that specify a destination 1808, a zeroth source 1810 (src0), a first source 1812 (srcl), and a second source 1814 (src2).

[0197]

[0250] The opcode field 1802 may specify an opcode that identifies the instruction 1800 to execution logic. In one embodiment, the opcode field 1802 includes one or more bits that, if enabled, indicate that the instruction is to be executed by a matrix accelerator (e.g., matrix accelerator 1423). In one embodiment, the opcode field 1802 may also include one or more bits that specify that the instruction 1800 is to be executed by special purpose dot product logic, such as dot product logic in the matrix accelerator 1423 (e.g., systolic array circuit 1640).

[0198]

[0251] Systolic depth 1804 (sdepth) can be used to specify the number of systolic layers to use to process the input data. In one embodiment, systolic depth 1804 can be provided as a recent value. Iteration count 1806 (rcount) can be used to specify the number of dpas instructions to be generated with dst and src0 advancing successive registers, src1 remaining the same, and src2 advancing N elements, where N is the destination format.

[0199]

[0252] The destination 1808, zeroth source 1810 (src0), first source 1812 (srcl), and second source 1814 (srcl) can be used to specify the destination where the computation is written and the location where the source data can be retrieved. In one embodiment, the destination 1808 can specify a register where the data is to be written. In one embodiment, the destination 1808 can be a scalar register, while in some embodiments, the destination can be a vector register that stores the output from multiple channels. The zeroth source 1810, first source 1812, and second source 1814 can be registers or immediate values ​​that contain one or more channels of source data, each channel having four elements to be processed by the systolic array circuit.

[0200]

[0253] In some embodiments, there may be additional fields other than those described. For example, in one embodiment, there is a source modifier field that specifies the numeric modification of the source operand. The value of each data element of the source operand can optionally have its absolute value taken and / or its sign inverted before being sent to the execution pipeline. An absolute value modifier can be applied before the negate modifier so that guaranteed negative values ​​can be generated. In one embodiment, there is a saturation field that can be used to suppress destination saturation. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data outside the saturation target range of that data type to the closest represented value in the target range.

[0201]

[0254] FIG. 18B illustrates a program code compilation process 1815 according to one embodiment. In one embodiment, a source code level description 1820 of a software program is compiled in a compiler 1830, which may include multiple levels of compilation, to a level having operations 1840 including or specifying an 8-bit dot product to be executed by processing logic. The operations 1840 may be operations specified in an intermediate language or may be program code that references primitives of a computation framework, such as primitives provided by a machine learning framework. The operations 1840 including or specifying an 8-bit dot product may then be further compiled by an additional compiler 1850, which may be a shader compiler, to machine level object code 1860, which includes an 8-bit dot product instruction to be executed by the accelerator for matrix operations as described herein.

[0202]

[0255] FIG. 19 is a flow chart illustrating an embodiment of a method 1900 for executing an instruction for systolic dot product accumulation on 8-bit floating-point format input operands. The method 1900 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 1900 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-18 may not be repeated or discussed below. In some implementations, a data processing system, such as the data processing system 1400 of FIG. 14, may perform the method 1900.

[0203]

[0256] Method 1900 begins at processing block 1910 where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a decoded matrix instruction that operates on 8-bit floating-point format operands and can cause the GPGPU to perform parallel dot product operations. At processing block 1920, a set of pipeline commands is determined to execute the decoded matrix instruction on a matrix accelerator using one or more 8-bit floating-point format operands (e.g., BF8 operands).

[0204]

[0257] A set of pipeline commands are then scheduled to the systolic dot product pipeline to execute the decoded matrix instruction using one or more 8-bit floating-point format operands at processing block 1930. Finally, at processing block 1940, in response to completion of the set of pipeline commands, the decoded matrix instruction is retired.

[0205]

[0258] FIG. 20 is a flow chart illustrating an embodiment of a method 2000 for systolic dot product accumulation for 8-bit floating-point format input operands. The method 2000 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 2000 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-19 may not be repeated or discussed below. In some implementations, a systolic array, such as the systolic array circuit 1640 of FIG. 16 or the systolic array circuit of FIG. 17, may perform the method 2000.

[0206]

[0259] The method 2000 begins at process block 2010 where source values ​​and operation depth for an instruction are fetched for execution by a matrix operation accelerator of a GPGPU. In one implementation, the source values ​​are 8-bit floating-point format operands (e.g., BF8 operands). At process block 2020, a set of products is generated based on element-wise multiplication of the source input elements using a 4-bit multiplier.

[0207]

[0260] In processing block 2030, the multiplier outputs are normalized using a 32-bit shifter for each multiplier. Then, in processing block 2040, a sum is calculated over the set of normalized multiplier outputs, and the sum is rounded to the nearest even number. Finally, in processing block 2050, in the final depth layer of the matrix operation accelerator, a sum is calculated between the set of normalized multiplication outputs and the initial accumulator value. The sum is then rounded to the destination output precision using rounding to the nearest even number.

[0208] Converting floating-point data to and from 8-bit floating-point format

[0261] The present embodiment is for converting floating point data to and from 8-bit floating point format data.

[0209]

[0262] As discussed earlier, advances in deep learning allow ML models to leverage lower precision arithmetic to train neural networks. Traditional training platforms support IEEE-754 FP16 and BFLOAT16 data formats in high performance systolic array implementations. These implementations use high precision accumulators to prevent precision loss during long chains of dot product operations. Within neural networks, these high precision outputs should be rounded down to a lower precision format during post-processing of the layer before being sent as input to the next layer. For example, traditional hardware implementations for neural networks support rounding from FP32 to FP16 and BF16.

[0210]

[0263] As mentioned above, 8-bit FP format data (e.g., BFLOAT8, 1s-5e-2m) can improve training and inference performance. Hardware implementations of BFLOAT8 FMA can use either FP32 or FP16 accumulators to maintain numerical precision. However, conventional systems do not have hardware support to round FP32 or FP16 FMA output to BFLOAT8 during post-processing. Conventional systems may provide slower software implementations that use sequence arithmetic and bitwise instructions to perform this rounding operation. For example, this function can be emulated in software using a sequence of arithmetic, bitwise, and compare instructions. Such slow software implementations result in a performance penalty for smaller irregular kernels that are often used in deep neural network training.

[0211]

[0264] An embodiment proposes instructions for converting floating-point data to 8-bit floating-point format data. In one implementation, the conversion instructions of the embodiment perform a down-conversion from IEEE-754 FP32 or FP16 to BFLOAT8 with nearest-to-even rounding. In one implementation, the conversion instructions of the embodiment perform an up-conversion from BFLOAT8 to FP32 or FP16 to facilitate mixed-precision arithmetic operations using the BFLOAT8 memory format.

[0212]

[0265] The embodiments provide instructions and hardware solutions for converting floating point data to 8-bit floating point format data. The instructions and hardware techniques of the embodiments herein replace long instruction sequences with a single instruction that can be used by a programmer. This can result in performance improvements for irregular kernel operations in neural networks. The embodiments also enable mixed precision 8-bit floating point format (e.g., BFLOAT8) training, which can accelerate the training throughput of neural networks.

[0213]

[0266] 21 is a block diagram illustrating an 8-bit FP format conversion process 2110 performed by an instruction pipeline 2100 according to an embodiment. The instruction pipeline 2100 can be configured to perform the 8-bit FP format conversion process 2110. The instruction pipeline 2100 can be used to accelerate hardware instructions and can include an instruction fetch & decode unit 1421 that can fetch and decode hardware instructions, and a controller unit 2120 (such as scheduler controller 1422) that can schedule the decoded instructions to one or more execution units and / or matrix accelerators 1423 in the computation blocks 1424A-1424N (collectively referred to as computation blocks 1424). The instruction pipeline 2100 may also include a selection circuit 2130, such as a collection of multiplexers (muxes), to route input data to the computation block 1424 and / or the matrix accelerator 1423 according to the 8-bit FP format encoded in the hardware instruction of the 8-bit FP format conversion process 2110.

[0214]

[0267] In one embodiment, the hardware instructions can be scheduled to the computation block 1424 and / or offloaded to the matrix accelerator 1423 (e.g., for computation using the systolic array circuitry 2140). One or more hardware instructions and associated data for performing the 8-bit FP format conversion process 2110 can be stored in the memory 2150. The output of the hardware instructions can also be stored in the memory 2150. The memory 2150 can be any memory described herein, including the system memory 1412, the GPGPU memory 1418, or one or more cache memories 1427, 1430, as in FIG. 14 .

[0215]

[0268] In one embodiment, the operation block 1424 can execute one or more hardware instructions to perform the 8-bit FP format conversion operation 2110 using the processing unit 2160. The processing unit 2160 can include a combination of programmable & fixed function hardware that can be configured to perform the 8-bit FP format conversion operation. In some implementations, the processing unit 2160 can be a vector processing unit (VPU). In some implementations, the processing unit 2160 can be a floating point unit (FPU). The processing unit 2160 can include a conversion circuit 2162, a round to nearest (RNE) operation circuit 2164, and a special processing circuit 2166.

[0216]

[0269] In an embodiment, the hardware instructions for performing the 8-bit FP format conversion process 2110 provide data conversion between IEEE-754 FP32 or FP16 data and the BFLOAT8 format. The data conversion may include down-conversion from FP32 / FP16 to an 8-bit FP format (e.g., BF8) or up-conversion from an 8-bit FP format (e.g., BF8) to FP32 / FP16. FIG. 15 above illustrates an exemplary BF8 binary format that may be utilized as the 8-bit FP format in an embodiment. The BFLOAT8 binary format is expressed as a sign, exponent, and mantissa bit. The 5-bit exponent uses 15 offset values ​​that can represent normal floating-point values ​​between 6.1e-05 and 5.7344e+04. The format also supports subnormal values ​​that extend the dynamic range downward to the smallest representable value of 1.5e-05.

[0217]

[0270] When converting downwards from FP32 or FP16 to BF8, values ​​are rounded using the round-to-nearest-even (RTNE) process. In both cases, when converting from FP32 or FP16, subnormals are supported. When upconverting from BF8 to either FP16 or FP32, exponent values ​​in 8-bit FP format (BF8) are appropriately scaled and the mantissa is zero-extended.

[0218]

[0271] In an embodiment, the conversion circuitry 2162 may include programmable & fixed function hardware to perform the conversion process described above. The RNE rounding circuitry 2164 may include programmable & fixed function hardware to perform RNE rounding of the converted data. The special processing circuitry 2166 may include programmable & fixed function hardware to handle corner cases encountered when converting and / or rounding data, such as underflow, overflow, denormalization, etc.

[0219]

[0272] In some implementations, an instruction for conversion of 8-bit FP format data as described herein may take the following form:

[0273] mov dst, src0

[0274] When the conversion circuitry 2162 down converts from FP32 / FP16 to BF8, the instruction should preserve subnormal values ​​on output. In some embodiments, the special processing circuitry 2166 may exhibit saturation behavior that results in overflow (i.e., large values ​​do not saturate to BF8_MAX). The RNE rounding circuitry 2164 should round the mantissa using a round-to-nearest even process. Some example implementations of instructions for conversion of 8-bit FP format data when performing down conversion from FP32, FP16 to BF8 are detailed below:

[0275] mov <bf8> , <fp32>

[0276] rice <bf8> , <fp16>

[0277] When the conversion circuit 2162 up-converts from FP32 / FP16 to BF8, the exponent value is rescaled and the value is renormalized. The mantissa bits are zero-extended for the LSB bits. Some example implementations of instructions for conversion of 8-bit FP format data when performing up-conversion from BF8 to FP32 or FP16 are detailed below:

[0278] mov <fp32> , <bf8>

[0279] rice <fp16> , <bf8>

[0280] FIG. 22A illustrates an instruction 2200 that may be executed by a processing unit in accordance with an embodiment described herein. FIG. 22A illustrates fields of a mov instruction that converts 8-bit floating-point format input operands, which may be executed by a processing unit such as a VPU or FPU provided by one embodiment. FIG. 22A illustrates fields of a mov instruction 2200 that, when executed, causes a processing unit to convert the mov instruction to or from an 8-bit floating-point format input operand (e.g., a BF8 operand). The mov instruction copies a data item referenced by its second operand (i.e., the contents of a register, the contents of memory, or a constant value) to a location referenced by its first operand (i.e., a register or memory).

[0220]

[0281] In one embodiment, the instruction 2200 includes an opcode field 2202 and an operand field for specifying a destination 2204 and a source 2206 (src).

[0221]

[0282] The opcode field 2202 may specify an opcode that identifies the instruction 2200 to execution logic. In one embodiment, the opcode field 2202 includes one or more bits that, when enabled, indicate that the instruction should be executed by a processing unit of an operational block (e.g., operational block 1424).

[0222]

[0283] Destination 2204 and source 2206 (src) can be used to specify the destination where the computation is written and the location where the source data can be retrieved. In one embodiment, destination 2204 can specify a register where the data is written. In one embodiment, destination 2204 can be a scalar register, but in some embodiments, the destination can be a vector register that stores the output from multiple channels. Source (src) 2206 can be an immediate value or a register containing one or more channels of source data.

[0223]

[0284] In some embodiments, there may be additional fields other than those shown. For example, in one embodiment, there is a source modifier field that specifies the numeric modification of the source operand. The value of each data element of the source operand may optionally have its absolute value taken and / or its sign inverted before being sent to the execution pipeline. The absolute value modifier may be applied before the negate modifier so that guaranteed negative values ​​can be generated. In one embodiment, there is a saturation field that may be used to suppress saturation of the destination. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range of the data type to the closest represented value in the target range.

[0224]

[0285] FIG. 22B illustrates a program code compilation process 2215 according to one embodiment. In one embodiment, a source code level description 2220 of a software program is compiled in a compiler 2230, which may include multiple levels of compilation, to a level having operations 2240 including or specifying 8-bit FP format conversion instructions to be executed by processing logic. The operations 2240 may be operations specified in an intermediate language or may be program code that references primitives of a computing framework, such as primitives provided by a machine learning framework. The operations 2240 including or specifying 8-bit FP format conversion instructions may then be further compiled by an additional compiler 2250, which may be a shader compiler, to machine level object code 2260, which includes 8-bit FP format conversion instructions to be executed by a processing unit (e.g., VPU, FPU) of a computer block, as described herein.

[0225]

[0286] The following is an example of pseudocode for converting floating-point data to or from 8-bit floating-point format data (e.g., a BF8 operand) according to an embodiment.

[0226]

number

[0287] FIG. 23 is a flow chart illustrating an embodiment of a method 2300 of executing instructions to convert floating-point data to 8-bit floating-point format data. The method 2300 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 2300 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-22 may not be repeated or discussed below. In some implementations, a data processing system, such as the data processing system 1400 of FIG. 14, may perform the method 2300.

[0227]

[0288] Method 2300 begins at processing block 2310 where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a decoded instruction that causes the GPGPU to perform conversion of operands to and from 8-bit floating point format. In processing block 2320, a set of commands is determined to execute the decoded vector instruction on an arithmetic block of the GPGPU.

[0228]

[0289] In processing block 2330, the set of commands is scheduled to a computation block of the GPGPU to execute the decoded instructions and perform the conversion of the operands to and from 8-bit floating point format. Then, in processing block 2340, the decoded instructions are retired upon completion of the set of commands.

[0229]

[0290] FIG. 24 is a flow chart illustrating an embodiment of a method 2400 for converting floating-point data to 8-bit floating-point format data. The method 2400 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 2400 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-23 may not be repeated or discussed below. In some implementations, a processing unit, such as the processing unit 2160 of FIG. 21, may perform the method 2400.

[0230]

[0291] The method 2400 begins at process block 2410 where a source value of an instruction is fetched to be executed by an arithmetic block of the GPGPU. In some implementations, the source value is converted to a different data format, where the source value is at least one 8-bit floating point format operand or is converted to an 8-bit floating point format operand. At decision block 2420, it is determined whether the source value is equal to 0, infinity, or not-a-number (NaN). If so, the method 2400 proceeds to process block 2425 where the source value is returned to the destination as a special use case value (e.g., 0, infinity, etc.).

[0231]

[0292] If, at decision block 2420, the source value is not equal to 0, infinity, or NaN, the method 2400 proceeds to process block 2430, where the source value is converted to the destination signed magnitude format by scaling, normalizing, and converting the source value. Then, at process block 2440, a round-to-nearest-even process is applied to the converted source value.

[0232]

[0293] At decision block 2450, it is determined whether an overflow, underflow, or non-normal condition occurred. If so, the method 2400 proceeds to processing block 2460 where the converted and rounded source value is returned as a special use case value (e.g., 0, infinity, etc.). On the other hand, if an overflow, underflow, or non-normal condition did not occur, the method 2400 proceeds to processing block 2470 where the converted and rounded source value is returned as the destination value.

[0233] Performs efficient probabilistic rounding on floating-point format data values

[0294] Embodiments herein provide for performing efficient probabilistic rounding on floating-point format data values.

[0234]

[0295] As deep learning training moves to 8-bit floating-point formats (e.g., BF8, 1s-5e-2m), numerical errors introduced due to loss of precision can significantly impact ML model convergence. One way to compensate for precision loss is to use 'rounding' when converting the accumulated FMA output in FP32 or FP16 to BF8 before being passed as input to the next layer of the neural network.

[0235]

[0296] However, rounding errors accumulated over long chains of dot-product operations are also a concern for the numerical stability of iterative solutions used in training deep neural networks. This issue is exacerbated at lower precisions due to the larger machine 'ε' (=0.125) in BF8 compared to FP16 (=4.88e-04) and BF16 (=3.90e-03).

[0236]

[0297] When using the BF8 data format across multiple workloads, stochastic rounding can reduce the accumulation of rounding errors and help achieve convergence. Stochastic rounding refers to a non-deterministic rounding process that rounds a real number to the next larger or smaller floating-point number with a probability (1 minus the relative distance to that number). Full-scale hardware support for stochastic rounding would include a floating-point pseudorandom number generator that would be expensive to build and verify.

[0237]

[0298] However, in the context of deep neural network training, deep learning training has fewer constraints on random number generators and can often reuse random numbers without affecting the numerical stability of the solver. Based on the relaxed random number generator constraints, embodiments provide a combination of hardware and instructions to accelerate stochastic rounding using low-precision random bits (e.g., 8 bits for FP16 → BF8, 16 bits for FP32 → FP16) that are generated and managed in software.

[0238]

[0299] Embodiments herein provide one or more instructions to apply a stochastic rounding operation when a higher precision output of an arithmetic operation is converted to a lower precision format (e.g., BF8 (1s-5e-2m), HF8 (1s4e3m), FP16, and BF16 floating-point formats). These instructions may include one or two higher precision source operands and a third input operand that includes an integer random number generated by a software-based pseudorandom number generator (PRNG). In some implementations, the PRNG software may use an inexpensive PSNR algorithm such as xoroshiro128++ or equivalent. The output is stored in a destination data format specified by the instructions.

[0239]

[0300] The instructions and hardware of the embodiments herein provide the technical advantage of replacing extensive instruction sequences with a single instruction that can be used by a programmer for improved speed and efficiency of neural network training performance. The embodiments also allow a programmer to use an algorithm to generate and manage (cache and reuse) random numbers while decoupling the PRNG from rounding operations to reduce hardware complexity. Additionally, the embodiments accelerate backpropagation of BFLOAT8 mixed precision training to improve the speed and efficiency of neural network training.

[0240]

[0301] 25 is a block diagram illustrating an 8-bit FP format conversion using a probabilistic rounding operation 2510 performed by an instruction pipeline 2500, according to an embodiment. The instruction pipeline 2500 can be configured to perform the 8-bit FP format conversion using the probabilistic rounding operation 2510. The instruction pipeline 2500 can be used to accelerate hardware instructions and can include an instruction fetch & decode unit 1421 that can fetch and decode hardware instructions, and a controller unit 2520 (such as scheduler controller 1422) that can schedule the decoded instructions to one or more execution units and / or matrix accelerator 1423 in the computation blocks 1424A-1424N (collectively referred to as computation blocks 1424). The instruction pipeline 2500 may also include a selection circuit 2530, such as a collection of multiplexers (muxes), to route input data to the arithmetic block 1424 and / or the matrix accelerator 1423 according to the 8-bit FP format encoded in the hardware instruction for 8-bit FP format conversion using a stochastic rounding operation 2510.

[0241]

[0302] In one embodiment, the hardware instructions can be scheduled to the computation block 1424 and / or offloaded to the matrix accelerator 1423 (e.g., for computation using the systolic array circuitry 2540). One or more hardware instructions and associated data for performing the 8-bit FP format conversion process 2110 using the stochastic rounding operation 2510 can be stored in the memory 2550. The output of the hardware instructions can also be stored in the memory 2550. The memory 2550 can be any memory described herein, including the system memory 1412, the GPGPU memory 1418, or one or more cache memories 1427, 1430, as in FIG. 14.

[0242]

[0303] In one embodiment, the operation block 1424 can execute one or more hardware instructions to perform 8-bit FP format conversion with stochastic rounding operation 2510 using the processing unit 2560. The processing unit 2560 can include a combination of programmable & fixed function hardware that can be configured to perform 8-bit FP format conversion with stochastic rounding operation. In some implementations, the processing unit 2560 can be a vector processing unit (VPU). In some implementations, the processing unit 2560 can be a floating point unit (FPU). The processing unit 2560 can include a conversion circuit 2562, a stochastic rounding circuit 2564, and a specialized processing circuit 2166.

[0243]

[0304] In an embodiment, an instruction to perform 8-bit FP format conversion using stochastic rounding operations may perform stochastic rounding during conversion from a higher precision floating point to a lower precision floating point. The instruction may take the following form:

[0305] srnd dest, src0, src1

[0306] In this instruction, src0 is the source operand containing the high-precision floating-point input, and src1 contains the random integer to be used by the rounding hardware. The random integer is generated by software using a PRNG algorithm such as xoroshiro128++. The output of the rounding operation is returned in dst in the low-precision floating-point format specified by the instruction opcode.

[0244]

[0307] During the conversion performed by the conversion circuit 2562, a normalized sign-magnitude representation of src0 is generated. The conversion circuit 2562 may include programmable & fixed function hardware to perform the conversion process. The stochastic rounding circuit 2564 then adds the random integer from src1 to the normalized sign-magnitude representation of src0 using a fixed point adder 2565 to generate an intermediate result. The random integer is PRNG 2570 generated by software using a PRNG algorithm. The stochastic rounding circuit 2564 then truncates the intermediate result to the size of the destination mantissa format after performing any exponent adjustment. The stochastic rounding circuit 2564 may include programmable & fixed function hardware to perform the stochastic rounding process. The special processing circuit 2566 may include programmable & fixed function hardware to handle corner cases encountered when converting and / or rounding data, such as underflow, overflow, denormalization, etc.

[0245]

[0308] In some embodiments, the number of random bits used in the rounding operation may depend on the input and output data formats defined in the instruction opcode. Table 1 below provides a list of exemplary supported input and output formats and the number of random bits used to perform the rounding operation.

[0246]

number

[0309] In some embodiments, the width of the random number may vary depending on the source and destination data formats. Assuming the source data format has an N-bit mantissa and the destination data format has a K-bit mantissa, a (NK)-bit random number may be used to perform the rounding in the stochastic rounding circuit 2564.

[0247]

[0310] 26 is a block diagram illustrating fixed-point addition 2600 of sign-magnitude representations of mantissa and random number, according to an embodiment. A source mantissa 2601 (leading 1) and a random number 2605 are shown being added to generate a sum result 2610. The source mantissa includes an N-bit mantissa 2602, where K bits 2604 of the mantissa represent the number of mantissa bits used in the destination format. Prior to addition, the bits of the random number 2605 are aligned to the (NK) least significant bits of the source mantissa 2601. The sum result 2610 illustrates the sum result, which is the remaining addition of the two leading bits (X) and the mantissa bit (x).

[0248]

[0311] FIG. 27A illustrates an instruction 2700 that may be executed by a processing unit in accordance with an embodiment described herein. FIG. 27A illustrates fields of an instruction to convert a floating-point format input operand using probabilistic rounding. The instruction may be executed by a processing unit such as a VPU or FPU provided by an embodiment. FIG. 27A illustrates fields of an instruction 2700 that, when executed, causes a processing unit to execute an instruction to convert a floating-point format input operand using probabilistic rounding. In one embodiment, the instruction 2700 includes an opcode field 2702 and operand fields for specifying a destination 2704, a zeroth source (src0) 2706, and a first source (src1) 2708.

[0249]

[0312] The opcode field 2702 may specify an opcode that identifies the instruction 2700 to execution logic. In one embodiment, the opcode field 2702 includes one or more bits that, when enabled, indicate that the instruction should be executed by a processing unit of an operational block (e.g., operational block 1424).

[0250]

[0313] The destination 2704, zeroth source 2706 (src0), and first source 2708 (src1) can be used to specify the destination where the computation is written and the location where the source data can be retrieved. In one embodiment, the destination 2704 can specify a register where the data is written. In one embodiment, the destination 2704 can be a scalar register, but in some embodiments, the destination can be a vector register that stores the output from multiple channels. The zeroth source (src0) 2706 and the first source (src1) 2708 can be immediate values ​​or registers that contain one or more channels of source data.

[0251]

[0314] In some embodiments, there may be additional fields other than those shown. For example, in one embodiment, there is a source modifier field that specifies the numeric modification of the source operand. The value of each data element of the source operand may optionally have its absolute value taken and / or its sign inverted before being sent to the execution pipeline. The absolute value modifier may be applied before the negate modifier so that guaranteed negative values ​​can be generated. In one embodiment, there is a saturation field that may be used to suppress saturation of the destination. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range of the data type to the closest represented value in the target range.

[0252]

[0315] FIG. 27B illustrates a program code compilation process 2715 according to one embodiment. In one embodiment, a source code level description 2720 of a software program is compiled in a compiler 2730, which may include multiple levels of compilation, to a level having operations 2740 including or specifying FP format conversion instructions using probabilistic rounding executed by a processing logic. The operations 2740 may be operations specified in an intermediate language or may be program code referencing primitives of a computing framework, such as primitives provided by a machine learning framework. The operations 2740 including or specifying FP format conversion using probabilistic rounding instructions may then be further compiled by an additional compiler 2750, which may be a shader compiler, to a machine level object code 2760, which includes FP format conversion with probabilistic rounding instructions executed by a processing unit (e.g., VPU, FPU) of a computer block, as described herein.

[0253]

[0316] Below is a first pseudo-code example for implementing efficient probabilistic rounding on floating-point format data values ​​according to an embodiment.

[0254]

number

[0317] Below is a second simplified pseudo-code example for implementing efficient probabilistic rounding on floating-point data values ​​according to an embodiment.

[0255]

number

[0318] FIG. 28 is a flow chart illustrating an embodiment of a method 2800 for executing instructions to perform efficient probabilistic rounding on floating-point values. The method 2800 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 2800 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-27 may not be repeated or discussed below. In one implementation, a data processing system, such as the data processing system 1400 of FIG. 14, may perform the method 2300.

[0256]

[0319] Method 2800 begins at processing block 2810 where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a decoded instruction that causes the GPGPU to perform 8-bit floating point format conversion with probabilistic rounding. Then, at processing block 2820, a set of commands is determined to execute the decoded vector instruction on an arithmetic block of the GPGPU.

[0257]

[0320] In processing block 2830, the set of commands is scheduled to a computation block of the GPGPU to execute the decoded instructions to perform 8-bit floating point format conversion with probabilistic rounding. Finally, in processing block 2840, the decoded instructions are retired upon completion of the set of commands.

[0258]

[0321] FIG. 29 is a flow chart illustrating an embodiment of a method 2900 for performing efficient stochastic rounding on floating-point values. The method 2900 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 2900 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-28 may not be repeated or discussed below. In some implementations, a processing unit, such as the processing unit 2560 of FIG. 25, may perform the method 2900.

[0259]

[0322] The method 2900 begins at processing block 2910 where a source value is fetched for an instruction to be executed by an arithmetic block of the GPGPU. In one implementation, the source value is converted from a higher precision floating point to a lower precision floating point. At decision block 2920, it is determined whether the source value is equal to 0, infinity, or NaN. If so, the method 2900 proceeds to processing block 2925 where the source value is returned to the destination as a special use case value. If at decision block 2920, the source value is not equal to 0, infinity, or NaN, the method 2900 proceeds to processing block 2930 where the source value is converted to the sign-magnitude format of the destination and the converted source value is normalized.

[0260]

[0323] A random number is then added to the converted and normalized source value in processing block 2940. In one implementation, the random number has a size determined based on the data formats of the source and destination operands and the destination operand. In one implementation, the random number is obtained from PRNG software. In processing block 2950, ​​an exponent adjustment of the resulting sum is performed and the resulting sum is truncated to the size of the destination operand mantissa format to generate the resulting destination value.

[0261]

[0324] At decision block 2960, it is determined whether an overflow, underflow, or non-normal condition occurred. If so, the method 2900 proceeds to processing block 2970 where the special use case value is returned as the resulting destination value. On the other hand, if an overflow, underflow, or non-normal condition did not occur, the method 2900 proceeds to processing block 2980 where the resulting destination value is returned.

[0262] Hybrid floating-point systolic arithmetic

[0325] The embodiments herein provide hybrid floating-point systolic arithmetic.

[0263]

[0326] Advances in deep learning algorithms have enabled models to utilize low-precision arithmetic for training neural networks. The noise-resilient properties of deep neural networks have also enabled experimentation with custom data formats that can be used for various deep learning tasks. One such custom data format that has gained widespread acceptance in the deep learning community and is being adopted by hardware manufacturers is BFLOAT16.

[0264]

[0327] As smaller bit widths (8 bits or less) are used in deep learning, further customization of data formats may be implemented for efficient allocation of bits. For example, it is known that during backpropagation, error gradients, which tend to have a wider distribution, will utilize a data format with a higher dynamic range (i.e., larger exponent), while the forward (or inference) path can benefit from higher numerical precision (i.e., larger mantissa) to reduce numerical errors. This behavior is more evident in smaller models (fewer model parameters) optimized for edge devices. In smaller bit width data formats, this leads to a trade-off between dynamic range and numerical precision.

[0265]

[0328] In addition to trading off bit allocation between exponent and mantissa, floating-point formats also allow customizing the numeric distribution by choosing an appropriate exponent bias or zero point of the numeric distribution. Given the typical Gaussian (near 0) data distribution of most tensors used in deep learning applications, an exponent bias is typically chosen to maximize the number of smaller values ​​that can be represented by the format. This can partially compensate for having a smaller dynamic range by favoring a significant part of the numeric distribution.

[0266]

[0329] Two 8-bit floating-point representations are introduced that can be used to train deep neural networks. One of these formats, BFLOAT8, uses the 's1.e5.m2' binary representation with a symmetric distribution of numbers. The other format, HFLOAT8, is represented in the 's1.e4.m3' format with an asymmetric exponent bias, with a numerical distribution biased towards smaller numbers. Using a combination of BFLOAT8 and HFLOAT8 formats together to address various parts of the training pipeline may result in improved model accuracy. Mixing multiple data formats into a single training flow may result in hybrid floating-point operations between input matrices represented in different binary formats. As the industry moves to 8-bit and sub-8-bit data formats, this kind of hybrid operation will become more common. However, conventional systems with floating-point hardware do not support arithmetic operations between operands that use different binary encodings or that use non-conventional exponent biases.

[0267]

[0330] Embodiments address this technical problem by providing extensions to DPAS hardware to support custom binary encodings for input operands and enable hybrid floating-point arithmetic. Binary format information for input operands, such as exponent size and / or exponent bias, can be built into the hardware or can be optionally expressed as part of the instruction encoding. The hardware extensions of embodiments can utilize that information to rebias and convert input arguments to a common internal format before performing the requested arithmetic operation.

[0268]

[0331] FIG. 30 is a block diagram illustrating two 8-bit floating-point formats using different binary encodings and exponent biases, according to an embodiment. The BFLOAT8 (or Brain-Float8) format 3000 on the left shows the BFLOAT8 binary format using the s1.e5.m2 format, which includes one sign bit 3002, five exponent bits 3004, and two mantissa bits 3006. The HFLOAT8 (or Hybrid-Float8) format 3010 on the right shows the HFLOAT8 binary format using the s1.e4.m3 format, which includes one sign bit 3012, four exponent bits 3014, and three mantissa bits 3016. Furthermore, the HFLOAT8 format 3010 uses a larger exponent bias to shift the number distribution towards smaller numbers. The differences between these two formats are summarized in Table 2 below.

[0269]

number

[0332] The hybrid floating-point hardware of the present embodiments provides a technical advantage that overcomes the above-mentioned deficiencies by allowing applications to select from a list of available floating-point formats that are best suited for various portions of the training pipeline to maximize accuracy. Additionally, embodiments can support multiple data formats with incremental changes to the hardware. This improves processor performance and neural network training throughput.

[0270]

[0333] 31 is a block diagram illustrating a hybrid 8-bit FP format systolic operation performed by an instruction pipeline 3100, according to an embodiment. The instruction pipeline 3100 can be configured to perform a hybrid 8-bit FP format systolic operation 3110, such as, but not limited to, a dot product operation. The dot product of two vectors is a scalar value equal to the sum of the products of corresponding components of the vectors. The dot product can be calculated as shown in Equation (1) below.

[0271]

number

[0334] The dot product may be used in convolution operations of neural networks such as convolutional neural networks (CNNs). The instruction pipeline 3100 used to accelerate hardware instructions may include an instruction fetch & decode unit 1421 that may fetch and decode the hardware instructions, and a controller unit 3120 (such as a scheduler controller 1422) that may schedule the decoded instructions to one or more execution units in the computation blocks 1424A-1424N (collectively referred to as computation blocks 1424) and / or the matrix accelerator 1423. The instruction pipeline 3100 may also include a selection circuit 1630, such as a collection of multiplexers (muxes), to route input data to the computation blocks 1424 and / or the matrix accelerator 1423 according to the hybrid 8-bit FP format encoded in the hardware instructions of the hybrid 8-bit FP format systolic computation 3110.

[0272]

[0335] In one embodiment, the hardware instructions may be scheduled to the computation block 1424 and offloaded to the matrix accelerator 1423. One or more hardware instructions and associated data for performing the hybrid 8-bit FP format systolic computation 3110 may be stored in the memory 3150. Output of the hardware instructions may also be stored in the memory 3150. The memory 1650 may be any memory described herein, including the system memory 1412, the GPGPU memory 1418, or one or more cache memories 1427, 1430, as in FIG. 14 .

[0273]

[0336] In one embodiment, the matrix accelerator 1423 can execute one or more hardware instructions to perform the hybrid 8-bit FP format systolic operations 3110 using the systolic array circuitry 3140. The systolic array circuitry 3140 can include a combination of programmable and fixed function hardware that can be configured to perform dot product operations. The functional units in the operation block 1424 can also be configured to perform dot product operations, but the systolic array circuitry 3140 can be configured to perform a limited subset of dot product operations at a significantly higher throughput for the operation block 1424.

[0274]

[0337] In an embodiment, a DPAS instruction is provided to perform a systolic dot product & accumulate operation on hybrid 8-bit floating-point format data (e.g., BF8 and HF8) source operands from a register file, accumulate the results in a selected precision (fp32, fp16, bf16), and write the final output back to the register file. This DPAS instruction for performing a hybrid 8-bit FP format systolic operation 3110 accepts three input operands to operate c += a*b, where the 'a' and 'b' operands are of a hybrid 8-bit FP type, such as BF8 or HF8. Other combinations and variations of FP format types of the input operands are possible in embodiments and are not limited to BF8 or HF8 formats.

[0275]

[0338] FIG. 32 is a block diagram illustrating a hybrid FMA unit 3200 of a systolic array circuit for performing hybrid floating-point systolic operations, according to an embodiment. In one embodiment, the hybrid FMA unit 3200 may be part of the systolic array circuit 3140 described with respect to FIG. 31. In one embodiment, the hybrid FMA unit 3200 performs operations of DPAS instructions having hybrid FP format operands. The hybrid FMA implementation of the hybrid FMA unit 3200 can accept custom floating-point formats and internally convert them to a common format with higher precision before performing arithmetic operations.

[0276]

[0339] In an embodiment, information about the custom binary format, such as the number of bits allocated for the exponent and the exponent offset that should be used, is stored in an integer bitmap (hereafter "imm").<imm.cbf> ") may be passed along with the instruction as a fourth argument to the FMA instruction. Several examples of hybrid DPAS instructions of embodiments are shown below using various combinations of input (e.g., BF8 and HF8) and output arguments.

[0277] hdpas_01. <sdepth> x <rcount> <f32> <f32> <hf8> <bf8><imm.cbf> hdpas_02. <sdepth> x <rcount> <f16> <f16> <bf8> <hf8><imm.cbf> hdpas_12. <sdepth> x <rcount> <f32> <f32> <hf8> <hf8><imm.cbf> dst src0 src1 src2. imm

[0340] The instruction encoding is<hdpas_xx> where 'xx' indicates which of the input arguments (src1, src2, or both) are allowed to use the custom input format. The implementation of the instruction encoding can vary depending on the encoding scheme used by the target architecture.

[0278]

[0341] 32, the hybrid FMA operations of an embodiment performed by hybrid FMA unit 3200 are performed on src1 and src2 operands represented in HFLOAT8 and BFLOAT8 data formats, respectively. Both of these formats not only use different binary formats with different bit allocations for the exponent and mantissa, but also use different exponent biases (e.g., BFLOAT8 bias=15, HFLOAT8 bias=11).

[0279]

[0342] The hybrid FMA unit 3200 may include multiple re-bias & normalization units 3210a-h, multiple multipliers 3220a-d, multiple shifters 3230a-3230r, and an adder 3240. The details of the internal bit-width may vary within the hybrid FMA unit 3200 depending on the input and output precision requirements.

[0280]

[0343] The first stage of the hybrid FMA unit 3200 includes rebias & normalize units 3210a-3210h that can convert the incoming operands (src1 (HF8) and src2 (BF8)) into a common 's1.e8.m3' binary format that can accommodate both BFLOAT8 and HFLOAT8 formats and their subnormal values ​​(e.g., DAZ=0).

[0281]

[0344] The second stage of the hybrid FMA unit 3200 includes multipliers 3220a-3220d. The multipliers 3220a-3220d use the extended s1.e8.m3 format as input and generate an intermediate 17-bit sign-magnitude representation (s1.e8.m2.6).

[0282]

[0345] The third stage of hybrid FMA unit 3200 includes shifters 3230a-3230e, which can normalize the multipliers 3220a-3220d outputs along with src0 (which contains the preceding accumulated sum) using, for example, a 32-bit shifter.

[0283]

[0346] The final stage of the hybrid FMA unit includes an adder 3240. The adder 3240 includes an adder tree that generates a 27-bit mantissa as part of a result in, for example, s1.e8.m2.27 format. The adder 3240 rounds this result down to s1.e8.23m format using round-to-nearest-even.

[0284]

[0347] FIG 33A illustrates a hybrid dot product with accumulate instruction 3300 that may be performed by a systolic array circuit according to an embodiment described herein. FIG 33A illustrates fields of a hybrid dot product with accumulate instruction 3300 that may be performed by a systolic matrix logic provided by an embodiment operating on hybrid 8-bit floating-point format input operands. FIG 33A illustrates fields of a hybrid dot product with accumulate instruction 3300 that, when executed, causes the systolic matrix accelerator to perform a dot product with accumulate on hybrid 8-bit floating-point format input operands (e.g., BF8 and HF8 operands). In one embodiment, the instruction 3300 includes an opcode field 3302, a systolic depth 3304 (sdepth), a repeat count 3306 (rcount), and operand fields that specify a destination 3308, a zeroth source 3310 (src0), a first source 3312 (srcl), a second source 3314 (src2), and an integer bitmap (imm) field 3316.

[0285]

[0348] The opcode field 3302 may specify an opcode that identifies the instruction 3300 to the execution logic. In one embodiment, the opcode field 3302 includes one or more bits that, if enabled, indicate that the instruction is to be executed by a matrix accelerator (e.g., matrix accelerator 1423). In one embodiment, the opcode field 3302 may also include one or more bits that specify that the instruction 3300 is to be executed by special purpose dot product logic, such as dot product logic in the matrix accelerator 1423 (e.g., systolic array circuitry 3140).

[0286]

[0349] Systolic depth 3304 (sdepth) can be used to specify the number of systolic layers to use to process the input data. In one embodiment, systolic depth 3304 can be provided as a last value. Iteration count 3306 (rcount) can be used to specify the number of dpas instructions to be generated with dst and src0 advancing successive registers, src1 remaining the same, and src2 advancing N elements, where N is the destination format.

[0287]

[0350] The destination 3308, zeroth source 3310 (src0), first source 3312 (srcl), and second source 3314 (srcl) can be used to specify the destination where the computation is written and the location where the source data can be retrieved. In one embodiment, the destination 3308 can specify a register where the data is to be written. In one embodiment, the destination 3308 can be a scalar register, while in some embodiments, the destination can be a vector register that stores the output from multiple channels. The zeroth source 3310, first source 3312, and second source 3314 can be registers or immediate values ​​that contain one or more channels of source data, each channel having four elements to be processed by the systolic array circuit.

[0288]

[0351] The integer bitmap (imm) field 3316 can be used to specify information about the custom binary format of at least one source operand (e.g., src1 3312 and / or src2 3314), such as the number of bits allocated for the exponent and the exponent offset to be used. This information can be passed in the instruction 3300 as an integer bitmap in the imm field 3316.

[0289]

[0352] In some embodiments, there may be additional fields other than those described. For example, in one embodiment, there is a source modifier field that specifies the numeric modification of the source operand. The value of each data element of the source operand may optionally have its absolute value taken and / or its sign inverted before being sent to the execution pipeline. The absolute value modifier may be applied before the negate modifier so that guaranteed negative values ​​can be generated. In one embodiment, there is a saturation field that may be used to suppress saturation of the destination. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data outside the saturation target range of that data type to the closest represented value in the target range.

[0290]

[0353] FIG. 18B illustrates a program code compilation process 3315 according to one embodiment. In one embodiment, a source code level description 3320 of a software program is compiled in a compiler 3330, which may include multiple levels of compilation, to a level having operations 3340 including or specifying a hybrid 8-bit FP dot product to be executed by a processing logic. The operations 3340 may be operations specified in an intermediate language or may be program code that references primitives of a computation framework, such as primitives provided by a machine learning framework. The operations 3340 including or specifying a hybrid 8-bit FP dot product may then be further compiled by an additional compiler 1850, which may be a shader compiler, to a machine level object code 3360, which includes a hybrid 8-bit FP dot product instruction to be executed by an accelerator for matrix operations as described herein.

[0291]

[0354] Below is an example pseudocode for implementing hybrid floating-point systolic operations, according to an embodiment.

[0292]

number

[0355] FIG. 34 is a flow chart illustrating an embodiment of a method 3400 for executing instructions of hybrid floating-point systolic operations. The method 3400 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 3400 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-33 may not be repeated or discussed below. In some implementations, a data processing system, such as the data processing system 1400 of FIG. 14, may perform the method 3400.

[0293]

[0356] Method 3400 begins at processing block 3410 where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction is decoded into a decoded matrix instruction that operates on hybrid 8-bit floating-point format operands and can cause the GPGPU to perform parallel dot product operations. At processing block 3420, a set of pipeline commands is determined for executing the decoded matrix instruction on a matrix accelerator using one or more 8-bit floating-point format operands.

[0294]

[0357] A set of pipeline commands are then scheduled to the systolic dot product pipeline to execute the decoded matrix instruction using one or more hybrid 8-bit floating-point format operands in processing block 3430. Finally, in processing block 3440, in response to completion of the set of pipeline commands, the decoded matrix instruction is retired.

[0295]

[0358] FIG. 35 is a flow chart illustrating an embodiment of a method 3500 for hybrid floating-point systolic operations. The method 3500 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 3500 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-34 may not be repeated or discussed below. In some implementations, a systolic array, such as the systolic array circuit 1640 of FIG. 31, may perform the method 3500.

[0296]

[0359] The method 3500 begins at process block 3510 where source values ​​and computation depths for an instruction are fetched for execution by a matrix operation accelerator of a GPGPU. In one implementation, the source values ​​are hybrid 8-bit floating point format operands. At process block 3520, the source value inputs are rebiased and normalized as part of the conversion to a common binary format.

[0297]

[0360] Next, in processing block 3530, a set of products is generated based on the element-wise multipliers of the source input elements in the common binary format. Then, in processing block 3540, the multiplier outputs and accumulator inputs are normalized using shifters for each multiplier and for the accumulator inputs. In processing block 3550, a sum is calculated for the set of normalized multiplier outputs, and the sum is rounded to the nearest even number. Finally, in processing block 3560, the sum is rounded to the destination output precision using round-to-nearest even.

[0298] Performing mixed-mode arithmetic with 8-bit floating-point operands

[0361] An embodiment provides for performing mixed-mode operations on 8-bit floating-point format operands.

[0299]

[0362] Advances in deep learning algorithms allow models to utilize lower precision arithmetic for training neural networks. Traditional training platforms can support IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. However, 8-bit FP (such as BFLOAT8, 1s-5e-2m) may be utilized to improve training and inference performance.

[0300]

[0363] While most of the core operations of neural networks like convolutional & linear layers may be able to utilize 8-bit FP format data types, there are still parts of deep neural networks that operate under mixed precision regime (e.g. 8-bit FP format and 16-bit or 32-bit FP format). Some examples of parts of deep neural networks that operate under mixed precision regime are BatchNorm and LayerNorm operations, which allow a layer to accept 8-bit FP format inputs (e.g. BFLOAT8) coming from the previous layer while maintaining their internal statistics (such as mean and variance) with higher precision.

[0301]

[0364] The current approach in conventional systems to address this mixed precision problem is to up-convert the input tensors to an appropriate higher precision format before performing the operation, and then down-convert them to a lower precision for the systolic or output tensors afterwards. However, these conversion steps in conventional approaches incur additional overhead to store ultra-precision copies of the input tensors, increasing register bandwidth pressure and dependencies.

[0302]

[0365] The embodiments herein address these technical problems by providing instructions for performing mixed-mode operations on 8-bit FP format (e.g., BFLOAT8 and other IEEE-754 FP formats) input operands. FIG. 15 above illustrates an exemplary BF8 binary format that may be utilized as the 8-bit FP format of the embodiments. The BFLOAT8 binary format is represented as sign, exponent, and mantissa bits. The 5-bit exponent uses an offset value of 15 that can represent normal floating-point values ​​between 6.1e-05 and 5.7344e+04. The format also supports subnormal values, which extends the dynamic range down to the minimum representable value of 1.5e-05.

[0303]

[0366] These instructions for performing mixed-mode operations can accept at least one input operand in 8-bit FP format (e.g., BFLOAT8), while other inputs can be in standard floating-point or half-precision floating-point format, for example. Embodiments provide a set of instructions for frequently occurring operations that can operate on the above-mentioned mixed-mode operands, such as multiply (MUL), ADD, multiply-accumulate (MAC), SEL, and subtract (SUB).

[0304]

[0367] The present embodiments provide technical advantages that overcome the above-mentioned technical problems by reducing the footprint and bandwidth requirements for register files. Additionally, the embodiments improve end-to-end training performance for networks that have a large percentage of BatchNorm and LayerNorm operations, for example. Furthermore, enabling mixed-precision 8-bit FP format training can help accelerate training in neural networks in terms of training throughput.

[0305]

[0368] 36 is a block diagram illustrating a mixed-mode 8-bit FP format operation 3610 performed by an instruction pipeline 3600 according to an embodiment. The instruction pipeline 3600 can be configured to perform the mixed-mode 8-bit FP format operation 3610. The instruction pipeline 3600 can be used to accelerate hardware instructions and can include an instruction fetch & decode unit 1421 that can fetch and decode hardware instructions, and a controller unit 3620 (such as scheduler controller 1422) that can schedule the decoded instructions to one or more execution units and / or matrix accelerator 1423 in the computation blocks 1424A-1424N (collectively referred to as computation blocks 1424). The instruction pipeline 3600 may also include selection circuitry 3630, such as a collection of multiplexers (muxes), to route input data to the operation block 1424 and / or the matrix accelerator 1423 according to the mixed-mode 8-bit FP format encoded in the hardware instruction of the mixed-mode 8-bit FP format operation 3610.

[0306]

[0369] In one embodiment, the hardware instructions may be scheduled to the computation block 1424 and / or offloaded to the matrix accelerator 1423 (e.g., for computation for computation using the systolic array circuitry 3640). One or more hardware instructions and associated data for performing the mixed-mode 8-bit FP format computation 3610 may be stored in memory 3650. Output of the hardware instructions may also be stored in memory 3650. Memory 3650 may be any memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430, as in FIG. 14 .

[0307]

[0370] In one embodiment, the arithmetic block 1424 may execute one or more hardware instructions to perform the mixed-mode 8-bit FP format operations 3610 using the processing unit 3660. The processing unit 3660 may include a combination of programmable & fixed function hardware that may be configured to perform the mixed-mode 8-bit FP format operations. In some implementations, the processing unit 3660 may be a vector processing unit (VPU). In some implementations, the processing unit 3660 may be a floating point unit (FPU). The processing unit 3660 may include a conversion circuit 3662, a round to nearest (RNE) operation circuit 3664, and a special processing circuit 3666.

[0308]

[0371] In some embodiments, a hardware instruction for performing mixed-mode 8-bit FP format operations 3610 results in a mixed-mode operation on 8-bit FP (e.g., BFLOAT8) input operands. The instruction accepts at least one 8-bit FP format (e.g., BFLOAT8) input operand, while other input operands may be in IEEE-754 floating-point or half-precision floating-point data formats.

[0309]

[0372] The conversion circuit 3662 may include programmable & fixed function hardware to perform the conversion process described above. The conversion circuit 3662 may internally up-convert 8-bit FP format (e.g., BF8) operands to a higher precision format to match the format of the other input operands, and the operation is performed with the higher precision. The data conversion of the conversion circuit 3662 renormalizes the 8-bit FP format inputs to match the dynamic range of the target precision and extends the mantissa with zeros in the least significant bits (LSBs). Subnormal values ​​for BFLOAT8 inputs are preserved and normalized to the target precision. The RNE rounding circuit 3664 may include programmable & fixed function hardware to perform RNE rounding operations on the converted data. The special processing circuit 3666 may include programmable & fixed function hardware to handle corner cases encountered when converting and / or rounding data, such as underflow, overflow, and denormalization.

[0310]

[0373] In some implementations, an instruction for conversion of 8-bit FP format data as described herein may take the following form: mac <f32> <f32> <f32> <bf8> mac <f16> <f16> <f16> <bf8> sub <f16> <f16> <bf8> add <f32> <f16> <bf8> I have <f16> <f16> <bf8> dst src0 src1 src2

[0374] Some examples of 8-bit FP format mixed modes are detailed below:

[0375] Instructions with two source operands (mov, add, cmp, sel, mul, etc.): one of the sources is in 8-bit FP format (e.g., BFLOAT8) and the other is a higher precision type. The destination is either in 8-bit FP format or a higher precision type.

[0311]

[0376] Instructions with three source operands (such as mac): one or two of the sources are in 8-bit FP format (e.g., BFLOAT8), the rest are higher precision types. The destination is either in 8-bit FP format or a higher precision type.

[0312]

[0377] 37 illustrates an example schematic diagram of a hardware circuit 3700 for performing a mixed-mode MAC operation using at least one 8-bit FP format operand, according to an embodiment. In one implementation, the hardware circuit 3700 may be implemented within the processing unit 3660 described with respect to FIG.

[0313]

[0378] As shown in the example of FIG. 37, a hardware circuit 3700 for performing a mixed-mode MAC operation accepts input operands of FP16(src1) 3704 and BF8(src2) 3706 and accumulates them with a cumulative sum src0(F16) 3702. The final output (dst(FP16) 3750) is converted to an FP16 output. Conversion circuits 3710a, 3710b, 3710c internally up-convert the src1 3704 and src2 3706 inputs to FP32. The conversion circuits 3710a-c may be the same as the conversion circuit 3662 described with respect to FIG. 36. In an embodiment, the conversion circuits 3710a-c may maintain subnormal values ​​for all inputs (e.g., DAZ=0).

[0314]

[0379] Multiplier 3720 can multiply the FP32 inputs received from conversion circuits 3710b and 3710c to generate an intermediate output. The intermediate output from multiplier 3720 is normalized and accumulated in adder 3730 with src0 input 3702 (converted to FP32 format by conversion circuit 3710a).

[0315]

[0380] Finally, another conversion circuit 3740 (which may be the same as conversion circuit 3662 of FIG. 36) converts the FP32 sum to an FP16 output 3750. In an embodiment, the conversion circuit 3740 preserves subnormal values ​​for all output (dst) data types (e.g., FTZ=0).

[0316]

[0381] Figure 38A illustrates a set of instructions 3800 executable by a processing unit according to embodiments described herein. Figure 38A illustrates fields of instructions 3800 for performing mixed-mode operations using 8-bit FP format operands. The instructions 3800 include, but are not limited to, a mixed-mode mac instruction 3812, a mixed-mode sub instruction 3814, a mixed-mode add instruction 3816, and a mixed-mode mul instruction 3818. Other mixed-mode instructions for operations on 8-bit FP format operands may be implemented by embodiments.

[0317]

[0382] An instruction 3800 is executable by a processing unit, such as a VPU or FPU, provided by an embodiment. Figure 38A illustrates fields of an instruction 3800 that, when executed, causes a processing unit to execute an instruction to perform a mixed-mode operation using 8-bit FP format operands. In one embodiment, the instruction 3800 includes an opcode field 3802 and operand fields that specify a destination 3804, a zeroth source (src0) 3806, a first source (src1) 3808, and / or a second source (src2) 3810.

[0318]

[0383] The opcode field 3802 may specify an opcode that identifies the instruction 3800 to execution logic. In one embodiment, the opcode field 3802 includes one or more bits that, when enabled, indicate that the instruction should be executed by a processing unit of an operational block (e.g., operational block 1424).

[0319]

[0384] The destination 3804, the zeroth source 3806 (src0), the first source 3808 (src1), and the second source 3806 (src2) can be used to specify the destination where the computation is written and the location where the source data can be retrieved. In one embodiment, the destination 3804 can specify a register where the data is written. In one embodiment, the destination 3804 can be a scalar register, but in some embodiments, the destination can be a vector register that stores the output from multiple channels. The zeroth source 3806 (src0), the first source 3808 (src1), and the second source 3806 (src2) can be immediate values ​​or registers that contain one or more channels of source data.

[0320]

[0385] In some embodiments, there may be additional fields other than those shown. For example, in one embodiment, there is a source modifier field that specifies the numeric modification of the source operand. The value of each data element of the source operand may optionally have its absolute value taken and / or its sign inverted before being sent to the execution pipeline. The absolute value modifier may be applied before the negate modifier so that guaranteed negative values ​​can be generated. In one embodiment, there is a saturation field that may be used to suppress saturation of the destination. If saturation is enabled, the output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range of the data type to the closest represented value in the target range.

[0321]

[0386] FIG. 38B illustrates a program code compilation process 3815 according to one embodiment. In one embodiment, a source code level description 3820 of a software program is compiled in a compiler 3830, which may include multiple levels of compilation, to a level having operations 3840 including or specifying 8-bit FP mixed-mode instructions to be executed by processing logic. The operations 3840 may be operations specified in an intermediate language or may be program code that references primitives of a computing framework, such as primitives provided by a machine learning framework. The operations 3840 including or specifying 8-bit FP mixed-mode instructions may then be further compiled by an additional compiler 3850, which may be a shader compiler, to machine level object code 3860, which includes 8-bit FP mixed-mode instructions to be executed by a processing unit (e.g., VPU, FPU) of a computer block, as described herein.

[0322]

[0387] Below is example pseudocode for performing mixed-mode 8-bit FP format operations according to an embodiment.

[0323]

number

[0388] FIG. 39 is a flow chart illustrating an embodiment of a method 3900 for executing an instruction that performs a mixed-mode operation on 8-bit floating-point format operands. The method 3900 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of the method 3900 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-38 may not be repeated or discussed below. In one implementation, a data processing system, such as the data processing system 1400 of FIG. 14, may perform the method 3900.

[0324]

[0389] Method 3900 begins at processing block 3910 where a single instruction is fetched and decoded for execution within the GPGPU. In one implementation, the single instruction may be decoded into a matrix instruction that causes the GPGPU to execute 8-bit floating point format mixed mode operations. At processing block 3920, a set of commands is determined to execute the decoded vector instruction in an operation block of the GPGPU.

[0325]

[0390] The set of commands is then scheduled to the computation block of the GPGPU to execute the decoded instructions to perform 8-bit floating point format mixed-mode operations in processing block 3930. Finally, in processing block 3940, in response to completion of the set of commands, the decoded instructions are retired.

[0326]

[0391] FIG. 40 is a flow chart illustrating an embodiment of a method 4000 for performing mixed-mode operations on 8-bit floating-point format operands. Method 4000 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. The processes of method 4000 are shown in a linear sequence for brevity and clarity in the description; however, it is contemplated that any number of them may be performed in parallel, asynchronously, or in a different order. Furthermore, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-39 may not be repeated or discussed below. In some implementations, a processing unit such as processing unit 3660 of FIG. 36 may perform method 4000.

[0327]

[0392] The method 4000 begins at processing block 4010 where source values ​​for an instruction are fetched for an operation to be performed by an operation block of the GPGPU. In one implementation, the source values ​​are mixed-mode 8-bit floating-point format operands. At processing block 4020, the source value inputs are rebiased and normalized as part of the conversion to a common binary format. Then, at processing block 4030, an operation is performed on the source input elements in the common binary format.

[0328]

[0393] The operation output is then normalized using a shifter in processing block 4040. The normalized output is then converted to the destination format in processing block 4050 to generate a result value. Finally, in processing block 4060, the result value is returned to the destination operand.

[0329]

[0394] The following examples relate to further embodiments: Example 1 is an apparatus for providing support for 8-bit floating-point format operands in a computing architecture. In one embodiment, example 1 provides for accumulating systolic dot products for input operands in 8-bit floating-point format. The apparatus of example 1 includes a processor, the processor including: a decoder for decoding fetched instructions for execution into decoded instructions, the decoded instructions being matrix instructions operating on 8-bit floating-point operands to cause the processor to execute parallel dot product operations; a controller for scheduling the decoded instructions, the controller providing input data to the 8-bit floating-point operands according to an 8-bit floating-point data format specified by the decoded instructions; and a systolic dot product circuit for executing the decoded instructions using systolic layers, each systolic layer including one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders including a systolic dot product circuit for generating dot products of 8-bit floating-point operands.

[0330]

[0395] In example 2, the subject matter of example 1 can optionally include: the shifter normalizes an output of the multiplier. In example 3, the subject matter of any one of examples 1-2 can optionally include: the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier. In example 4, the subject matter of any one of examples 1-3 can optionally include: the adder includes an addition tree that adds products generated by the multipliers normalized by the shifter, and the adder rounds a result of the addition tree by rounding to the nearest even number.

[0331]

[0396] In example 5, the subject matter of any one of examples 1-4 can optionally include: the result is rounded to a destination precision specified by the decoded instruction. In example 6, the subject matter of any one of examples 1-5 can optionally include: the systolic dot product circuit performs a post-accumulation of an accumulator source operand, where the post-accumulation accumulates the accumulator source operand following generation of a dot product of the 8-bit floating-point operand. In example 7, the subject matter of any one of examples 1-6 can optionally include: the systolic dot product circuit performs an accumulation of an accumulator source operand, where the accumulation accumulates the accumulator source operand in a first stage of the systolic dot product circuit or in one of the intermediate stages of the systolic dot product circuit.

[0332]

[0397] In example 8, the subject matter of any one of examples 1-7 can optionally include: the processor includes a graphics processing unit (GPU). In example 8, the subject matter of any one of examples 1-8 can optionally include: the apparatus is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple threads (SIMT) machine.

[0333]

[0398] Example 10 is a method for supporting 8-bit floating-point format operands in an arithmetic architecture, the method including: a processor decoding an instruction fetched for execution into a decoded instruction, the decoded instruction being a matrix instruction that operates on 8-bit floating-point operands and causes the processor to perform a parallel dot product operation; a processor scheduling the decoded instruction, the processor providing input data to the 8-bit floating-point operands according to an 8-bit floating-point data format specified by the decoded instruction; and a systolic dot product circuit of the processor executing the decoded instruction using systolic layers, each systolic layer including one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders generating a dot product of the 8-bit floating-point operands.

[0334]

[0399] In example 11, the subject matter of example 10 can optionally include: the shifter normalizes the output of the multiplier, the adder includes an addition tree that adds products generated by the multiplier normalized by the shifter, and the adder rounds a result of the addition tree by rounding to the nearest even number. In example 12, the subject matter of any one of examples 10-11 can optionally include: the result is rounded to a destination precision specified by the decoded instruction. In example 13, the subject matter of any one of examples 10-12 can optionally include: the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier.

[0335]

[0400] In example 14, the subject matter of any one of examples 10-13 can optionally include: the systolic dot product circuit further includes performing a post-accumulation of an accumulator source operand, where the post-accumulation accumulates the accumulator source operand following generation of the dot product of the 8-bit floating-point operand. In example 15, the subject matter of any one of examples 10-14 can optionally include: the systolic dot product circuit further includes performing an accumulation of an accumulator source operand, where the accumulation accumulates the accumulator source operand in a first stage of the systolic dot product circuit or in one of the intermediate stages of the systolic dot product circuit.

[0336]

[0401] Example 16 is a non-transitory computer-readable medium that assists in supporting 8-bit floating-point format operands in a computing architecture. In example 16, a non-transitory computer-readable medium is capable of storing instructions that, when executed by one or more processors, cause the processors to perform a method including: decoding, by the one or more processors, instructions fetched for execution into decoded instructions, the decoded instructions being matrix instructions operating on 8-bit floating-point operands to cause the one or more processors to perform parallel dot product operations; scheduling, by the one or more processors, the decoded instructions providing input data to the 8-bit floating-point operands according to an 8-bit floating-point data format specified by the decoded instructions; and executing, by a systolic dot product circuit of the one or more processors, the decoded instructions using a systolic layer, each systolic layer including one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders generating dot products of 8-bit floating-point operands.

[0337]

[0402] In example 17, the subject matter of example 16 can optionally include: the shifter normalizes the output of the multiplier, the adder includes an addition tree that adds products produced by the multipliers normalized by the shifter, and the adder rounds a result of the addition tree by rounding to the nearest even number. In example 18, the subject matter of any one of examples 16-17 can optionally include: the result is rounded to a destination precision specified by the decoded instruction.

[0338]

[0403] In example 19, the subject matter of any one of examples 16-18 can optionally include: the instructions cause the one or more processors to: cause the systolic dot product circuit to perform a post-accumulation of an accumulator source operand, the post-accumulation accumulating the accumulator source operand following generation of a dot product of an 8-bit floating-point operand. In example 20, the subject matter of any one of examples 16-19 can optionally include: the instructions cause the one or more processors to: cause the systolic dot product circuit to perform an accumulation of an accumulator source operand, the accumulation accumulating the accumulator source operand in a first stage of the systolic dot product circuit or in one of the intermediate stages of the systolic dot product circuit.

[0339]

[0404] Example 21 is a system for assisting in supporting 8-bit floating-point format operands in a computing architecture, the one or more processors of example 21 communicatively coupled to a memory and including: a decoder for decoding fetched instructions for execution into decoded instructions, the decoded instructions being matrix instructions operating on 8-bit floating-point operands to cause a graphics processing unit to perform parallel dot product operations; a controller for scheduling the decoded instructions, the controller providing input data to the 8-bit floating-point operands according to an 8-bit floating-point data format specified by the decoded instructions; and a systolic dot product circuit for executing the decoded instructions using systolic layers, each systolic layer including one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders including a systolic dot product circuit for generating dot products of the 8-bit floating-point operands.

[0340]

[0405] In example 22, the subject matter of example 21 can optionally include: the shifter normalizes an output of the multiplier. In example 23, the subject matter of any one of examples 21-22 can optionally include: the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier. In example 24, the subject matter of any one of examples 21-23 can optionally include: the adder includes an addition tree that adds products generated by the multipliers normalized by the shifter, and the adder rounds a result of the addition tree by rounding to the nearest even number.

[0341]

[0406] In example 25, the subject matter of any one of examples 21-24 can optionally include: the result is rounded to a destination precision specified by the decoded instruction. In example 26, the subject matter of any one of examples 21-25 can optionally include: the systolic dot product circuit performs a post-accumulation of an accumulator source operand, the post-accumulation accumulating the accumulator source operand following generation of a dot product of the 8-bit floating-point operand. In example 27, the subject matter of any one of examples 21-26 can optionally include: the systolic dot product circuit performs an accumulation of an accumulator source operand, the accumulation accumulating the accumulator source operand in a first stage of the systolic dot product circuit or in one of the intermediate stages of the systolic dot product circuit.

[0342]

[0407] In example 28, the subject matter of any one of examples 21-27 can optionally include: the processor includes a graphics processing unit (GPU). In example 28, the subject matter of any one of examples 21-28 can optionally include: the apparatus is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple threads (SIMT) machine.

[0343]

[0408] Example 30 is an apparatus for assisting in supporting 8-bit floating-point format operands in a computing architecture, the apparatus including: means for decoding fetched instructions for execution into decoded instructions, the decoded instructions being matrix instructions operating on 8-bit floating-point operands causing the processor to perform parallel dot product operations; means for scheduling the decoded instructions, the decoded instructions providing input data to the 8-bit floating-point operands according to an 8-bit floating-point data format specified by the decoded instructions; and means for executing the decoded instructions using systolic layers, each systolic layer including one or more sets of interconnected multipliers, shifters, and adders, each set of multipliers, shifters, and adders generating dot products of 8-bit floating-point operands. In example 31, the subject matter of example 30 optionally includes an apparatus further configured to perform the method of any one of examples 11-15.

[0344]

[0409] Example 32 is at least one machine-readable medium including a plurality of instructions that, in response to being executed on a computing device, cause the computing device to perform the method of any one of Examples 10-15. Example 33 is an apparatus for supporting 8-bit floating-point format operands in a computing architecture, configured to perform the method of any one of Examples 10-15. Example 34 is an apparatus for supporting 8-bit floating-point format operands in a computing architecture, having means for performing the method of any one of Examples 10-15. Details of the examples may be used anywhere in one or more embodiments.

[0345]

[0410] Example 35 is an apparatus for supporting 8-bit floating-point format operands in a computing architecture, and in particular for supporting converting floating-point data to or from 8-bit floating-point format data. The apparatus of example 35 includes a plurality of graphics processing unit (GPU) processors, which: fetch a source value of an instruction executed by a computing block of the processor (the source value is converted to a different data format, and the source value is at least one of an 8-bit floating-point format operand or is converted to the 8-bit floating-point operand); convert the source value to a destination signed magnitude format by applying rescaling, normalizing, and transforming and nearest even rounding to the converted source value; and return the converted and rounded source value as a destination value.

[0346]

[0411] Example 36 is an apparatus for supporting 8-bit floating-point format operands in an arithmetic architecture, and in particular for supporting efficient probabilistic rounding of floating-point format data values. The apparatus of Example 36 includes a processor of a plurality of graphics processing units (GPUs), which: fetches source values ​​for instructions to be executed by an arithmetic block of the processor (the source values ​​are converted from a higher precision floating-point to a lower precision floating-point); converts the source values ​​to a destination signed magnitude format and normalizes the converted source values; adds a random number to the converted and normalized source values ​​(the random number has a size determined based on the data formats of the source and destination operands, and the random number is obtained from a PRNG); performs an exponent adjustment on the resulting sum and truncates the resulting sum to the size of the mantissa format of the destination operand to generate a resulting destination value; and returns the resulting destination value.

[0347]

[0412] Example 37 is an apparatus for supporting 8-bit floating-point format operands in a computing architecture, and in particular for supporting hybrid floating-point systolic operations. The apparatus of example 37 includes a plurality of graphics processing unit (GPU) processors, which: fetch an operation depth and a source value for an instruction executed by a matrix operation accelerator of the processor, the source value including a hybrid 8-bit floating-point format operand; rebias and normalize the source value as part of a conversion to a common binary format; generate a set of products based on element-wise multiplication of the rebiased and normalized source values ​​in the common binary format; normalize multiplier outputs and accumulator inputs using shifters for each multiplier and for the accumulator input; calculate a sum of the set of normalized multiplier outputs and round the sum to the nearest even number; and round the calculated sum to a destination output precision by rounding to the nearest even number.

[0348]

[0413] Example 38 is an apparatus for supporting 8-bit floating-point format operands in a computing architecture, and in particular for supporting mixed-mode operations with 8-bit floating-point format operands. The apparatus of example 38 includes a plurality of graphics processing unit (GPU) processors, which: fetch source values ​​of instructions for operations to be performed by computing blocks of the processors, the source values ​​including mixed-mode 8-bit floating-point format operands; rebias and normalize the source values ​​as part of the conversion to the common binary format; perform the operation on the rebiased and normalized source values ​​in the common binary format; normalize the output using a shifter; convert the normalized output to a destination format to generate a result value; and return the result value to the destination operand.

[0349]

[0414] The foregoing description and drawings should be considered in an illustrative and not a restrictive sense. Those skilled in the art will appreciate that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the features set forth in the appended claims. < / f16> < / f16> < / f16> < / f32> < / f16> < / f16> < / f16> < / f16> < / f16> < / f32> < / f32> < / f32> < / hf8> < / f32> < / f32> < / rcount> < / sdepth> < / bf8> < / f16> < / f16> < / rcount> < / sdepth> < / hf8> < / f32> < / f32> < / rcount> < / sdepth> < / fp16> < / fp32> < / bf8> < / bf8>

Claims

1. 1. An apparatus including an integrated circuit chip, the integrated circuit chip comprising: a plurality of registers storing a plurality of data elements including 8-bit floating point data elements and 32-bit floating point data elements; a decoding circuit for decoding a single matrix instruction having fields indicating an opcode and a location of a first source matrix including a first plurality of 8-bit floating-point data elements encoded in a first 8-bit floating-point format, a second source matrix including a second plurality of 8-bit floating-point data elements encoded in a second 8-bit floating-point format, and a third source matrix including a plurality of 32-bit floating-point data elements, wherein the first 8-bit floating-point format includes a sign bit, a 5-bit exponent value, and a 2-bit mantissa value, and the second 8-bit floating-point format includes a sign bit, a 4-bit exponent value, and a 3-bit mantissa value; and an execution circuit including a matrix accelerator for accelerating a matrix operation, wherein in response to the single matrix instruction, the execution circuit generates a plurality of products based on the first plurality of 8-bit floating point data elements of the first source matrix and the second plurality of 8-bit floating point data elements of the second source matrix, and accumulates each product of the plurality of products with a corresponding 32-bit floating point data element of the third source matrix to generate a corresponding 32-bit floating point result data element of a result matrix; An apparatus comprising:

2. 10. The apparatus of claim 1 further comprising a package assembly, the package assembly comprising: the integrated circuit chip including a graphics processor chiplet; a first base chiplet including a first interconnect fabric and a first global cache coupled to the first interconnect fabric, the graphics processor chiplet being stacked on the first base chiplet, a first interconnect structure coupling the graphics processor chiplet to the first interconnect fabric; a second base chiplet coupled to the first base chiplet by a second interconnect structure, the second base chiplet including a second interconnect fabric and a second global cache coupled to the second interconnect fabric; a processor core chiplet stacked on the second base chiplet, the processor core including a plurality of processor cores, a third interconnect structure coupling the processor core chiplet to the second interconnect fabric; 13. An apparatus comprising:

3. 3. The apparatus of claim 2, wherein the graphics processor chiplet is manufactured using a process technology that is different from the process technology used to manufacture the first and second base chiplets.

4. 4. The device according to claim 2 or 3, further comprising: one or more memory controllers coupling the graphics processor chiplets and the processor core chiplets to a unified memory, the graphics processor chiplets and the processor core chiplets accessing the unified memory sharing a unified virtual address space.

5. 5. Apparatus as claimed in any preceding claim, further comprising a scheduler operable to schedule a set of commands for execution by said execution circuitry in response to said single matrix instruction.

6. 6. Apparatus according to any one of claims 1 to 5, wherein the execution circuitry is for executing the single matrix instruction over a plurality of single instruction multiple data channels.

7. 7. The apparatus of claim 6, for multiplying a group of 8-bit floating point data elements of the first plurality of 8-bit floating point data elements of the first source matrix by a corresponding group of 8-bit floating point data elements of the second plurality of 8-bit floating point data elements of the second source matrix in each single instruction multiple data channel of the plurality of single instruction multiple data channels.

8. 8. Apparatus according to claim 6 or 7, wherein the single command multiple data channel comprises a 32-bit single command multiple data channel.

9. 9. The apparatus of claim 8, wherein in one of the 32-bit single instruction multiple data channels, four groups of the first plurality of 8-bit floating point data elements of the first source matrix are multiplied with four corresponding groups of the second plurality of 8-bit floating point data elements of the second source matrix.

10. 5. The apparatus of claim 4, further comprising a plurality of memory management units that provide virtual-to-physical address mapping.

11. 11. The apparatus of claim 10, wherein the plurality of memory management units includes a first memory management unit associated with the processor core chiplet and a second memory management unit associated with the graphics processor chiplet.

12. 12. The apparatus of claim 11, wherein the first and second memory management units are synchronized according to the unified virtual address space.

13. 13. The apparatus of claim 10, wherein the plurality of memory management units includes an input / output memory management unit for managing a plurality of sets of page tables that map virtual addresses to physical addresses, including virtual addresses of the unified virtual address space shared by the graphics processor chiplets and the processor core chiplets.

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