Constant voltage generation circuit and semiconductor device

Abstract

To improve the output accuracy of a constant voltage generation circuit.SOLUTION: A constant voltage generation circuit 10 includes: a load R1 connected between a first power supply terminal VIN and an application terminal of a node voltage VA; a constant voltage generating device D1 connected between the application terminal of the node voltage VA and a second power supply terminal GND; and a leakage current correction circuit 11 suppressing a leakage current IL (D1) of the constant voltage generating device D1 from flowing into a load R1 by causing a correction current IB to flow into the application terminal of the node voltage VA.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a constant voltage generating circuit and a semiconductor device including the same. [Background technology]

[0002] Conventionally, a constant voltage generating circuit has been proposed that generates a desired constant voltage by utilizing the breakdown voltage of a Zener diode or the like.

[0003] As an example of the related art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-030139 A

[0005] [overview] However, in a conventional constant voltage generating circuit, there is a risk that the output accuracy may be impaired due to, for example, a leakage current in a Zener diode.

[0006] For example, a constant voltage generation circuit according to the present disclosure includes a load connected between a first power supply terminal and a node voltage application terminal, a constant voltage generation element connected between the node voltage application terminal and a second power supply terminal, and a leakage current correction circuit configured to suppress a leakage current of the constant voltage generation element from flowing to the load by flowing a correction current to the node voltage application terminal. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a comparative example of a constant voltage generating circuit. [Diagram 2] FIG. 2 is a diagram showing how node voltages drop under low input and high temperature conditions. [Diagram 3] FIG. 3 is a diagram showing a first embodiment of a constant voltage generating circuit. [Figure 4] FIG. 4 is a diagram showing how a decrease in node voltage is suppressed. [Diagram 5] FIG. 5 is a diagram showing a second embodiment of the constant voltage generating circuit. [Figure 6] FIG. 6 is a diagram showing a third embodiment of the constant voltage generating circuit. [Figure 7] FIG. 7 is a diagram showing a modified example of the constant voltage generating element. [Figure 8] FIG. 8 is a diagram showing a configuration example of a semiconductor device including a constant voltage generating circuit.

[0008] [Detailed Description] <Constant voltage generating circuit (comparison example)> 1 is a diagram showing a comparative example of a constant voltage generating circuit (= a configuration to be compared with various embodiments described later). A constant voltage generating circuit 10 of this comparative example receives an input voltage VIN (e.g., 3 to 45 V) and outputs a constant voltage REG (e.g., 4.6 to 5.5 V). Referring to this diagram, the constant voltage generating circuit 10 includes a resistor R1, a Zener diode D1, and a transistor M0 (e.g., an N-channel type DMOSFET [double diffused oxide semiconductor field effect transistor]).

[0009] A first end of the resistor R1 is connected to the application end of the input voltage VIN. A second end of the resistor R1 is connected to the application end of the node voltage VA. The resistor R1 connected in this manner corresponds to a load connected between the first power supply end (the application end of the input voltage VIN in this figure) and the application end of the node voltage VA. Note that a current source or the like may be used as the load instead of the resistor R1.

[0010] Zener diode D1 (corresponding to the first Zener diode) corresponds to a constant voltage generating element connected between the application terminal of the node voltage VA and the second power supply terminal (the application terminal of the ground voltage GND in this diagram). In accordance with this diagram, the cathode of Zener diode D1 is connected to the application terminal of the node voltage VA. The anode of Zener diode D1 is connected to the application terminal of the ground voltage GND.

[0011] The drain of transistor M0 is connected to the application terminal of the input voltage VIN. The source of transistor M0 is connected to the application terminal of the constant voltage REG. The gate of transistor M0 is connected to the application terminal of the node voltage VA. Transistor M0 connected in this manner functions as a voltage follower that receives the node voltage VA as an input and outputs the constant voltage REG. Therefore, the constant voltage REG is a voltage (=VA-Vth(M0)) that is lower than the node voltage VA by the on-threshold voltage Vth(M0) of transistor M0.

[0012] In this diagram, a high-voltage element (for example, a DMOSFET with a drain-source withstand voltage of 45 V or more) having a withstand voltage higher than the potential difference between the input voltage VIN and the ground voltage GND is used as the transistor M0.

[0013] Furthermore, the transistor M0 may be omitted if a large current capability is not required for the constant voltage generating circuit 10. In that case, the node voltage VA may be output as it is as the constant voltage REG.

[0014] By the way, the Zener diode D1 breaks down when a voltage higher than the breakdown voltage VDLZ(D1) is applied between the anode and cathode. Therefore, when the input voltage VIN is higher than the breakdown voltage VDLZ(D1), the upper limit of the node voltage VA is clamped at the breakdown voltage VDLZ(D1) of the Zener diode D1. At this time, a current IA (=(VIN-VDLZ(D1)) / R1) flows through resistor R1 and Zener diode D1.

[0015] Furthermore, a constant voltage REG (=VA-Vth(M0)) appears at the source of transistor M0, which is lower than the node voltage VA by the on-threshold voltage Vth(M0) of transistor M0. For example, if VA=VDLZ(D1)≈5.5V and Vth(M0)≈0.9V, then REG≈4.6V. In this way, the constant voltage generating circuit 10 easily generates the constant voltage REG by utilizing the characteristics of the Zener diode D1.

[0016] FIG. 2 is a diagram showing how the node voltage VA drops under low input and high temperature conditions. The horizontal axis of this diagram represents the ambient temperature Ta. Meanwhile, the vertical axis of this diagram represents the node voltage VA and the input voltage VIN. Note that in this diagram, the input voltage VIN is assumed to be lower than the breakdown voltage VDLZ(D1) of the Zener diode D1. For example, VIN may be 5V and VDLZ(D1) may be 5.5V.

[0017] When the input voltage VIN is lower than the breakdown voltage VDLZ(D1) of the Zener diode D1, the Zener diode D1 does not break down. Therefore, the current IA does not flow through the resistor R1 and the Zener diode D1. Therefore, the node voltage VA is pulled up to the input voltage VIN through the resistor R1. In other words, VA ≈ VIN.

[0018] However, at high temperatures (e.g., Ta>120°C), a leakage current IL(D1) occurs at the PN junction of the Zener diode D1. This leakage current IL(D1) flows through a path from the application terminal of the input voltage VIN via resistor R1 and Zener diode D1 to the application terminal of the ground voltage GND. Therefore, the node voltage VA becomes lower than the input voltage VIN by the voltage drop at resistor R1 (=IL(D1)×R1). As a result, a similar voltage drop occurs in the constant voltage REG (=VA-Vth(M0)), which may cause an insufficient operating voltage for the downstream circuit.

[0019] By lowering the resistance of resistor R1, the voltage drop of node voltage VA (and thus constant voltage REG) caused by leakage current IL (D1) can be suppressed. However, such a measure has the tradeoff of increasing current consumption.

[0020] In the following, various embodiments are proposed that can improve the output accuracy under low input and high temperature conditions without increasing current consumption.

[0021] <Constant voltage generating circuit (first embodiment)> 3 is a diagram showing a first embodiment of the constant voltage generating circuit 10. The constant voltage generating circuit 10 of this embodiment is based on the comparative example (FIG. 1) and further includes a leakage current correction circuit 11.

[0022] The leakage current correction circuit 11 suppresses the leakage current IL(D1) of the Zener diode D1 from flowing through the resistor R1 by flowing a correction current IB to the application terminal of the node voltage VA. Referring to this figure, the leakage current correction circuit 11 includes a Zener diode D2, a transistor M1 (e.g., an N-channel type DMOSFET), and transistors M2 and M3 (e.g., P-channel type DMOSFETs).

[0023] In this diagram, high-voltage elements (for example, DMOSFETs with a drain-source withstand voltage of 45 V or more) having a withstand voltage higher than the potential difference between the input voltage VIN and the ground voltage GND are used as transistors M1 to M3.

[0024] The Zener diode D2 (corresponding to a second Zener diode) corresponds to a correction current generating element that is connected between the source of the transistor M1 and the application terminal of the ground voltage GND and generates the correction current IB. In accordance with this figure, the cathode of the Zener diode D2 is connected to the source of the transistor M1. The anode of the Zener diode D2 is connected to the application terminal of the ground voltage GND.

[0025] The Zener diode D2 should have the same leakage characteristics as the Zener diode D1. That is, it is desirable that the leakage current IL(D2) of the Zener diode D2 is equal to the leakage current IL(D1) of the Zener diode D1. For example, the Zener diodes D1 and D2 may be formed in the same pattern adjacent to each other on a semiconductor substrate.

[0026] The transistor M1 forms a bias circuit for applying a voltage lower than the breakdown voltage VDLZ(D2) of the Zener diode D2 between the anode and cathode of the Zener diode D2. For example, the source of the transistor M1 is connected to the cathode of the Zener diode D2. The gate of the transistor M1 is connected to the application terminal of the node voltage VA. Therefore, a voltage (=VA-Vth(M1)) lower than the node voltage VA by the on-threshold voltage Vth(M1) of the transistor M1 is applied to the cathode of the Zener diode D2.

[0027] As described above, the upper limit of the node voltage VA is clamped by the breakdown voltage VDLZ(D1) of the Zener diode D1. Therefore, the upper limit of the voltage applied to the cathode of the Zener diode D2 is VDLZ(D1)-Vth(M1).

[0028] Therefore, when VDLZ(D1)≈VDLZ(D2), the voltage applied between the anode and cathode of the Zener diode D2 is lower than the breakdown voltage VDLZ(D2) of the Zener diode D2. Therefore, no matter what input voltage VIN is applied, the Zener diode D2 will not break down. In other words, only the leakage current IL(D2) flows through the Zener diode D2. The leakage current IL(D2) of the Zener diode D2 flows to the drain of the transistor M2 as the correction current IB described above.

[0029] The sources of the transistors M2 and M3 are both connected to an application terminal of the input voltage VIN. The gates of the transistors M2 and M3 are both connected to the drain of the transistor M2. The drain of the transistor M2 is connected to the drain of the transistor M1. The drain of the transistor M3 is connected to an application terminal of the node voltage VA.

[0030] The transistors M2 and M3 connected in this way form a current mirror CM that mirrors the correction current IB (= IL(D2)) flowing through the drain of the transistor M2 and causes it to flow from the drain of the transistor M3 to the application end of the node voltage VA. Note that the mirror ratio of the current mirror CM may be, for example, 1:1.

[0031] However, due to the characteristics of the Zener diode D1, even if the correction current IB is somewhat larger than the leakage current IL(D1), the breakdown voltage VDLZ(D1) can be maintained at a constant value (for example, about 5.5V). Therefore, the mirror ratio of the current mirror CM does not necessarily have to be 1:1.

[0032] For example, the mirror ratio of the current mirror CM can be set to 1:X (where X > 1), and IB > IL(D1) can be intentionally set. According to such a design, even if there is a mismatch in the leakage currents IL(D1) and IL(D2), the leakage current IL(D1) of the Zener diode D1 can be completely covered by the correction current IB. Therefore, a decrease in the node voltage VA (and thus the constant voltage REG) can be reliably suppressed (details will be described later).

[0033] Conversely, even if the mirror ratio of the current mirror CM is 1:Y (where 0 < Y < 1), compared with the previous comparative example (Figure 1), a decrease in the node voltage VA (and thus the constant voltage REG) can be suppressed.

[0034] Note that at low temperatures and normal temperatures (for example, Ta ≤ 25°C), almost no leakage current IL(D2) flows through the Zener diode D2. Therefore, the current mirror CM also does not operate. Thus, the leakage current correction circuit 11 does not affect the operation of the constant voltage generation circuit 10.

[0035] FIG. 4 is a diagram showing how the drop in node voltage VA is suppressed even under low input and high temperature conditions. The horizontal axis of this diagram represents the ambient temperature Ta. Meanwhile, the vertical axis of this diagram represents the node voltage VA and the input voltage VIN. Note that in this diagram, as in the above-mentioned FIG. 2, the input voltage VIN is assumed to be lower than the breakdown voltage VDLZ(D1) of the Zener diode D1. For example, VIN may be 5V and VDLZ(D1) may be 5.5V.

[0036] As mentioned above, when the input voltage VIN is lower than the breakdown voltage VDLZ(D1) of the Zener diode D1, the Zener diode D1 does not break down. Therefore, the current IA does not flow through the resistor R1 and the Zener diode D1. Therefore, the node voltage VA is pulled up to the input voltage VIN through the resistor R1. In other words, VA ≈ VIN.

[0037] However, at high temperatures (e.g., Ta > 120°C), a leakage current IL(D1) occurs at the PN junction of Zener diode D1. When the leakage current IL(D1) flows through resistor R1, a voltage drop (=IL(D1) × R1) occurs at resistor R1, which leads to a drop in node voltage VA (see the dashed line in the diagram).

[0038] On the other hand, in the constant voltage generating circuit 10 of this embodiment, when a leakage current IL(D1) occurs in the Zener diode D1, a leakage current IL(D2) also occurs in the Zener diode D2.

[0039] The leakage current IL(D2) of the Zener diode D2 is fed as the correction current IB from the leakage current correction circuit 11 to the application terminal of the node voltage VA. Therefore, the leakage current IL(D1) of the Zener diode D1 is partially or entirely covered by the correction current IB (=IL(D2)). In other words, even if the leakage current IL(D1) of the Zener diode D1 occurs, it becomes difficult for the current to flow through the resistor R1 (ideally, no current flows).

[0040] As a result, the voltage drop at resistor R1 is small, so the drop in node voltage VA (and thus constant voltage REG) can be suppressed. In other words, even under low input and high temperature conditions, node voltage VA is maintained at approximately the input voltage VIN. This makes it difficult for the subsequent circuit to run out of operating voltage.

[0041] Furthermore, with the constant voltage generating circuit 10 of this embodiment, it is not necessary to unnecessarily reduce the resistance value of the resistor R1. Therefore, it is possible to improve the output accuracy under low input and high temperature conditions without increasing current consumption.

[0042] <Constant voltage generating circuit (second embodiment)> 5 is a diagram showing a second embodiment of the constant voltage generating circuit 10. The constant voltage generating circuit 10 of this embodiment is based on the first embodiment (FIG. 3) described above, but the Zener diode D2 described above is replaced with a transistor M4 (e.g., an NDMOSFET). In addition, due to the above element replacement, the transistor M1 is omitted.

[0043] The drain of the transistor M4 is connected to the drain of the transistor M3. The gate and source of the transistor M4 are both connected to the application terminal of the ground voltage GND. That is, the gate and source of the transistor M4 are shorted, that is, the transistor M4 is always in an off state.

[0044] In the transistor M4 that is always in an off state, a leakage current IL(M4) is generated at the PN junction under high temperatures, similar to the leakage current IL(D1) of the Zener diode D1. Therefore, even in a configuration in which the leakage current IL(M4) of the transistor M4 is used as the correction current IB, the same effects as those of the first embodiment (FIG. 3) can be obtained. In other words, the correction current generating element that generates the correction current IB is not limited to the Zener diode D2, and may be a dummy element that can pass a leakage current equivalent to that of the Zener diode D1.

[0045] As described above, the mirror ratio of the current mirror CM is arbitrary.

[0046] <Constant voltage generating circuit (third embodiment)> Fig. 6 is a diagram showing a third embodiment of a constant voltage generating circuit. The constant voltage generating circuit 10 of this embodiment is based on the second embodiment (Fig. 5) described above, but has a modified internal configuration of the current mirror CM. In accordance with this diagram, the current mirror CM includes transistors M5 and M6 (e.g., P-channel MOSFETs) in addition to the transistors M2 and M3 described above. The following description focuses on the modified points.

[0047] The sources of the transistors M5 and M6 are both connected to an application terminal of the input voltage VIN. The gates of the transistors M5 and M6 are both connected to the drain of the transistor M5. The drain of the transistor M5 is connected to the source of the transistor M2. The drain of the transistor M6 is connected to the source of the transistor M3. The gates of the transistors M2 and M3 are both connected to the drain of the transistor M2. The drain of the transistor M2 is connected to the drain of the transistor M1. The drain of the transistor M3 is connected to an application terminal of the node voltage VA.

[0048] Here, transistors M5 and M6 are each a low-voltage element (eg, a MOSFET with a drain-source withstand voltage of 5 to 7 V) with a withstand voltage lower than the potential difference between the input voltage VIN and the ground voltage GND.

[0049] The transistors M2 and M3, which are high-voltage elements, form the clamp stage clp. The transistors M5 and M6, which are low-voltage elements, form the mirror stage mir. The clamp stage clp clamps the voltage applied to the mirror stage mir to a voltage lower than the withstand voltage of the mirror stage mir (=the drain-source withstand voltage of each of the transistors M5 and M6). The mirror stage mir mirrors the correction current IB with higher accuracy than the clamp stage clp.

[0050] With this configuration, the withstand voltage of the current mirror CM is ensured, while the accuracy of the mirror ratio is improved. However, it should be noted that the lower limit voltage of the operation of the leakage current correction circuit 11 is higher by the on-threshold voltages Vth(M5) and Vth(M6) of the transistors M5 and M6. In addition, if the high withstand voltage of the current mirror CM is not required, the clamp stage clp may be omitted.

[0051] <Constant voltage generating element (modified example)> 7 is a diagram showing a modified example of the constant voltage generating element. In the above embodiment, the Zener diode D1 is exemplified as the constant voltage generating element. However, the constant voltage generating element is not limited to this in any way.

[0052] For example, the constant voltage generating element may include a diode-connected transistor (regardless of N-channel type, P-channel type, npn type, or pnp type) as shown in this figure. When a diode-connected transistor is used as the constant voltage generating element, the gate-source voltage Vgs or base-emitter voltage Vbe of the transistor is used to generate a constant voltage. The constant voltage generating element may also include a combination of the above elements.

[0053] <Semiconductor device> 8 is a diagram showing an example of the configuration of a semiconductor device including a constant voltage generating circuit 10. In the semiconductor device 100 of this example, the constant voltage generating circuit 10, a reference voltage source 20, and a linear power supply 30 are integrated.

[0054] The constant voltage generating circuit 10 generates a constant voltage REG from an input voltage VIN and outputs it to a reference voltage source 20. The constant voltage generating circuit 10 functions as a pre-regulator provided in front of a linear power supply 30 (corresponding to a main regulator). A pre-regulator is required to have high output stability even under low input and high temperature conditions. Therefore, the above-mentioned constant voltage generating circuit 10, which can meet this requirement, is extremely suitable as a pre-regulator.

[0055] The reference voltage source 20 generates a predetermined reference voltage REF from a constant voltage REG. In particular, when the input voltage VIN fluctuates over a wide range, it is desirable to generate the reference voltage REF from a constant voltage REG that has stabilized the input voltage IN to a certain degree, rather than directly generating the reference voltage REF from the input voltage VIN. With this configuration, the desired reference voltage VREF is generated stably, regardless of fluctuations in the input voltage VIN.

[0056] The linear power supply 30 generates an output voltage VOUT from an input voltage VIN. Referring to the figure, the linear power supply 30 includes a transistor 31 (e.g., a PMOSFET), a feedback voltage generating circuit 32, and an operational amplifier 33.

[0057] The transistor 31 functions as an output transistor of the linear power supply 30. The source of the transistor 31 is connected to an application terminal of the input voltage VIN. The drain of the transistor 31 is connected to an application terminal of the output voltage VOUT. The gate of the transistor 31 is connected to an output terminal of the operational amplifier 33. The transistor 31 may be external to the semiconductor device 100.

[0058] The feedback voltage generating circuit 32 generates a feedback voltage FB (for example, a divided voltage of the output voltage VOUT) according to the output voltage VOUT. The feedback voltage generating circuit 32 may be externally attached to the semiconductor device 100. In addition, when the output voltage VOUT is within the input dynamic range of the operational amplifier 33, the feedback voltage generating circuit 32 may be omitted.

[0059] The operational amplifier 33 controls the gate of the transistor 31 so that the feedback voltage FB and the reference voltage REF are equal (imaginary short).

[0060] The subsequent circuit that operates by receiving the constant voltage REG from the constant voltage generating circuit 10 is not limited to the above. For example, although not shown, the constant voltage REG may be used as a threshold voltage of a comparator. In other words, the constant voltage generating circuit 10 can be used for a wide range of applications.

[0061] <Additional Notes> The above disclosure will be summarized below.

[0062] For example, a constant voltage generation circuit according to the present disclosure is configured (first configuration) to include a load connected between a first power supply terminal and a node voltage application terminal, a constant voltage generation element connected between the node voltage application terminal and a second power supply terminal, and a leakage current correction circuit configured to suppress leakage current of the constant voltage generation element from flowing to the load by flowing a correction current to the node voltage application terminal.

[0063] In the constant voltage generating circuit according to the first configuration, the constant voltage generating element may be a Zener diode, a diode-connected transistor, or a configuration including a combination thereof (second configuration).

[0064] In the constant voltage generating circuit according to the second configuration, the leakage current correction circuit may be configured (third configuration) to include a correction current generating element configured to generate the correction current.

[0065] Furthermore, in the constant voltage generating circuit of the third configuration, the constant voltage generating element may include a first Zener diode, the correction current generating element may include a second Zener diode configured to have the same leakage characteristics as the first Zener diode, and the leakage current correction circuit may include a bias circuit configured to apply a voltage lower than a breakdown voltage to the second Zener diode (fourth configuration).

[0066] In the constant voltage generating circuit according to the third configuration, the correction current generating element may include a transistor that is always in an off state (fifth configuration).

[0067] In addition, in the constant voltage generating circuit according to any one of the third to fifth configurations, the leakage current correction circuit may be configured (sixth configuration) to include a current mirror configured to mirror the correction current and flow it to the application terminal of the node voltage.

[0068] Furthermore, in the constant voltage generating circuit of the sixth configuration, the current mirror may include a clamp stage and a mirror stage, the clamp stage being formed of a high-voltage element having a withstand voltage higher than the potential difference between the first power supply terminal and the second power supply terminal, and clamping the voltage applied to the mirror stage to a voltage lower than the withstand voltage of the mirror stage, and the mirror stage being formed of a low-voltage element having a withstand voltage lower than the potential difference between the first power supply terminal and the second power supply terminal, and may be configured to mirror the correction current with higher accuracy than the clamp stage (seventh configuration).

[0069] Moreover, the constant voltage generating circuit according to any one of the first to seventh configurations may be configured (eighth configuration) further including a voltage follower configured to receive the node voltage as an input and output a constant voltage.

[0070] In the constant voltage generating circuit according to any one of the first to eighth configurations, the load may include a resistor (ninth configuration).

[0071] Furthermore, for example, a semiconductor device according to the present disclosure is configured (tenth configuration) to include a constant voltage generating circuit having any one of the first to ninth configurations described above, and a subsequent circuit configured to operate upon receiving the constant voltage.

[0072] According to the present disclosure, the output accuracy of a constant voltage generating circuit can be improved.

[0073] <Other> In addition to the above-described embodiments, the various technical features of the present disclosure can be modified in various ways without departing from the spirit of the technical creation.

[0074] For example, the transistors M0 and M1 to M6 in the above embodiment may be replaced with bipolar transistors, in which case the gate, drain, and source in the above description are replaced with the base, collector, and emitter, respectively.

[0075] Thus, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. The technical scope of the present disclosure is defined by the claims, and it should be understood that all modifications within the meaning and scope of the claims are included. [Explanation of symbols]

[0076] 10 Constant voltage generation circuit (pre-regulator) 11 Leakage current compensation circuit 20 Reference voltage source 30 Linear Power Supply 31 Transistor (PMOSFET) 32 Feedback voltage generation circuit (voltage divider) 33 Operational Amplifiers 100 Semiconductor device clp Clamp stage CM Current Mirror D1 Zener diode (constant voltage generating element) D2 Zener diode (correction current generating element) M0 transistor (NDMOSFET) M1 Transistor (NDMOSFET) M2 Transistor (PDMOSFET) M3 Transistor (PDMOSFET) M4 Transistor (NDMOSFET, correction current generating element) M5 Transistor (PMOSFET) M6 Transistor (PMOSFET) mir Mirror stage R1 Resistor (load)

Claims

1. a load connected between the first power supply terminal and an application terminal of the node voltage; a constant voltage generating element connected between the node voltage application terminal and a second power supply terminal; a leakage current correction circuit configured to suppress a leakage current of the constant voltage generating element from flowing to the load by flowing a correction current to an application terminal of the node voltage; A constant voltage generating circuit comprising:

2. 2. The constant voltage generating circuit according to claim 1, wherein the constant voltage generating element includes a Zener diode, a diode-connected transistor, or a combination thereof.

3. The constant voltage generating circuit according to claim 2 , wherein the leakage current correction circuit includes a correction current generating element configured to generate the correction current.

4. the constant voltage generating element includes a first Zener diode, the correction current generating element includes a second Zener diode configured to have the same leakage characteristics as the first Zener diode; 4. The constant voltage generating circuit according to claim 3, wherein the leakage current correction circuit includes a bias circuit configured to apply a voltage lower than a breakdown voltage to the second Zener diode.

5. 4. The constant voltage generating circuit according to claim 3, wherein the correction current generating element includes a transistor that is normally in an off state.

6. 4. The constant voltage generating circuit according to claim 3, wherein the leakage current correction circuit includes a current mirror configured to mirror the correction current and flow it to an application terminal of the node voltage.

7. the current mirror includes a clamp stage and a mirror stage; the clamp stage is formed of a high-voltage element having a withstand voltage higher than a potential difference between the first power supply terminal and the second power supply terminal, and clamps a voltage applied to the mirror stage to a voltage lower than the withstand voltage of the mirror stage; 7. The constant voltage generating circuit according to claim 6, wherein the mirror stage is formed of a low-voltage element having a withstand voltage lower than a potential difference between the first power supply terminal and the second power supply terminal, and mirrors the correction current with higher accuracy than the clamp stage.

8. The constant voltage generating circuit according to claim 1 , further comprising a voltage follower configured to receive the node voltage as an input and output a constant voltage.

9. The constant voltage generating circuit according to claim 1 , wherein the load includes a resistor.

10. A constant voltage generating circuit according to any one of claims 1 to 9, A subsequent circuit configured to operate upon receiving the constant voltage; A semiconductor device comprising:

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