Image sensor testing system

Abstract

To execute an analysis contributing to reliability improvement, not just ordinary pass / fail test, on an image sensor device without extending a test time.SOLUTION: A testing system 100 inspects an image sensor as a DUT 2. A test module 120 causes a corresponding DUT 2 to generate a test image IMG. An image capture module 130 captures the test image IMG generated by the corresponding DUT 2. An image processing engine 140 processes the test image stored in a corresponding image capture module 130. An edge computer 150 is connected to the image processing engine 140 via a dedicated network, and processes the image data transferred from the image processing engine 140.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to testing of image sensors. [Background technology]

[0002] Image sensor tests are roughly divided into DC parametric tests, function tests, and image processing tests. DC parametric tests include voltage application and current measurement, current application and voltage measurement, and power supply current measurement. Function tests include I / F (interface) tests. DC parametric tests and function tests are similar to those for other DUTs such as memory and SoC (System On Chip).

[0003] Image processing tests are tests specific to image sensors. In image processing tests, the image sensor is illuminated with light and an image is taken using the image sensor. The image generated by the image sensor is then processed. Since this image processing is inefficient when performed by a general computer, an image processing engine designed specifically for image processing is used. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. WO2005 / 121739 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, the capacity of image data has increased remarkably with the advancement of high-definition image sensors, and further increases in resolution are expected in the future. In addition, image sensors are now installed not only in cameras but also in mobile devices and automobiles, and their applications are expanding greatly. Furthermore, one mobile device is now equipped with multiple image sensors. This has resulted in an increase in the number of devices to be inspected. In such a situation, there is a demand for further shortening of test times.

[0006] Furthermore, image sensors for automotive and medical use require higher reliability, so in addition to the usual pass / fail judgment, useful analysis is also required to ensure reliability.

[0007] The present disclosure has been made in this context, and it is an exemplary purpose of an embodiment thereof to provide a test system suitable for measuring a large number of image sensors. [Means for solving the problem]

[0008] An aspect of the present disclosure relates to a test system for inspecting an image sensor as a device under test. The test system includes a plurality of test modules corresponding to a plurality of devices under test, each of which causes a corresponding device under test to generate a test image, a plurality of image capture modules corresponding to a plurality of devices under test, each of which captures a test image generated by a corresponding device under test, a plurality of image processing engines corresponding to a plurality of devices under test, each of which processes the test image stored in a corresponding image capture module, a control unit for controlling the test system, and an edge computer. Each of the image processing engines has a first interface and a second interface, the first interface is connected to the control unit, and the second interface is connected to the edge computer, and is capable of transmitting data to each of the control unit and the edge computer.

[0009] An aspect of the present disclosure also relates to a test system. The test system includes a plurality of test modules corresponding to a plurality of devices under test, each of which causes a corresponding device under test to generate a test image, a plurality of image capture modules corresponding to a plurality of devices under test, each of which captures a test image generated by a corresponding device under test, a plurality of image processing engines corresponding to a plurality of devices under test, each of which processes the test images stored in the corresponding image capture module, a control unit for controlling the test system, and an edge computer. The plurality of image processing engines and the edge computer are connected via a dedicated network, and the edge computer is capable of processing images transferred from the image processing engines.

[0010] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. Effect of the Invention

[0011] According to an aspect of the present disclosure, a system suitable for testing multiple image sensors can be provided. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram of a test system according to an embodiment. [Diagram 2] 1 is a flowchart showing an example of a test flow by a test system. [Diagram 3] 5 is a flowchart showing an example of an image processing test in the test system according to the embodiment. [Figure 4] FIG. 4 is a sequence diagram of an image processing test in the test system according to the embodiment. [Diagram 5] FIG. 1 is a block diagram of a test system according to a comparative technique. [Figure 6] FIG. 1 is a diagram showing a configuration of a test system. [Figure 7] FIG. 2 is a diagram showing a network configuration of a test system. [Figure 8] FIG. 11 is a diagram illustrating a process of an edge computer according to the second embodiment. [Figure 9] FIG. 13 is a diagram showing the distribution of PASS / FAIL of dies in a wafer. [Figure 10] FIG. 13 is a diagram showing a test sequence according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0014] A test system according to one embodiment inspects an image sensor as a device under test. The test system includes a plurality of test modules corresponding to a plurality of devices under test, each of which causes a corresponding device under test to generate a test image, a plurality of image capture modules corresponding to a plurality of devices under test, each of which captures a test image generated by a corresponding device under test, a plurality of image processing engines corresponding to a plurality of devices under test, each of which processes the test image stored in a corresponding image capture module, a control unit for controlling the test system, and an edge computer. Each of the image processing engines has a first interface and a second interface, the first interface is connected to the control unit, and the second interface is connected to the edge computer, and is capable of transmitting data to each of the control unit and the edge computer.

[0015] For comparison, consider a configuration in which data obtained by the image processing engine is transmitted to the edge computer via the control unit. When a configuration in which the image processing engine generates information required by the edge computer is adopted, the image processing engine transmits information required by the control unit and information required by the edge computer to the control unit, resulting in a huge communication load and a bottleneck. When a configuration in which the control unit generates information required by the edge computer is adopted, the amount of data to be transmitted from the image processing engine to the control unit decreases, but the calculation load of the control unit increases. Compared to such a comparison technique, in a test system according to one embodiment, two independent interfaces are provided in the image processing engine, and it is possible to directly transmit information required by the edge computer to the edge computer and directly transmit information required by the processing unit to the processing unit. This solves the communication bottleneck problem, suppresses an increase in the calculation load of the processing unit, and enables a large number of image sensors to be tested at high speed.

[0016] In one embodiment, the control unit and the edge computer may be capable of executing different processes in parallel.

[0017] In one embodiment, the edge computer may be capable of performing statistical analysis based on data obtained for multiple devices under test.

[0018] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0019] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0020] Similarly, "a state in which component C is provided between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0021] 1 is a block diagram of a test system 100 according to an embodiment. The test system 100 inspects a plurality of image sensors as devices under test (DUTs) 2. The number of DUTs is assumed to be n. The test system 100 includes a control unit 110, n test modules 120_1 to 120_n, n image capture modules 130_1 to 130_n, n image processing engines (IPEs) 140_1 to 140_n, and a lighting device 160, and further includes an edge computer 150 embedded therein.

[0022] The lighting device 160 is disposed so as to be able to irradiate light onto the plurality of n test modules 120_1 to 120_n. The on / off, brightness, color, etc., of the lighting device 160 can be controlled by the control unit 110.

[0023] A plurality of n test modules 120_1 to 120_n correspond to n DUTs 2_1 to 2_n. The i-th (i=1, 2, . . . n) test module 120_i captures an image of the corresponding DUT 2_i with or without light being irradiated thereon to generate a test image IMGi.

[0024] A plurality of n image capture modules 130_1 to 130_n correspond to n DUTs 2_1 to 2_n. The i-th image capture module 130_i includes a memory for capturing a test image IMGi generated by the corresponding DUT 2_i.

[0025] The plurality of n image processing engines 140_1 to 140_n correspond to the n DUTs 2_1 to 2_n. A test image IMGi stored in the i-th image capture module 130_i is transferred to the corresponding image processing engine 140_i. The image capture module 130 and the image processing engine 140 are connected via a high-speed image transmission bus.

[0026] The image processing engine 140_i processes the test image IMG_i. For example, the image processing engine 140_i judges the PASS / FAIL of the corresponding DUT2_i based on the test image IMG_i.

[0027] The image processing engine 140 can execute a program independent of the test program executed by the site controller 114. The image processing engine 140 may process the test image IMG to generate other secondary image data, or tertiary or quaternary image data obtained by further processing (hereinafter collectively referred to as secondary image data). The image processing engine 140 may also process the test image IMG or the secondary image data to determine PASS / FAIL of the DUT2. The image processing engine 140 may also process the test image IMG or the secondary image data to generate some value (for example, the number of pixels that satisfy a specific condition, etc.).

[0028] The plurality of image processing engines 140_1 to 140_n are connected to the control unit 110 via a system controller network 170. Data generated by the image processing engines 140 is transferred to the control unit 110 via the system controller network 170.

[0029] The control unit 110 executes a test program, controls the test system 100 in an integrated manner, and executes a test flow in accordance with the test program. The control unit 110 includes, but is not limited to, a system controller 112 and a site controller 114. The system controller 112 controls the site controller 114. The site controller 114 controls the test module 120, image capture module 130, and image processing engine 140 that operate under its control.

[0030] 2 is a flowchart showing an example of a test flow by the test system 100. The test flow includes a DC parametric test S100, a function test S200, and an image processing test S300. The DC parametric test S100 and the function test S200 are conceptually the same as those for general memory devices and SoCs. Specifically, the DC parametric test S100 performs voltage application and current measurement, current application and voltage measurement, power supply current measurement, etc. The function test S200 performs an I / F (interface) test, etc.

[0031] The image processing test S300 is a test specific to the image sensor. In the image processing test, the DUT2 captures an image with or without light being irradiated onto the DUT2. The test image IMG generated by the DUT2 is then processed. Since this image processing is inefficient when performed by a general computer, an image processing engine 140 designed specifically for image processing is used. The image processing engine 140 performs a PASS / FAIL judgment (good or bad judgment) of the DUT2.

[0032] Returning to Fig. 1, in this embodiment, the image processing engine 140 is provided with an independent first interface IF1 and second interface IF2. The first interface IF1 is connected to the control unit 110 via a system controller network 170. Data generated by the image processing engine 140, for example, the result of a PASS / FAIL judgment of the DUT2 and various information associated therewith, are transferred to the control unit 110 via the system controller network 170.

[0033] The second interface IF2 is connected to the edge computer 150 via an IPE-dedicated network 180. The IPE-dedicated network 180 is independent of the system controller network 170, and is capable of transmitting large amounts of data such as image data at high speed. The image processing engine 140 can transfer the test image IMG, a secondary image generated by itself, or other values ​​to the edge computer 150 via the IPE-dedicated network 180.

[0034] The edge computer 150 processes image data received from the image processing engine 140. Since the edge computer 150 is connected to a plurality of image processing engines 140, the edge computer 150 handles a plurality of image data corresponding to a plurality of DUTs 2_1 to 2_n. Therefore, the edge computer 150 has a function (HPC: High Performance Computing) for performing data processing and complex calculations at high speed. The edge computer 150 has a hardware configuration that is optimal for machine learning, artificial intelligence, and the like.

[0035] The edge computer 150 can execute image processing and other arithmetic processing in parallel with the image processing engine 140. The processing executed by the edge computer 150 is not particularly limited, and various processing can be executed as described later. The edge computer 150 is also connected to the system controller network 170. The edge computer 150 transmits data obtained as a result of the processing to the control unit 110 via the system controller network 170.

[0036] 3 is a flowchart showing an example of an image processing test S300 in the test system 100 according to the embodiment. This flowchart does not necessarily limit the order of execution of the processes, and the order of execution of some of the processes can be changed as necessary.

[0037] In step S302, settings are made for the illumination device 160. In step S304, settings are made for the operating conditions of the DUT 2. The operating conditions include settings for the exposure time and sensitivity, for example.

[0038] In operation S306, the operating conditions of the image capture module 130 are set.

[0039] In process S308, DUT2 is powered on.

[0040] In process S310, the site controller 114 of the control unit 110 executes the pattern and controls the test module 120. This causes the DUT 2 to capture an image under the preset conditions. The captured test image IMG is then captured by the image capture module 130 (S312) and transferred to the image processing engine 140 (S314).

[0041] The image processing engine 140 and the edge computer 150 process the test image IMG or the secondary image (S316), and use the results of the image processing to determine PASS / FAIL of the DUT2 (S318).

[0042] 4 is a sequence diagram of an image processing test S300 in the test system 100 according to the embodiment. The control unit 110 executes a test program and controls the test module 120 to perform various settings (S400). After the settings are completed, the test module 120 sends an instruction to the DUT 2 to take an image (S402), and the DUT 2 takes an image (S404). The test image IMG generated by the DUT 2 is transferred to the image processing engine 140 via the image capture module 130 (S406). Thus, the image processing engine 140 acquires the test image IMG (S408).

[0043] The image processing engine 140 transfers the test image, or the secondary image, to the edge computer 150 (S410). Thus, the image processing engine 140 acquires the test image IMG (or the secondary image) (S412).

[0044] The image processing engine 140 and the edge computer 150 execute their respective image processes in parallel (S414, S416). The image processing engine 140 performs a PASS / FAIL determination (S418) and transmits the determination result to the control unit 110 (S420). The edge computer 150 also transmits information obtained by the image processing S416 to the control unit 110.

[0045] The edge computer 150 and the image processing engine 140 can communicate bidirectionally via the IPE dedicated network 180. Therefore, an image or value obtained by the edge computer 150 may be transmitted to the image processing engine 140 (S422). The image processing engine 140 may determine the PASS / FAIL of the DUT2 using the data received from the edge computer 150. Alternatively, the edge computer 150 may determine the PASS / FAIL of the DUT2 based on a determination condition different from that of the image processing engine 140.

[0046] The above is the configuration and operation of the test system 100. According to this test system 100, by adding the edge computer 150, parallel processing of the image processing engine 140 and the edge computer 150 becomes possible, enabling high-speed testing.

[0047] The advantages of test system 100 are made clear by comparison with the comparative art.

[0048] FIG. 5 is a block diagram of a test system 100R according to the comparative technique. As in the embodiment, the comparative technique also incorporates an edge computer 150. Note that the comparative technique is not a well-known technique, but is a configuration that the present inventor has considered. The differences between the embodiment and the comparative technique will be described. In the comparative technique, the image processing engine 140 has only a single IF, and there is no IPE-dedicated network 180. The edge computer 150 is connected only to the system controller network 170.

[0049] In this comparative technique, image data is transferred from the image processing engine 140 to the edge computer 150 via the system controller network 170. The system controller network 170 is connected to other hardware constituting the test system 100R, and its bandwidth is, for example, about 1 Gbps, and is not intended for the transmission of image data. If image data is transferred using such a narrow-band system controller network 170, the system controller network 170 becomes a bottleneck, causing delays in processing.

[0050] In contrast, in this embodiment, an image processing engine 140 having two interfaces IF1 and IF2 is used, and an IPE dedicated network 180 is added in addition to the system controller network 170. The IPE dedicated network 180 has a bandwidth of 10 Gbps or more. Therefore, it becomes possible to transfer image data to the edge computer 150 at high speed via the IPE dedicated network 180, and the bottleneck problem can be solved.

[0051] Fig. 6 is a diagram showing the configuration of the test system 100. The test system 100 includes a mainframe 200, a test head 210, a computer 220, and an edge computer 150. The mainframe 200 is the tester body, and houses the control unit 110 and image processing engine 140 shown in Fig. 1. As shown in Fig. 6, the image processing engine 140 is a rack-mounted hardware, and can be attached to the rear side of the mainframe 200.

[0052] 1 and other power supply circuits are housed in the test head 210. A socket board and a motherboard that serve as an interface 212 with the DUT 2 are provided on the upper portion of the test head 210.

[0053] The computer 220 is a user interface, and a user operates the test system 100 via the computer 220. The edge computer 150 has a housing separate from the mainframe 200.

[0054] 7 is a diagram showing the network configuration of test system 100. Mainframe 200 includes first network switch 172 and second network switch 182. First network switch 172 and second network switch 182 are both housed in a rack of mainframe 200.

[0055] The image processing engine 140 includes two network interface cards (NICs) 142 and 144. The first NIC 142 is connected to a first network switch 172. The NIC 142 and the first network switch 172 are components of a system controller network 170. The system controller 112 and the site controller 114 are also connected to the first network switch 172. The first network switch 172 has a bandwidth of, for example, 1 Gbps.

[0056] The second NIC 144 is connected to a second network switch 182. The NIC 144 and the second network switch 182 are components of an IPE dedicated network 180. An edge computer 150 is connected to the second network switch 182. Since the IPE dedicated network 180 is used for transmitting large amounts of image data, the second network switch 182 has a bandwidth of, for example, 10 Gbps.

[0057] The above is the configuration of the test system 100. Next, the processing by the edge computer 150 will be described with reference to several examples.

[0058] Example 1 The edge computer 150 processes the image data received from the multiple image processing engines 140_1 to 140_n individually. The processing executed by the edge computer 150 may be processing required for PASS / FAIL judgment of DUT2_1 to 2_n. In this case, the processing required for PASS / FAIL judgment of DUT2 can be distributed and processed in parallel by the image processing engine 140 and the edge computer 150, so that the time required for PASS / FAIL judgment can be shortened.

[0059] Example 2 In conventional test systems, the PASS / FAIL judgment of DUT2 was made only by comparing the characteristics of the DUT2 unit with the test standard values, so there was a high possibility that devices with latent defects or low long-term reliability would be judged as good.

[0060] 8 is a diagram for explaining the processing of the edge computer 150 according to the second embodiment. The image processing engine 140 tests the DUT2 against standard values ​​(USL: Upper Specification Limit, LSL: Lower Specification Limit), while the edge computer 150 discriminates outliers from among DUTs within the standard values ​​by statistical analysis such as PAT (AEC-Q001) and machine learning analysis such as Gaussian regression for the test data obtained from each of the DUTs 2_1 to 2_n, and detects field defects due to reliability degradation at an early stage.

[0061] In an example of analysis that applies a machine learning model, an estimated value obtained by calculation is compared with an actual measurement value. A DUT with a large difference between the estimated value and the actual measurement value due to some random defect in the process is determined to be an outlier and its reliability risk is judged. A DUT that is judged to be PASS in both the reliability risk judgment by the edge computer 150 and the PASS / FAIL judgment against the specification value by the image processing engine 140 is ultimately judged to be a non-defective product.

[0062] Example 3 9 is a diagram showing the pass / fail (PASS / FAIL) distribution of dies (DUTs) in a wafer. FAIL indicates a defective die 602, and PASS indicates a pass die 604. As shown in FIG. 9, there are cases where defective dies 602 are concentrated in one location on a wafer 600. In such cases, in conventional test equipment, a die 608 adjacent to the fail area 606 is determined to be pass. However, there is a high possibility that the die 608 adjacent to the fail area 606 has a latent defect.

[0063] In the test system 100 according to the embodiment, image data of multiple chips (DUTs) in the same wafer is processed by the edge computer 150. Therefore, a good die 608 adjacent to a defective area 606 can be determined as a defective product (GDBN: Good Die in Bad Neighborhood) in real time.

[0064] In this way, wafer analysis makes it possible to identify latent defects within the same wafer, and by combining it with lot analysis, it also becomes possible to identify latent defects within the same lot.

[0065] Example 4 Conventionally, all chips and all wafers were tested for all items. In contrast, in the fourth embodiment, the edge computer 150 is used to skip subsequent image capture and calculation processing, or change the analysis algorithm or image capture method based on the test image and the primary processing data obtained by processing the test image.

[0066] For example, in the fourth embodiment, the test system 100 performs the following process.

[0067] FIG. 10 is a diagram illustrating a test sequence according to the fourth embodiment.

[0068] 1) During the data collection period T1 before the start of the lot, pilot tests are performed on several dies, and the measurement data obtained there is accumulated in the edge computer 150. In this example, the test includes 10 test items TI. The edge computer 150 then analyzes the accumulated data using machine learning and artificial intelligence to determine one or more test items (candidate skip items) TI' that may be skipped. In FIG. 9, the candidate skip items are hatched.

[0069] 2) After the start of the lot, a monitoring period T2 is set up for a while. During the monitoring period T2, tests are performed on all items, including the skip candidate items TI'. Then, the skip candidate items TI' are monitored in real time to see if any fails have occurred.

[0070] 2-1) During the monitoring period T2, if no fail occurs for the skip candidate item TI', the skip candidate item TI' becomes a skipped item TI". Conversely, if a fail occurs, the skip candidate item TI' becomes a normal item that is not skipped, and is subsequently subject to inspection.

[0071] 3) After the monitoring period T2, the sampling period T3 begins. In the sampling period T3, inspections are performed for all items other than the skipped item TI”.

[0072] This makes it possible to omit some test items, thereby shortening the test time.

[0073] During the sampling period T3, all items including the skipped item TI″ are tested periodically (slots t0 and t1 in FIG. 9). At this time, since no failure occurs in the skipped item in slot t0, the skipped item TI″ is maintained.

[0074] At slot t1, a failure occurs in one of the skipped items TI". In this case, the skipped item TI" in which the failure occurred reverts to being a normal test item that is not skipped.

[0075] Example 5 In the fifth embodiment, the edge computer 150 accumulates data, processes data related to the current DUT while referring to the accumulated data, and performs grading and binning processing of the DUT in real time.

[0076] Example 6 APC (Advanced Process Control) and SPC (Statistical Process Control) rules can be set in the edge computer 150 to perform deviation and fail analysis of image data, and when the rules are not met, testing control actions can be implemented in real time. For example, fail analysis can determine whether a defect is a problem specific to the device or a problem with the measurement system, including the light source and lens.

[0077] The present invention has been described based on the embodiments, but the embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments without departing from the spirit of the present invention defined in the claims. [Explanation of symbols]

[0078] 100 Test Systems 110 Control section 112 System Controller 114 Site Controller 120 Test Modules 2 DUT 130 Image Capture Module 140 Image Processing Engine 150 Edge Computer 160 Lighting Equipment 170 System Controller Network 172 First Network Switch 180 IPE Dedicated Network 182 Second Network Switch 200 Mainframe 210 Test Head 220 Computer

Claims

1. A test system for inspecting an image sensor as a device under test, comprising: a plurality of test modules corresponding to the plurality of devices under test, each of which causes a corresponding device under test to generate a test image; a plurality of image capture modules corresponding to the plurality of devices under test, each of which captures the test image generated by a corresponding device under test; a plurality of image processing engines corresponding to the plurality of devices under test, each image processing engine processing the test images stored in a corresponding image capture module; A control unit for controlling the test system; Edge computers and Equipped with A test system characterized in that each of the multiple image processing engines has a first interface and a second interface, the first interface is connected to the control unit, and the second interface is connected to the edge computer, and data can be transmitted to each of the control unit and the edge computer.

2. A test system for inspecting an image sensor as a device under test, comprising: a plurality of test modules corresponding to the plurality of devices under test, each of which causes a corresponding device under test to generate a test image; a plurality of image capture modules corresponding to the plurality of devices under test, each of which captures the test image generated by a corresponding device under test; a plurality of image processing engines corresponding to the plurality of devices under test, each image processing engine processing the test images stored in a corresponding image capture module; A control unit for controlling the test system; Edge computers and Equipped with A test system characterized in that the multiple image processing engines and the edge computer are connected via a dedicated network, and the edge computer processes images transferred from the image processing engines.

3. 3. The test system according to claim 1, wherein the control unit and the edge computer are capable of executing different processes in parallel.

4. 3. The test system according to claim 1, wherein the edge computer is capable of performing statistical analysis based on data obtained for the plurality of devices under test.

Images