Semiconductor device and data storage system containing the same

Abstract

To provide a semiconductor device where a manufacturing step is simple, and an electric characteristic and reliability are improved, and provide a data storage system.SOLUTION: A semiconductor device 100 contains: a first semiconductor structure S1 containing a substrate 201, and a capacitor structure 200 that vertically overlaps with a circuit element 221 and an element separation region 209 on the substrate; and a second semiconductor structure S2 that contains a gate electrode 130 sequentially laminated onto an upper surface of a plate layer 101 arranged onto the first semiconductor structure along a Z direction that is vertical to the upper surface so as to be separated from each other, and a channel structure CH extended in the Z direction via the gate electrode. The capacitor structure contains a first electrode structure containing a first capacitor electrode that is extended in the Z direction, and is laminated along the Z direction, and a second electrode structure containing a second capacitor electrode laminated along the Z direction. Both of the first electrode structure and the second electrode structure are alternately arranged so as to be separated from each other in an X direction that is parallel to the upper surface of the substrate, extend in a Y direction that is vertical to the Z direction and the X direction, and have a plate form.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In a data storage system that requires data storage, a semiconductor device capable of storing a large amount of data is required. Accordingly, methods for increasing the data storage capacity of the semiconductor device are being researched. For example, as one method for increasing the data storage capacity of the semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device which can be manufactured easily and has improved electrical characteristics and reliability. Another object of the present invention is to provide a data storage system including a semiconductor device which can be easily manufactured and has improved electrical characteristics and reliability. [Means for solving the problem]

[0004] According to one aspect of the present invention, a semiconductor device is provided that includes a first semiconductor structure including a substrate, an active region in the substrate, a circuit element on the substrate, an isolation region defining the active region, impurity regions disposed in the active region on both sides of the circuit element, a circuit wiring structure electrically connected to the circuit element, and a capacitor structure disposed on the isolation region and vertically overlapping the isolation region, a plate layer disposed on the first semiconductor structure, gate electrodes stacked in sequence on the plate layer at a distance from each other along a first direction perpendicular to an upper surface of the plate layer, a channel structure extending in the first direction via the gate electrode, and and a second semiconductor structure including an upper wiring structure electrically connected to the channel structure, the capacitor structure including a first electrode structure extending in the first direction and including a first capacitor electrode stacked along the first direction, a second electrode structure including a second capacitor electrode stacked along the first direction, and a first insulating structure disposed between the first electrode structure and the second electrode structure, the first capacitor electrodes and the second capacitor electrodes are alternately arranged spaced apart from each other in a second direction parallel to an upper surface of the substrate and extend in a third direction perpendicular to the first and second directions, and the first capacitor electrodes and the second capacitor electrodes may have a plate shape.

[0005] According to another aspect of the present invention, a semiconductor device achieved to achieve the above object includes a substrate including an active region, a circuit element on the active region, an isolation region defining the active region, impurity regions disposed in the active region on both sides of the circuit element, a first electrode structure disposed on the isolation region, vertically overlapping the isolation region, and extending in a first direction perpendicular to an upper surface of the substrate, a second electrode structure disposed on the isolation region, vertically overlapping the isolation region, and spaced from the first electrode structure in a second direction perpendicular to the first direction, and an insulating structure disposed between the first electrode structure and the second electrode structure, wherein each of the first electrode structure and the second electrode structure may extend in a third direction perpendicular to the first and second directions and have a plate shape.

[0006] According to one aspect of the present invention, there is provided a data storage system including a semiconductor storage device including a substrate, an active region in the substrate, circuit elements on the substrate, an isolation region defining the active region, a wiring structure electrically connected to the circuit elements, a capacitor structure disposed on the isolation region and vertically overlapping the isolation region, a memory cell, and an input / output pad; and a controller electrically connected to the semiconductor storage device via the input / output pad and controlling the semiconductor storage device, the capacitor structure being perpendicular to an upper surface of the substrate. The semiconductor device may include a first electrode structure including a first capacitor electrode extending in a first direction and stacked along the first direction, a second electrode structure including a second capacitor electrode stacked along the first direction, and a first insulating structure disposed between the first electrode structure and the second electrode structure, the first capacitor electrodes and the second capacitor electrodes are alternately arranged spaced apart from each other in a second direction parallel to an upper surface of the substrate and extend in a third direction perpendicular to the first and second directions, and the first capacitor electrodes and the second capacitor electrodes may have a plate shape. Effect of the Invention

[0007] According to the present invention, by providing a capacitor structure that is disposed on an isolation region and vertically overlaps the isolation region, it is possible to provide a semiconductor device and a data storage system including the same having improved electrical characteristics and reliability.

[0008] The various and beneficial advantages and effects of the present invention are not limited to the above, but will be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic block diagram of a semiconductor device according to an exemplary embodiment; [Diagram 2] 1 is a circuit diagram showing a charge pump circuit included in a voltage generator of a semiconductor device according to an exemplary embodiment. [Diagram 3] 1 is a schematic perspective view of a semiconductor device according to an exemplary embodiment; [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 5a] FIG. 2 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, showing a schematic cross-sectional view of a capacitor structure. [Figure 5b] 1 is a plan view of a capacitor structure of a semiconductor device according to an exemplary embodiment; [Figure 5c] 1 is a perspective view showing a capacitor structure of a semiconductor device according to an exemplary embodiment; [Figure 6] FIG. 2 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, showing a schematic cross-sectional view of a capacitor structure. [Figure 7] FIG. 2 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, showing a schematic cross-sectional view of a capacitor structure. [Figure 8] FIG. 2 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, showing a schematic cross-sectional view of a capacitor structure. [Figure 9a] FIG. 2 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, showing a schematic cross-sectional view of a capacitor structure. [Figure 9b] 1 is a plan view of a capacitor structure of a semiconductor device according to an exemplary embodiment; [Figure 10] FIG. 2 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, showing a schematic cross-sectional view of a capacitor structure. [Figure 11] FIG. 2 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, showing a schematic cross-sectional view of a capacitor structure. [Figure 12] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 13] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 14] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 15]1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 16] FIG. 1 is a diagram of a data storage system including a semiconductor device according to an exemplary embodiment. [Figure 17] 1 is a perspective view of a data storage system including a semiconductor device according to an exemplary embodiment; [Figure 18] 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following, terms such as "upper", "upper part", "upper surface", "upper", "lower", "lower surface", "under", "side" and the like are understood to refer to the drawings unless otherwise indicated by reference numerals.

[0011] FIG. 1 is a schematic block diagram of a semiconductor device according to an exemplary embodiment.

[0012] 1, the semiconductor device 100 includes a memory cell array 20 and a peripheral circuit 30. The semiconductor device 100 may be a memory device, for example, a non-volatile memory such as a flash memory, or a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0013] The memory cell array 20 includes a plurality of memory cells. The plurality of memory cells are coupled to a row decoder 33 via a plurality of word lines WL and to a read / write circuit 35 via a plurality of bit lines BL. In an exemplary embodiment, a plurality of memory cells arranged along the same row are coupled to the same word line WL, and a plurality of memory cells arranged along the same column are coupled to the same bit line BL. In some embodiments, the memory array 20 includes a plurality of memory blocks, each of which includes a plurality of memory cells.

[0014] The peripheral circuit 30 receives an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 100, and transmits and receives data DATA to and from devices outside the semiconductor device 100. The peripheral circuit 30 includes a row decoder 33, a read / write circuit 35, a control logic 37, and a voltage generator 38 that generates various voltages necessary for the operation of the semiconductor device 100. Depending on the embodiment, the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit (not shown) and an error correction circuit for correcting errors in the data DATA read from the memory cell array 20.

[0015] The control logic 37 is coupled to the row decoder 33, the voltage generator 38, and the input / output circuitry. The control logic 37 controls the overall operation of the semiconductor device 100. The control logic 37 generates various internal control signals used within the semiconductor device 100 in response to a control signal CTRL received from an external device. For example, the control logic 37 adjusts the voltage levels provided to the word lines WL and bit lines BL when performing a memory operation such as a program operation or an erase operation.

[0016] The row decoder 33 selects some of the memory cells in response to an address ADDR and selects at least one word line WL, and transmits a voltage for performing a memory operation to the selected word line WL.

[0017] The read / write circuit 35 is connected to the memory cell array 20 via bit lines BL. The read / write circuit 35 includes a writer driver or a sense amplifier. Specifically, during a program operation, the read / write circuit 35 operates as a writer driver to apply a voltage corresponding to data DATA to be stored in the memory cell array 20 to the bit lines BL. Meanwhile, during a read operation, the read / write circuit 35 operates as a sense amplifier to sense the data DATA stored in the memory cell array 20.

[0018] The voltage generator 38 includes a controller 52 , an oscillator 54 , and a charge pump 56 .

[0019] The charge pump 56 includes a plurality of charge pumps, each of which includes at least one switch element and at least one pumping capacitor. The output voltage of the charge pump 56 is used for the operation of the semiconductor device 100. As an example, the row decoder 33 uses the output voltage of the charge pump 56 to input a bias voltage to the word line WL for performing a program operation, an erase operation, a read operation, or the like.

[0020] The controller 52 controls the operation of the oscillator 54. For example, the controller 52 determines the frequency of the clock signal CLK that the oscillator 54 outputs to the charge pump 56 based on at least one of PVT (Process, Voltage, Temperature) information of the semiconductor device 100 and a target level of the voltage to be output by the charge pump 56. As an example, when the charge pump 56 includes multiple charge pumps, the controller 52 determines which of the multiple charge pumps is to be selected to actually operate.

[0021] The oscillator 54 outputs a clock signal CLK that turns on and off at least one switch element included in the charge pump 56. The clock signal CLK output by the oscillator 54 is determined in response to a control signal VGC from the controller 52. For example, the oscillator 54 sets the frequency and swing range of the clock signal CLK to be different depending on the control signal VGC transmitted by the controller 52.

[0022] FIG. 2 is a circuit diagram showing a charge pump circuit included in a voltage generator of a semiconductor device according to an exemplary embodiment.

[0023] 2, the charge pump circuit 56a includes a plurality of diodes DI, a plurality of pumping capacitors CP, and an output capacitor COUT. The plurality of diodes DI are connected in series with each other, and a plurality of pumping capacitors CP are connected to nodes between the plurality of diodes DI. The first diode receives a power supply voltage VCC having a predetermined level, and the last diode outputs an output current IOUT to an output node.

[0024] Each of the pumping capacitors CP is charged or discharged by a clock signal CLK or a complementary clock signal CLKB phase-converted by an inverter INV to have an opposite phase to the clock signal CLK. For example, the odd-numbered pumping capacitors CP are charged or discharged by the clock signal CLK, and the even-numbered pumping capacitors CP are charged or discharged by the complementary clock signal CLKB.

[0025] FIG. 3 is a schematic perspective view of a semiconductor device according to an exemplary embodiment.

[0026] 3, the semiconductor device 10a includes a peripheral circuit structure PERI and a memory cell structure CELL. The memory cell structure CELL is disposed on the peripheral circuit structure PERI. The memory cell structure CELL is an area in which the memory cell array 20 of FIG. 1 is disposed, and the peripheral circuit structure PERI is an area in which the peripheral circuit 30 of FIG. 1 is disposed. In some embodiments, the memory cell structure CELL may be disposed below the peripheral circuit structure PERI, on the contrary.

[0027] The memory cell structure CELL includes a first region R1 and a second region R2. The first region R1 is a region in which the memory cell array 20 is arranged. The second region R2 corresponds to a region for electrically connecting the memory cells of the memory cell array 20 to peripheral circuits. The second region R2 is arranged in at least one direction of the first region R1. For example, the second region R2 is arranged at at least one end of the first region R1 in the x direction.

[0028] The pumping capacitors CP constituting the charge pump circuits 56, 56a in Figures 1 and 2 are arranged in the peripheral circuit structure PERI. For example, but not limited to, the pumping capacitors CP are arranged under the second region R2 of the memory cell structure CELL in the peripheral circuit structure PERI. In some embodiments, the pumping capacitors CP may be arranged under the first region R1 of the memory cell structure CELL in the peripheral circuit structure PERI.

[0029] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0030] 5a is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, which is a schematic cross-sectional view of a capacitor structure. FIG 5a shows an enlarged view of region "A" of FIG 4.

[0031] Figure 5b is a plan view of a capacitor structure of a semiconductor device according to an exemplary embodiment, showing a plane along section line II' of Figure 5a.

[0032] FIG. 5c is a perspective view illustrating a capacitor structure of a semiconductor device according to an exemplary embodiment.

[0033] 4 to 5c, the semiconductor device 100 includes a peripheral circuit structure PERI that is a first semiconductor structure S1 including a substrate 201, and a memory cell structure CELL that is a second semiconductor structure S2 that includes a plate layer 101.

[0034] The first semiconductor structure S 1 includes a substrate 201 , an impurity region 205 and an isolation region 209 in the substrate 201 , a circuit element 221 disposed on the substrate 201 , a peripheral region insulating layer 290 , a circuit contact plug 270 , and a circuit wiring line 275 .

[0035] The substrate 201 has a top surface extending in the x-direction and the y-direction. An active region is defined in the substrate 201 by an isolation region 209. An impurity region 205 containing impurities is disposed in a part of the active region. The substrate 201 includes a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 is provided as a bulk wafer or an epitaxial layer.

[0036] The circuit elements 221 include planar transistors. Each circuit element 221 includes a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. On both sides of the circuit gate electrode 225, impurity regions 205 are disposed in the substrate 201 as source / drain regions.

[0037] The peripheral area insulating layer 290 is disposed on the circuit element 221 on the substrate 201. The peripheral area insulating layer 290 includes a plurality of insulating layers formed in different process steps. The peripheral area insulating layer 290 is made of an insulating material.

[0038] The circuit contact plug 270 and the circuit wiring line 275 constitute the circuit wiring structure 270, 275 electrically connected to the circuit element 221 and the impurity region 205. The circuit wiring structure 270, 275 are referred to as a lower wiring structure. The circuit contact plug 270 has a cylindrical shape, and the circuit wiring line 275 has a line shape. An electrical signal is applied to the circuit element 221 through the circuit contact plug 270 and the circuit wiring line 275. In a region not shown, the circuit contact plug 270 is also connected to the circuit gate electrode 225. The circuit wiring line 275 is connected to the circuit contact plug 270, has a line shape, and is arranged in a plurality of layers. The circuit contact plug 270 and the circuit wiring line 275 include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each structure may further include a diffusion barrier layer. In an exemplary embodiment, the number of layers of circuit contact plugs 270 and circuit wiring lines 275 may vary.

[0039] The circuit wiring structures 270, 275 include a capacitor structure 200. The capacitor structure 200 includes lines and contacts that are disposed at the same level as the other circuit contact plugs 270 and the circuit wiring lines 275, respectively. The capacitor structure 200 is disposed horizontally spaced apart from other regions of the circuit wiring structures 270, 275. The capacitor structure 200 is electrically connected to some of the circuit elements 221. The capacitor structure 200 is disposed in, but is not limited to, the second region R2. In some embodiments, the capacitor structure 200 is disposed under the first region R1 of the memory cell structure CELL, or under both the first and second regions R1, R2.

[0040] The memory cell structure CELL has first and second regions R1 and R2, and includes a source structure SS, a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 140 alternately stacked with the gate electrode 130, a channel structure CH disposed to penetrate the stacked structure of the gate electrode 130, and a contact plug 170 connected to the gate electrode 130 and extending vertically. The memory cell structure CELL further includes a horizontal insulating layer 113 disposed under the gate electrode 130, a substrate insulating layer 121 disposed to penetrate the plate layer 101, a stud 185 on the contact plug 170, and a cell region insulating layer 190 covering the gate electrode 130.

[0041] In the memory cell structure CELL, the first region R1 is a region where the gate electrode 130 is vertically stacked to form a memory cell or is connected to the contact plug 170. The second region R2 may be an outer region of the plate layer 101.

[0042] The source structure SS includes a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104, which are stacked in sequence. The plate layer 101 has a plate shape and functions as at least a part of a common source line of the semiconductor device 100. The plate layer 101 includes a conductive material, for example, a semiconductor material. The plate layer 101 further includes an impurity. The plate layer 101 is provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

[0043] The first and second horizontal conductive layers 102, 104 are sequentially stacked on the upper surface of the plate layer 101 in a region where the channel structure CH is disposed. The first horizontal conductive layer 102 functions as a part of a common source line of the semiconductor device 100, for example, functions as a common source line together with the plate layer 101. The first horizontal conductive layer 102 is directly connected to a channel layer in the channel structure CH. The first and second horizontal conductive layers 102, 104 include a semiconductor material, for example, polycrystalline silicon.

[0044] The horizontal insulating layer 113 is disposed on the plate layer 101 at the same level as the first horizontal conductive layer 102. The horizontal insulating layer 113 includes first and second horizontal insulating layers 111 and 112 alternately stacked on the plate layer 101. The horizontal insulating layer 113 is a layer remaining after a portion of the horizontal insulating layer 113 is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100. The horizontal insulating layer 113 includes silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 include different insulating materials.

[0045] The substrate insulating layer 121 is disposed to penetrate the plate layer 101, the horizontal insulating layer 113, and the second horizontal conductive layer 104. The substrate insulating layer 121 includes an insulating material, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0046] The gate electrodes 130 are stacked vertically on the plate layer 101 at a distance, and form a stacked structure together with the interlayer insulating layer 140. The stacked structure includes lower and upper stacked structures stacked vertically. The gate electrodes 130 include first upper gate electrodes 130U1 and 130U2 forming string selection transistors, memory gate electrodes 130M forming a plurality of memory cells, and second lower gate electrodes 130L1 and 130L2 forming ground selection transistors. The number of memory gate electrodes 130M forming memory cells is determined according to the capacity of the semiconductor device 100.

[0047] The gate electrodes 130 are stacked vertically on the first region R1 and spaced apart from each other, and extend to different lengths in the x direction to form a stepped structure. Due to the stepped structure, the lower gate electrode 130 extends longer than the upper gate electrode 130 disposed on the lower gate electrode 130, and each gate electrode 130 has a contact region 130P exposed to the upper part from the interlayer insulating layer 140. The gate electrodes 130 are connected to contact plugs 170 at the contact regions 130P, which are end regions.

[0048] The gate electrode 130 includes a metal material, such as tungsten (W). In some embodiments, the gate electrode 130 includes a polysilicon or metal silicide material. The gate electrode 130 includes the same material throughout. In an exemplary embodiment, the gate electrode 130 further includes a diffusion barrier, for example, the diffusion barrier includes tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0049] The interlayer insulating layers 140 are disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 140 are also disposed to extend in the x direction and spaced apart from each other in a direction perpendicular to the top surface of the plate layer 101. The interlayer insulating layers 140 include an insulating material such as silicon oxide or silicon nitride.

[0050] The channel structures CH extend in the z direction through the gate electrode 130 and are connected to the plate layer 101. The channel structures CH each form one memory cell string and are arranged on the plate layer 101 in rows and columns spaced apart from each other. The channel structures CH are arranged in a lattice pattern in the xy plane or in a zigzag pattern in one direction. The channel structures CH have a columnar shape and inclined side surfaces, and the horizontal width of the channel structures CH may be narrower as they approach the plate layer 101.

[0051] The channel structure CH includes lower and upper channel structures CH1 and CH2 that are vertically stacked. The channel structure CH has a form in which the lower channel structure CH1 and the upper channel structure CH2 are connected, and has a bent part due to a difference in width in the connection region. However, the number of channel structures stacked along the z direction may be variously changed according to the embodiment. Each of the channel structures CH includes a channel layer disposed in a channel hole, a gate dielectric layer, a channel buried insulating layer, and an upper channel pad.

[0052] The contact plug 170 is connected to the contact region 130P of the gate electrode 130. The contact plug 170 penetrates at least a portion of the cell region insulating layer 190 and is connected to each of the contact regions 130P of the gate electrode 130 exposed at the top. The contact plug 170 penetrates the gate electrode 130 under the contact region 130P, penetrates the second horizontal conductive layer 104, the horizontal insulating layer 113, and the plate layer 101, and is connected to a circuit wiring line 275 in the peripheral circuit structure PERI. The contact plug 170 is separated from the gate electrode 130 under the contact region 130P by the contact insulating layer 160. The contact plug 170 is separated from the plate layer 101, the horizontal insulating layer 113, and the second horizontal conductive layer 104 by the substrate insulating layer 121.

[0053] Each of the contact plugs 170 has a shape that extends horizontally in the contact region 130P. The contact plug 170 includes a vertical extension portion 170V extending along the z direction and a horizontal extension portion 170H that extends horizontally from the vertical extension portion 170V and contacts the gate electrode 130. The horizontal extension portion 170H may be disposed along the periphery of the vertical extension portion 170V and may be surrounded on all sides by the gate electrode 130. The contact plug 170 is separated from the gate electrode 130 under the contact region 130P, i.e., the gate electrode 130 that is not electrically connected, by the contact insulating layer 160.

[0054] The contact plug 170 includes a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some embodiments, the contact plug 170 includes a barrier layer extending along the side and bottom surfaces or has an air gap therein.

[0055] The contact insulating layers 160 are disposed under the contact regions 130P so as to surround each side of the contact plugs 170. The contact insulating layers 160 are disposed around each of the contact plugs 170 and spaced apart from each other along the z direction. The contact insulating layers 160 are disposed at substantially the same level as the gate electrodes 130. The contact insulating layers 160 include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0056] The stud 185 constitutes a cell wiring structure electrically connected to a memory cell in the memory cell structure CELL. The stud 185 is connected to the channel structure CH and the contact plug 170, and is electrically connected to the channel structure CH and the gate electrode 130. The stud 185 includes a metal, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0057] The cell region insulating layer 190 is disposed to cover the stacked structure of the gate electrode 130 and the contact plug 170. The cell region insulating layer 190 is made of an insulating material and may be formed of a plurality of insulating layers.

[0058] The through plug 164 and the capacitor contact 165 are disposed in a second region R2 of the memory cell region CELL, which is an outer region of the plate layer 101. The through plug 164 and the capacitor contact 165 extend to the peripheral circuit region PERI by passing through the cell region insulating layer 190. The through plug 164 and the capacitor contact 165 are disposed to connect the stud 185 of the memory cell region CELL to the circuit wiring line 275 of the peripheral circuit region PERI. The through plug 164 and the capacitor contact 165 include a conductive material, for example, a metal material such as tungsten (W), copper (Cu), or aluminum (Al). The through plug 164 and the capacitor contact 165 are formed in the same process step as the contact plug 170, include the same material, and have the same internal structure.

[0059] The capacitor structure 200 is disposed in the second region R2, and is disposed across the peripheral circuit region PERI and the memory cell region CELL. The capacitor structure 200 functions to store electric charges. The capacitor structure 200 includes a first electrode structure 210, a second electrode structure 220, and an insulating structure IL. The capacitor structure 200 forms a pumping capacitor CP of the charge pump circuits 56, 56a described above with reference to FIGS. 1 to 3. The capacitor structure 200 is disposed on the element isolation region 209, and vertically overlaps the element isolation region 209.

[0060] The first electrode structure 210 includes first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f stacked in a direction perpendicular to the top surface of the substrate 201, for example, in the z direction. The second electrode structure 220 includes second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f stacked in the z direction. The first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f are alternately arranged at a distance from each other in the x direction parallel to the top surface of the substrate 201. The first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are formed together in the process of forming the circuit contact plug 270 and the circuit wiring line 275, and are therefore disposed at substantially the same level as the circuit wiring structures 270, 275. The first electrode structure 210 and the second electrode structure 220 are disposed on the element isolation region 209, and are therefore not electrically connected to the circuit element 221.

[0061] The capacitor structure 200 is disposed on a substrate 201. The first electrode structure 210 and the second electrode structure 220 are disposed on the isolation region 209 and penetrate at least a portion of the isolation region 209. The lowermost portions of the first electrode structure 210 and the second electrode structure 220 are located at a lower level than the lowermost portions of the circuit wiring structures 270 and 275, but are not limited thereto. The first electrode structure 210 and the second electrode structure 220 have different electric potentials. According to an embodiment, the first electrode structure 210 and the second electrode structure 220 receive an electric signal through separate wiring connected to at least a portion of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f. According to an exemplary embodiment, the capacitor contacts 165 apply a bias to the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f. This creates a potential difference between the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f. The amount of charge that the capacitor structure 200 can store is proportional to the product of the potential difference and the capacitance of the capacitor structure 200. The capacitance is proportional to the dielectric constant of the insulating structure IL and the product of the areas of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f arranged on the left and right sides of the insulating structure IL, which face each other, and is inversely proportional to the distance between the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f arranged on the left and right sides of the insulating structure IL.

[0062] As shown in Fig. 5c, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are in the form of plates extending in the y and z directions, but are not limited thereto. According to other embodiments, at least some of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f may be in the form of a line or a column.

[0063] Since the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are arranged in a plate shape, the areas of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are increased compared to when they are arranged in a pillar shape, thereby maximizing the capacitance of the capacitor structure 200. In addition, each of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f extends in the z-direction to penetrate at least a portion of the device isolation region 209, thereby improving the capacitance of the capacitor structure 200. The deeper the device isolation region 209, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f, and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are formed, the more the capacitance of the capacitor structure 200 can be improved.

[0064] In an embodiment, the number of layers constituting each of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may be variously changed.

[0065] The first electrode structure 210 and the second electrode structure 220 include a metal material, for example, tungsten (W), copper (Cu), or aluminum (Al). The first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f include, but are not limited to, the same material. In other embodiments, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f include a different material from the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f. For example, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f include a metal material, and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f include a semiconductor material. The insulating structure IL is an insulating layer including an insulating material, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. According to an exemplary embodiment, the insulating structure IL may be composed of multiple insulating layers. The dielectric constant of the insulating structure IL increases as it becomes closer to the substrate 201 or the element isolation region 209.

[0066] As shown in FIG. 5b, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f, which are located at the same level as the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f, respectively, and the insulating structure IL disposed therebetween form one MIM (Metal-Insulator-Metal) capacitor, and the respective capacitances are C1a, C1b, C1c, C1d, C1e, and C1f, which have different values ​​from each other, but are not limited thereto. The lowermost first capacitor electrode 210a, the lowermost second capacitor electrode 220a and the element isolation region 209 therebetween form one MIM capacitor, and the capacitance is C2.

[0067] 6 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, which is a schematic cross-sectional view of a capacitor structure 200a, showing an area corresponding to FIG.

[0068] 6, in the capacitor structure 200a, the bottom ends of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are located at a level higher than the top surface of the substrate 201. According to an exemplary embodiment, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are disposed on the element isolation region 209 and spaced apart from the top surface of the element isolation region 209. At some stages in the manufacturing process of the semiconductor device 100a, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are formed together in the process of forming the circuit wiring structures 270, 275 without a separate process of penetrating the element isolation region 209, thereby reducing process costs and difficulty.

[0069] 7 is a schematic cross-sectional view of a capacitor structure 200b in an enlarged partial cross-sectional view of a semiconductor device according to an exemplary embodiment, showing an area corresponding to FIG.

[0070] 7, the first semiconductor structure S1 further includes a stopper layer SL disposed on a portion of the surface of the substrate 201 along the surface of the substrate 201 in the element isolation region 209. According to an exemplary embodiment, at least a portion of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f contact the stopper layer SL, but is not limited thereto. According to another embodiment, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are disposed apart from the stopper layer SL. The stopper layer SL serves to prevent the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f from contacting the substrate 201. The stopper layer SL includes at least one of insulating materials, for example, SiN, SiON, SiCN, SiOC, SiOCN, and SiO. The stopper layer SL and the first insulating structure IL1 may include other materials, but are not limited thereto.

[0071] 8 is a schematic cross-sectional view of a capacitor structure 200c in accordance with an exemplary embodiment of a semiconductor device, the cross-sectional view showing an area corresponding to FIG.

[0072] 8, the semiconductor device further includes a third electrode structure 230 and a fourth electrode structure 240 disposed on the impurity region 205 and the circuit element 221. The third electrode structure 230 extends in the y direction and is stacked on the impurity region 205 in the z direction, and the fourth electrode structure 240 extends in the y direction and is stacked on the circuit element 221 in the z direction. The second insulation structure IL2 is disposed between the third electrode structure 230 and the fourth electrode structure 240. Although the second insulation structure IL2 represents an insulation structure IL on the impurity region 205 and the circuit element 221, the second insulation structure IL2 includes the same material as the first insulation structure IL1 since it is formed in substantially the same process step as the first insulation structure IL1. The third electrode structure 230, the fourth electrode structure 240, and the second insulating structure IL2 disposed between the third electrode structure 230 and the fourth electrode structure 240 form one MIM capacitor, and the capacitances are C1b, C1c, C1d, C1e, and C1f, which have different values, but are not limited to this. Also, the second electrode structure 220, the third electrode structure 230, and the insulating structure IL disposed between the second electrode structure 220 and the third electrode structure 230 form one MIM capacitor, and the capacitances are C3, C1b, C1c, C1d, C1e, and C1f, which have different values, but are not limited to this.

[0073] 9a is a schematic cross-sectional view of a capacitor structure 200d in accordance with an exemplary embodiment of a semiconductor device, the cross-sectional view showing an area corresponding to FIG.

[0074] 9b is a plan view of a capacitor structure 200d of a semiconductor device according to an exemplary embodiment, taken along line II-II' of FIG. 9a.

[0075] 9a and 9b, the first semiconductor structure S1 further includes dummy patterns DP that are spaced apart from each other in the x and y directions and vertically overlap the capacitor structure 200d. The dummy patterns DP are defined by isolation regions 209. According to an exemplary embodiment, the isolation regions 209 are disposed between the dummy patterns DP. The circuit elements 221 are not disposed on the dummy patterns DP, but are not limited thereto. When the circuit elements 221 are disposed on the dummy patterns DP, they are not connected to the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f and are referred to as dummy circuit elements. The dummy patterns DP serve to prevent a dishing phenomenon in which the isolation regions 209 become downwardly convex when a subsequent planarization process is performed. Although the dummy patterns DP are shown to be spaced apart in an island-type arrangement, the present invention is not limited to the illustrated example. At least a portion of the first electrode structure 210 and the second electrode structure 220 vertically overlaps the dummy pattern DP. According to an exemplary embodiment, the first electrode structure 210 and the second electrode structure 220 that vertically overlap the dummy pattern DP are spaced apart from the dummy pattern DP, and the first electrode structure 210 and the second electrode structure 220 that do not vertically overlap the dummy pattern DP are disposed on the element isolation region 209 between the dummy patterns DP. Since the first electrode structure 210 and the second electrode structure 220 penetrate at least a part of the isolation region 209, the area of ​​the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f that constitute the capacitor structure 200d facing each other increases, thereby increasing the capacitance. The lowermost first capacitor electrode 210a and the lowermost second capacitor electrode 220a and the isolation region 209 therebetween form one MIM capacitor, and the capacitance is C2. According to an exemplary embodiment, the MIM capacitor formed by the lowermost first capacitor electrode 210a, the lowermost second capacitor electrode 210b, and the insulating structure IL has capacitances C1a1, C1a2, and C1a3.The capacitance varies depending on the area, length, and material of the lowermost first capacitor electrode 210a and the lowermost second capacitor electrode 210b.

[0076] 10 is a schematic cross-sectional view of a capacitor structure 200e in accordance with an exemplary embodiment of a semiconductor device, the cross-sectional view showing an area corresponding to FIG.

[0077] 10, unlike the capacitor structure 200d of FIG 9a, first capacitor electrodes 210a, 210b, 210c, 210d, 210e, 210f and second capacitor electrodes 220a, 220b, 220c, 220d, 220e, 220f are disposed at a level higher than the top surface of the isolation region 209 and spaced apart from the dummy pattern DP. Additionally, the description of FIG 9a and FIG 9b may be applied to the description of the dummy pattern DP.

[0078] 11 is a schematic cross-sectional view of a capacitor structure 200f, which is an enlarged partial cross-sectional view of a semiconductor device according to an exemplary embodiment, and shows an area corresponding to FIG.

[0079] 11, the semiconductor device further includes dummy patterns DP spaced apart from each other in the x and y directions and arranged between the circuit elements 221. Also, in the element isolation region 209, a stopper layer SL is further arranged on a part of the surface of the substrate 201 and the surface of the dummy patterns DP along the surface of the substrate 201 and the surface of the dummy patterns DP. The description of the dummy patterns DP is the same as that of FIGS. 9a and 9b. After forming the stopper layer SL to cover the dummy patterns DP, the element isolation region 209 is formed between the dummy patterns DP and to cover the stopper layer SL, and the upper surface of the dummy patterns DP is exposed through a planarization process. As a result, the stopper layer SL does not cover the upper surface of the dummy patterns DP. In addition, the description of the stopper layer SL described above in FIG. 7 can be similarly applied.

[0080] FIG. 12 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0081] Referring to FIG. 12, a semiconductor device 100a includes a first semiconductor structure S1 and a second semiconductor structure S2 bonded by a wafer bonding method.

[0082] The first semiconductor structure S1 is described in the peripheral circuit structure PERI of FIG. 4. However, the first semiconductor structure S1 further includes a first bonding structure 280, which includes a first bonding via 282, a first bonding pad 284, and a first bonding insulating layer 286. The first bonding via 282 is connected to the circuit wiring structures 270 and 275. The first bonding pad 284 is connected to the first bonding via 282. The first bonding via 282 and the first bonding pad 284 include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc., and each of the structures further includes a diffusion barrier layer. The first bonding insulating layer 286 also functions as a diffusion barrier layer for the first bonding pad 284, and includes at least one of SiCN, SiO, SiN, SiOC, SiON, and SiOCN. The first bonding insulating layer 286 has a thickness that is less than the thickness of the first bonding pad 284, but is not limited to this.

[0083] The first bonding pad 284 is connected to the second bonding pad 184 of the second semiconductor structure S2. The first bonding structure 280 is directly contacted and bonded or connected to the second bonding structure 180 by hybrid bonding. For example, the first bonding pad 284 is in contact with the second bonding pad 184 and bonded by copper (Cu)-copper (Cu) bonding, and the first bonding insulating layer 286 is in contact with the second bonding insulating layer 186 and bonded by dielectric-to-dielectric bonding. The first bonding structure 280, together with the second bonding structure 180, provides an electrical connection path by bonding the first semiconductor structure S1 and the second semiconductor structure S2. Some of the first bonding pads 284 are not connected to the lower circuit wiring line 275 and are arranged only for bonding. A first bonding insulation layer 286 is disposed around the first bonding pad 284 .

[0084] 4 applies to the second semiconductor structure S2. The second semiconductor structure S2 further includes a second bonding structure 180 including a second bonding via 182, a second bonding pad 184, and a second bonding insulating layer 186. The second semiconductor structure S2 further includes a cell wiring line 181 and a passivation layer 106 covering the upper surface of the plate layer 101.

[0085] The second bonding via 182 and the second bonding pad 184 are disposed under the stud 185. In some embodiments, the cell wiring line 181 is further disposed between the second bonding via 182 and the stud 185. The second bonding via 182 connects the stud 185 and the second bonding pad 184, and the second bonding pad 184 is bonded to the first bonding pad 184 of the first semiconductor structure S1. The second bonding insulating layer 186 is bonded to and connected to the first bonding insulating layer 286 of the first semiconductor structure S1. The second bonding via 182 and the second bonding pad 184 include a conductive material, for example, copper (Cu). The second bonding insulating layer 186 includes at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0086] The cell wiring line 181 constitutes an upper wiring structure electrically connected to the memory cells in the memory cell region CELL. The cell wiring line 181 is connected to the contact plug 170 and the through plug 164, and is electrically connected to the gate electrode 130 and the channel structure CH. In an exemplary embodiment, the number of wiring lines constituting the upper wiring structure may be changed in various ways. The cell wiring line 181 includes a metal, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0087] The passivation layer 106 is disposed on the upper surface of the plate layer 101 to protect the semiconductor device 100a. The passivation layer 106 includes an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon carbide, and may be composed of multiple insulating layers according to an embodiment. In this embodiment, the upper end of the contact plug 170 is located in the substrate insulating layer 121.

[0088] FIG. 13 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary embodiment, and is a schematic cross-sectional view of a capacitor structure.

[0089] 13, the semiconductor device 100b further includes a second capacitor structure 300 in the semiconductor device 100a of FIG. 12. The second capacitor structure 300 includes a capacitor contact 165 and a substrate insulating layer 121. The second capacitor structure 300 is disposed in a second region R2 that is located outside the plate layer 101. The capacitor contact 165 penetrates a portion of the substrate insulating layer 121. In the substrate insulating layer 121, adjacent capacitor contacts 165 have different potentials. According to an exemplary embodiment, a semiconductor device 100b is provided in which capacitance is improved by the capacitor contacts 165 having different potentials from the substrate insulating layer 121 between the capacitor contacts 165.

[0090] FIG. 14 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0091] 14, the semiconductor device 100c includes a first semiconductor structure S1 and a second semiconductor structure S2 bonded by a wafer bonding method. The second semiconductor structure S2 includes a memory semiconductor chip, and the first semiconductor structure S1 includes, but is not limited to, a logic semiconductor chip.

[0092] The second semiconductor structure S2 is disposed at the bottom, and the first semiconductor structure S1 is disposed on the second semiconductor structure S2 in a mirror form. The description of the peripheral circuit structure PERI in FIG. 4 applies to the first semiconductor structure S1. However, the first semiconductor structure S1 further includes a first bonding via 282, a first bonding pad 284, and a first bonding insulating layer 286, which are a first bonding structure 280. The description of the memory cell structure CELL in FIG. 4 applies to the second semiconductor structure S2. The second semiconductor structure S2 further includes a second bonding structure 180 including a second bonding via 182, a second bonding pad 184, and a second bonding insulating layer 186. The first bonding pad 284 is connected on the upper surface of the second bonding pad 184 of the second semiconductor structure S2. The first bonding structure 280 is directly contacted and bonded or connected to the second bonding structure 180 by hybrid bonding. Additionally, content that overlaps with the content described above in FIG. 12 has been omitted.

[0093] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0094] 15, in the semiconductor device 100c of FIG. 14, the third semiconductor structure S3 is disposed on the first semiconductor structure S1. The third semiconductor structure S3 is applied with the description of the peripheral circuit structure PERI of FIG. 4. The third semiconductor structure S3 has a symmetrical structure with the first semiconductor structure S1, and the description of the first semiconductor structure S1 can be applied substantially similarly. The description of the substrate 201, the element isolation region 209, and the peripheral region insulating layer 290 of the first semiconductor structure S1 is applied substantially similarly to the substrate 301, the element isolation region 309, and the peripheral region insulating layer 290 of the third semiconductor structure S3. The third semiconductor structure S3 is disposed on the element isolation region 309 and further includes a third capacitor structure 400 vertically overlapping the element isolation region 309. The substrate 301 and the element isolation region 309 are partially removed from the lower surface of the third semiconductor structure S3 by a planarization process, and a portion of the third capacitor structure 400 is exposed. The top surface of the first semiconductor structure S1 is subjected to a planarization process to partially remove the substrate 201 and the isolation region 209, thereby exposing a portion of the first capacitor structure 200. The first capacitor structure 200 of the first semiconductor structure S1 and the third capacitor structure 400 of the third semiconductor structure S3 are bonded to be connected to each other. The substrate 201 of the first semiconductor structure S1 and the substrate 301 of the third semiconductor structure S3 are bonded in direct contact with each other. The isolation region 209 of the first semiconductor structure S1 and the isolation region 309 of the third semiconductor structure S3 are bonded in direct contact with each other. Since the first semiconductor structure S1 includes a first capacitor structure 200 on the element isolation region 209, the second semiconductor structure S2 includes a second capacitor structure 300 on the substrate insulating layer 121, and the third semiconductor structure S3 includes a third capacitor structure 400 on the element isolation region 309, it is possible to maximize capacitance within the semiconductor device 100d and improve the integration density and electrical characteristics of the semiconductor device 100d.

[0095] FIG. 16 is a diagram illustrating a data storage system including a semiconductor device according to an exemplary embodiment.

[0096] 16, a data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) including one or more semiconductor devices 1100, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device.

[0097] The semiconductor device 1100 may be a non-volatile memory device, for example, a NAND flash memory device as described above with reference to FIGS. 1 to 15. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed next to the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1, UL2, first and second gate lower lines LL1, LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0098] In the second structure 1100S, each memory cell string CSTR includes lower transistors LT1, LT2 adjacent to a common source line CSL, upper transistors UT1, UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1, LT2 and the upper transistors UT1, UT2. The number of the lower transistors LT1, LT2 and the number of the upper transistors UT1, UT2 may vary depending on the embodiment.

[0099] In an exemplary embodiment, the upper transistors UT1 and UT2 include string selection transistors, and the lower transistors LT1 and LT2 include ground selection transistors. The gate lower lines LL1 and LL2 are the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 are the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0100] In an exemplary embodiment, the lower transistors LT1, LT2 include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1, UT2 include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 is used for an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0101] The common source line CSL, the first and second gate lower lines LL1, LL2, the word line WL, and the first and second gate upper lines UL1, UL2 are electrically connected to the decoder circuit 1110 via a first connecting line 1115 extending from within the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connecting line 1125 extending from within the first structure 1100F to the second structure 1100S.

[0102] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1100 communicates with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 through an input / output connection wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0103] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the data storage system 1000 includes multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1100.

[0104] The processor 1210 controls the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 operates according to a predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a controller interface 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written in the memory cell transistor MCT of the semiconductor device 1100, data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. are transmitted. The host interface 1230 provides a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0105] FIG. 17 is a perspective view that illustrates a schematic diagram of a data storage system including a semiconductor device according to an exemplary embodiment.

[0106] 17, a data storage system 2000 according to an exemplary embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0107] The main board 2001 includes a connector 2006 including a plurality of pins coupled to an external host. In the connector 2006, the number and arrangement of the plurality of pins vary depending on a communication interface between the data storage system 2000 and the external host. In an exemplary embodiment, the data storage system 2000 communicates with the external host through any of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the data storage system 2000 operates with power supplied from the external host via the connector 2006. The data storage system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0108] The controller 2002 records data to or reads data from the semiconductor package 2003 to improve the operating speed of the data storage system 2000 .

[0109] DRAM 2004 is a buffer memory for mitigating the speed difference between semiconductor package 2003, which is a data storage space, and an external host. DRAM 2004 included in data storage system 2000 also operates as a kind of cache memory, providing space for temporarily storing data in a control operation for semiconductor package 2003. When data storage system 2000 includes DRAM 2004, controller 2002 further includes a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0110] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b are each a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, a connection structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0111] The package substrate 2100 is a printed circuit board including package top pads 2130. Each semiconductor chip 2200 includes an I / O pad 2210. The I / O pad 2210 corresponds to the I / O pad 1101 of FIG. 16. Each of the semiconductor chips 2200 includes a gate stack structure 3210 and a memory channel structure 3220. Each of the semiconductor chips 2200 includes the semiconductor device described above with reference to FIGS. 1 to 15.

[0112] In an exemplary embodiment, the connection structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Thus, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the connection structure 2400 in the form of a bonding wire.

[0113] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0114] Fig. 18 is a cross-sectional view showing a schematic diagram of a semiconductor package according to an exemplary embodiment. Fig. 18 illustrates an exemplary embodiment of the semiconductor package 2003 of Fig. 17, and conceptually shows a region of the semiconductor package 2003 of Fig. 17 cut along the cutting line III-III'.

[0115] 18, in the semiconductor package 2003, a package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, a package upper pad 2130 (see FIG. 17) disposed on an upper surface of the package substrate body 2120, a package lower pad 2125 disposed on a lower surface of the package substrate body 2120 or exposed through the lower surface, and an internal wiring 2135 electrically connecting the package upper pad 2130 and the package lower pad 2125 inside the package substrate body 2120. The package upper pad 2130 is electrically connected to a connection structure 2400. The lower pad 2125 is connected to a wiring pattern 2005 of a main substrate 2001 of a data storage system 2000 through a conductive connection part 2800 as shown in FIG. 17.

[0116] Each of the semiconductor chips 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 on the common source line 3205, a memory channel structure 3220 and an isolation region penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the memory channel structure 3220, and a gate contact plug 3235 electrically connected to a word line (WL, see FIG. 16) of the gate stack structure 3210. As described above with reference to FIGS. 1 to 15, each of the semiconductor chips 2200 includes a capacitor structure 200 vertically overlapping the device isolation region 209 on the device isolation region 209.

[0117] Each of the semiconductor chips 2200 includes a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 is disposed outside the gate stack structure 3210 and is further disposed to penetrate the gate stack structure 3210. Each of the semiconductor chips 2200 further includes an I / O pad 2210 (see FIG. 17 ) electrically connected to the peripheral wiring 3110 of the first structure 3100.

[0118] The present invention is not limited to the above-described embodiments and drawings. Therefore, within the scope of the technical idea of ​​the present invention, various substitutions, modifications, and combinations of the embodiments are possible by those having ordinary skill in the art, and these also belong to the scope of the present invention. [Explanation of symbols]

[0119] CH Channel structure 20 Memory Cell Array 30 Peripheral circuits 100 Semiconductor device 101 Plate Layer 102, 104 First and second horizontal conductive layers 111 First horizontal insulating layer 112 Second horizontal insulating layer 121 Substrate insulation layer 130 Gate electrode 140 Interlayer insulation layer 160 Contact insulation layer 170 Contact plug 180 Second bonding structure 190 Cell area insulating layer 200 Capacitor Structure 201 Substrate 205 Impurity region 209 Element isolation area 210 First electrode structure 220 Second electrode structure 221 Circuit Elements 290 Peripheral area insulating layer

Claims

1. a first semiconductor structure including: a substrate; an active region in the substrate; a circuit element on the substrate; an isolation region defining the active region; impurity regions disposed in the active region on both sides of the circuit element; a circuit interconnect structure electrically connected to the circuit element; and a capacitor structure disposed on the isolation region and vertically overlapping the isolation region; a second semiconductor structure including: a plate layer disposed on the first semiconductor structure; gate electrodes stacked on the plate layer at a distance from each other along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes extending along the first direction via the gate electrodes; and an upper wiring structure electrically connected to the channel structure; The capacitor structure includes: a first electrode structure extending in the first direction and including a first capacitor electrode stacked along the first direction, a second electrode structure including a second capacitor electrode stacked along the first direction, and a first insulating structure disposed between the first electrode structure and the second electrode structure, the first capacitor electrodes and the second capacitor electrodes are alternately arranged apart from each other in a second direction parallel to an upper surface of the substrate and extend in a third direction perpendicular to the first and second directions; The semiconductor device, wherein the first capacitor electrode and the second capacitor electrode have a plate shape.

2. Each of the first electrode structure and the second electrode structure includes a first capacitor electrode and a second capacitor electrode stacked along the first direction, 2. The semiconductor device according to claim 1, wherein at least a portion of the first capacitor electrode and the second capacitor electrode extends into at least a portion of the element isolation region.

3. the first semiconductor structure further includes a stopper layer disposed on a portion of a surface of the substrate along a surface of the substrate in the isolation region; 3. The semiconductor device according to claim 2, wherein at least a portion of the first capacitor electrode and the second capacitor electrode is in contact with the stopper layer.

4. the stopper layer includes an insulating material; The semiconductor device according to claim 3 , wherein the stopper layer and the first insulating structure include different materials.

5. 3. The semiconductor device of claim 2, wherein the first capacitor electrode comprises a metallic material, and the second capacitor electrode comprises a semiconductor material.

6. The semiconductor device according to claim 2 , wherein the bottom of each of the first electrode structure and the second electrode structure is located at a lower level than the bottom of the circuit wiring structure.

7. 2. The semiconductor device of claim 1, wherein the first semiconductor structures further include dummy patterns spaced apart from each other in the second direction and the third direction and arranged in a region vertically overlapping the capacitor structure.

8. 8. The semiconductor device according to claim 7, further comprising a stopper layer disposed on a portion of the surface of the substrate and the surface of the dummy pattern along the surface of the substrate and the surface of the dummy pattern in the element isolation region.

9. the element isolation region is disposed between the dummy patterns, The semiconductor device of claim 7 , wherein at least a portion of the first electrode structure and the second electrode structure vertically overlaps the dummy pattern.

10. 8. The semiconductor device of claim 7, wherein at least a portion of the first electrode structure and the second electrode structure vertically overlapping the isolation region extends into at least a portion of the isolation region.

11. the first insulating structure includes a plurality of dielectric layers; 2. The semiconductor device according to claim 1, wherein the dielectric constant of the plurality of dielectric layers increases toward the top surface of the substrate.

12. The semiconductor device according to claim 1 , wherein the first electrode structure and the second electrode structure are disposed at the same level as the circuit wiring structure.

13. a third electrode structure extending in the first direction and stacked on the impurity region along the first direction; a fourth electrode structure extending in the first direction and stacked on the circuit element along the first direction; The semiconductor device of claim 1 , further comprising: a second insulating structure disposed between the third electrode structure and the fourth electrode structure.

14. a lower bonding structure connected to the circuit wiring structure and an upper bonding structure bonded to the lower bonding structure, the lower bonding structure includes a lower bonding via connected to the circuit wiring structure and a lower bonding pad connected to the lower bonding via, the upper bonding structure includes an upper bonding via connected to the upper wiring structure and an upper bonding pad connected to the upper bonding via, 2. The semiconductor device according to claim 1, wherein the lower bonding pad and the upper bonding pad are bonded to each other.

15. a substrate including an active region; a circuit element on the active area; an isolation region defining the active region; impurity regions disposed within the active region on either side of the circuit element; a first electrode structure disposed on the isolation region, vertically overlapping the isolation region, and extending in a first direction perpendicular to an upper surface of the substrate; a second electrode structure disposed on the isolation region, vertically overlapping the isolation region, and spaced apart from the first electrode structure in a second direction perpendicular to the first direction; an insulating structure disposed between the first electrode structure and the second electrode structure, The semiconductor device according to claim 1, wherein each of the first electrode structure and the second electrode structure extends in a third direction perpendicular to the first direction and the second direction, and has a plate shape.

16. The semiconductor device of claim 15, wherein a portion of at least one of the first electrode structure and the second electrode structure extends into at least a portion of the isolation region.

17. dummy patterns disposed apart from each other in the second direction and the third direction and disposed between the circuit elements, The semiconductor device of claim 15, wherein at least a portion of the first electrode structure and the second electrode structure vertically overlaps the dummy pattern.

18. a stopper layer disposed on a portion of the surface of the substrate along the surface of the substrate in the element isolation region; The semiconductor device according to claim 15 , wherein at least a portion of the first electrode structure and the second electrode structure contacts the stopper layer.

19. a semiconductor storage device including a substrate, an active region in the substrate, circuit elements on the substrate, an isolation region defining the active region, an interconnect structure electrically connected to the circuit elements, and a capacitor structure disposed on and vertically overlapping the isolation region, a memory cell, and an input / output pad; a controller electrically connected to the semiconductor storage device via the input / output pad and configured to control the semiconductor storage device; The capacitor structure includes: a first electrode structure extending in a first direction perpendicular to an upper surface of the substrate and including a first capacitor electrode stacked along the first direction, a second electrode structure including a second capacitor electrode stacked along the first direction, and a first insulating structure disposed between the first electrode structure and the second electrode structure, the first capacitor electrodes and the second capacitor electrodes are alternately arranged spaced apart from each other in a second direction parallel to an upper surface of the substrate and extend in a third direction perpendicular to the first and second directions, the first capacitor electrodes and the second capacitor electrodes having a plate shape.

20. 20. The data storage system of claim 19, wherein the first electrode structure and the second electrode structure are not electrically isolated from the circuit element.

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