Silicon carbide semiconductor wafer, silicon carbide semiconductor device, and method for manufacturing silicon carbide single crystal

Abstract

To suppress expansion of a BPD to an SSF.SOLUTION: In an SiC wafer forming an SiC substrate 11 formed of an n-type SiC doped with an n-type impurity, an SiC substrate 11 includes B in the concentration of at least 9.0×1016 / cm3.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a silicon carbide (hereinafter referred to as SiC) semiconductor wafer, a SiC semiconductor device, and a method for producing a SiC single crystal. [Background technology]

[0002] Due to its excellent semiconductor properties, SiC is being put to practical use as a material for various semiconductor devices such as vehicle power devices. However, SiC single crystal substrates contain wavy dislocations with dislocation lines on the (0001) plane, known as basal plane dislocations (hereinafter referred to as BPDs).

[0003] When an epitaxial film is grown on such a SiC single crystal substrate to configure a SiC semiconductor device equipped with a switching element such as a MOSFET (short for Metal Oxide Semiconductor Field Effect Transistor), a built-in diode is configured. When this SiC semiconductor device is applied to an inverter circuit or the like and the built-in diode operates in a bipolar manner due to the reflux operation during switching, there is a possibility that the BPD will expand into a Shockley stacking fault (hereinafter referred to as SSF). That is, holes passing near the BPD recombine with electrons in the n-type layer, generating large recombination energy, and the BPD expands into an SSF. Since the SSF occupies a larger area than the BPD and is a defect that is likely to degrade the electrical characteristics of the SiC semiconductor device, it is desirable to suppress the expansion of the BPD into an SSF.

[0004] Meanwhile, a technology for suppressing the expansion of BPDs into SSFs has been proposed in Patent Document 1. In this technology, when manufacturing a SiC semiconductor device in which an epitaxial film is disposed on one surface of a SiC single crystal substrate, p-type impurities are mixed in when manufacturing an ingot used to form an n-type SiC single crystal substrate. This improves the crystallinity in the SiC single crystal substrate, and the energy required for the BPDs to expand into SSFs increases, thereby suppressing the expansion of BPDs into SSFs. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-57381 Summary of the Invention [Problem to be solved by the invention]

[0006] However, although the incorporation of p-type impurities into the SiC single crystal substrate has the effect of suppressing the expansion of the BPD into the SSF, this effect is not sufficiently obtained depending on the current flowing through the built-in diode provided in the SiC semiconductor device.

[0007] An object of the present disclosure is to provide a silicon carbide semiconductor wafer, a silicon carbide semiconductor device, and a method for producing a silicon carbide single crystal, which are capable of suppressing the expansion of BPD into SSF. [Means for solving the problem]

[0008] One aspect of the present disclosure is a method for producing a semiconductor device comprising: A SiC wafer constituting a SiC substrate (11) made of n-type SiC doped with n-type impurities, The SiC substrate contains B (boron), and the B concentration in the SiC substrate is 9.0×10 16 / cm 3 This is said to be the above.

[0009] In this way, while introducing B into the n-type SiC substrate, the B concentration is limited to 9.0×10 16 / cm 3 This makes it possible to prevent the BPD from expanding into the SSF.

[0010] Another aspect of the present disclosure is a method for producing a method for manufacturing a semiconductor device comprising: A SiC substrate (11) made of n-type SiC doped with n-type impurities; an n-type low concentration layer (13) formed on the SiC substrate and having a lower n-type impurity concentration than the SiC substrate; a p-type deep layer (15) formed on the low concentration layer and having a plurality of linear portions whose longitudinal direction is in one direction in the surface direction of the substrate; an n-type JFET section (14) disposed on the low concentration layer and having a linear portion sandwiched between the deep layers; a p-type base region (17) disposed on the JFET portion and the deep layer; an n-type source region (18) formed in a surface layer portion of the base region; the trench gate structure including a gate insulating film (22) formed on a wall surface of a gate trench (21) penetrating the source region and the base region, and a gate electrode (23) formed on the gate insulating film; a source electrode (25) electrically connected to the source region and the base region; a drain electrode (26) electrically connected to the substrate; A built-in diode (40) is formed by a pn junction including the deep layer, the JFET portion, and the low concentration layer, and the current density of the current flowing when the built-in diode operates as a reflux junction is 11.6 A / mm 2 That is all. The SiC substrate contains B, and the B concentration in the SiC substrate is 9.0×10 16 / cm 3 This is said to be the above.

[0011] In this way, the current density of the current flowing when the built-in diode is in freewheeling mode is 11.6A / mm 2 For applications where the B concentration in the SiC substrate is 9.0×10 16 / cm 3 This makes it possible to prevent the BPD from expanding into the SSF.

[0012] Another aspect of the present disclosure is A method for producing an n-type SiC single crystal, comprising the steps of: Placing a seed crystal (202) for growing a SiC single crystal on one side of a pedestal (205) placed in a growth crucible (204); and supplying a pyrolyzed SiC raw material, an n-type dopant, and B to the surface of the seed crystal, thereby producing a SiC ingot (203) composed of an n-type SiC single crystal on the surface of the seed crystal, In growing the SiC ingot, the B concentration in the SiC ingot is set to 9.0×10 16 / cm 3 That is all.

[0013] In this way, when producing n-type SiC single crystals, the B concentration in the SiC ingot is 9.0 × 10 16 / cm 3 For this reason, a SiC wafer sliced ​​from a SiC ingot is used to ensure that the current density of the current flowing when the built-in diode operates in reflux mode is 11.6 A / mm 2 When a vertical MOSFET having the above structure is manufactured, it is possible to suppress the expansion of the BPD into the SSF.

[0014] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0015] [Figure 1] 1 is a perspective cross-sectional view of a SiC semiconductor device described in a first embodiment. [Diagram 2] FIG. 2 is an explanatory diagram of a current path in a SiC semiconductor device. [Figure 3A] FIG. 4 is an explanatory diagram showing the state of holes and electrons in the vicinity of a built-in diode. [Figure 3B] FIG. 1 is an explanatory diagram of defect growth caused by BPD near a built-in diode. [Figure 4] This is a binarized image of a photoluminescence (PL) image in which the degree of expansion of the SSF was confirmed by non-destructive testing using the PL method. [Diagram 5] FIG. 13 is a diagram showing the relationship between the B concentration and the area occupancy rate of SSF and the amount of warpage of a SiC wafer. [Figure 6] FIG. 13 is a diagram showing the change in hole density for each portion in the vicinity of the buffer layer when the B concentration in the SiC substrate is changed. [Figure 7] FIG. 13 is a graph showing the change in hole density at the interface between the SiC substrate and the buffer layer with respect to the B concentration. [Figure 8A] FIG. 13 is a diagram showing the relationship between the B concentration and the electrical stress at which the SSF is 3% when there is no drop in the n-type impurity concentration. [Figure 8B] FIG. 13 is a diagram showing the relationship between the B concentration and the electrical stress at which the SSF is 3% when there is a drop in the n-type impurity concentration. [Figure 9] FIG. 2 is a diagram showing the N concentration in a SiC substrate, a buffer layer, and a low-concentration layer. [Figure 10A] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. [Figure 10B] 10B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 10A. [Figure 10C] 10C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10B. [Figure 10D] 10D is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 10C. [Figure 10E] 10E is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10D. [Figure 10F] 10B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 10E. [Figure 10G] 10B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 10F. [Figure 11] FIG. 13 is a diagram showing the amount of warpage of multiple SiC wafer samples before an element formation process and after a deep layer formation process. [Figure 12] FIG. 2 is a schematic diagram showing how SiC wafers are sliced ​​from a SiC ingot. [Figure 13A] FIG. 13 is a graph showing the relationship between the B concentration and the amount of warpage in a 6-inch wafer. [Figure 13B] FIG. 13 is a graph showing the relationship between the B concentration and the amount of warpage in an 8-inch wafer. [Figure 14] FIG. 11 is a perspective cross-sectional view of a SiC semiconductor device described in a second embodiment. [Figure 15A] 15A to 15C are cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. [Figure 15B] 15B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 15A. [Figure 15C] 15C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 15B. [Figure 15D] 15D is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 15C. [Figure 15E] 15B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 15D. [Figure 15F] 15B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 15E. [Figure 16] FIG. 2 is a cross-sectional view showing the growth of a SiC ingot in a growth crucible. [Figure 17A] 1 is a graph showing the contents of various impurity elements contained in a SiC substrate. [Figure 17B] 1 is a graph showing the contents of various impurity elements contained in a raw material powder. [Figure 18A] FIG. 2 is a diagram showing the relationship between the concentration of each p-type impurity in a raw material powder and the concentration of each p-type impurity in a SiC substrate. [Figure 18B] 1 is a diagram showing the relationship between the concentration of each p-type impurity in a raw material powder, the concentration of each p-type impurity in a SiC substrate, and the ratio RP / S and the magnification factor RS / P. [Figure 19] FIG. 13 is a graph showing the change in concentration of p-type impurities when a normal crucible that has not been purified is used and a high-purity crucible that has been purified is used. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following, including other embodiments described below, the same reference numerals will be used to denote the same or equivalent parts in each embodiment.

[0017] (First embodiment) A first embodiment of the present disclosure will be described below. First, the configuration of a SiC semiconductor device according to the present embodiment will be described with reference to FIG.

[0018] [Configuration of SiC semiconductor device] The SiC semiconductor device according to this embodiment is formed with an inverted vertical MOSFET having a trench gate structure as shown in FIG. 1 as a semiconductor element. The vertical MOSFET shown in these figures is formed in a cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming a peripheral breakdown voltage structure so as to surround the cell region, but only the vertical MOSFET is shown here. In the following, directions perpendicular to each other as shown in FIG. 1 will be described as the X direction, the Y direction, and the Z direction. Specifically, the width direction of the vertical MOSFET is the X direction, the depth direction of the vertical MOSFET intersecting the X direction is the Y direction, and the thickness direction or depth direction of the vertical MOSFET, i.e., the normal direction to the XY plane, is the Z direction.

[0019] As shown in FIG. 1, the SiC semiconductor device has n-type impurities doped therein. + A vertical SiC substrate 11 is used. The SiC substrate 11 constitutes a drain region of a vertical MOSFET 30. The SiC substrate 11 has an off angle of 0 to 8° with respect to the (0001) Si plane, and has an n-type impurity concentration of 1.0×10 19 / cm 3 The thickness is specified as 350 μm or 500 μm. The 350 μm thickness means that the thickness is in the range of 325 to 375 μm, and the 500 μm thickness means that the thickness is in the range of 475 to 525 μm.

[0020] Although the SiC substrate 11 is of n-type, it contains at least B (boron) as a p-type impurity. The reason for this will be described later, but the forward current flowing through the built-in diode 40 of the vertical MOSFET 30 shown in the equivalent circuit of FIG. 2 is 600 A or more, and the current density is 11.6 A / mm 2 If you are assuming the above, set the B concentration to 9×10 16 / cm 3 In addition, the forward current flowing through the built-in diode 40 is set to 800 A or more, and the current density is set to 15.0 A / mm 2 If this is assumed, the B concentration should be 1.5×10 17 / cm 3 The forward current assumed to flow through the built-in diode 40 refers to a current that can flow as a reflux current during reflux operation when the SiC semiconductor device is applied to an inverter circuit or the like, or in other words, refers to the magnitude of the current stress applied to the built-in diode 40. Hereinafter, the forward current assumed to flow through the built-in diode 40 is also referred to as the current stress.

[0021] Preferably, when the thickness of the SiC substrate 11 is 350 μm, the B concentration is 1.75×10 17 / cm 3 In the following, if the specification is 500 μm, the B concentration is 7.2 × 10 17 / cm 3 It would be better to use the following.

[0022] On the main surface of the SiC substrate 11, a n-type semiconductor layer made of SiC that constitutes a part of the drift layer is formed. - A n-type buffer layer 12 is formed on the surface of the SiC substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the SiC substrate 11, and has an n-type impurity concentration between that of the SiC substrate 11 and a low concentration layer 13 described later. The buffer layer 12 has a thickness of, for example, about 1 μm and an n-type impurity concentration of 6.0×10 17 ~1.5×10 18 / cm 3 On the buffer layer 12, a n-type SiC layer is formed, which is a part of a drift layer having a lower concentration than the SiC substrate 11. -A low concentration layer 13 of the mold is formed.

[0023] In the cell region, an n-type JFET section 14 constituting a part of a drift layer made of SiC is formed on the low-concentration layer 13. The low-concentration layer 13 is connected to the JFET section 14 on the side opposite to the SiC substrate 11. Furthermore, in addition to the JFET section 14, a p-type deep layer 15 is formed on the low-concentration layer 13.

[0024] The JFET section 14 and the deep layer 15 constitute a saturation current suppression layer, and are both extended in the X direction as the longitudinal direction, and are arranged alternately and repeatedly in the Y direction. That is, when viewed from the normal direction to the main surface of the SiC substrate 11, at least a part of the JFET section 14 and the deep layer 15 are each formed into a plurality of lines, in other words, stripes, and are arranged alternately.

[0025] In this embodiment, the JFET section 14 is formed below the deep layer 15. Therefore, the striped portions of the JFET section 14 are connected below the deep layer 15, but each striped portion is disposed between a plurality of deep layers 15.

[0026] The deep layer 15 is composed of an ion-implanted layer formed by ion-implanting p-type impurities. As described above, the deep layer 15 is striped, and each line-shaped portion of the striped deep layer 15 has a constant width and is disposed at equal intervals. The p-type impurity concentration is constant in the depth direction, for example, 5×10 17 / cm 3 Moreover, the deep layer 15 has a thickness, which is the dimension in the Z direction from the top surface to the bottom, of 1 μm or less.

[0027] Furthermore, an n-type current spreading layer 16 constituting a part of the drift layer made of SiC is formed on the JFET section 14 and the deep layer 15. The current spreading layer 16 is a layer that allows the current flowing through the channel of the vertical MOSFET 30 to be diffused in the Y direction, and is formed in contact with the tip side in the depth direction of the gate trench 21 described later, and has, for example, a higher n-type impurity concentration than the low concentration layer 13. However, it is not essential that the current spreading layer 16 has a higher impurity concentration than the low concentration layer 13, and may have, for example, the same impurity concentration as the low concentration layer 13.

[0028] In this embodiment, the drift layer is composed of the buffer layer 12, the low concentration layer 13, the JFET section 14, and the current spreading layer 16. However, the configuration of the drift layer is arbitrary, and for example, the drift layer may have a structure without a buffer layer.

[0029] A p-type base region 17 made of SiC is formed on the current spreading layer 16. In addition, a n-type base region 17 made of SiC is formed on the base region 17. + A p-type source region 18 is formed in the base region 17. The base region 17 has a lower p-type impurity concentration than the deep layer 15. The source region 18 has a higher n-type impurity concentration than the current spreading layer 16.

[0030] In addition, the p-type impurity concentration is made higher than that of the base region 17 so that the p-type impurity concentration is higher from the surface of the source region 18 to the base region 17. + In the present embodiment, the contact region 19 is configured in a line shape with the Y direction as the longitudinal direction. Furthermore, below the contact region 19, a p-type coupling layer 20 that connects the base region 17 and the deep layer 15 is formed. The coupling layer 20 is formed in a line shape with the Y direction as the longitudinal direction together with the contact region 19, and is disposed on both sides of the current spreading layer 16.

[0031] The contact region 19 and the coupling layer 20 play a role in coupling the deep layer 15 and the base region 17 to a source electrode 25 described later in order to fix the deep layer 15 and the base region 17 to the source potential.

[0032] The contact regions 19 and the coupling layers 20 may be formed at any interval, but in this embodiment, they are formed on both sides of a trench gate structure, which will be described later. The width of the contact regions 19 and the coupling layers 20 may be any width, but in this embodiment, they are set to be equal to or smaller than the interval between adjacent trench gate structures.

[0033] Furthermore, a gate trench 21 is formed with a predetermined width and a predetermined depth so as to penetrate the source region 18 and the base region 17 and reach the current spreading layer 16. The above-mentioned base region 17 and source region 18 are formed so as to contact the side surface of this gate trench 21, and the contact region 19 is arranged so as to be away from the gate trench 21. The gate trench 21 is formed in a line-shaped layout with the X direction as the width direction, the direction intersecting the longitudinal direction of the JFET section 14 and the deep layer 15, the Y direction as the longitudinal direction here, and the Z direction as the depth direction. As shown in FIG. 1, the gate trench 21 is formed in a stripe shape with a plurality of gate trenches 21 arranged at equal intervals in the X direction, and the base region 17, the source region 18, the contact region 19, and the coupling layer 20 are arranged between each of them.

[0034] A portion of the base region 17 located on the side of the gate trench 21 serves as a channel region connecting the source region 18 and the current spreading layer 16 when the vertical MOSFET 30 is in operation, and the inner wall surface of the gate trench 21 including the channel region is covered with a gate insulating film 22. A gate electrode 23 made of doped Poly-Si is formed on the surface of the gate insulating film 22, and the gate insulating film 22 and the gate electrode 23 are disposed in the gate trench 21 to form a trench gate structure. Furthermore, an interlayer insulating film 24 is formed so as to cover the gate electrode 23.

[0035] As shown in FIG. 1, a source electrode 25 and the like are formed on the surface of the source region 18 and the surface of the gate electrode 23 via an interlayer insulating film 24. The source electrode 25 is made of a plurality of metals, for example, Ni / Al. Among the plurality of metals, at least the n-type SiC, specifically the part in contact with the source region 18 and the gate electrode 23 in the case of n-type doping, is made of a metal capable of ohmic contact with the n-type SiC. Among the plurality of metals, at least the p-type SiC, specifically the part in contact with the contact region 19 is made of a metal capable of ohmic contact with the p-type SiC. The source electrode 25 is electrically insulated from the SiC part by being formed on the interlayer insulating film 24, but is electrically in contact with the source region 18 and the contact region 19 through a contact hole 24a formed in the interlayer insulating film 24.

[0036] Meanwhile, a drain electrode 26 electrically connected to the SiC substrate 11 is formed on the back surface side of the SiC substrate 11. With this structure, a vertical MOSFET 30 of an n-channel type with an inversion type trench gate structure is formed. A cell region is formed by arranging a plurality of such vertical MOSFETs 30. Although not shown, a peripheral breakdown withstand structure such as a guard ring is formed so as to surround the periphery of the cell region, thereby forming a SiC semiconductor device.

[0037] In the SiC semiconductor device having such a configuration, a built-in diode 40 is formed in the vertical MOSFET 30 by pn junctions between the low concentration layer 13, the JFET portion 14, etc. and the deep layer 15, the coupling layer 20, etc.

[0038] The above is an example of the basic configuration of the SiC semiconductor device according to this embodiment. As will be described later, this SiC semiconductor device is used, for example, in an inverter circuit for driving a three-phase motor that uses the vertical MOSFET 30 as a switching element.

[0039] [Defective growth caused by BPD] As described above, the SiC semiconductor device has a structure in which the vertical MOSFET 30 with a trench gate structure and the built-in diode 40 formed of a pn junction are provided in the cell region. BPDs exist in the drift layer including the SiC substrate 11 and the buffer layer 12, and defects due to these BPDs may occur in the SiC semiconductor device.

[0040] As shown in FIG. 2, an equivalent circuit of the SiC semiconductor device is shown as a circuit configuration having a MOSFET 30 and a built-in diode 40. When the vertical MOSFET 30 is on, an on-current I flows from the drain electrode 26 to the source electrode 25. ON 2 correspond to the source electrode 25, the drain electrode 26, and the gate electrode 23, respectively. Specifically, when a predetermined voltage, for example, 20 V, is applied to the gate electrode 23, a channel region is formed in the surface of the base region 17 that contacts the gate trench 21, and an on-current I ON flows.

[0041] Thereafter, when the SiC semiconductor device is turned off, a reverse bias is applied and the device is in a reverse conducting state, so that the built-in diode 40 functions as a freewheeling diode, and a freewheeling current I OFF flows. At this time, as shown in FIG. 3A, holes that have diffused from the p-type layer side to the n-type layer side of the pn junction that constitutes the built-in diode 40 recombine with electrons in the n-type layer. Because the recombination energy between these holes and electrons is large, the BPD50 expands and an SSF60 is generated, as shown in FIG. 3B. The SSF60 expands as the current stress on the built-in diode 40 accumulates. Since the SSF60 occupies a larger area than the BPD50, the on-current I ON and the reflux current I OFF In addition, since the SSF 60 expands in response to the stress of current flow to the built-in diode 40, the electrical characteristics after operation are degraded compared to the electrical characteristics immediately after manufacture, that is, before the SSF 60 is generated.

[0042] For example, a reverse bias is applied to the SiC semiconductor device of this embodiment to generate a reflux current I OFF Current was passed through the SSF60, and the state of the SSF60 after the current was passed was confirmed. Figure 4 is a binarized PL image showing the degree of expansion of the SSF60 confirmed by non-destructive testing using the PL method. The multiple white linear lines running vertically in the figure are the SSF60. As shown in this figure, it can be seen that the SSF60 expands in the active region of the cell region of the SiC semiconductor device, that is, in the region where the source electrode 25 is located and where current is passed. This expansion of the SSF60, which occupies a large area, increases the on-current I ON and the reflux current I OFF This impedes the formation of the conductive layer, resulting in a deterioration of the electrical characteristics.

[0043] In order to suppress the deterioration of the electrical characteristics, it is necessary to provide a SiC semiconductor device having excellent diode current degradation characteristics, which can suppress the expansion of BPD 50 to SSF 60 even when stress is accumulated on built-in diode 40.

[0044] In particular, when a SiC semiconductor device is applied to an in-vehicle power card, the amount of current flowing through one chip becomes large, and it is unavoidable that the built-in diode 40 turns on even if current is passed through the channel region. Also, even when a large current is used in a freewheel mode in which a freewheel current flows, it is important to provide a SiC semiconductor device with excellent diode current degradation characteristics so as to suppress hole injection and prevent the SSF60 from expanding.

[0045] [B concentration in SiC substrate] As shown in the above-mentioned Patent Document 1, by doping an n-type SiC single crystal substrate with a p-type impurity, it is possible to obtain the effect of suppressing the expansion of BPD50 into SSF60. However, it has been confirmed that the effect of suppressing the expansion of BPD50 into SSF60 cannot be obtained sufficiently by simply doping with a p-type impurity. +It was found that the effect of suppressing the expansion of the required BPD50 to the SSF60 can be obtained by introducing B, which is a p-type impurity, into the SiC substrate 11 and adjusting the B concentration to a predetermined concentration or more. Furthermore, it was found that the B concentration required to obtain this effect varies depending on the magnitude of the return current flowing in the forward direction of the built-in diode 40 when the SiC semiconductor device is applied to an inverter or the like, and the required B concentration increases as the return current increases.

[0046] Specifically, assuming that the SiC semiconductor device is applied to an inverter and that the current stress is 600 A or more and 800 A or more, a reverse bias was applied to the SiC semiconductor device and a forward current was passed through the built-in diode 40. Then, the B concentration in the SiC substrate 11 was changed to examine the change in the SSF area occupancy rate (%) after current passage, and the results shown in FIG. 5 were obtained. A current stress of 600 A or more is when the current density, calculated by dividing this current value by the area of ​​the active region through which current actually flows, of the cell region in which the vertical MOSFET 30 is formed, is 11.6 A / mm 2 In the experiment, the actual current flow was 656 A, assuming a current stress of 600 A or more. In this case, the current density was 12.66 A / mm 2 In addition, the current density of the current flowing through the active area is 14.6 A / mm 2 In the experiment, the actual current flow was 900A, assuming a current stress of 800A or more. In this case, the current density was 16.41A / mm 2 It was.

[0047] As shown in this figure, in both cases where the electrical stress is 600 A or more and 800 A or more, the SSF area occupancy rate is reduced by introducing B into the SiC substrate 11. 16 / cm 3If the SSF area occupancy is less than this, the SSF area occupancy rate is high. This indicates that the effect of suppressing the expansion of BPD50 to SSF60 is not sufficient. As a result, excellent diode conduction degradation characteristics cannot be obtained.

[0048] In contrast, when the return current is 600 A or more, in this case 656 A, the B concentration is at least 9.0 × 10 16 / cm 3 When the SSF area occupancy rate is 800A or more, the SSF area occupancy rate can be reduced to 3% or less. In addition, when the SSF area occupancy rate is 800A or more, even in the case of 900A, the B concentration is at least 1.5×10 17 / cm 3 Above this, the SSF area occupancy rate can be reduced to 3% or less, which means that the effect of suppressing the expansion of BPD50 to SSF60 can be sufficiently obtained.

[0049] From this result, when the SiC semiconductor device is applied in a form in which the current stress of the built-in diode 40 is 600 A or more in order to ensure the diode current degradation characteristics, the B concentration in the SiC substrate 11 should be set to 9.0×10 16 / cm 3 In addition, when the SiC semiconductor device is applied in a form in which the current stress of the built-in diode 40 is 800 A or more, the B concentration in the SiC substrate 11 is set to 1.5×10 17 / cm 3 This makes it possible to obtain a SiC semiconductor device that has excellent diode current degradation characteristics. Note that the greater the current stress, the higher the B concentration in the SiC substrate 11 required to obtain excellent diode current degradation characteristics. Here, the actual current that flowed in the experiment assuming a 600 A specification was 656 A, and the required B concentration at that time was 9.0×10 16 / cm 3 However, in the case of 600A, the required B concentration is less than that, so it is at least 9.0 × 10 16 / cm 3 Similarly, if the actual current flowing in an experiment assuming a specification of 800A is 900A, the required B concentration is 1.5×10 17 / cm 3 However, in the case of 800A, the required B concentration is less than that, so it is at least 1.5 × 10 17 / cm 3 Anything above that is good.

[0050] On the other hand, the SSF area occupancy rate decreases as the B concentration in the SiC substrate 11 increases. However, it has been found that if the B concentration in the SiC substrate 11 is made too high, problems occur when the SiC substrate 11 is in a wafer state.

[0051] The SiC substrate 11 is + The SiC semiconductor device is constructed by dicing a vertical MOSFET 30 and the like into chip units. Specifically, an element formation process is performed on the SiC wafer to form vertical MOSFETs 30 and the like, and then the SiC semiconductor device is constructed by dicing into chip units. The part that was the SiC wafer is called the SiC substrate 11.

[0052] SiC wafers are wafers of a specified number of inches, for example, 6-inch or 8-inch wafers, and are transported to various devices such as epitaxial growth devices and ion implantation devices for device formation processes. Depending on the amount of warping in the SiC wafer, the vacuum chuck of the device may not be able to hold the SiC wafer, or the SiC wafer may move from the desired transport position during transport, making it difficult to carry out the device formation process. For this reason, it is necessary to keep the amount of warping in the SiC wafer within a specified range.

[0053] However, when the B concentration in the SiC substrate 11 is increased, the amount of warping of the SiC wafer increases, and it becomes impossible to keep the amount within the specified range, so that the device formation process cannot be performed satisfactorily. The relationship between the amount of warping and the B concentration of the SiC wafer was examined by conducting an experiment using a 6-inch SiC wafer with a thickness of 350 μm. The results are shown in FIG.

[0054] As shown in this figure, the higher the B concentration in the SiC substrate 11, the greater the amount of warpage. To facilitate smooth transportation during the device formation process and smooth adsorption of the SiC wafer to a vacuum chuck, it is preferable that the amount of warpage is 300 μm or less. To achieve this, when the SiC wafer is a 6-inch wafer with a diameter of 350 μm, the B concentration should be set to 1.75×10 as shown in FIG. 5 and FIG. 13A described later. 17 / cm 3 For this reason, when a 6-inch wafer with a thickness of 350 μm is used as the SiC wafer, the B concentration in the SiC substrate 11 is preferably set to 1.75×10 17 / cm 3 The following is the case.

[0055] In addition, when the SiC wafer was an 8-inch wafer, similar experiments were performed for the cases where the thickness was 350 μm and 500 μm. As a result, as shown in FIG. 13B described later, the B concentration in the SiC substrate 11 was 1.8×10 17 / cm 3 It is preferable to set it to less than 7.2×10 for a 500μm specification. 17 / cm 3 It has been confirmed that the following is preferable.

[0056] That is, regardless of whether the SiC wafer is a 6-inch wafer or an 8-inch wafer, when the thickness is 350 μm, the B concentration in the SiC substrate 11 is set to 1.75×10 17 / cm 3 If the SiC wafer is an 8-inch wafer with a thickness of 500 μm, the B concentration in the SiC substrate 11 is set to 7.2×10 17 / cm 3 The amount of warpage can be suppressed if the following is satisfied. Therefore, the B concentration in the SiC substrate 11 is set so as to satisfy these requirements.

[0057] The "warpage amount" here means the amount of warpage that occurs during the element formation process. The "warpage amount" is calculated as the difference in height between the highest and lowest points on one side of the SiC wafer when the SiC wafer is placed on a flat surface. Usually, the SiC wafer is not completely flat, and has some warpage even at the initial stage before the element formation process is performed. The SiC wafer during transportation is subjected to not only the warpage that occurs during the element formation process, but also the initial warpage of the SiC wafer. However, it is difficult to completely eliminate the initial warpage, and even if the warpage can be reduced, it may occur in a range of about 200 μm at the most. For this reason, it is necessary to adjust the warpage amount to a level that does not interfere with the execution of the element formation process even if the initial warpage is added. The B concentration in the SiC substrate 11 is specified so that the warpage amount is within the range that does not interfere with the execution of the element formation process.

[0058] In addition, when the built-in diode 40 is operated as a bipolar diode by the reflux operation, the hole density at the interface between the SiC substrate 11 and the buffer layer 12 is set to 1.2×10 16 / cm 3 It has been confirmed that hole injection into the SiC substrate 11 can be suppressed if the B concentration in the SiC substrate 11 is set within the above range as in this embodiment. 16 / cm 3 It was also possible to meet the condition of keeping the noise level below 0.05%.

[0059] In a simulation, we confirmed the change in hole density in each part when the current stress of the built-in diode is set to 600 A or more and a trap site is formed in the SiC substrate 11 by an acceptor assumed to be B. Specifically, when the B concentration in the SiC substrate 11 is set to 1.0×10 15 / cm 3 , 1.0×10 17 / cm 3 , 1.0×10 19 / cm 3The change in hole density for each portion near the buffer layer 12 was investigated. FIG. 6 shows the results. FIG. 7 is a linear approximation diagram of the hole density at the interface between the SiC substrate 11 and the buffer layer 12 for each B concentration used in the simulation. The measurement conditions were a gate voltage Vg=3.5V, a source-drain current Isd=470A, a gate-source voltage Vgs=-3.5V, and a temperature Tj=175°C.

[0060] As shown in FIG. 6 and FIG. 7, the B concentration in the SiC substrate 11 is set to 1.0×10 15 / cm 3 In this case, the hole density is 1.8×10 16 / cm 3 However, when the B concentration in the SiC substrate 11 was increased to 1.0×10 17 / cm 3 In this case, the hole density is 1.1×10 16 / cm 3 The B concentration is 1.0×10 19 / cm 3 In this case, the hole density is 2.0×10 15 / cm 3 As shown in Figure 7, linear approximation shows that the B concentration is approximately 7.0 × 10 16 / cm 3 When the hole density is 1.2×10 16 / cm 3 It became.

[0061] Therefore, when the current stress of the built-in diode 40 is set to 600 A or more, the B concentration in the SiC substrate 11 is set to 7.0×10 16 / cm 3 or more, it is possible to suppress the hole current from flowing to the buffer layer 12 side. In this embodiment, when the current stress of the built-in diode 40 is set to 600 A or more, the B concentration in the SiC substrate 11 is set to 9.0×10 16 / cm 3 Therefore, the hole density is set to 1.2×10 16 / cm 3Since the hole current can be prevented from flowing to the buffer layer 12 side, it is possible to prevent the BPDs 50 in the SiC substrate 11 from expanding to the SSFs 60.

[0062] A similar simulation was also performed when the current stress of the built-in diode 40 was set to 800 A or more. In this case, the B concentration was set to 1.5×10 17 / cm 3 If the hole density is set to 1.2×10 16 / cm 3 Therefore, in this case as well, it is possible to suppress the expansion of the BPDs 50 in the SiC substrate 11 to the SSFs 60, similarly to the above.

[0063] As described above, in this embodiment, when the current stress of the built-in diode 40 is set to 600 A or more, the B concentration in the SiC substrate 11 is set to 9.0×10 16 / cm 3 However, 7.0×10 16 / cm 3 If the current stress of the built-in diode 40 is set to 800 A or more, the above effect can be obtained. 17 / cm 3 The above effects can be obtained if the forward current passing through the built-in diode 40 is 12.66 A / mm or more. These are expressed as the B concentration in the SiC substrate 11 for two modes, ie, the magnitude of the current stress of 600 A or more and 800 A or more, and can be quantified as the B concentration relative to the magnitude of the current stress. As shown in FIG. 8A, when the current stress is 12.66 A / mm 2 In the case of B concentration 7.0×10 16 / cm 3 The current stress is 16.41A / mm 2 In the case of B concentration of 1.5×10 17 / cm 3A straight line L1 can be drawn connecting the plots of these two points. This straight line L1 is the boundary line where the SSF area occupancy rate becomes 3% after the application of electrical stress. Therefore, by setting the B concentration in the SiC substrate 11 for the expected electrical stress so that the relationship between the B concentration in the SiC substrate 11 and the magnitude of the electrical stress is in the region to the right of the straight line L1, it is possible to suppress the expansion of BPD50 to SSF60.

[0064] It is possible to suppress the expansion of BPD50 to SSF60 by adjusting the B concentration in the SiC substrate 11, but it has been confirmed that the n-type impurity concentration in the buffer layer 12 can also have an effect. Specifically, as shown by the dashed line La in Fig. 9, the concentration of N doped as an n-type impurity is gradually decreased depending on the location from the SiC substrate 11, to the buffer layer 12, to the low concentration layer 13. For the buffer layer 12, the n-type impurity concentration is 6.0 x 10 17 ~1.5×10 18 / cm 3 The concentration profile is set to a value smaller than the concentration distribution in the thickness direction. For example, 1.0×10 18 / cm 3 The target value is ±0.5×10 18 / cm 3 However, as shown by the solid line Lb, the n-type impurity concentration of the buffer layer 12 on the SiC substrate 11 side drops to 6.0×10 17 / cm 3 In this case, the ratio of BPD50 expanding into SSF60 may be higher than in the case of the concentration profile of the dashed line La. For this reason, it is preferable to keep the n-type impurity concentration of the buffer layer 12 within a concentration range of ±50% of the target value and to prevent a drop in the n-type impurity concentration. Although it is preferable to prevent a drop, even if a drop does occur, it is possible to deal with this by defining a boundary line at which the SSF area occupancy rate becomes 3% after applying an electrical stress. For example, when the electrical stress is 11.6 A / mm 2 In this case, the B concentration is 9×10 16 / cm 3It was confirmed that it is desirable for the electrical stress to be 16.0A / mm 2 If the B concentration is 1.5×10 17 / cm 3 In this case, as shown in FIG. 8B, the current stress is 11.6 A / mm 2 B concentration 9.0 x 10 16 / cm 3 The electrical stress is 16.0A / mm 2 In the case of B concentration of 1.5×10 17 / cm 3 A straight line L2 can be drawn connecting the plots of these two points. This straight line L2 can be used as the boundary line at which the SSF area occupancy rate becomes 3% after applying electrical stress.

[0065] [Manufacturing method of SiC semiconductor device] Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described with reference to Figures 10A to 10G, which are cross-sectional perspective views showing a portion corresponding to Figure 1 during the manufacturing process.

[0066] [Step shown in FIG. 10A] First, n + In the SiC wafer to be prepared for forming the SiC substrate 11, the B concentration is set to 9.0×10 16 / cm 3 If the thickness is 800A or more, the B concentration is 1.5×10 17 / cm 3 In addition, for the SiC wafer to be prepared, if the thickness is 350 μm, the B concentration is set to 1.75 × 10 17 / cm 3 If the thickness is 500 μm, the B concentration is preferably 7.2×10 or less, taking into account the amount of warping. 17 / cm 3 It is preferable to set it as follows.

[0067] Then, an epitaxial film is grown on the surface of the SiC substrate 11 to form a buffer layer 12 and a low concentration layer 13 made of SiC. Next, a mask (not shown) is formed on the surface of the low concentration layer 13, and the mask is patterned by photolithography or the like so that the region where the JFET section 14 is to be formed is opened. Specifically, the mask is patterned so that only the cell region is opened. Then, n-type impurities such as N or P are ion-implanted from above the mask and heat treatment is performed to form the JFET section 14. Thereafter, the mask is removed. As the mask, for example, an LTO (Low Temperature Oxide) film or the like is used. In this embodiment, a mask is also used in the process described later, and for each mask, for example, an LTO film or the like is used.

[0068] [Step shown in FIG. 10B] A mask 31 is formed and patterned by photolithography or the like so that the mask 31 has an opening in a region where the deep layer 15 is to be formed. Then, p-type impurities such as Al are ion-implanted from above the mask 31 and heat treatment is performed to form the deep layer 15.

[0069] [Step shown in FIG. 10C] A current spreading layer 16 made of SiC is epitaxially grown on the low concentration layer 13, the JFET section 14, and the deep layer 15. In this way, a drift layer is formed by the buffer layer 12, the low concentration layer 13, the JFET section 14, and the current spreading layer 16.

[0070] Next, a mask (not shown) is formed, and the mask is patterned by photolithography or the like so that an area where the coupling layer 20 is to be formed is opened. Then, p-type impurities such as Al are ion-implanted from above the mask and heat-treated to form the coupling layer 20. At this time, the coupling layer 20 is extended in a direction intersecting the extension direction of the deep layer 15. Therefore, even if there is some positional deviation when the coupling layer 20 is formed, it is possible to suppress the occurrence of a defect in which the deep layer 15 and the coupling layer 20 are not connected.

[0071] [Step shown in FIG. 10D] A base region 17 is formed by epitaxially growing a p-type impurity layer on the current spreading layer 16 and the coupling layer 20. Subsequently, a source region 18 is formed on the base region 17 by epitaxially growing an n-type impurity layer.

[0072] [Step shown in FIG. 10E] A mask (not shown) is formed, and the mask is patterned by photolithography or the like so that an opening is formed in a region where the contact region 19 is to be formed. Furthermore, p-type impurities such as Al are ion-implanted from above the mask and heat-treated, thereby forming the contact region 19.

[0073] [Step shown in FIG. 10F] After forming a mask (not shown), the mask is patterned so as to open an area where the gate trench 21 is to be formed. Then, anisotropic etching is performed, and if necessary, isotropic etching or sacrificial layer oxidation is performed to form the gate trench 21.

[0074] [Step shown in FIG. 10G] A gate insulating film 22 is formed by thermal oxidation or CVD (chemical vapor deposition) in a location including inside the gate trench 21. Next, a polysilicon layer doped with n-type impurities is formed on the surface of the gate insulating film 22, and then an etch-back process or the like is performed so that the gate insulating film 22 and the gate electrode 23 remain in the gate trench 21. This completes the trench gate structure.

[0075] Although not shown, subsequent steps include forming an interlayer insulating film 24, forming a contact hole 24a, forming a source electrode 25 and a gate wiring, and forming a drain electrode 26 on the back surface side of the SiC substrate 11. In this manner, the SiC semiconductor device of this embodiment is manufactured.

[0076] A vertical device such as a SiC power MOSFET can create a high-field resistant device with a short vertical distance, that is, a distance in the Z-axis direction, which is the thickness, compared to a Si device. In addition, in SiC, impurities do not diffuse like in Si, so there is a tendency to increase the dose of ion implantation when forming an impurity layer to increase the impurity concentration. In addition, in order to improve the withstand voltage of the gate insulating film 22, it is necessary to deepen the ion implantation depth for forming the deep layer 15, and ion implantation processing is performed with high acceleration energy. For example, in the ion implantation process of the deep layer 15 described above, ions are implanted to a relatively shallow position of 1 μm or less, so high acceleration ion implantation is performed with high ion implantation energy, even though it is 1 MeV or less.

[0077] When an ion implantation process is performed with a high impurity concentration and a deep implantation depth, there is a tendency for significant warping to occur in the SiC wafer that constitutes the SiC substrate 11. However, as a result of careful investigation, it was found that the amount of warping itself does not depend on the impurity concentration or implantation depth in the ion implantation, but on the B concentration in the SiC wafer, that is, the amount of B that was mixed in during the manufacture of the SiC ingot.

[0078] FIG. 11 shows the results of measuring the amount of warpage of a plurality of SiC wafer samples before the element formation process and after the deep layer 15 formation process. The horizontal axis of FIG. 11 shows the sample number, and the first English notation A to J indicates the ingot number, and the next numbers 1 to 15 indicate the order of the cut SiC wafers. The same ingot number means that the SiC wafers are cut from the same SiC ingot. For example, A-1 indicates the "first" SiC wafer cut from the SiC ingot numbered "A". The order of the cut SiC wafers indicates the number when they are cut in order from the tip side of the SiC ingot. For example, assume that the SiC ingot 100 shown in FIG. 12 is obtained. In this case, the SiC wafers 102 are cut in order from the growth surface 101 side of the SiC ingot 100 toward the seed crystal 110 side, and the order of the cut SiC wafers 102 is represented by numbers.

[0079] In the regions R1 and R2 enclosed by the dashed lines in Fig. 11, when SiC wafers 102 obtained from the same SiC ingot 100 are compared, the warpage amounts are similar before the element formation process and also after the deep layer 15 formation process. However, when the SiC wafers 102 in the region R1 and the SiC wafers 102 in the region R2 are compared, the warpage amounts are similar after the deep layer 15 formation process, even though the warpage amounts are similar before the element formation process. This is due to the B concentration in the SiC wafers 102. Since the B concentration is similar in the same SiC ingot 100, the warpage amounts after the deep layer 15 formation process are similar, but if the B concentration is different, the warpage amounts after the deep layer 15 formation process will not be similar.

[0080] Thus, it is found that the amount of warpage of SiC wafer 102 during the device formation process depends on the B concentration in SiC wafer 102, that is, the amount of B contained in SiC ingot 100 during the manufacture of SiC ingot 100. Therefore, in order to control the amount of warpage, it is necessary to adjust the B concentration in the SiC wafer constituting SiC substrate 11 in advance.

[0081] When the relationship between the amount of warpage and the B concentration in the SiC substrate 11 was examined, the results shown in FIG. 13A were obtained for 6-inch wafers, and the results shown in FIG. 13B were obtained for 8-inch wafers. For 6-inch wafers, the case where the thickness was 350 μm was examined. For 8-inch wafers, the cases where the thickness was 350 μm and 500 μm were examined. This relationship was basically obtained by actual measurements, but where there were gaps between the plots of multiple actual measurements, values ​​calculated by interpolation and extrapolation were used.

[0082] 13A and 13B, regardless of the size of the SiC wafer 102, the amount of warpage increased as the B concentration in the SiC substrate 11 increased. In the case of a 6-inch wafer, the B concentration at which the amount of warpage was 300 μm was 1.75×10 17 / cm3 Similarly, in the case of an 8-inch wafer, the B concentration at which the warpage is 300 μm is 1.8 × 10 17 / cm 3 , 7.2×10 for 500μm specifications 17 / cm 3 It was.

[0083] For this reason, as explained in the process shown in FIG. 10A, in the case of a thickness specification of 350 μm, the B concentration is preferably 1.75×10 17 / cm 3 If the thickness is 500 μm, the B concentration is preferably 7.2×10 17 / cm 3 This not only makes it possible to produce a SiC semiconductor device with excellent diode current-carrying characteristics, but also makes it possible to suppress the amount of warping of the SiC wafer 102 during the element formation process within a specified range. This therefore makes it possible to satisfactorily transport the SiC wafer 102 during the element formation process and to satisfactorily adsorb the SiC wafer 102 to a vacuum chuck, thereby enabling the element formation process to be carried out smoothly.

[0084] Second embodiment A second embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the vertical MOSFET 30 provided in the SiC semiconductor device is changed, and other aspects are the same as those of the first embodiment, so only the differences from the first embodiment will be described.

[0085] In the first embodiment, the deep layer 15 is connected to the base region 17 via the coupling layer 20, but in this embodiment, as shown in Figure 14, the coupling layer 20 is eliminated and the deep layer 15 is directly connected to the base region 17.

[0086] Also in this embodiment, the current spreading layer 16 is formed so as to contact the tip side in the depth direction of the gate trench 21, but this may be omitted. Since the current spreading layer 16 is provided on the part of the JFET section 14 located between the deep layers 15, the n-type impurity concentration of the surface layer of the JFET section 14 may be made higher than that of the part located below it, and this may be used as the current spreading layer 16.

[0087] Furthermore, a p-type electric field relaxation layer 27 is provided along the bottom surface of the gate trench 21. The electric field relaxation layer 27 is composed of, for example, a p-type layer having a lower impurity concentration than the deep layer 15. Specifically, the electric field relaxation layer 27 is formed along the longitudinal direction of the gate trench 21. That is, the electric field relaxation layer 27 extends along the Y-axis direction intersecting with the deep layer 15. In addition, the electric field relaxation layer 27 in this embodiment is formed shallower than the JFET portion 14 and the deep layer 15, but may be formed so that the bottom surface reaches the low concentration layer 13 by penetrating the JFET portion 14 and the deep layer 15.

[0088] In this manner, the deep layer 15 may be directly connected to the base region 17. In the SiC semiconductor device having this structure, the B concentration in the SiC substrate 11 is set to the concentration described in the first embodiment, thereby preventing the BPD 50 from expanding to the SSF 60. Furthermore, by setting the B concentration in consideration of the amount of warpage, the amount of warpage of the SiC wafer 102 during the element formation process can be kept within a specified range.

[0089] In addition, in the case of the structure of this embodiment, the distance from the bottom of the deep layer 15 to the bottom of the gate insulating film 22 is shorter than that in the first embodiment, so there is a concern about the penetration of an electric field into the gate insulating film 22. However, since the electric field relaxation layer 27 is provided along the bottom surface of the gate trench 21, the penetration of an electric field into the gate insulating film 22 located at the bottom of the gate trench 21 can be suppressed, and the gate insulating film breakdown can be suppressed. In addition, by forming the electric field relaxation layer 27 so as to be in contact with the bottom surface of the gate trench 21, the electrostatic capacitance between the gate electrode 23 and the drain electrode 26, i.e., the feedback capacitance, can be reduced, and the switching speed can be improved. Furthermore, by providing the electric field relaxation layer 27, the creeping up of the electric field to the JFET section 14 arranged between the electric field relaxation layers 27 can be suppressed, and the breakdown voltage can be improved.

[0090] The electric field relaxation layer 27 may be divided into a plurality of parts along the Y-axis direction. However, the electric field relaxation layer 27 is formed so as to be electrically connected to the base region 17 via the deep layer 15.

[0091] Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described with reference to FIGS. 15A to 15F.

[0092] [Step shown in FIG. 15A] 10A in the first embodiment, a SiC wafer constituting a SiC substrate 11 with a desired B concentration is prepared, and then a buffer layer 12 and a low-concentration layer 13 are epitaxially grown. At this time, the thickness of the low-concentration layer 13 is set to a thickness equal to the thickness of the JFET section 14, the current spreading layer 16, and further the thickness of the base region 17, the source region 18, and the contact region 19.

[0093] [Step shown in FIG. 15B] After forming a mask (not shown), n-type impurities such as N and P are ion-implanted into the surface of the low concentration layer 13 and heat-treated to form the JFET section 14 and current spreading layer 16, which are composed of ion-implanted layers. The JFET section 14 and the current spreading layer 16 are implanted with different doses of n-type impurities and different ion implantation energies.

[0094] [Step shown in FIG. 15C] 10B of the first embodiment is performed, and a mask (not shown) is formed so as to open the region where the deep layer 15 is to be formed. Then, p-type impurities such as Al are ion-implanted from above the mask and heat-treated to form the deep layer 15 composed of an ion-implanted layer.

[0095] 15B, the low concentration layer 13 made of an epitaxial film is formed thick. In this case, when forming the deep layer 15, the ion implantation energy is increased so that ions can be implanted to a deep position of 1 μm or more from the surface of the low concentration layer 13 that will become the source region 18 in a later process. For example, the deep layer 15 is formed by performing high-acceleration ion implantation with a high ion implantation energy of 1 MeV or more.

[0096] When an ion implantation process is performed with a high impurity concentration and a deep implantation depth, there is a tendency for large warpage to occur in the SiC wafer 102 for forming the SiC substrate 11. However, this does not depend on the impurity concentration or implantation depth in the ion implantation, but on the B concentration in the SiC wafer 102, that is, the content of B mixed in during the manufacture of the SiC ingot 100. Therefore, even if an ion implantation process is performed with a high ion implantation energy of 1 MeV or more as in this embodiment, it is possible to suppress the amount of warpage of the SiC wafer 102 during the element formation process within a specified range.

[0097] [Step shown in FIG. 15D] After placing a mask that opens a cell region (not shown) on the surface layer of the low concentration layer 13, p-type impurities such as Al are ion-implanted and heat-treated. As a result, a base region 17 made of an ion-implanted layer is formed on the JFET section 14, the deep layer 15, and the current spreading layer 16.

[0098] [Step shown in FIG. 15E] A mask (not shown) having an opening in a region where source region 18 is to be formed is formed, and then n-type impurities such as N or P are ion-implanted from above the mask into the surface layer of low concentration layer 13 and heat-treated. As a result, source region 18 composed of an ion-implanted layer is formed on base region 17. Next, a mask (not shown) having an opening in a region where contact region 19 is to be formed is formed, and then p-type impurities such as Al are ion-implanted from above the mask and heat-treated. As a result, contact region 19 composed of an ion-implanted layer is formed.

[0099] [Step shown in FIG. 15F] After forming a mask (not shown), the mask is patterned so as to open an area where the gate trench 21 is to be formed. Then, anisotropic etching is performed to form the gate trench 21. Furthermore, using the mask (not shown) as it is, p-type impurities such as Al are ion-implanted into the bottom surface of the gate trench 21 and heat treatment is performed, thereby forming the electric field relaxation layer 27.

[0100] The subsequent steps are the same as those shown in Fig. 10G and subsequent steps in the first embodiment. In this manner, the SiC semiconductor device of this embodiment is manufactured.

[0101] As described above, in this embodiment, the ion implantation energy in the ion implantation step is higher than in the first embodiment, but it is possible to keep the amount of warpage of the SiC wafer 102 within a specified range. This allows for good transportation during the device formation process and good adsorption of the SiC wafer 102 to a vacuum chuck, making it possible to smoothly carry out the device formation process.

[0102] Third embodiment A third embodiment will be described. In this embodiment, in addition to the B concentration in the SiC substrate 11, the relationship with other p-type impurities is specified, and the rest is the same as in the first and second embodiments.

[0103] In order to prepare the SiC wafer 102 for forming the SiC substrate 11, a SiC single crystal is grown in a growth crucible by sublimation or gas growth. Specifically, a SiC ingot made of a SiC single crystal is manufactured and sliced ​​to form the SiC wafer 102. Then, the B concentration of the SiC ingot is adjusted to a desired value so that the B concentration in the SiC substrate 11 is the desired concentration. That is, the B concentration of the SiC ingot is 9.0×10 at a current stress of 600 A or more. 16 / cm 3 or more, 1.5×10 for 800A or more 17 / cm 3 Furthermore, taking into account the amount of warping, if the specification is 350 μm, the 17 / cm 3 Below, for 500μm specifications, multiply by 10 17 / cm 3 The B concentration of the SiC ingot is adjusted as follows: At this time, it was found that the element ratio of the p-type impurity element finally contained in the SiC substrate 11 is determined according to the element ratio of the SiC raw material used for growing the SiC single crystal.

[0104] As an example, a case where a crystal growth experiment was performed by sublimation using a SiC single crystal manufacturing apparatus 200 shown in FIG. 16 will be described. In the sublimation method, a raw material powder 201 made of powdered SiC, which is a SiC raw material, is heated and sublimated to produce a SiC ingot 203 on the surface of a seed crystal 202 made of a SiC single crystal. In the experiment, a growth crucible 204 made of graphite or the like was induction heated to about 2500° C., whereby the raw material powder 201 placed below a pedestal 205 was thermally decomposed, and a SiC ingot 203 was grown on the surface of the seed crystal 202 attached to the pedestal 205. In addition to the SiC powder made of powdered SiC, B powder containing boron carbide or boron nitride was introduced as a B raw material as the raw material powder 201. In addition, N2 gas was introduced as an n-type dopant to obtain an n-type SiC ingot 203.

[0105] In addition to B, various impurities including p-type impurity elements are mixed into raw material powder 201, and the content of these impurities depends on the purity of raw material powder 201. Experiments were carried out to measure the content of various p-type impurity elements contained in raw material powder 201 and the content of various p-type impurity elements contained in SiC substrate 11 obtained by manufacturing SiC wafer 102 using SiC ingot 203 manufactured using raw material powder 201. FIG. 17A is a graph showing the content of various impurity elements contained in SiC substrate 11, and FIG. 17B is a graph showing the content of various impurity elements contained in raw material powder 201.

[0106] In addition, the ratio R P / S and the magnification R of the p-type impurity content in the raw powder 201 to the p-type impurity content in the SiC substrate 11. S / P The ratio R P / S or magnification R S / P Ratio R indicates the ease of incorporation of an element into the SiC substrate 11. P / S The larger the magnification R S / P It is shown that the smaller the value of , the easier the element is incorporated into the SiC substrate 11. Figures 18A and 18B show a summary of the results.

[0107] As shown in this figure, the B concentration in the raw powder 201 is 7.0×10 17 / cm 3 At this time, the B concentration in the SiC substrate 11 is 9.5×10 17 / cm 3 The ratio R P / S is 136%, multiplier R S / P was 0.7 times. As for p-type impurities, for example, Al (aluminum), Nb (niobium), Ti (titanium), V (vanadium), Fe (iron), etc., the results are as shown in Figs. 18A and 18B. As shown in Fig. 18B, the ratio R P / S and magnification R S / P18A, the ratio of the content of each element in raw material powder 201 to the content in SiC substrate 11 approximates a straight line of 1:1. In other words, the level of impurity content in raw material powder 201, in other words, the quality of raw material powder 201, is important, and once this is determined, the B concentration in SiC substrate 11, etc. can be adjusted.

[0108] For example, for B, the magnification R S / P is 0.7 times, that is, if the B concentration in the raw material powder 201 is 0.7 times the target value, the B concentration in the SiC substrate 11 can be set to the target value. For this reason, the SiC ingot 203 is grown with the B concentration in the raw material powder 201 set to about 0.7 times the target value of the B concentration in the SiC substrate 11. Similarly, for Al, the SiC ingot 203 is grown with the Al concentration in the raw material powder 201 set to about 1.4 times the target value. For Nb, the SiC ingot 203 is grown with the Nb concentration in the raw material powder 201 set to about 1.5 times the target value. For Ti, the SiC ingot 203 is grown with the Ti concentration in the raw material powder 201 set to about 6.7 times the target value. For V, the SiC ingot 203 is grown with the V concentration in the raw material powder 201 set to about 10 times the target value. Regarding Fe, the SiC ingot 203 is grown so that the Fe concentration in the raw material powder 201 is about 1.7 times the target value. This allows the concentrations of various p-type impurities in the SiC substrate 11 to be set to desired target values.

[0109] In addition, when the impurity concentration in the SiC substrate 11 has an upper limit and the target value is set to be equal to or lower than the upper limit, the impurity concentration in the raw powder 201 is multiplied by the target impurity concentration R S / P This allows the impurity concentration in the SiC substrate 11 to be set to a desired upper limit or lower. In addition, if there is a lower limit for the impurity concentration in the SiC substrate 11 and the target value is set to be equal to or higher than the lower limit, the impurity concentration in the raw powder 201 is set to be equal to or lower than the target value of the impurity concentration by multiplying the impurity concentration by the multiplication factor R S / PThis makes it possible to set the impurity concentration in the SiC substrate 11 to a desired lower limit or higher.

[0110] Furthermore, the B concentration in the SiC substrate 11 is 7.0×10 16 ~×1.4×10 17 / cm 3 The concentrations of various p-type impurities were measured when the concentration of various p-type impurities other than B was 100 μm, and it was investigated whether the expansion of BPD50 to SSF60 was affected due to changes in the concentration of various p-type impurities other than B. It was also investigated whether the amount of warping of the SiC wafer 102 was affected. As a result, it was confirmed that the impact on the expansion of BPD50 to SSF60 and the impact on the amount of warping of the SiC wafer 102 were limited, and that it was sufficient to mainly adjust the B concentration. Specifically, the amount of other impurities contained was measured when the B concentration in the SiC substrate 11 was set to a range that suppressed the expansion of BPD50 to SSF60 while keeping the amount of warping within a specified range. As a result, it was found that the total impurity concentration of p-type impurities other than B was 2.3×10 17 / cm 3 For an 8-inch wafer, the figure is 2.9×10 17 / cm 3 In addition, the Al concentration was 5.0×10 for both the 6-inch and 8-inch wafers. 15 / cm 3 Below, Ti concentration is 1.0×10 16 / cm 3 Below, V concentration is 4.0×10 15 / cm 3 Below, Fe concentration is 6.0×10 16 / cm 3 Therefore, if the total impurity concentration of p-type impurities other than B is equal to or less than these concentrations, by adjusting at least only the B concentration to the range described in the first and second embodiments, it is possible to suppress the expansion of BPD50 to SSF60 and keep the amount of warpage within the specified range.

[0111] Although the case where the SiC ingot 203 is manufactured by the sublimation method has been described as an example here, it may be manufactured by a gas growth method. In the case of the gas growth method, a gas inlet is provided at the bottom of the growth crucible 204, and an exhaust port is provided at the top or side of the growth crucible 204, and the SiC raw material gas, n-type dopant, and B dopant gas are introduced to manufacture the SiC ingot 203.

[0112] In the case of the sublimation method, after the raw material powder 201 is placed in the growth crucible 204, the state of the raw material powder 201 cannot be confirmed during growth, but in the case of the gas growth method, the introduced gas can be controlled. For this reason, the gas growth method makes it easier to control the concentration of p-type impurities including B in the SiC ingot 203 than the sublimation method. In fact, the SiC ingot 203 was manufactured by each of the sublimation method and the gas growth method, and the concentration of each p-type impurity was measured. When the deviation of the actual impurity concentration from the target value was confirmed, the actual impurity concentration of B was closer to the target value with the gas growth method than with the sublimation method. For other p-type impurities, the actual impurity concentration of the gas growth method was sometimes closer to the target value, and conversely, the actual impurity concentration of the sublimation method was sometimes closer to the target value. For this reason, when it is necessary to control the B concentration more precisely, it is better to use the gas growth method, but when it is necessary to control the concentration of other p-type impurities, both the gas growth method and the sublimation method can be controlled to the same extent.

[0113] When the SiC ingot 203 is manufactured by the gas growth method, a B-containing gas is introduced into the growth crucible 204 in addition to the SiC raw material gas and the n-type dopant gas. For example, any one of SiH4, H2SiCl2, and HSiCl3 as the Si raw material and any one of C3H8 and C2H4 as the C raw material are introduced into the growth crucible 204 as the SiC raw material gas. In addition, N2 or the like is introduced as the n-type dopant gas, and a B-containing gas such as BCl3 or B2H3 is introduced. This makes it possible to manufacture an ingot of a SiC single crystal having the above-mentioned B concentration. At this time, by also introducing an etching gas such as HCl and a carrier gas such as H2 into the growth crucible 204, it becomes possible to optimize the atmosphere in the crucible and suppress the generation of polycrystals, and it becomes possible to manufacture the SiC ingot 203 more satisfactorily.

[0114] Furthermore, in the sublimation method, it was also measured whether the purity of the growth crucible 204 affects the accuracy of the p-type impurity concentration. Specifically, if Cl2 gas or the like is supplied to the growth crucible 204 before the growth of the SiC ingot 203 to perform a metal removal process, the constituent material of the growth crucible 204, for example, graphite or graphite coated with a high melting point metal, can be highly purified. For each of the cases where this high purification was performed and not performed, the SiC ingot 203 was manufactured, and the p-type impurity concentration in the SiC substrate 11 was measured when a SiC semiconductor device was manufactured using the SiC wafer 102 cut from the ingot 203. FIG. 19 shows the results, and it was confirmed that the difference in the p-type impurity concentration in the SiC substrate 11 was small whether high purification was performed or not, and that the p-type impurity concentration could be accurately controlled in either case. Therefore, it is possible to control the p-type impurity concentration regardless of whether high purification was performed or not.

[0115] In this case, when manufacturing the SiC ingot 203 by the sublimation method, a B raw material powder containing boron carbide or boron nitride as a B raw material is added to the raw material powder 201 in order to adjust the B concentration. In addition, for example, aluminum carbide powder may be added as an Al raw material to adjust the Al concentration, titanium carbide powder may be added as a Ti raw material to adjust the Ti concentration, and tantalum carbide powder may be added as a Ta raw material to adjust the Ta concentration. Of course, when adjusting the concentrations of multiple p-type impurity elements, multiple combinations of these elements may be added to the raw material powder 201. Also, a sintered body may be used instead of a powder containing a p-type impurity element.

[0116] Alternatively, the raw material powder 201 may be made of only highly pure SiC, and a chloride gas, for example, BCl3 for a B raw material, or a hydride gas, for example, B2H3 for a B raw material, may be introduced into the growth crucible 204 as a p-type dopant gas.

[0117] In addition to the fine-grained SiC powder, a coarser grained B powder with a concentration of 1.2×10 17 / cm 3 The above-mentioned SiC powders may be prepared and stacked in two layers to be used as raw material powder 201. Specifically, fine-grained SiC powder may be placed on top of coarse-grained SiC powder, and the p-type impurity element may be supplied to the growth surface of SiC ingot 203 through the gaps between the fine-grained SiC powder.

[0118] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0119] For example, in the third embodiment, a case where p-type impurities other than B are introduced when manufacturing the SiC ingot 203 has been described, but p-type impurities other than B may not be introduced into the SiC ingot 203. For example, before placing the seed crystal 202 used to manufacture the SiC ingot 203 in a growth crucible, a heat treatment is performed to remove p-type impurities other than B in the raw material powder 201. At this time, if the raw material powder 201 contains B raw material powder containing boron carbide or boron nitride, B will remain sufficiently even after the heat treatment, so that B will not be completely removed. Alternatively, the B raw material powder containing boron carbide or boron nitride may be placed after performing a heat treatment to remove p-type impurities other than B from the raw material powder 201. Then, after the p-type impurities other than B have been removed, the seed crystal 202 is placed in a growth crucible and a SiC ingot 203 is produced, whereby it is possible to achieve a desired B concentration in the SiC ingot 203 while keeping the concentration of p-type impurities other than B as low as possible.

[0120] In addition, in the above embodiments, 6-inch and 8-inch wafers are given as examples of the SiC wafer 102, but the present disclosure can also be applied to wafers of different dimensions. Even in such cases, the B concentration that can suppress the expansion of BPD50 to SSF60 is set to 9.0×10 when the current stress is 600 A or more. 16 / cm 3 When the electrical stress is 800A or more, the B concentration is 1.5×10 17 / cm 3 More than that would be good.

[0121] (In view of the present disclosure) The present disclosure described above can be understood from the following viewpoints, for example.

[0122] [First viewpoint] A silicon carbide wafer constituting a silicon carbide substrate (11) made of n-type silicon carbide doped with n-type impurities, The silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0×10 16 / cm 3 Silicon carbide wafers are said to be as follows: [Second viewpoint] The boron concentration is 1.5×10 17 / cm 3 The silicon carbide wafer according to the first aspect, as described above. [Third Perspective] The wafer is made of a 6-inch or 8-inch wafer having a thickness of 325 to 375 μm, and the boron concentration is 1.75×10 17 / cm 3 A silicon carbide wafer according to a first or second aspect, which is as follows: [Fourth viewpoint] The wafer is an 8-inch wafer with a thickness of 475 to 525 μm, and the boron concentration is 7.2 × 10 17 / cm 3 A silicon carbide wafer according to a first or second aspect, which is as follows: [Fifth viewpoint] A silicon carbide substrate (11) made of n-type silicon carbide doped with n-type impurities; an n-type low concentration layer (13) formed on the silicon carbide substrate and having a lower n-type impurity concentration than the silicon carbide substrate; a p-type deep layer (15) formed on the low concentration layer and having a plurality of linear portions whose longitudinal direction is in one direction in the surface direction of the substrate; an n-type JFET section (14) disposed on the low concentration layer and having a linear portion sandwiched between the deep layers; a p-type base region (17) disposed on the JFET portion and the deep layer; an n-type source region (18) formed in a surface layer portion of the base region; the trench gate structure including a gate insulating film (22) formed on a wall surface of a gate trench (21) penetrating the source region and the base region, and a gate electrode (23) formed on the gate insulating film; a source electrode (25) electrically connected to the source region and the base region; a drain electrode (26) electrically connected to the substrate; The deep layer, the JFET portion, and the low concentration layer constitute a built-in diode (40), and the current density of the current flowing when the built-in diode operates as a reflux junction is 11.6 A / mm 2 That is all. The silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0×10 16 / cm 3 The silicon carbide semiconductor device is as described above. [Sixth viewpoint] The current density of the current flowing when the built-in diode operates in a freewheeling state is 14.6 A / mm 2 That is all. The boron concentration is 1.5×10 17 / cm 3 The silicon carbide semiconductor device according to a fifth aspect is as described above. [Seventh viewpoint] The silicon carbide substrate has a thickness of 325 to 375 μm, and the boron concentration is 1.75×10 17 / cm 3 A silicon carbide semiconductor device according to a fifth or sixth aspect, which is as follows: [Eighth viewpoint] The silicon carbide substrate has a thickness of 475 to 525 μm, and the boron concentration is 7.2×10 17 / cm 3 A silicon carbide semiconductor device according to a fifth or sixth aspect, which is as follows: [Ninth viewpoint] The silicon carbide semiconductor device according to any one of the fifth to eighth aspects, wherein the deep layer has a thickness of 1 μm or less. [10th viewpoint] An n-type current spreading layer (16) formed on the JFET portion and the deep layer and in contact with the tip side of the gate trench in the depth direction; A p-type connection layer (20) that connects the base region and the deep layer, the base region is formed on the current spreading layer and the coupling layer; The silicon carbide semiconductor device according to any one of fifth to eighth aspects, wherein the deep layer is constituted by an ion-implanted layer, and a depth from a surface of the source region to a bottom of the deep layer is 1 μm or more. [Eleventh viewpoint] The silicon carbide semiconductor device according to any one of a fifth to tenth aspects, wherein the low concentration layer is constituted by an epitaxial film formed on the silicon carbide substrate. [12th viewpoint] A method for producing an n-type silicon carbide single crystal, comprising the steps of: Placing a seed crystal (202) for growing a silicon carbide single crystal on one surface of a pedestal (205) disposed in a growth crucible (204); and supplying a pyrolyzed silicon carbide raw material, an n-type dopant, and boron to the surface of the seed crystal, thereby producing a silicon carbide ingot (203) composed of an n-type silicon carbide single crystal on the surface of the seed crystal, In growing the silicon carbide ingot, the boron concentration in the silicon carbide ingot is increased to 9.0×10 16 / cm 3 The above is a method for producing a silicon carbide single crystal. [13th viewpoint] The method for producing a silicon carbide single crystal according to a twelfth aspect, wherein, in growing the silicon carbide ingot, a raw material powder (201) having a boron raw material powder containing boron carbide or boron nitride as a raw material of the boron in addition to silicon carbide powder as the silicon carbide raw material is placed below the pedestal, an n-type dopant is supplied, and the raw material powder is heated and decomposed and supplied to the seed crystal, thereby producing the silicon carbide ingot by a sublimation method. [14th viewpoint] a silicon carbide source gas and an n-type dopant gas, as well as a boron dopant gas, are supplied from below the pedestal, and the silicon carbide source gas is heated and decomposed before being supplied to the seed crystal, thereby producing the silicon carbide ingot by a gas growth method. [Explanation of symbols]

[0123] 11...SiC substrate, 12...buffer layer, 13...low concentration layer, 14...JFET section, 15...deep layer, 16...current spreading layer, 17...base region, 18...source region, 19...contact region, 20...connection layer, 21...gate trench, 22...gate insulating film, 23...gate electrode, 24...interlayer insulating film, 25...source electrode, 26...drain electrode, 27...field relaxation layer, 30...vertical MOSFET, 31...mask, 40...built-in diode, 100...SiC ingot, 101...growth surface, 102...SiC wafer, 110...seed crystal, 200...SiC single crystal manufacturing apparatus, 201...raw material powder, 202...seed crystal, 203...SiC ingot, 204...growth crucible, 205...pedestal

Claims

1. A silicon carbide wafer that constitutes a silicon carbide substrate (11) composed of n-type silicon carbide doped with an n-type impurity, It is composed of a 6-inch wafer or an 8-inch wafer with a thickness of 325 to 375 μm, Boron is contained in the silicon carbide substrate, and the boron concentration in the silicon carbide substrate is 9.0×10 １６ / cm ３ or more and 1.75×10 17 / cm 3 or less, a silicon carbide wafer.

2. A silicon carbide wafer that constitutes a silicon carbide substrate (11) composed of n-type silicon carbide doped with an n-type impurity, It is composed of an 8-inch wafer with a thickness of 475 to 525 μm, Boron is contained in the silicon carbide substrate, and the boron concentration in the silicon carbide substrate is 9.0×10 １６ / cm ３ or more and 7.2×10 17 / cm 3 or less, a silicon carbide wafer.

3. The boron concentration is 1.5×10 １７ / cm ３ or more, the silicon carbide wafer according to claim 1 or 2.

4. A silicon carbide substrate (11) composed of n-type silicon carbide doped with an n-type impurity, An n-type low-concentration layer (13) formed on the silicon carbide substrate and having a lower n-type impurity concentration than the silicon carbide substrate, A p-type deep layer (15) formed on the low-concentration layer and having a plurality of linear portions with one direction in the plane direction of the substrate as the longitudinal direction, An n-type JFET portion (14) disposed on the low-concentration layer and having a linear portion sandwiched between the deep layers, A p-type base region (17) disposed on the JFET portion and the deep layer, An n-type source region (18) formed on the surface layer portion of the base region, A trench gate structure having a gate insulating film (22) formed on a wall surface of a gate trench (21) penetrating the source region and the base region, and a gate electrode (23) formed on the gate insulating film; A source electrode (25) electrically connected to the source region and the base region; A drain electrode (26) electrically connected to the substrate, and; A built-in diode (40) is formed by the deep layer, the JFET portion, and the low-concentration layer, and when the built-in diode performs a reflux operation, the current density of the current flowing is 11.6 A / mm ２ or more; The silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0×10 １６ / cm ３ or more, a silicon carbide semiconductor device.

5. When the built-in diode performs a reflux operation, the current density of the current flowing is 14.6 A / mm ２ or more; The boron concentration is 1.5×10 １７ / cm ３ or more, the silicon carbide semiconductor device according to claim 4.

6. The silicon carbide substrate has a thickness of 325 to 375 μm, and the boron concentration is 1.75×10 １７ / cm ３ or less, the silicon carbide semiconductor device according to claim 4 or 5.

7. The silicon carbide substrate has a thickness of 475 to 525 μm, and the boron concentration is 7.2×10 １７ / cm ３ or less, the silicon carbide semiconductor device according to claim 4 or 5.

8. The deep layer has a thickness of 1 μm or less, the silicon carbide semiconductor device according to claim 4 or 5.

9. An n-type current dispersion layer (16) formed on the JFET portion and the deep layer, and formed in contact with the tip side in the depth direction of the gate trench; A p-type connection layer (20) that connects the base region and the deep layer; The base region is formed on the current dispersion layer and the connection layer; The deep layer is composed of an ion implantation layer, and the depth from the surface of the source region to the bottom of the deep layer is 1 μm or more. The silicon carbide semiconductor device according to claim 4 or 5.

10. The low concentration layer is composed of an epitaxial film formed on the silicon carbide substrate. The silicon carbide semiconductor device according to claim 4 or 5.

11. A method for manufacturing an n-type single crystal of silicon carbide, Placing a seed crystal (202) for growing a single crystal of silicon carbide on one surface of a pedestal (205) disposed in a growth crucible (204); By supplying a silicon carbide raw material decomposed by heating, an n-type dopant, and boron to the surface of the seed crystal, manufacturing a silicon carbide ingot (203) composed of an n-type single crystal of silicon carbide on the surface of the seed crystal; When growing the silicon carbide ingot, the boron concentration in the silicon carbide ingot is 9.0×10 １６ / cm ３ or more and 1.75×10 17 / cm 3 or less; A method for manufacturing a single crystal of silicon carbide, wherein the silicon carbide ingot is sliced to form a 6-inch wafer or an 8-inch wafer having a thickness of 325 to 375 μm.

12. A method for manufacturing an n-type single crystal of silicon carbide, Placing a seed crystal (202) for growing a single crystal of silicon carbide on one surface of a pedestal (205) disposed in a growth crucible (204); By supplying a silicon carbide raw material, an n-type dopant, and boron that are thermally decomposed onto the surface of the seed crystal, a silicon carbide ingot (203) composed of an n-type silicon carbide single crystal is manufactured on the surface of the seed crystal. In growing the silicon carbide ingot, the boron concentration in the silicon carbide ingot is set to 9.0×10 １６ / cm ３ or higher and 7.2×10^17 / cm^3 or lower. A method for manufacturing a silicon carbide single crystal, comprising slicing the silicon carbide ingot to form an 8-inch wafer having a thickness of 475 to 525 μm.

13. In growing the silicon carbide ingot, a raw material powder (201) containing a boron raw material powder such as boron carbide or boron nitride, which is a raw material of boron, in addition to the silicon carbide powder as the silicon carbide raw material, is disposed below the pedestal, and an n-type dopant is supplied. The silicon carbide ingot is manufactured by the sublimation method by heating and decomposing the raw material powder and supplying it to the seed crystal. The method for manufacturing a silicon carbide single crystal according to claim 11 or 12.

14. In growing the silicon carbide ingot, a boron dopant gas is supplied in addition to the silicon carbide raw material gas and the n-type dopant gas below the pedestal, and the silicon carbide raw material gas is heated and decomposed and supplied to the seed crystal. The silicon carbide ingot is manufactured by the gas growth method. The method for manufacturing a silicon carbide single crystal according to claim 11 or 12.

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