Semiconductor devices

Abstract

To provide a semiconductor device with improved characteristics.SOLUTION: A semiconductor device according to the present invention includes: a lower circuit pattern which is formed on a substrate; a bit line shield structure which is formed on the lower circuit pattern; a first insulating interlayer which is formed in an opening extending through the bit line shield structure; a bit line structure which is formed on the bit line shield structure, and at least partially overlaps the bit line shield structure in a direction perpendicular to an upper surface of the substrate; a first contact plug which extends through the first insulating interlayer to contact the bit line structure, and is electrically connected to the lower circuit pattern; a channel which is formed on the bit line structure; and a capacitor which is formed on the channel and is electrically connected to the channel.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to memory devices including vertical channels. [Background technology]

[0002] To increase the integration density of semiconductor devices, memory devices including vertical channel transistors have been developed. In a vertical channel memory device, a bitline shield is formed that partially surrounds the bitline.

[0003] When the vertical channel memory device has a COP structure, a separate wiring structure that bypasses the bit line shield is required to electrically connect the bit line and the lower circuit pattern to each other. Therefore, the density of the vertical channel memory device is reduced because an area is required to form the wiring structure. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems in conventional memory devices, and an object of the present invention is to provide a semiconductor device having improved characteristics. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, a semiconductor device according to the present invention is characterized in that it comprises a lower circuit pattern formed on a substrate, a bit line shield structure formed on the lower circuit pattern, a first interlayer insulating film formed in an opening penetrating the bit line shield structure, a bit line structure formed on the bit line shield structure and at least partially overlapping the bit line shield structure in a direction vertical to an upper surface of the substrate, a first contact plug penetrating the first interlayer insulating film, contacting the bit line structure and electrically connected to the lower circuit pattern, a channel formed on the bit line structure, and a capacitor formed on the channel and electrically connected thereto.

[0006] In order to achieve the above-mentioned object, a semiconductor device according to the present invention includes a bit line shield plate formed on a substrate and having a flat shape parallel to an upper surface of the substrate; a bit line shield structure formed on the bit line shield plate, protruding perpendicular to an upper surface of the substrate, and including bit line shield fins spaced apart from each other along a first direction parallel to the upper surface of the substrate and extending in a second direction parallel to the upper surface of the substrate and orthogonal to the first direction; a plurality of bit line structures formed on the bit line shield plate, each formed between adjacent bit line shield fins along the first direction and each extending in the second direction; channels formed on the bit line structures; and capacitors formed on the channels and electrically connected thereto, wherein the bit line shield plate has a plurality of openings formed therethrough, and each of the bit line structures overlaps at least one of the openings in the vertical direction.

[0007] In order to achieve the above object, a semiconductor device according to the present invention is characterized in that it comprises a lower circuit pattern formed on a substrate, first and second bonding films stacked on the lower circuit pattern along a direction perpendicular to an upper surface of the substrate, a bit line shield structure formed on the second bonding film and including an opening, an interlayer insulating film formed between the second bonding film and the bit line shield structure, covering a lower surface of the bit line shield structure and filling the opening, a bit line structure formed on the bit line shield structure and at least partially overlapping the bit line shield structure in the vertical direction, a contact plug penetrating a portion of the interlayer insulating film formed in the opening, contacting the bit line structure and electrically connected to the lower circuit pattern, a channel formed on the bit line structure, and a capacitor formed on the channel and electrically connected thereto. Effect of the Invention

[0008] In a semiconductor device according to the present invention, a bit line shield structure adjacent to a bit line structure includes an opening therethrough, and the bit line structure is electrically connected to an underlying circuit pattern via a contact plug passing through the opening. Therefore, since it is not necessary to form a separate wiring structure that bypasses the bit line shield structure, the semiconductor device can have an improved integration density. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 4] 1 is a perspective view illustrating a shape of a bit line shield structure according to an embodiment of the present invention; [Diagram 5]1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 21]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 25] 2 is a perspective view illustrating a bit line shield structure included in a semiconductor device according to an embodiment of the present invention; [Figure 26] 2 is a perspective view illustrating a bit line shield structure included in a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Next, specific examples of embodiments for carrying out the semiconductor device according to the present invention will be described with reference to the drawings.

[0011] In the following detailed description of the invention (excluding the claims), two mutually intersecting horizontal directions parallel to the top surface of each of the first to third substrates are defined as the first and second directions (D1, D2), respectively, and the vertical direction perpendicular to the top surface of each of the first to third substrates is defined as the third direction (D3). In another embodiment, the first and second directions (D1, D2) are perpendicular to each other. Meanwhile, the first to third directions (D1, D2, D3) may refer not only to the directions shown in the drawings but also to the opposite directions.

[0012] 1 to 3 are plan views and cross-sectional views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a perspective view for explaining the shape of a bit line shield structure. Specifically, FIG. 1 is a plan view, FIG. 2 is a cross-sectional view taken along line AA' in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB' in FIG.

[0013] As shown in FIGS. 1 to 4, the semiconductor device includes a lower circuit pattern formed on a third substrate 600, a bit line structure 430, a bit line shield structure 460, first and second gate electrodes (140, 160), first and second gate insulation patterns (130, 150), a channel 125, a landing pad 180, and a capacitor 220. The semiconductor device further includes third and fourth bonding films (490, 730), first and second bonding pads (510, 750), first to sixth interlayer insulating films (170, 230, 480, 650, 660, 700), and an insulating film 450.

[0014] The third substrate 600 may comprise a semiconductor material such as, for example, silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, and the like. According to another embodiment, the third substrate 600 is a Silicon on Insulator (SOI) substrate or a Germanium-on-Insulator (GOI) substrate.

[0015] In one embodiment, the third substrate 600 includes a cell array region in which memory cells are formed, and a peripheral circuit region surrounding the cell array region in which peripheral circuit patterns for applying signals to the memory cells are formed. However, only the cell array region of the third substrate 600 is shown in the drawing. On the other hand, the semiconductor device has a COP (Cell Over Periphery) structure in which memory cells are formed on an underlying circuit pattern.

[0016] The lower circuit pattern is a circuit pattern that constitutes, for example, a bit line sense amplifier (BLSA), a sub-word line driver (SWD), a column decoder, a column select line (CSL) driver, an input / output sense amplifier (I / O SA), a write driver, etc. In the drawings, a lower circuit pattern constituting a BLSA is shown as an example. The underlying circuit pattern includes, for example, transistors, contact plugs, wiring, and vias.

[0017] The transistor includes a gate structure 630 formed on a third substrate 600 and a source-drain layer 605 formed adjacent thereto on top of the third substrate 600 . The gate structure 630 includes a third gate insulating pattern 610 and a third gate electrode 620, which are sequentially stacked along a third direction (D3). In one embodiment, the gate structures 630 extend in the second direction (D2) and are provided in a plurality of locations spaced apart from one another along the first direction (D1). Meanwhile, gate spacers are further provided on both side walls of the gate structure 630 .

[0018] The third gate insulating pattern 610 includes an oxide such as silicon oxide, and the third gate electrode 620 includes a conductive material such as a metal, a metal nitride, a metal silicide, impurity-doped polysilicon, etc. Each source-drain layer 605 includes an n-type impurity, such as phosphorus, arsenic, or the like, or a p-type impurity, such as boron, aluminum, or the like. In one embodiment, the transistors are formed at locations corresponding to the bit line structures 430 formed thereon.

[0019] A fourth interlayer insulating film 650 is formed on the third substrate 600 and covers the transistors. The second contact plugs 640 penetrate the fourth interlayer insulating film 650 and come into contact with the upper surfaces of the source / drain layers 605 . The fifth interlayer insulating film 660 is formed on the fourth interlayer insulating film 650 and the second contact plugs 640 . The first wiring 670, the first via 680 and the second wiring 690 are formed in the fifth interlayer insulating film 660 and are stacked sequentially along the third direction (D3), and the first wiring 670 contacts the upper surface of the second contact plug 640. The sixth interlayer insulating film 700 is formed on the fifth interlayer insulating film 660 and the second wiring 690 . The second via 710 and the third wiring 720 are formed in the sixth interlayer insulating film 700 and are sequentially stacked along the third direction (D3). The second via 710 contacts the upper surface of the second wiring 690.

[0020] The fourth bonding film 730 is formed on the sixth interlayer insulating film 700 and the third wiring 720 . The third contact plug 740 and the second bonding pad 750 are formed in the fourth bonding film 730 and are sequentially stacked along the third direction (D3), and the third contact plug 740 contacts the upper surface of the third wiring 720. The third bonding film 490 is formed on the fourth bonding film 730 and the second bonding pad 750 . The third interlayer insulating film 480 is formed on the third bonding film 490 .

[0021] The third to sixth interlayer insulating films (480, 650, 660, 700) each include an oxide such as silicon oxide or a low-k material, and the third and fourth bonding films (490, 730) each include an insulating material such as silicon carbonitride (SiCN). The second bond pad 750 comprises a metal such as, for example, copper, aluminum, or the like. In addition, the second and third contact plugs (640, 740), the first to third wirings (670, 690, 720), and the first and second vias (680, 710) each include a conductive material such as a metal, a metal nitride, a metal silicide, or polysilicon doped with impurities.

[0022] The bit line shield structure 460 is formed on the third interlayer insulating film 480 . In one embodiment, a bitline shield structure 460 includes a bitline shield plate 462 and a bitline shield fin 464 stacked in a third direction (D3) and in contact with each other. In one embodiment, the bit line shield plate 462 has a flat plate shape parallel to the top surface of the third substrate 600 . The bit line shield fins 464 protrude from the bit line shield plate 462 in the third direction (D3), extend in the second direction (D2), and are provided spaced apart from one another along the first direction (D1).

[0023] 17 to 19, in one embodiment, the bit line shield plate 462 includes a first opening 470, which penetrates the bit line shield plate 462 and the insulating film 450 formed thereon to expose the bottom surface of the second conductive pattern 420 included in the bit line structure 430. The first opening 470 is filled with a third interlayer insulating film 480 .

[0024] In one embodiment, the first openings 470 are provided spaced apart from each other along a fourth direction that forms an acute angle with the first and second directions (D1, D2), for example. Alternatively, the first openings 470 may be provided in a plurality of positions spaced apart from each other along the first and second directions (D1, D2), and may be arranged in a lattice shape when viewed from above, for example. Each bitline shield plate 462 and bitline shield fin 464 includes a conductive material such as, for example, a metal, a metal nitride, a metal silicide, or the like.

[0025] The insulating film 450 covers the top surface of the bitline shield structure 460 , ie, the top surface of the bitline shield plate 462 and the top surfaces and sidewalls of the bitline shield fins 464 . The insulating film 450 includes an oxide, such as, for example, silicon oxide. The bit line structures 430 are formed on the insulating film 450, extend in the second direction (D2), and are provided in a plurality of structures spaced apart from each other along the first direction (D1). Here, each bit line structure 430 is formed between adjacent bit line shield fins 464 in the first direction (D1), and the sidewalls thereof are covered with the insulating film 450. In one embodiment, each bitline structure 430 overlaps at least one of the first openings 470 formed in the bitline shield plate 462 in the third direction (D3).

[0026] In one embodiment, the bit line structure 430 includes a second conductive pattern 420, a barrier pattern 410, and a first conductive pattern 400, which are sequentially stacked along a third direction (D3). Here, the second conductive pattern 420 includes a metal and / or a metal nitride, the barrier pattern 410 includes a metal silicon nitride, such as titanium silicon nitride, and the first conductive pattern 400 includes, for example, impurity-doped polysilicon.

[0027] The first bonding pad 510 penetrates the lower part of the third bonding film 490, and the first contact plug 500 penetrates the third bonding film 490 and the portion of the third interlayer insulating film 480 formed in the first opening 470, and contacts the upper surface of the first bonding pad 510 and the upper surface of the second conductive pattern 420. In one embodiment, the first bond pads 510 and the first contact plugs 500 are provided in a plurality of locations spaced apart from each other along the fourth direction, or are arranged in a lattice pattern spaced apart from each other along the first and second directions (D1, D2), corresponding to the layout of the first openings 470. The first bond pad 510 comprises a metal such as, for example, copper, aluminum, or the like. The first contact plug 500 includes a conductive material such as, for example, a metal, a metal nitride, a metal silicide, or impurity-doped polysilicon.

[0028] The first and second cap patterns 250 and 255 extend in a first direction D1 from above the bit line structure 430 and the insulating film 450, and are provided in a plurality of patterns spaced apart from each other along a second direction D2. In one embodiment, the first and second cap patterns (250, 255) are alternately arranged along the first direction (D1). The first and second capping patterns (250, 255) each comprise an insulating nitride, such as, for example, silicon nitride, or an oxide, such as, for example, silicon oxide.

[0029] The first and second gate electrodes (140, 160) are formed on the first and second cap patterns (250, 255), respectively. Therefore, the first and second gate electrodes (140, 160) extend in the first direction (D1) and are provided in a plurality of locations spaced apart from each other along the second direction (D2). In one embodiment, the first and second gate electrodes (140, 160) are alternately arranged along the first direction (D1).

[0030] In one embodiment, the first gate electrode 140 has a line shape that extends linearly in a first direction (D1) when viewed from above. In contrast, the second gate electrode 160, in addition to having a line shape extending linearly in the first direction (D1), further includes protrusions that are spaced apart from each other along the first direction (D1) and protrude in the second direction (D2). The first gate electrode 140 may include, for example, impurity-doped polysilicon, and the second gate electrode 160 may include, for example, a metal, a metal nitride, a metal silicide, or the like. In one embodiment, the second gate electrode 160 serves as a word line for the semiconductor device, and the first gate electrode 140 serves as a back gate electrode.

[0031] The first gate insulation pattern 130 extends in a first direction (D1) from above the bit line structure 430 and the insulation film 450, and covers both sidewalls of the first gate electrode 140 and the first cap pattern 250 in a second direction (D2). Therefore, the first gate insulation patterns 130 are provided in a plurality of locations spaced apart from each other along the second direction (D2). The second gate insulation pattern 150 extends in a first direction (D1) from above the bit line structure 430 and the insulation film 450, and covers both sidewalls of the second gate electrode 160 and the second cap pattern 255 in the second direction (D2). Therefore, the second gate insulating patterns 150 are provided in a plurality of locations spaced apart from each other along the second direction (D2).

[0032] In one embodiment, the first gate insulating pattern 130 has a line shape that extends linearly in a first direction (D1) when viewed from above. Meanwhile, the second gate insulating pattern 150 has a staggered shape bent in the second direction (D2) and extending in the first direction (D1) when viewed from above. Here, one sidewall of the second gate insulating pattern 150 contacts a portion of one sidewall of the first gate insulating pattern 130 opposite thereto. In one embodiment, the first and second gate insulation patterns (130, 150) comprise an oxide, such as, for example, silicon oxide, or a nitride, such as, for example, silicon nitride. In another embodiment, the first and second gate insulating patterns (130, 150) have a composite film structure having a first film comprising an oxide, e.g., silicon oxide, and a second film comprising a nitride, e.g., silicon nitride.

[0033] A plurality of channels 125 are provided on the bit line structure 430 and the insulating film 450, spaced apart from each other along the first and second directions (D1, D2). In one embodiment, the channels 125 contact the upper surface of the first conductive pattern 400 included in each bit line structure 430 extending in the second direction (D2) and are provided in a plurality of channels spaced apart from each other along the second direction (D2). In one embodiment, one sidewall of the channel 125 in the second direction (D2) contacts the first gate insulation pattern 130, and the other sidewall of the channel 125 in the second direction (D2) and each of the sidewalls in the first direction (D1) contact the second gate insulation pattern 150. Channel 125 includes a semiconductor material such as, for example, silicon, germanium, silicon-germanium, or the like.

[0034] A first interlayer insulating film 170 is formed on the first and second gate electrodes (140, 160), the channel 125, and the first and second gate insulating patterns (130, 150). The first interlayer dielectric 170 may comprise, for example, an oxide such as silicon oxide or a low-k material.

[0035] The landing pad 180 penetrates the first interlayer insulating film 170 and contacts the upper surface of the channel 125 . Although the bottom surfaces of landing pads 180 are shown in the drawings as being larger than the top surfaces of the corresponding channels 125, the invention is not limited in this respect. Also, in the drawings, the landing pad 180 is shown as having a rectangular shape when viewed from above, however, the present invention is not limited thereto and may have other shapes, such as a circle, an oval, a rectangle with rounded corners, etc. The landing pad 180 may include, for example, a metal, a metal nitride, a metal silicide, or the like.

[0036] The capacitor 220 includes a first capacitor electrode 190 , a dielectric film 200 , and a second capacitor electrode 220 . In one embodiment, the first capacitor electrodes 190 are provided in a plurality of locations spaced apart from each other along the first and second directions (D1, D2) and contact the upper surfaces of the corresponding landing pads 180. In the drawings, the first capacitor electrode 190 is shown as having a rectangular shape when viewed from above, however, the present invention is not limited thereto and may have other shapes, such as a circle, an oval, a rectangle with rounded corners, etc. In addition, in the drawings, the first capacitor electrodes 190 are shown arranged in a lattice shape when viewed from above, but the present invention is not limited thereto, and the first capacitor electrodes 190 may be arranged in, for example, a honeycomb shape.

[0037] The first capacitor electrode 190 may include, for example, a metal, a metal nitride, a metal silicide, etc., the dielectric film 200 may include, for example, a metal oxide, and the second capacitor electrode 210 may include, for example, a metal, a metal nitride, a metal silicide, impurity-doped silicon-germanium, etc. The second interlayer insulating film 230 is formed on the first interlayer insulating film 170 and covers the capacitor 220 . The second interlayer dielectric 230 may comprise, for example, an oxide such as silicon oxide or a low-k material.

[0038] In the semiconductor device according to the embodiment of the present invention, current flows in a third direction (D3), i.e., a vertical direction, in the channel 125 formed between the bit line structure 430 and the landing pad 180, thereby the semiconductor device includes a vertical channel transistor (VCT) having a vertical channel. In the semiconductor device according to the embodiment of the present invention, a first opening 470 is formed penetrating a bit line shield plate 462 included in the bit line shield structure 460 and a portion of the insulating film 450 covering the lower surface of the bit line structure 430, and the first opening 470 is filled with a third interlayer insulating film 480.

[0039] Thus, the bit line structure 430 is electrically connected to the lower circuit pattern through the first contact plug 500 penetrating the portion of the third interlayer insulating film 480 formed in the first opening 470, and the first and second bond pads (510, 750) and third contact plug 740 connected thereto.

[0040] If the first opening 470 is not formed in the bit line shield structure 460 formed below the bit line structure 460, a separate wiring structure that bypasses the bit line shield structure 460 must be formed to electrically connect the lower circuit pattern and the bit line structure 430 to each other. This requires space for forming the wiring structure, which hinders high integration of semiconductor devices. However, in the semiconductor device according to the embodiment of the present invention, since the bit line shield structure 460 includes the first opening 470 as a passage for electrical connection between the bit line structure 430 and the lower circuit pattern, it is not necessary to form a separate wiring structure that bypasses the bit line shield structure 460, thereby improving the integration density of the semiconductor device.

[0041] 5 to 24 are plan views and cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, Figures 5, 7, 9, 11, 15, 17, and 20 are plan views, Figures 6, 8, 10, 12, 14, 18, 21, and 23 are cross-sectional views taken along line A-A' in the corresponding plan views, and Figures 13, 16, 19, 22, and 24 are cross-sectional views taken along line B-B' in the corresponding plan views.

[0042] As shown in Figures 5 and 6, the second bulk of the first substrate structure including the first bulk 100, the buried oxide film 110, and the second bulk is patterned to form a preliminary channel 120, and a first gate insulation pattern 130 is formed on the sidewall of the preliminary channel 120, and then a first gate electrode 140 is formed between the first gate insulation patterns 130. In one embodiment, the auxiliary channels 120 extend in a first direction (D1) and are provided in a plurality of locations spaced apart from one another along a second direction (D2).

[0043] The first gate insulating pattern 130 is formed by forming a first gate insulating film on the preliminary channel 120 and the buried oxide film 110 and then performing an anisotropic etching process thereon. In one embodiment, the first gate insulating pattern 130 is formed on both side walls of the preliminary channel 120 in the second direction (D2) and extends in the first direction (D1). The first gate electrode 140 is formed by forming a first gate electrode film on the preliminary channel 120, the first gate insulation pattern 130, and the buried oxide film 110, and then performing a planarization process on the first gate electrode film until the top surface of the preliminary channel 120 is exposed.

[0044] Planarization steps include, for example, chemical mechanical polishing (CMP) steps and / or etch-back steps. Meanwhile, the preliminary channel 120 and the upper portion of the first gate insulating pattern 130 are partially removed by a planarization process. In one embodiment, the first gate electrodes 140 extend in a first direction (D1) between the first gate insulation patterns 130 and are provided in a plurality of locations spaced apart from each other along a second direction (D2).

[0045] As shown in Figures 7 and 8, after patterning the preliminary channel 120 to form a channel 125, a second gate insulation pattern 150 is formed on the sidewalls of the channel 125 and the first gate insulation pattern 130, and a second gate electrode 160 is formed between the second gate insulation patterns 150. In an embodiment, the channels 125 are provided spaced apart from each other along the first direction (D1) from one sidewall of each of the first gate insulating patterns 130 extending in the first direction (D1). The second gate insulating pattern 150 is formed by forming a second gate insulating film on the channel 125, the first gate insulating pattern 130, the first gate electrode 140, and the buried oxide film 110, and then performing an anisotropic etching process thereon.

[0046] In one embodiment, the second gate insulating pattern 150 is formed on one sidewall in the second direction (D2) of the channel 125 and the first gate insulating pattern 130 and extends in the first direction (D1). In one embodiment, the second gate insulation pattern 150 may have a staggered shape, bent in the second direction (D2) and extending in the first direction (D1), instead of a line shape extending linearly in the first direction (D1) when viewed from above. The second gate electrode 160 is formed by forming a second gate electrode film on the channel 125, the first and second gate insulation patterns (130, 150), and the buried oxide film 110, and then performing a planarization process on the second gate electrode film until the top surface of the channel 125 is exposed.

[0047] Planarization steps include, for example, chemical mechanical polishing (CMP) steps and / or etch-back steps. Meanwhile, the channel 125 and the upper portions of the first and second gate insulating patterns 130 and 150 are partially removed by the planarization process. In one embodiment, the second gate electrodes 160 extend in the first direction (D1) between the second gate insulating patterns 150 and are provided in a plurality of locations spaced apart from each other along the second direction (D2). In one embodiment, the second gate electrode 160, when viewed from above, in addition to having a line shape extending linearly in the first direction (D1), further includes protrusions that are spaced apart from each other along the first direction (D1) and protrude in a second direction (D2).

[0048] As shown in Figures 9 and 10, a first interlayer insulating film 170 is formed on the first and second gate electrodes (140, 160), the channel 125, and the first and second gate insulation patterns (130, 150), and then a landing pad 180 is formed through the first interlayer insulating film 170 to contact the upper surface of the channel 125. In one embodiment, the landing pads 180 are provided spaced apart from each other along the first and second directions (D1, D2) and contact the upper surfaces of the corresponding channels 125.

[0049] As shown in Figures 11 to 13, a first capacitor electrode 190 is formed on the first interlayer insulating film 170 and the landing pad 180, contacting the upper surface of the landing pad 180, and then a dielectric film 200 is formed on the first capacitor electrode 190, the landing pad 180, and the first interlayer insulating film 170, and a second capacitor electrode 210 is formed on the dielectric film 200. In one embodiment, the first capacitor electrodes 190 are provided in a plurality of locations spaced apart from each other along the first and second directions (D1, D2) and contact the upper surfaces of the corresponding landing pads 180. The first capacitor electrode 190 , the dielectric film 200 , and the second capacitor electrode 210 form a capacitor 220 .

[0050] As shown in FIGS. 14 to 16, a second interlayer insulating film 230 covering the capacitor 220 is formed on the first interlayer insulating film 170, and then a first bonding film 240 is formed on the second interlayer insulating film 230. In addition, a second bonding film 310 is formed on the second substrate 300, and after these are turned upside down, the first substrate structure and the second substrate 300 are bonded to each other such that the second bonding film 310 and the first bonding film 240 come into contact with each other.

[0051] Thereafter, the bonded first substrate structure and second substrate 300 are inverted upside down, and the first bulk 100 and buried oxide film 110 included in the first substrate structure are removed, thereby exposing the top surfaces of the first and second gate electrodes (140, 160), the channel 125, and the first and second gate insulation patterns (130, 150). Thereafter, upper portions of the first and second gate electrodes 140 and 160 are removed to form first and second recesses, respectively, and first and second cap patterns 250 and 255 are formed to fill the first and second recesses.

[0052] Thereafter, a first conductive film, a barrier film, and a second conductive film are sequentially stacked on the first and second cap patterns (250, 255), the channel 125, and the first and second gate insulation patterns (130, 150), and then partially etched to form a first conductive pattern 400, a barrier pattern 410, and a second conductive pattern 420, respectively, thereby forming a bit line structure 430 including these. In one embodiment, the bit line structures 430 extend in the second direction (D2) and are provided in a plurality spaced apart relation to each other along the first direction (D1).

[0053] The etching process also partially removes the channel 125 and the upper portions of the first and second gate insulation patterns (130, 150), thereby forming a third recess 440 between the bit line structures 430 that exposes the upper surfaces of the channel 125 and the first and second gate insulation patterns (130, 150).

[0054] As shown in Figures 17 to 19, after forming an insulating film 450 on the bit line structure 430, the first and second cap patterns (250, 255), the channel 125, and the first and second gate insulation patterns (130, 150), a bit line shield structure 460 is formed on the insulating film 450 by filling the third recess 440 and having a top surface higher than the top surface of the insulating film 450. The bitline shield structure 460 includes a bitline shield plate 462 formed at a height above the top surface of the bitline structure 430 and a bitline shield fin 464 formed at a height below the bitline shield plate 462 . In one embodiment, the bit line shield plate 462 has a flat plate shape, and the bit line shield fins 464 extend in the second direction (D2) and are provided spaced apart from each other along the first direction (D1).

[0055] Then, the bit line shield plate 462 included in the bit line shield structure 460 and the insulating film 450 formed thereunder are partially removed to form a first opening 470 that exposes the top surface of the second conductive pattern 420 included in the bit line structure 430. In one embodiment, the first openings 470 are provided spaced apart from each other, for example along a fourth direction that forms an acute angle with the first and second directions (D1, D2), but the present invention is not limited thereto.

[0056] As shown in FIGS. 20 to 22, a third interlayer insulating film 480 is formed on the bit line structure 430 and the bit line shield structure 460 to fill the first opening 470. A third bonding film 490 is formed on the third interlayer insulating film 480. Then, a first contact plug 500 is formed that penetrates the lower part of the third bonding film 490 and the third interlayer insulating film 480 to contact an upper surface of the second conductive pattern 420 included in the bit line structure 430, and a first bonding pad 510 is formed that penetrates the upper part of the third bonding film 490 to contact an upper surface of the first contact plug 500. In one embodiment, the first contact plugs 500 and the first bonding pads 510 correspond to the first openings 470 and are spaced apart from one another, for example along a fourth direction that forms an acute angle with the first and second directions (D1, D2).

[0057] As shown in FIGS. 23 and 24, a transistor is formed on a third substrate 600, a fourth interlayer insulating film 650 covering the transistor is formed, and then a second contact plug 640 penetrating the fourth interlayer insulating film 650 is formed. The transistor includes a gate structure 630 formed on a third substrate 600 and a source-drain layer 605 formed on an adjacent portion of the third substrate 600, and the gate structure 630 includes a third gate insulating pattern 610 and a third gate electrode 620 which are sequentially stacked.

[0058] Thereafter, a fifth interlayer insulating film 660 , a first wiring 670 , a first via 680 , and a second wiring 690 are formed on the fourth interlayer insulating film 650 and the second contact plug 640 . Thereafter, a sixth interlayer insulating film 700, a second via 710, and a third wiring 720 are formed on the fifth interlayer insulating film 660 and the second wiring 690. Thereafter, a fourth bonding film 730 , a third contact plug 740 , and a second bonding pad 750 are formed on the sixth interlayer insulating film 700 and the third wiring 720 .

[0059] Referring again to Figures 1 to 4, after the third substrate 600 is turned upside down, the third substrate 600 is bonded to the first substrate structure and the second substrate 300 such that the fourth bonding film 730 and the third bonding film 490 come into contact with each other. In one embodiment, the bottom surface of the second bond pad 750 formed in the fourth bonding film 730 contacts the top surface of the first bond pad 510 formed in the third bonding film 490 . Thereafter, the first substrate structure and the second and third substrates (300, 600) bonded to each other are further inverted upside down, and then the second substrate 300 and the first and second bonding films (240, 310) are removed, thereby completing the manufacture of the semiconductor device of the present invention.

[0060] 25 and 26 are perspective views illustrating a bit line shield structure included in a semiconductor device according to an embodiment of the present invention, and correspond to FIG. 4. FIG. As shown in FIG. 25, the bitline shield plate 462 included in the bitline shield structure 460 includes a second opening 472 therethrough. In one embodiment, the second opening 472 extends along a fourth direction that forms an acute angle with the first and second directions (D1, D2). Thus, the bit line structure 430 is electrically connected to the lower circuit pattern through the first contact plug 500 penetrating the portion of the third interlayer insulating film 480 formed in the second opening 472, and the first and second bond pads (510, 750) and third contact plug 740 connected thereto.

[0061] As shown in FIG. 26, the bitline shield plate 462 included in the bitline shield structure 460 includes a third opening 474 therethrough. In one embodiment, the third openings 474 extend in the second direction (D2) and are provided in a plurality of locations spaced apart from each other along the first direction (D1).

[0062] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0063] 100 First Bulk 110 Buried oxide film 120 spare channels 125 Channels 130, 150, 610 (1st to 3rd) gate insulation patterns 140, 160, 620 (first to third) gate electrodes 170, 230, 480, 650, 660, 700 (1st to 6th) interlayer insulating films 180 Landing Pad 190, 210 (first, second) capacitor electrodes 200 Dielectric film 220 Capacitor 240, 310, 490, 730 (1st to 4th) bonding films 250, 255 (1st, 2nd) cap patterns 300, 600 (2nd, 3rd) boards 400, 420 (first and second) conductive patterns 410 Barrier Pattern 430 Bit Line Structure 450 Insulating film 460 Bit Line Shielding Structure 462 Bit Line Shield Plate 464 bit line shield fins 470 First Opening 500 First Contact Plug 510, 750 (1st, 2nd) bonding pads 605 Source / Drain layer 630 Gate Structure 670, 690 (1st, 2nd) wiring 680, 710 (1st, 2nd) vias

Claims

1. a lower circuit pattern formed on the substrate; a bit line shield structure formed on the lower circuit pattern; a first interlayer insulating film formed in an opening penetrating the bit line shield structure; a bit line structure formed on the bit line shield structure and at least partially overlapping the bit line shield structure in a direction perpendicular to an upper surface of the substrate; a first contact plug penetrating the first interlayer insulating film, contacting the bit line structure and electrically connecting to the lower circuit pattern; a channel formed over the bit line structure; a capacitor formed on and electrically connected to the channel.

2. the bit line structures are provided in a plurality of locations spaced apart from one another along a first direction parallel to an upper surface of the substrate; 2. The semiconductor device according to claim 1, wherein each of the bit line structures extends in a second direction parallel to a top surface of the substrate and perpendicular to the first direction.

3. 3. The semiconductor device according to claim 2, wherein the openings are provided in a plurality at intervals along a third direction that is parallel to an upper surface of the substrate and forms an acute angle with the first and second directions.

4. 3. The semiconductor device according to claim 2, wherein the opening extends in a third direction that is parallel to an upper surface of the substrate and forms an acute angle with the first and second directions.

5. The openings are provided in a plurality of locations spaced apart from each other along the first direction, 3. The semiconductor device according to claim 2, wherein each of the openings extends in the second direction.

6. The bit line shield structure includes: a bit line shield plate having a flat shape parallel to an upper surface of the substrate; 2. The semiconductor device according to claim 1, further comprising: bit line shield fins formed on the bit line shield plate, protruding in a direction perpendicular to an upper surface of the substrate, extending in the second direction, and spaced apart from each other along the first direction.

7. The semiconductor device according to claim 6 , wherein the bit line structure is formed between the bit line shield fins adjacent to each other in the first direction.

8. a second interlayer insulating film formed on the substrate and covering the lower circuit pattern; a first bonding film formed on the second interlayer insulating film; A second bonding film formed on the first bonding film, the first interlayer insulating film is formed on the second bonding film and covers a lower surface of the bit line shield structure; 2. The semiconductor device according to claim 1, wherein the first contact plug partially penetrates the second bonding film.

9. a first bonding pad formed in the second bonding film and in contact with a lower surface of the first contact plug; a second contact plug formed in the first bonding film and in contact with the lower circuit pattern; 9. The semiconductor device according to claim 8, further comprising: a second bonding pad formed in the first bonding film and in contact with an upper surface of the second contact plug and a lower surface of the first bonding pad.

10. the first and second bonding films each contain silicon carbonitride (SiCN); 10. The semiconductor device of claim 9, wherein the first and second bond pads each comprise copper or aluminum.

11. a bit line shield plate formed on a substrate and parallel to an upper surface of the substrate; a bit line shield structure formed on the bit line shield plate, protruding in a direction perpendicular to an upper surface of the substrate, the bit line shield structure including bit line shield fins spaced apart from each other along a first direction parallel to the upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction; a plurality of bit line structures formed on the bit line shield plate, each of the bit line shield structures being formed between adjacent bit line shield fins along the first direction and each of the bit line structures extending in the second direction; channels respectively formed on the bit line structures; a capacitor formed on and electrically connected to the channel, the bit line shield plate has a plurality of openings formed therethrough; Each of the bit line structures overlaps at least one of the openings in the vertical direction.

12. 12. The semiconductor device according to claim 11, wherein the openings are provided in a plurality of locations spaced apart from each other along a third direction that forms an acute angle with the first and second directions.

13. 12. The semiconductor device according to claim 11, wherein the opening extends in a third direction that is parallel to an upper surface of the substrate and forms an acute angle with the first and second directions.

14. 12. The semiconductor device according to claim 11, wherein the openings are provided in a plurality of locations spaced apart from one another along the first direction, and each of the openings extends in the second direction.

15. an interlayer insulating film formed in the opening; 12. The semiconductor device according to claim 11, further comprising a contact plug penetrating the interlayer insulating film and contacting a lower surface of the bit line structure. Semiconductor device.

16. Further comprising a lower circuit pattern formed on the substrate; The semiconductor device according to claim 15 , wherein the contact plug is electrically connected to the lower circuit pattern.

17. a lower circuit pattern formed on the substrate; a first bonding film and a second bonding film laminated on the lower circuit pattern along a direction perpendicular to the upper surface of the substrate; a bit line shield structure formed on the second bonding film and including an opening; an interlayer insulating film formed between the second bonding film and the bit line shield structure, covering a lower surface of the bit line shield structure and filling the opening; a bit line structure formed on the bit line shield structure and at least partially overlapping the bit line shield structure in the vertical direction; a contact plug that penetrates the interlayer insulating film formed in the opening, contacts the bit line structure, and is electrically connected to the lower circuit pattern; a channel formed over the bit line structure; a capacitor formed on and electrically connected to the channel.

18. the bit line structures are provided in a plurality of locations spaced apart from one another along a first direction parallel to an upper surface of the substrate; 20. The semiconductor device of claim 17, wherein each of the bit line structures extends in a second direction parallel to a top surface of the substrate and perpendicular to the first direction.

19. 20. The semiconductor device according to claim 18, wherein the openings are provided in a plurality at intervals along a third direction that is parallel to an upper surface of the substrate and forms an acute angle with the first and second directions.

20. The bit line shield structure includes: a bit line shield plate having a flat shape parallel to an upper surface of the substrate; 20. The semiconductor device of claim 18, further comprising: bit line shield fins formed on the bit line shield plate, protruding in the vertical direction, extending in the second direction, and spaced apart from each other along the first direction.

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