Nitride semiconductor device

Abstract

To improve a proof pressure and reliability of a nitride semiconductor device.SOLUTION: A nitride semiconductor device 100 includes: a semiconductor substrate 18; and a nitride semiconductor layer 20 formed above the semiconductor substrate 18. The nitride semiconductor layer 20 includes: a first superlattice buffer layer 106; a second superlattice buffer layer 108 formed above the first superlattice buffer layer 106; and an electron transport layer 24 formed above the second superlattice buffer layer 108. The first superlattice buffer layer 106 includes first superlattice structure including a first layer and a second layer which are alternately arranged. The first layer is constructed by AlxGa1-xN, here, an inequality of 0<x<1 is satisfied. The second layer is constituted of GaN. The second superlattice buffer layer 108 includes second superlattice structure including a third layer and a fourth layer which are alternately arranged. The third layer is constituted of AlyGa1-yN, here, an inequality of 0<y<x is satisfied. The fourth layer is constituted of GaN.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transit layer formed of a gallium nitride (GaN) layer, and an electron supply layer formed of an aluminum gallium nitride (AlGaN) layer. In the electron transit layer, a 2DEG is formed near the interface of the heterojunction between the electron transit layer and the electron supply layer. In the nitride semiconductor device of Patent Document 1, a GaN layer doped with acceptor-type impurities (p-type GaN layer) is provided on the electron supply layer and directly below the gate electrode. In this configuration, the p-type GaN layer raises the energy level of the conduction band near the heterojunction interface between the electron transit layer and the electron supply layer in the region directly below it, so that the channel directly below the p-type GaN layer can be eliminated. This realizes a normally-off operation of the nitride semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-73506 A

[0005] [overview] In a nitride semiconductor device, a nitride semiconductor layer (e.g., a GaN layer, an AlGaN layer, etc.) is formed on a semiconductor substrate made of a material different from that of the nitride semiconductor layer. The lattice constant mismatch between the semiconductor substrate and the nitride semiconductor layer causes misfit dislocations in the nitride semiconductor layer, and as a result, a plurality of dislocation lines can be formed in the nitride semiconductor layer. Such dislocation lines in the nitride semiconductor layer can cause a decrease in the breakdown voltage of the nitride semiconductor device, an increase in leakage current, etc.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a nitride semiconductor layer formed above the semiconductor substrate, and at least one electrode formed above the nitride semiconductor layer. The nitride semiconductor layer includes a first superlattice buffer layer, a second superlattice buffer layer formed above the first superlattice buffer layer, an electron traveling layer formed above the second superlattice buffer layer and composed of a first nitride semiconductor, and an electron supply layer formed above the electron traveling layer and composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The first superlattice buffer layer has a first superlattice structure including a first layer and a second layer arranged alternately, the first layer is composed of Al x Ga 1-x N, where 0 < x < 1, and the second layer is composed of GaN. The second superlattice buffer layer has a second superlattice structure including a third layer and a fourth layer arranged alternately, the third layer is composed of Al y Ga 1-y N, where 0 < y < x, and the fourth layer is composed of GaN.

[0007] Other features and aspects will become apparent from the following detailed description, drawings, and claims.

Brief Description of the Drawings

[0008] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Diagram 2]FIG. 2 is an enlarged plan view of the nitride semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic diagram showing a laminated structure of a part of a nitride semiconductor layer formed above a semiconductor substrate. [Diagram 5] FIG. 5 is a schematic diagram for explaining the mechanism by which dislocation lines disappear due to a superlattice structure. [Figure 6] FIG. 6 is a schematic diagram showing a first modified example of the laminated structure of a part of the nitride semiconductor layer formed above the semiconductor substrate. [Figure 7] FIG. 7 is a schematic diagram showing a second modification of the laminate structure of a portion of the nitride semiconductor layer formed above the semiconductor substrate. [Figure 8] FIG. 8 is a schematic diagram showing a third modification of the laminate structure of a part of the nitride semiconductor layer formed above the semiconductor substrate. [Figure 9] FIG. 9 is a schematic cross-sectional view of a nitride semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a schematic diagram showing a laminated structure of a part of a nitride semiconductor layer formed above a semiconductor substrate.

[0009] [Detailed Description] Hereinafter, some embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0010] The following detailed description provides a comprehensive understanding of the described method, device, and / or system. Modifications and equivalents of the described method, device, and / or system will be apparent to those skilled in the art. Except for operations that necessarily occur in a specific order, the order of operations is exemplary and may be changed as is apparent to those skilled in the art. Descriptions of functions and structures that are well known to those skilled in the art may be omitted.

[0011] Exemplary embodiments may have different forms and are not limited to the examples set forth, however the examples set forth are sufficient and complete to convey the full scope of the present disclosure to those skilled in the art.

[0012] First Embodiment (Schematic structure of nitride semiconductor device) A schematic structure of an exemplary nitride semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1 to 3. In this embodiment, the nitride semiconductor device 10 may be configured as a semiconductor chip on which a high electron mobility transistor (HEMT) is formed. FIG. 1 is a schematic plan view of the exemplary nitride semiconductor device 10. FIG. 2 is an enlarged plan view of the nitride semiconductor device 10. FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F3-F3 in FIG. 2.

[0013] 1 to 3, the Z-axis direction of the mutually orthogonal X, Y and Z axes is a direction orthogonal to the surface of the semiconductor substrate 18 (see FIG. 3). Note that the term "planar view" used in this specification means viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless otherwise specified explicitly.

[0014] 1, the nitride semiconductor device 10 may include a gate pad 12, a source pad 14, and a drain pad 16 formed on an upper surface 10A having a rectangular shape in a plan view. The gate pad 12, the source pad 14, and the drain pad 16 may be electrically connected to a gate electrode, a source electrode, and a drain electrode (for example, the gate electrode 32, the source electrode 36, and the drain electrode 38 shown in FIG. 2) of a HEMT formed in a semiconductor chip, respectively. The gate pad 12, the source pad 14, and the drain pad 16 may constitute external connection terminals of the nitride semiconductor device 10.

[0015] 1, the nitride semiconductor device 10 includes a plurality of source pads 14 and a plurality of drain pads 16. The plurality of source pads 14 and the plurality of drain pads 16 may be arranged alternately in the X-axis direction. The number of pads 12, 14, and 16 arranged on the upper surface 10A can be determined arbitrarily according to the needs of a particular application.

[0016] The layout of the gate pad 12, the source pad 14, and the drain pad 16 is not limited to the example shown in Figure 1. The gate pad 12, the source pad 14, and the drain pad 16 can be arranged in any other layout.

[0017] FIG. 3 shows a schematic cross-sectional view of an active region of a HEMT located below the source pad 14 or drain pad 16 shown in FIG. 1. As shown in FIG. 3, the nitride semiconductor device 10 includes a semiconductor substrate 18 and a nitride semiconductor layer 20 formed above the semiconductor substrate 18. In this disclosure, the term "above" has the meaning of both "on" and "above" unless expressly stated otherwise. That is, the expression "a first layer is formed above a second layer" does not exclude a structure in which the first layer can be directly disposed on the second layer in contact with the second layer in some embodiments, but other layers are formed between the first layer and the second layer in other embodiments.

[0018] The semiconductor substrate 18 may be formed of silicon (Si), silicon carbide (SiC), sapphire (Al2O3), or other substrate materials. The semiconductor substrate 18 may be composed of a material different from that of the nitride semiconductor layer 20. In one example, the semiconductor substrate 18 may be a Si substrate, particularly a Si substrate with a (111) plane as the growth plane. The semiconductor substrate 18 may have an off-angle greater than 0°. The off-angle of the semiconductor substrate 18 may be greater than 0° and equal to or less than 1°. The thickness of the semiconductor substrate 18 may be, for example, 200 μm or more and 1500 μm or less.

[0019] The nitride semiconductor layer 20 may include a buffer layer 22 formed above the semiconductor substrate 18, an electron transit layer 24 formed above the buffer layer 22, and an electron supply layer 26 formed above the electron transit layer 24. In this embodiment, the nitride semiconductor layer 20 may have a bottom surface 20B in contact with the semiconductor substrate 18. The bottom surface 20B of the nitride semiconductor layer 20 may be included in the buffer layer 22.

[0020] The buffer layer 22 may include one or more layers made of a nitride semiconductor. The buffer layer 22 may be made of any material capable of suppressing the occurrence of warping or cracks caused by the difference in thermal expansion coefficient between the semiconductor substrate 18 and layers (such as an electron transit layer 24 and an electron supply layer 26 described below) formed above the buffer layer 22. Details of the buffer layer 22 will be described later with reference to FIG. 4.

[0021] The electron travel layer 24 may be in contact with the buffer layer 22. The electron travel layer 24 is made of a first nitride semiconductor. The first nitride semiconductor may contain GaN. In this embodiment, the first nitride semiconductor may contain GaN as a main component. The thickness of the electron travel layer 24 may be, for example, 0.5 μm or more and 2 μm or less. Preferably, the thickness of the electron travel layer 24 may be 760 nm or less. More preferably, the thickness of the electron travel layer 24 may be 500 nm or more and 760 nm or less.

[0022] In order to suppress the leakage current in the electron transport layer 24, impurities may be introduced into a part of the electron transport layer 24 to make the region other than the surface layer region of the electron transport layer 24 semi-insulating. In this case, the impurity may be, for example, C. The impurity concentration in the electron transport layer 24 may be, for example, 4×10 16 cm -3 or more. That is, the electron transport layer 24 may include a plurality of GaN layers with different impurity concentrations, and in one example, a C-doped GaN layer and an undoped GaN layer. In this case, the C-doped GaN layer may be in contact with the buffer layer 22. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 17 cm -3 or more and 9×10 19 cm -3 or less. The undoped GaN layer is formed on the C-doped GaN layer and may have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer may be in contact with the electron supply layer 26. In one example, the electron transport layer 24 may include a C-doped GaN layer with a thickness of 0.4 μm and an undoped GaN layer with a thickness of 0.4 μm. Also, the C concentration in the C-doped GaN layer may be about 2×10 19 cm -3 or so.

[0023] The electron supply layer 26 is composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The second nitride semiconductor may include AlGaN. In the present embodiment, the second nitride semiconductor may include AlGaN as a main component. In one example, the electron supply layer 26 is composed of Al a Ga 1-a N, where 0.1 < a < 0.4 may be satisfied, and more preferably, 0.1 < a < 0.3 may be satisfied. The electron supply layer 26 may have a thickness of 5 nm or more and 20 nm or less. More preferably, the electron supply layer 26 may have a thickness of 8 nm or more.

[0024] The first nitride semiconductor (e.g., GaN) constituting the electron transit layer 24 and the second nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 26 have different lattice constants. Therefore, the electron transit layer 24 and the electron supply layer 26 form a lattice-mismatched heterojunction. The energy level of the conduction band of the electron transit layer 24 near the heterojunction interface is lower than the Fermi level due to spontaneous polarization of the electron transit layer 24 and the electron supply layer 26 and piezoelectric polarization caused by crystal distortion near the heterojunction interface. As a result, a two-dimensional electron gas (2DEG) 28 spreads in the electron transit layer 24 at a position close to the heterojunction interface between the electron transit layer 24 and the electron supply layer 26 (for example, within a range of about several nm from the interface). The 2DEG 28 in the electron transit layer 24 functions as a channel of the nitride semiconductor device 10. The sheet carrier density of the 2DEG 28 generated in the electron transit layer 24 can be increased by increasing at least one of the Al composition and the thickness of the electron supply layer 26.

[0025] The nitride semiconductor layer 20 may further include a gate layer 30 formed above the electron supply layer 26. The gate layer 30 may be in contact with a part of the electron supply layer 26. The gate layer 30 includes a bottom surface 30B in contact with the electron supply layer 26 and an upper surface 30A opposite to the bottom surface 30B.

[0026] The gate layer 30 is composed of a third nitride semiconductor containing acceptor-type impurities. The third nitride semiconductor may contain GaN. In this embodiment, the third nitride semiconductor may contain GaN as a main component. The acceptor-type impurities may contain at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 30 is 7×10 18 cm -3 More than 1×10 20 cm -3 The gate layer 30 may be a gallium nitride layer doped with acceptor-type impurities (a p-type GaN layer).

[0027] The nitride semiconductor device 10 may further include a gate electrode 32. The gate electrode 32 may be in contact with the upper surface 30A of the gate layer 30. The gate electrode 32 may be composed of one or more metal layers. In one example, the gate electrode 32 may be composed of titanium nitride (TiN). In another example, the gate electrode 32 may include a first metal layer composed of Ti and a second metal layer composed of TiN provided on the first metal layer. The gate electrode 32 can form a Schottky junction with the gate layer 30. The thickness of the gate electrode 32 may be, for example, 50 nm or more and 200 nm or less. The gate electrode 32 may have an area smaller than the upper surface 30A of the gate layer 30 in a plan view.

[0028] The nitride semiconductor device 10 may further include a passivation layer 34 covering the electron supply layer 26, the gate layer 30, and the gate electrode 32. The passivation layer 34 has a first opening 34A and a second opening 34B. The first opening 34A and the second opening 34B are spaced apart in the X-axis direction. The gate layer 30 is located between the first opening 34A and the second opening 34B. More specifically, the gate layer 30 may be located between the first opening 34A and the second opening 34B, and closer to the first opening 34A than the second opening 34B. The passivation layer 34 may be formed of at least one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON), for example. The thickness of the passivation layer 34 may be, for example, 80 nm or more and 150 nm or less.

[0029] The nitride semiconductor device 10 further includes a source electrode 36 in contact with the electron supply layer 26 through the first opening 34A, and a drain electrode 38 in contact with the electron supply layer 26 through the second opening 34B. The source electrode 36 and the drain electrode 38 may be formed of one or more metal layers (e.g., any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, etc.).

[0030] At least a portion of the source electrode 36 is filled in the first opening 34A, and therefore can make ohmic contact with the 2DEG 28 directly below the electron supply layer 26 through the first opening 34A. Similarly, at least a portion of the drain electrode 38 is filled in the second opening 34B, and therefore can make ohmic contact with the 2DEG 28 directly below the electron supply layer 26 through the second opening 34B.

[0031] Thus, the nitride semiconductor device 10 includes at least one electrode (eg, the gate electrode 32, the source electrode 36, or the drain electrode 38) formed above the nitride semiconductor layer 20.

[0032] (field plate electrode) The nitride semiconductor device 10 may optionally further include a field plate electrode 40 formed on the passivation layer 34 and extending at least partially into a region between the gate layer 30 and the drain electrode 38 in a plan view. In the example shown in FIG. 3, the field plate electrode 40 is formed integrally with the source electrode 36. Of the electrodes formed integrally, the source electrode 36 may include at least a portion embedded in the first opening 34A of the passivation layer 34, and the field plate electrode 40 may include the remaining portion. Note that the field plate electrode 40 may not necessarily be continuous with the source electrode 36 as long as it is electrically connected to the source electrode 36.

[0033] The field plate electrode 40 is spaced apart from the drain electrode 38. The field plate electrode 40 may include an end portion 40A located between the drain electrode 38 (second opening 34B) and the gate layer 30 in a plan view.

[0034] The field plate electrode 40 can alleviate electric field concentration near the end of the gate electrode 32 when a drain voltage is applied to the drain electrode 38 in a zero bias state where no gate voltage is applied to the gate electrode 32.

[0035] (Cross-sectional shape of gate layer) The gate layer 30 may include a ridge portion 42 that is in contact with the electron supply layer 26 and includes an upper surface 30A, and a first extension portion 44 and a second extension portion 46 that are in contact with the electron supply layer 26 and extend outward from the ridge portion 42 in a planar view and are thinner than the ridge portion 42. Note that in the present disclosure, the first extension portion 44 and the second extension portion 46 may be collectively referred to as the "extension portion."

[0036] The first extension portion 44 extends from the ridge portion 42 toward the first opening 34A. The first extension portion 44 partially covers the surface of the electron supply layer 26 between the ridge portion 42 and the first opening 34A in a plan view. The first extension portion 44 does not reach the source electrode 36 embedded in the first opening 34A.

[0037] The second extension portion 46 extends from the ridge portion 42 toward the second opening 34B. The second extension portion 46 partially covers the surface of the electron supply layer 26 between the ridge portion 42 and the second opening 34B in a plan view. The second extension portion 46 does not reach the drain electrode 38 embedded in the second opening 34B.

[0038] The ridge portion 42 is between the first extension portion 44 and the second extension portion 46, and is formed integrally with the first extension portion 44 and the second extension portion 46. Due to the presence of the first extension portion 44 and the second extension portion 46, the bottom surface 30B of the gate layer 30 has a larger area than the top surface 30A. In the example shown in FIG. 3, the second extension portion 46 may extend longer toward the outside of the ridge portion 42 in a planar view than the first extension portion 44. That is, the second extension portion 46 may have a larger dimension in the X-axis direction than the first extension portion 44. The first extension portion 44 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.3 μm or less. On the other hand, the second extension portion 46 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.6 μm or less.

[0039] The ridge portion 42 corresponds to a relatively thick portion of the gate layer 30. The ridge portion 42 may have a thickness of, for example, 80 nm or more and 150 nm or less. In one example, the ridge portion 42 may have a thickness greater than 110 nm. The first extension portion 44 and the second extension portion 46 have a thickness smaller than the thickness of the ridge portion 42. In one example, the first extension portion 44 and the second extension portion 46 may have a thickness equal to or less than half the thickness of the ridge portion 42.

[0040] Each of the first extension 44 and the second extension 46 may include a flat portion having a substantially constant thickness. In one example, the flat portion of the first extension 44 and the second extension 46 may have a thickness of 5 nm or more and 25 nm or less. In this specification, the term "substantially constant thickness" refers to the thickness being within the range of manufacturing variation (e.g., 20%). As shown in the figure, each of the first extension 44 and the second extension 46 may further include an intermediate portion between the flat portion and the ridge portion 42 that is thicker than the flat portion. In one example, the intermediate portion may have a thickness that gradually decreases as it moves away from the ridge portion 42.

[0041] When the field plate electrode 40 is provided, an end 40A of the field plate electrode 40 may be located between the second extension portion 46 and the drain electrode 38 in a plan view. (Plane layout of nitride semiconductor device) Next, an example of a planar layout of an active region of the nitride semiconductor device 10 will be described with reference to Fig. 2. In Fig. 2, the gate electrode 32, the source electrode 36, the drain electrode 38, and the field plate electrode 40 are depicted with dashed lines. In addition, for the passivation layer 34, the first opening 34A and the second opening 34B are depicted with solid lines, and the other portions are shown transparently. In Fig. 2, the first extension portion 44 and the second extension portion 46 are omitted.

[0042] 2, the gate layer 30 may be formed to surround the drain electrode 38 in a plan view. The gate layer 30 may include a main body portion 48 extending in the Y-axis direction and a connection portion 50 connecting two adjacent main body portions 48. The main body portion 48 of the gate layer 30 is disposed between the first opening 34A and the second opening 34B of the passivation layer 34.

[0043] The gate electrode 32 is disposed so as to overlap with the gate layer 30 in a planar view. Thus, like the gate layer 30, the gate electrode 32 may be formed so as to surround the drain electrode 38 in a planar view. The gate electrode 32 may include a main body portion 52 extending in the Y-axis direction and a connection portion 54 connecting two adjacent main body portions 52.

[0044] The nitride semiconductor device 10 may include a gate wiring 56, a source wiring 58, and a drain wiring 60. In FIG. 2, the gate wiring 56, the source wiring 58, and the drain wiring 60 are depicted by dashed lines. The gate wiring 56, the source wiring 58, and the drain wiring 60 are located above the source electrode 36 and the drain electrode 38 in the Z-axis direction. The gate wiring 56 may extend in the X-axis direction and be disposed above the connection portion 54 of the gate electrode 32. The source wiring 58 and the drain wiring 60 may extend in the X-axis direction and be disposed so as to intersect with the source electrode 36 and the drain electrode 38 in a plan view. In one example, the gate electrode 32 may be electrically connected to the gate wiring 56 through a via 62 disposed above the connection portion 54. The source electrode 36 may be electrically connected to the source wiring 58 through a via 64. The drain electrode 38 may be electrically connected to the drain wiring 60 through a via 66. The gate wiring 56, the source wiring 58, and the drain wiring 60 may be electrically connected to the gate pad 12, the source pad 14, and the drain pad 16 shown in FIG. 1, respectively.

[0045] The planar layout of the active region of the nitride semiconductor device 10 is not limited to the example shown in Fig. 2. Any other planar layout may be used. (Details of the buffer layer) Next, with reference to FIG. 4, the details of the buffer layer 22 included in the nitride semiconductor layer 20 will be described. FIG. 4 is a schematic diagram showing a partial stacked structure of the nitride semiconductor layer 20 formed above the semiconductor substrate 18.

[0046] As shown in FIG. 4, the buffer layer 22 may include a base buffer layer 68 in contact with the semiconductor substrate 18. In one example, the base buffer layer 68 may be composed of aluminum nitride (AlN). The thickness of the base buffer layer 68 may be 100 nm or more and 300 nm or less.

[0047] The buffer layer 22 may further include a lower buffer layer 70, an intermediate buffer layer 72, and an upper buffer layer 74. In the present embodiment, the lower buffer layer 70 may be in contact with the base buffer layer 68.

[0048] The lower buffer layer 70 may have a first superlattice structure SL1 including a first layer SL1A and a second layer SL1B arranged alternately. The first layer SL1A is composed of Al x Ga 1-x N, where 0 < x < 1. x preferably satisfies 0.35 < x < 0.9, and more preferably 0.6 < x < 0.9. The second layer SL1B is composed of GaN. In the first superlattice structure SL1, the two-layer structure of the first layer SL1A and the second layer SL1B may be repeated 2 or more times and 500 or less times, and more preferably 5 or more times and 100 or less times. In the present embodiment, since the lower buffer layer 70 has the first superlattice structure SL1, it may also be referred to as the first superlattice buffer layer. The first layer SL1A located at the lowermost part of the first superlattice buffer layer (lower buffer layer 70) may be in contact with the base buffer layer 68.

[0049] The thickness of the first layer SL1A may be 5 nm or more and 7 nm or less. The thickness of the second layer SL1B may be 2 nm or more and 3 nm or less. The thickness of the first superlattice buffer layer (lower buffer layer 70) may be 100 nm or more. More preferably, the thickness of the first superlattice buffer layer (lower buffer layer 70) may be 100 nm or more and 300 nm or less.

[0050] The first superlattice buffer layer (lower buffer layer 70) may contain at least one of iron (Fe), carbon (C), and silicon (Si) as an impurity. The impurity concentration of the first superlattice buffer layer (lower buffer layer 70) can be, for example, 4×10 16 cm -3 or more.

[0051] The intermediate buffer layer 72 may have a second superlattice structure SL2 including a third layer SL2A and a fourth layer SL2B arranged alternately. The third layer SL2A is composed of Al y Ga 1-y N, where 0 < y < x. y preferably satisfies 0.1 < y < 0.65, and more preferably may satisfy 0.35 < y < 0.65. The fourth layer SL2B is composed of GaN. In the second superlattice structure SL2, the two-layer structure of the third layer SL2A and the fourth layer SL2B may be repeated 2 or more times and 500 or less times, and more preferably may be repeated 5 or more times and 100 or less times. In the present embodiment, since the intermediate buffer layer 72 has the second superlattice structure SL2, it may also be referred to as the second superlattice buffer layer. The second superlattice buffer layer (intermediate buffer layer 72) is formed above the first superlattice buffer layer (lower buffer layer 70). In the present embodiment, the second superlattice buffer layer (intermediate buffer layer 72) may be in contact with the first superlattice buffer layer (lower buffer layer 70). More specifically, the third layer SL2A located at the lowermost part of the second superlattice buffer layer (intermediate buffer layer 72) may be in contact with the second layer SL1B located at the uppermost part of the first superlattice buffer layer (lower buffer layer 70).

[0052] The thickness of the third layer SL2A may be 5 nm or more and 7 nm or less. The thickness of the fourth layer SL2B may be 2 nm or more and 3 nm or less. The thickness of the second superlattice buffer layer (intermediate buffer layer 72) may be 100 nm or more. More preferably, the thickness of the second superlattice buffer layer (intermediate buffer layer 72) may be 100 nm or more and 300 nm or less.

[0053] The second superlattice buffer layer (intermediate buffer layer 72) may contain at least one of iron (Fe), carbon (C), and silicon (Si) as an impurity. The impurity concentration of the second superlattice buffer layer (intermediate buffer layer 72) can be, for example, 4×10 16 cm -3 or more.

[0054] The upper buffer layer 74 may have a third superlattice structure SL3 including a fifth layer SL3A and a sixth layer SL3B arranged alternately. The fifth layer SL3A is composed of Al z Ga 1-z N, where 0 < z < y. Preferably, z may satisfy 0.1 < z < 0.4. The sixth layer SL3B is composed of GaN. In the third superlattice structure SL3, the two-layer structure of the fifth layer SL3A and the sixth layer SL3B may be repeated 2 times or more and 500 times or less, and more preferably, 5 times or more and 100 times or less. In the present embodiment, since the upper buffer layer 74 has the third superlattice structure SL3, it can also be referred to as the third superlattice buffer layer. The third superlattice buffer layer (upper buffer layer 74) is formed above the second superlattice buffer layer (intermediate buffer layer 72). In the present embodiment, the third superlattice buffer layer (upper buffer layer 74) may be in contact with the second superlattice buffer layer (intermediate buffer layer 72). More specifically, the fifth layer SL3A located at the lowermost part of the third superlattice buffer layer (upper buffer layer 74) may be in contact with the fourth layer SL2B located at the uppermost part of the second superlattice buffer layer (intermediate buffer layer 72).

[0055] The fifth layer SL3A may have a thickness of 5 nm or more and 7 nm or less. The sixth layer SL3B may have a thickness of 2 nm or more and 3 nm or less. The third superlattice buffer layer (upper buffer layer 74) may have a thickness of 100 nm or more. More preferably, the third superlattice buffer layer (upper buffer layer 74) may have a thickness of 100 nm or more and 300 nm or less.

[0056] The electron transit layer 24 may be formed above the third superlattice buffer layer (upper buffer layer 74). In this embodiment, the electron transit layer 24 may be in contact with the third superlattice buffer layer (upper buffer layer 74). More specifically, the electron transit layer 24 may be in contact with the sixth layer SL3B located at the top of the third superlattice buffer layer (upper buffer layer 74).

[0057] The third superlattice buffer layer (upper buffer layer 74) may contain at least one of iron (Fe), carbon (C), and silicon (Si) as an impurity. The impurity concentration of the third superlattice buffer layer (upper buffer layer 74) is, for example, 4×10 16 cm -3 It can be more than that.

[0058] (Functions of nitride semiconductor devices) The operation of the nitride semiconductor device 10 will be described below. The nitride semiconductor device 10 includes a semiconductor substrate 18, a nitride semiconductor layer 20 formed above the semiconductor substrate 18, and at least one electrode (for example, gate electrode 32, source electrode 36, drain electrode 38) formed above the nitride semiconductor layer 20. The nitride semiconductor layer 20 includes a first superlattice buffer layer (lower buffer layer 70), a second superlattice buffer layer (intermediate buffer layer 72) formed above the first superlattice buffer layer, an electron transport layer 24 formed above the second superlattice buffer layer and composed of a first nitride semiconductor, and an electron supply layer 26 formed above the electron transport layer 24 and composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The first superlattice buffer layer (lower buffer layer 70) has a first superlattice structure SL1 including alternately arranged first layer SL1A and second layer SL1B. The first layer SL1A is composed of Al x Ga 1-x N, where 0 < x < 1. The second layer SL1B is composed of GaN. The second superlattice buffer layer (intermediate buffer layer 72) has a second superlattice structure SL2 including alternately arranged third layer SL2A and fourth layer SL2B. The third layer SL2A is composed of Al y Ga 1-y N, where 0 < y < x. The fourth layer SL2B is composed of GaN.

[0059] In the nitride semiconductor device 10 of this embodiment, since the nitride semiconductor layer 20 includes the first superlattice buffer layer and the second superlattice buffer layer formed above the first superlattice buffer layer, the stress in the nitride semiconductor device 10 can be reduced, and the number of dislocation lines reaching the electron transport layer 24 or the electron supply layer 26 can be decreased. As a result, the breakdown voltage and reliability of the nitride semiconductor device 10 can be improved.

[0060] The mismatch in lattice constant between the semiconductor substrate 18 and the nitride semiconductor layer 20 may cause a plurality of dislocation lines in the nitride semiconductor layer 20. In the nitride semiconductor device 10, the semiconductor substrate 18 may be at the same potential as the source electrode 36, and therefore dislocation lines extending in a direction intersecting the plane of the semiconductor substrate 18 may reduce the vertical breakdown voltage of the nitride semiconductor device 10. In addition, if dislocation lines are present in a relatively upper portion of the nitride semiconductor layer 20 (e.g., the electron transit layer 24, the electron supply layer 26, the gate layer 30, etc.), there is a concern that the leakage current may increase and reliability may deteriorate due to electric field concentration.

[0061] In this regard, according to the nitride semiconductor device 10 of the present embodiment, the presence of multiple interfaces in the first superlattice structure SL1 and the second superlattice structure SL2 makes it possible to reduce dislocation lines that reach a relatively high portion of the nitride semiconductor layer 20.

[0062] FIG. 5 is a schematic diagram for explaining the mechanism of dislocation line disappearance by the superlattice structure. FIG. 5 illustrates a plurality of dislocation lines D1 to D6 that may be formed in a part of the first superlattice buffer layer having the first superlattice structure SL1. In the first superlattice structure SL1, the first layers SL1A and the second layers SL1B are alternately arranged, so that there are a plurality of interfaces at which the dislocation lines D1 to D6 may bend. The dislocation line D1 may bend at the interface between the first layer SL1A and the second layer SL1B, and thus may be inclined as a whole with respect to the stacking direction of the superlattice structure (the Z-axis direction shown in FIG. 3, which corresponds to the growth direction of the nitride semiconductor layer 20). In addition, the dislocation line D2 and the dislocation line D3 may bend at the interface between the first layer SL1A and the second layer SL1B, and thus may collide with each other, and as a result, may disappear above the position of collision. Dislocation lines D4 and D5 may collide with each other by bending at the interface between the first layer SL1A and the second layer SL1B, and as a result, may become one dislocation line D6 above the position of collision. In this way, in a superlattice structure in which the two-layer structure of AlGaN / GaN is repeated (for example, the first superlattice structure SL1, the second superlattice structure SL2, and the third superlattice structure SL3), since multiple interfaces exist, the density of dislocation lines can be reduced in the layers located higher up.

[0063] The nitride semiconductor layer 20 of the present embodiment may include a plurality of dislocation lines (such as the dislocation lines D1 to D6 shown in FIG. 5, for example). However, by the above-described dislocation line disappearance mechanism, the number of dislocation lines passing through the interface between the electron transport layer 24 and the electron supply layer 26 in the region below at least one electrode can be made smaller than the number of dislocation lines extending from the bottom surface 20B of the nitride semiconductor layer 20.

[0064] In addition, in the present embodiment, the AlGaN included in the first superlattice buffer layer has a larger Al composition than the AlGaN included in the second superlattice buffer layer. Therefore, the strain in the two-layer structure of AlGaN / GaN is larger in the first superlattice buffer layer than in the second superlattice buffer layer. The dislocation lines in the nitride semiconductor layer 20 are relatively numerous near the semiconductor substrate 18 (near the hetero-material interface). Therefore, by disposing the first superlattice buffer layer including AlGaN having a relatively large Al composition near the semiconductor substrate 18, the dislocation lines can be effectively eliminated. Also, by disposing the second superlattice buffer layer including AlGaN having a relatively small Al composition near the electron transport layer 24, the stress in the nitride semiconductor device 10 can be effectively reduced.

[0065] In the present embodiment, the nitride semiconductor layer 20 further includes a third superlattice buffer layer (upper buffer layer 74) formed above the second superlattice buffer layer (intermediate buffer layer 72). The third superlattice buffer layer (upper buffer layer 74) has a third superlattice structure SL3 including a fifth layer SL3A and a sixth layer SL3B arranged alternately. The fifth layer SL3A is composed of Al z Ga 1-z N, where 0 < z < y. The sixth layer SL3B is composed of GaN. The electron transport layer 24 may be formed above the third superlattice buffer layer (upper buffer layer 74).

[0066] In this embodiment, a first superlattice buffer layer containing AlGaN having a relatively large Al composition is disposed near the semiconductor substrate 18, and a third superlattice buffer layer containing AlGaN having a relatively small Al composition is disposed near the electron traveling layer 24. Therefore, according to the nitride semiconductor device 10 of this embodiment, the disappearance of dislocation lines and the reduction of stress can be performed more effectively. As a result, the breakdown voltage and reliability of the nitride semiconductor device 10 can be improved.

[0067] The nitride semiconductor device 10 of this embodiment has the following advantages. (1-1) The nitride semiconductor layer 20 includes a first superlattice buffer layer (lower buffer layer 70), a second superlattice buffer layer (intermediate buffer layer 72) formed above the first superlattice buffer layer, an electron traveling layer 24 formed above the second superlattice buffer layer (intermediate buffer layer 72) and composed of a first nitride semiconductor, and an electron supply layer 26 formed above the electron traveling layer 24 and composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The first superlattice buffer layer (lower buffer layer 70) has a first superlattice structure SL1 including alternately arranged first layer SL1A and second layer SL1B. The first layer SL1A is composed of Al x Ga 1-x N, where 0 < x < 1. The second layer SL1B is composed of GaN. The second superlattice buffer layer (intermediate buffer layer 72) has a second superlattice structure SL2 including alternately arranged third layer SL2A and fourth layer SL2B. The third layer SL2A is composed of Al y Ga 1-y N, where 0 < y < x. The fourth layer SL2B is composed of GaN.

[0068] According to this configuration, the stress in the nitride semiconductor device 10 can be reduced, and the number of dislocation lines reaching the electron traveling layer 24 or the electron supply layer 26 can be decreased, so that the breakdown voltage and reliability of the nitride semiconductor device 10 can be improved.

[0069] (1-2) The nitride semiconductor layer 20 may further include a third superlattice buffer layer (upper buffer layer 74) formed above the second superlattice buffer layer (intermediate buffer layer 72). The third superlattice buffer layer (upper buffer layer 74) has a third superlattice structure SL3 including a fifth layer SL3A and a sixth layer SL3B arranged alternately. The fifth layer SL3A is composed of Al z Ga 1-z N, where 0 < z < y. The sixth layer SL3B is composed of GaN. The electron traveling layer 24 may be formed above the third superlattice buffer layer (upper buffer layer 74).

[0070] According to this configuration, the first superlattice buffer layer including AlGaN having a relatively large Al composition is disposed near the semiconductor substrate 18, and the third superlattice buffer layer including AlGaN having a relatively small Al composition is disposed near the electron traveling layer 24. Therefore, the disappearance of dislocation lines and the reduction of stress can be performed more effectively.

[0071] (1-3) The nitride semiconductor layer 20 may further include a base buffer layer 68 in contact with the semiconductor substrate 18. The base buffer layer 68 may be composed of AlN. According to this configuration, the lattice strain in the vicinity of the interface between the semiconductor substrate 18 and the nitride semiconductor layer 20 can be reduced.

[0072] (1-4) In the region below at least one electrode, the number of dislocation lines passing through the interface between the electron traveling layer 24 and the electron supply layer 26 may be less than the number of dislocation lines extending from the bottom surface 20B of the nitride semiconductor layer 20.

[0073] According to this configuration, since the dislocation lines at positions relatively close to the electrode are reduced, the reliability of the nitride semiconductor device 10 can be improved. (1-5) In the first superlattice structure SL1, the two-layer structure of the first layer SL1A and the second layer SL1B may be repeated 2 or more times and 500 or less times.

[0074] According to this configuration, a plurality of interfaces are formed in the first superlattice structure SL1, so that dislocation lines in the nitride semiconductor layer 20 can be reduced. (1-6) In the second superlattice structure SL2, the two-layer structure of the third layer SL2A and the fourth layer SL2B may be repeated 2 to 500 times.

[0075] According to this configuration, a plurality of interfaces are formed in the second superlattice structure SL2, so that dislocation lines in the nitride semiconductor layer 20 can be reduced. (1-7) In the third superlattice structure SL3, the two-layer structure of the fifth layer SL3A and the sixth layer SL3B may be repeated 2 to 500 times.

[0076] According to this configuration, a plurality of interfaces are formed in the third superlattice structure SL3, so that dislocation lines in the nitride semiconductor layer 20 can be reduced. (1-8) The off-angle of the semiconductor substrate 18 may be greater than 0° and equal to or less than 1°. When the semiconductor substrate 18 has an off-angle, it is possible to suppress the generation of defects due to polarity inversion in the nitride semiconductor layer 20. Furthermore, by setting the off-angle to 1° or less, it is possible to suppress the deterioration of the film thickness uniformity of the nitride semiconductor layer 20 and the increase in surface roughness.

[0077] (1-9) The thickness of the electron transport layer 24 can be set to 760 nm or less. In the nitride semiconductor device 10, even if a relatively thin electron transport layer 24 is used, the dislocation density can be reduced.

[0078] (1-10) The nitride semiconductor layer 20 may further include a gate layer 30 formed above the electron supply layer 26. The gate layer 30 may be made of a third nitride semiconductor containing an acceptor-type impurity. With this configuration, the nitride semiconductor device 10 can achieve normally-off operation.

[0079] (1-11) The first superlattice buffer layer (lower buffer layer 70) may contain at least one of Fe, C, and Si as an impurity. According to this configuration, the leakage current in the first superlattice buffer layer (lower buffer layer 70) can be suppressed.

[0080] (1-12) The second superlattice buffer layer (intermediate buffer layer 72) may contain at least one of Fe, C, and Si as an impurity. According to this configuration, the leakage current in the second superlattice buffer layer (intermediate buffer layer 72) can be suppressed.

[0081] (1-13) The third superlattice buffer layer (upper buffer layer 74) may contain at least one of Fe, C, and Si as an impurity. According to this configuration, the leakage current in the third superlattice buffer layer (upper buffer layer 74) can be suppressed.

[0082] (1-14) The gate layer 30 is in contact with the electron supply layer 26 and may include a ridge portion 42 including the upper surface 30A of the gate layer 30, and extending portions 44, 46 that are in contact with the electron supply layer 26 and are thinner than the ridge portion 42 and extend outward in a plan view from the ridge portion 42. By including the extending portions 44, 46 that are thinner than the ridge portion 42 in the gate layer 30, local electric field concentration in the gate layer 30 can be suppressed. Therefore, the gate reliability of the nitride semiconductor device 10 can be improved.

[0083] (1-15) x may satisfy 0.35 < x < 0.9, and y may satisfy 0.1 < y < 0.65. By changing the Al composition of the AlGaN contained in the nitride semiconductor layer 20 stepwise in this way, the disappearance of dislocation lines and the reduction of stress can be performed more effectively in the nitride semiconductor device 10.

[0084] <Modification Example of the First Embodiment> Next, with reference to FIGS. 6 to 8, a modified example of the nitride semiconductor device 10 of the first embodiment will be described. In each of the modified examples described below, any one of the lower buffer layer 70, the intermediate buffer layer 72, and the upper buffer layer 74 may not have a superlattice structure.

[0085] (First Modified Example) FIG. 6 is a schematic diagram showing a first modified example of a stacked structure of a part of the nitride semiconductor layer 20 formed above the semiconductor substrate 18. In the first modified example, the nitride semiconductor layer 20 may include a lower buffer layer 70 (first superlattice buffer layer) having a first superlattice structure SL1, an intermediate buffer layer 72 (second superlattice buffer layer) having a second superlattice structure SL2, and an upper buffer layer 74 having no superlattice structure.

[0086] The first superlattice structure SL1 of the lower buffer layer 70 includes a first layer SL1A and a second layer SL1B arranged alternately. The first layer SL1A is composed of Al x Ga 1-x N, where 0 < x < 1. In the first modified example, x preferably satisfies 0.35 < x < 0.9, and more preferably may satisfy 0.6 < x < 0.9. The second layer SL1B is composed of GaN. Also, the second superlattice structure SL2 of the intermediate buffer layer 72 includes a third layer SL2A and a fourth layer SL2B arranged alternately. The third layer SL2A is composed of Al y Ga 1-y N, where 0 < y < x. In the first modified example, y preferably satisfies 0.1 < y < 0.65, and more preferably may satisfy 0.35 < y < 0.65. The fourth layer SL2B is composed of GaN. Other points of the first superlattice structure SL1 and the second superlattice structure SL2 of the first modified example may be the same as those of the first embodiment.

[0087] The upper buffer layer 74 is Al u Ga 1-uIt is composed of N, where 0 < u < y. Preferably, u may satisfy 0.1 < u < 0.4. The upper buffer layer 74 is disposed between the second superlattice buffer layer (intermediate buffer layer 72) and the electron traveling layer 24.

[0088] Thus, also in the first modification example, since the Al composition becomes smaller in the buffer layer located more upward, the stress in the nitride semiconductor device 10 can be effectively reduced. Further, since the nitride semiconductor layer 20 includes the first superlattice buffer layer and the second superlattice buffer layer, the number of dislocation lines reaching the electron traveling layer 24 or the electron supply layer 26 can be reduced. As a result, the breakdown voltage and reliability of the nitride semiconductor device 10 can be improved.

[0089] (Second modification example) FIG. 7 is a schematic diagram showing a second modification example of a stacked structure of a part of the nitride semiconductor layer 20 formed above the semiconductor substrate 18. In the second modification example, the nitride semiconductor layer 20 may include a lower buffer layer 70 (first superlattice buffer layer) having a first superlattice structure SL1, an intermediate buffer layer 72 having no superlattice structure, and an upper buffer layer 74 (second superlattice buffer layer) having a second superlattice structure SL2.

[0090] The first superlattice structure SL1 of the lower buffer layer 70 includes a first layer SL1A and a second layer SL1B arranged alternately. The first layer SL1A is composed of Al x Ga 1-x N, where 0 < x < 1. In the second modification example, x preferably satisfies 0.35 < x < 0.9, and more preferably 0.6 < x < 0.9. The second layer SL1B is composed of GaN. Further, the second superlattice structure SL2 of the upper buffer layer 74 includes a third layer SL2A and a fourth layer SL2B arranged alternately. The third layer SL2A is composed of Al y Ga 1-yIt is composed of N, where 0 < y < x. In the second modification example, y preferably satisfies 0.1 < y < 0.65, and more preferably 0.1 < y < 0.4. The fourth layer SL2B is composed of GaN. Other points of the first superlattice structure SL1 and the second superlattice structure SL2 in the second modification example may be the same as those in the first embodiment.

[0091] The intermediate buffer layer 72 is composed of Al i Ga 1-i N, where y < i < x. Preferably, i may satisfy 0.35 < i < 0.65. The intermediate buffer layer 72 is disposed between the first superlattice buffer layer (lower buffer layer 70) and the second superlattice buffer layer (upper buffer layer 74).

[0092] Thus, also in the second modification example, since the Al composition of the buffer layer positioned more upward is smaller, the stress in the nitride semiconductor device 10 can be effectively reduced. Further, since the nitride semiconductor layer 20 includes the first superlattice buffer layer and the second superlattice buffer layer, the number of dislocation lines reaching the electron traveling layer 24 or the electron supply layer 26 can be reduced. As a result, the breakdown voltage and reliability of the nitride semiconductor device 10 can be improved.

[0093] (Third Modification Example) FIG. 8 is a schematic diagram showing a third modification example of a partial stacked structure of a nitride semiconductor layer 20 formed above a semiconductor substrate 18. In the third modification example, the nitride semiconductor layer 20 may include a lower buffer layer 70 having no superlattice structure, an intermediate buffer layer 72 (first superlattice buffer layer) having a first superlattice structure SL1, and an upper buffer layer 74 (second superlattice buffer layer) having a second superlattice structure SL2.

[0094] The first superlattice structure SL1 of the intermediate buffer layer 72 includes alternately arranged first layer SL1A and second layer SL1B. The first layer SL1A is Al x Ga 1-xIt is composed of N, where 0 < x < 1. In the third modification example, x preferably satisfies 0.35 < x < 0.9, and more preferably 0.35 < x < 0.65. The second layer SL1B is composed of GaN. Further, the second superlattice structure SL2 of the upper buffer layer 74 includes a third layer SL2A and a fourth layer SL2B arranged alternately. The third layer SL2A is Al y Ga 1-y It is composed of N, where 0 < y < x. In the third modification example, y preferably satisfies 0.1 < y < 0.65, and more preferably 0.1 < y < 0.4. The fourth layer SL2B is composed of GaN. Other points of the first superlattice structure SL1 and the second superlattice structure SL2 in the third modification example may be the same as those in the first embodiment.

[0095] The lower buffer layer 70 is Al b Ga 1-b It is composed of N, where x < b < 1. Preferably, b may satisfy 0.6 < b < 0.9. The lower buffer layer 70 is disposed between the semiconductor substrate 18 and the first superlattice buffer layer (intermediate buffer layer 72).

[0096] Thus, also in the third modification example, since the Al composition of the buffer layer located higher is smaller, the stress in the nitride semiconductor device 10 can be effectively reduced. Further, since the nitride semiconductor layer 20 includes the first superlattice buffer layer and the second superlattice buffer layer, the number of dislocation lines reaching the electron traveling layer 24 or the electron supply layer 26 can be reduced. As a result, the breakdown voltage and reliability of the nitride semiconductor device 10 can be improved.

[0097] <Second Embodiment> FIG. 9 is a schematic cross-sectional view of a nitride semiconductor device 100 according to the second embodiment. As shown in FIG. 9, in the nitride semiconductor device 100, the nitride semiconductor layer 20 includes a buffer layer 102 instead of the buffer layer 22 (see FIG. 3) of the first embodiment. Other points of the nitride semiconductor device 100 may be the same as those of the nitride semiconductor device 10 of the first embodiment.

[0098] The buffer layer 102 may include a base buffer layer 104 in contact with the semiconductor substrate 18. In one example, the base buffer layer 104 may be made of aluminum nitride (AlN). The thickness of the base buffer layer 104 may be 100 nm or more and 300 nm or less.

[0099] The buffer layer 102 may further include a first superlattice buffer layer 106 and a second superlattice buffer layer 108. In the present embodiment, the first superlattice buffer layer 106 may be in contact with the base buffer layer 104. Also, the second superlattice buffer layer 108 may be in contact with the electron traveling layer 24.

[0100] FIG. 10 is a schematic diagram showing a partial stacked structure of the nitride semiconductor layer 20 formed above the semiconductor substrate 18. As shown in FIG. 10, the first superlattice buffer layer 106 may have a first superlattice structure SL1 including a first layer SL1A and a second layer SL1B arranged alternately. The first layer SL1A is made of Al x Ga 1-x N, where 0 < x < 1. x may preferably satisfy 0.35 < x < 0.9. The second layer SL1B is made of GaN. In the first superlattice structure SL1, the two-layer structure of the first layer SL1A and the second layer SL1B may be repeated 2 or more times and 500 or less times, and more preferably, 5 or more times and 100 or less times. The first layer SL1A located at the lowermost part of the first superlattice buffer layer 106 may be in contact with the base buffer layer 104.

[0101] The thickness of the first layer SL1A may be 5 nm or more and 7 nm or less. The thickness of the second layer SL1B may be 2 nm or more and 3 nm or less. The thickness of the first superlattice buffer layer 106 may be 100 nm or more. More preferably, the thickness of the first superlattice buffer layer 106 may be 100 nm or more and 300 nm or less.

[0102] The first superlattice buffer layer 106 may contain at least one of iron (Fe), carbon (C), and silicon (Si) as an impurity. The impurity concentration of the first superlattice buffer layer 106 can be, for example, 4×10 16 cm -3 or higher.

[0103] The second superlattice buffer layer 108 may have a second superlattice structure SL2 including alternately arranged third layer SL2A and fourth layer SL2B. The third layer SL2A is composed of Al y Ga 1-y N, where 0 < y < x. y may preferably satisfy 0.1 < y < 0.65. The fourth layer SL2B is composed of GaN. In the second superlattice structure SL2, the two-layer structure of the third layer SL2A and the fourth layer SL2B may be repeated 2 or more times and 500 or less times, more preferably 5 or more times and 100 or less times. The second superlattice buffer layer 108 is formed above the first superlattice buffer layer 106. In this embodiment, the second superlattice buffer layer 108 may be in contact with the first superlattice buffer layer 106. More specifically, the third layer SL2A located at the lowermost part of the second superlattice buffer layer 108 may be in contact with the second layer SL1B located at the uppermost part of the first superlattice buffer layer 106.

[0104] The thickness of the third layer SL2A may be 5 nm or more and 7 nm or less. The thickness of the fourth layer SL2B may be 2 nm or more and 3 nm or less. The thickness of the second superlattice buffer layer 108 may be 100 nm or more. More preferably, the thickness of the second superlattice buffer layer 108 may be 100 nm or more and 300 nm or less.

[0105] The second superlattice buffer layer 108 may contain at least one of iron (Fe), carbon (C), and silicon (Si) as an impurity. The impurity concentration of the second superlattice buffer layer 108 can be, for example, 4×10 16 cm -3 or higher.

[0106] Thus, also in the second embodiment, since the Al composition is smaller in the buffer layer located above (i.e., the second superlattice buffer layer 108), the stress in the nitride semiconductor device 100 can be effectively reduced. Further, since the nitride semiconductor layer 20 includes the first superlattice buffer layer 106 and the second superlattice buffer layer 108, the number of dislocation lines reaching the electron traveling layer 24 or the electron supply layer 26 can be reduced. As a result, the breakdown voltage and reliability of the nitride semiconductor device 100 can be improved.

[0107] The nitride semiconductor device 100 of this embodiment has the following advantages. (2-1) The nitride semiconductor layer 20 includes a first superlattice buffer layer 106, a second superlattice buffer layer 108 formed above the first superlattice buffer layer 106, an electron traveling layer 24 formed above the second superlattice buffer layer 108 and composed of a first nitride semiconductor, and an electron supply layer 26 formed above the electron traveling layer 24 and composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The first superlattice buffer layer 106 has a first superlattice structure SL1 including alternately arranged first layer SL1A and second layer SL1B. The first layer SL1A is composed of Al x Ga 1-x N, where 0 < x < 1. The second layer SL1B is composed of GaN. The second superlattice buffer layer 108 has a second superlattice structure SL2 including alternately arranged third layer SL2A and fourth layer SL2B. The third layer SL2A is composed of Al y Ga 1-y N, where 0 < y < x. The fourth layer SL2B is composed of GaN.

[0108] According to this configuration, the stress in the nitride semiconductor device 100 can be reduced, and the number of dislocation lines reaching the electron traveling layer 24 or the electron supply layer 26 can be reduced, so that the breakdown voltage and reliability of the nitride semiconductor device 100 can be improved.

[0109] (2-2) The nitride semiconductor layer 20 may further include a base buffer layer 104 in contact with the semiconductor substrate 18. The base buffer layer 104 may be made of AlN. According to this configuration, the lattice distortion in the vicinity of the interface between the semiconductor substrate 18 and the nitride semiconductor layer 20 can be reduced.

[0110] (2-3) In the region below at least one electrode, the number of dislocation lines passing through the interface between the electron transit layer 24 and the electron supply layer 26 may be smaller than the number of dislocation lines extending from the bottom surface 20B of the nitride semiconductor layer 20.

[0111] According to this configuration, dislocation lines in positions relatively close to the electrodes are reduced, and the reliability of the nitride semiconductor device 100 can be improved. (2-4) In the first superlattice structure SL1, the two-layer structure of the first layer SL1A and the second layer SL1B may be repeated 2 to 500 times.

[0112] According to this configuration, a plurality of interfaces are formed in the first superlattice structure SL1, so that dislocation lines in the nitride semiconductor layer 20 can be reduced. (2-5) In the second superlattice structure SL2, the two-layer structure of the third layer SL2A and the fourth layer SL2B may be repeated 2 to 500 times.

[0113] According to this configuration, a plurality of interfaces are formed in the second superlattice structure SL2, so that dislocation lines in the nitride semiconductor layer 20 can be reduced. (2-6) The off-angle of the semiconductor substrate 18 may be greater than 0° and equal to or less than 1°. When the semiconductor substrate 18 has an off-angle, it is possible to suppress the generation of defects due to polarity inversion in the nitride semiconductor layer 20. Furthermore, by setting the off-angle to 1° or less, it is possible to suppress the deterioration of the film thickness uniformity of the nitride semiconductor layer 20 and the increase in surface roughness.

[0114] (2-7) The thickness of the electron traveling layer 24 can be 760 nm or less. In the nitride semiconductor device 100, the dislocation density can be reduced even when a relatively thin electron traveling layer 24 is used.

[0115] (2-8) The nitride semiconductor layer 20 may further include a gate layer 30 formed above the electron supply layer 26. The gate layer 30 may be composed of a third nitride semiconductor containing acceptor-type impurities. According to this configuration, the normally-off operation of the nitride semiconductor device 100 can be realized.

[0116] (2-9) The first superlattice buffer layer 106 may contain at least one of Fe, C, and Si as an impurity. According to this configuration, the leakage current in the first superlattice buffer layer 106 can be suppressed.

[0117] (2-10) The second superlattice buffer layer 108 may contain at least one of Fe, C, and Si as an impurity. According to this configuration, the leakage current in the second superlattice buffer layer 108 can be suppressed.

[0118] (2-11) The gate layer 30 may be in contact with the electron supply layer 26 and include a ridge portion 42 including the upper surface 30A of the gate layer 30, and extension portions 44, 46 that are in contact with the electron supply layer 26 and extend outward from the ridge portion 42 in a plan view and are thinner than the ridge portion 42. By including the extension portions 44, 46 that are thinner than the ridge portion 42 in the gate layer 30, local electric field concentration in the gate layer 30 can be suppressed. Therefore, the gate reliability of the nitride semiconductor device 100 can be improved.

[0119] (2-12) x may satisfy 0.35 < x < 0.9, and y may satisfy 0.1 < y < 0.65. By changing the Al composition of the AlGaN contained in the nitride semiconductor layer 20 stepwise in this way, in the nitride semiconductor device 100, the disappearance of dislocation lines and the reduction of stress can be performed more effectively.

[0120] <Other changes> Each of the above-described embodiments and modified examples can be implemented with the following modifications.

[0121] 3 includes a base buffer layer 68, a lower buffer layer 70, an intermediate buffer layer 72, and an upper buffer layer 74, but the buffer layer 22 may further include an additional buffer layer (not shown). The additional buffer layer may be composed of a material similar to any of the base buffer layer 68, the lower buffer layer 70, the intermediate buffer layer 72, and the upper buffer layer 74, or may be composed of a material different from them. For example, the additional buffer layer may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0122] The buffer layer 22 does not necessarily have to include the base buffer layer 68. In that case, for example, the lower buffer layer 70, which is the first superlattice buffer layer, may be in contact with the semiconductor substrate 18.

[0123] The first superlattice buffer layer may have a thickness greater than that of the second superlattice buffer layer. By making the first superlattice buffer layer, which is disposed close to the semiconductor substrate 18 and contains AlGaN having a relatively large Al composition, thicker, the dislocation lines in the nitride semiconductor layer 20 may be further reduced. Note that making the first superlattice buffer layer thicker may mean increasing the number of repetitions of the two-layer structure of AlGaN / GaN in the first superlattice structure SL1.

[0124] The nitride semiconductor device 10 may be configured as a normally-on type HEMT. In that case, the nitride semiconductor layer 20 does not need to include the gate layer 30. One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent.

[0125] In this specification, the phrase "at least one of A and B" should be understood to mean "A only, B only, or both A and B." The directional terms used herein, such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," "rear," and the like, depend on the particular orientation of the device being described and illustrated. Various alternative orientations can be envisioned in this disclosure, and therefore these directional terms should not be construed in a narrow sense.

[0126] For example, the Z-axis direction used in this specification does not necessarily have to be the vertical direction, and does not necessarily have to completely coincide with the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0127] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[0128] (Appendix 1) A semiconductor substrate (18); a nitride semiconductor layer (20) formed above the semiconductor substrate (18); At least one electrode (32, 36, 38) formed above the nitride semiconductor layer (20); Equipped with The nitride semiconductor layer (20) is a first superlattice buffer layer (70;72;106); a second superlattice buffer layer (72; 74; 108) formed above the first superlattice buffer layer (70; 72; 106); an electron transit layer (24) formed above the second superlattice buffer layer (72; 74; 108) and made of a first nitride semiconductor; An electron supply layer (26) formed above the electron transport layer (24) and composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor, and including The first superlattice buffer layer (70; 72; 106) has a first superlattice structure (SL1) including a first layer (SL1A) and a second layer (SL1B) arranged alternately, and the first layer (SL1A) is Al x Ga 1-x N, where 0 < x < 1, and the second layer (SL1B) is composed of GaN. The second superlattice buffer layer (72; 74; 108) has a second superlattice structure (SL2) including a third layer (SL2A) and a fourth layer (SL2B) arranged alternately, and the third layer (SL2A) is Al y Ga 1-y N, where 0 < y < x, and the fourth layer (SL2B) is composed of GaN. A nitride semiconductor device.

[0129] (Appendix 2, Figure 4) The nitride semiconductor layer (20) further includes a third superlattice buffer layer (74) formed above the second superlattice buffer layer (72). The third superlattice buffer layer (74) has a third superlattice structure (SL3) including a fifth layer (SL3A) and a sixth layer (SL3B) arranged alternately. The fifth layer (SL3A) is Al z Ga 1-z N, where 0 < z < y, and the sixth layer (SL3B) is composed of GaN. The electron transport layer (24) is formed above the third superlattice buffer layer (72). The nitride semiconductor device according to Appendix 1.

[0130] (Appendix 3, Figure 6) The nitride semiconductor layer (20) further includes an upper buffer layer (74) disposed between the second superlattice buffer layer (72) and the electron transport layer (24). The upper buffer layer (74) is Al u Ga 1-uIt is composed of N, where 0 < u < y, the nitride semiconductor device described in Supplementary Note 1.

[0131] (Supplementary Note 4, Figure 7) The nitride semiconductor layer (20) further includes an intermediate buffer layer (72) disposed between the first superlattice buffer layer (70) and the second superlattice buffer layer (74), and the intermediate buffer layer (72) is composed of Al i Ga 1-i It is composed of N, where y < i < x, the nitride semiconductor device described in Supplementary Note 1.

[0132] (Supplementary Note 5, Figure 8) The nitride semiconductor layer (20) further includes a lower buffer layer (70) disposed between the semiconductor substrate (18) and the first superlattice buffer layer (72), and the lower buffer layer (70) is composed of Al b Ga 1-b It is composed of N, where x < b < 1, the nitride semiconductor device described in Supplementary Note 1.

[0133] (Supplementary Note 6) The nitride semiconductor layer (20) further includes a base buffer layer (68) in contact with the semiconductor substrate (18), and the base buffer layer (68) is composed of AlN, the nitride semiconductor device according to any one of Supplementary Notes 1 to 5.

[0134] (Supplementary Note 7) The second superlattice buffer layer (72; 74; 108) is in contact with the first superlattice buffer layer (70; 72; 106), the nitride semiconductor device according to any one of Supplementary Notes 1 to 3.

[0135] (Supplementary Note 8) The nitride semiconductor layer (20) has a bottom surface (20B) in contact with the semiconductor substrate (18) and includes a plurality of dislocation lines. The nitride semiconductor device according to any one of Appendices 1 to 7, wherein in a region below the at least one electrode (32, 36, 38), a number of dislocation lines passing through an interface between the electron transit layer (24) and the electron supply layer (26) is smaller than a number of dislocation lines extending from the bottom surface (20B) of the nitride semiconductor layer (20).

[0136] (Appendix 9) The nitride semiconductor device according to any one of appendix 1 to 8, wherein in the first superlattice structure (SL1), a two-layer structure of the first layer (SL1A) and the second layer (SL1B) is repeated 2 to 500 times.

[0137] (Appendix 10) 10. The nitride semiconductor device according to any one of claims 1 to 9, wherein the first nitride semiconductor includes GaN, and the second nitride semiconductor includes AlGaN.

[0138] (Appendix 11) 11. The nitride semiconductor device according to any one of claims 1 to 10, wherein the semiconductor substrate (18) is made of a material different from that of the nitride semiconductor layer (20).

[0139] (Appendix 12) 12. The nitride semiconductor device according to any one of claims 1 to 11, wherein the semiconductor substrate (18) is a Si substrate having a (111) growth surface.

[0140] (Appendix 13) 13. The nitride semiconductor device according to any one of claims 1 to 12, wherein the off-angle of the semiconductor substrate (18) is greater than 0° and equal to or less than 1°.

[0141] (Appendix 14) 14. The nitride semiconductor device according to any one of claims 1 to 13, wherein the first layer (SL1A) has a thickness of 5 nm or more and 7 nm or less, and the second layer (SL1B) has a thickness of 2 nm or more and 3 nm or less.

[0142] (Appendix 15) The nitride semiconductor device according to any one of Appendices 1 to 14, wherein the thickness of the first superlattice buffer layer (70; 72; 106) is 100 nm or more.

[0143] (Appendix 16) The nitride semiconductor device according to any one of Appendices 1 to 15, wherein the thickness of the electron traveling layer (24) is 760 nm or less.

[0144] (Appendix 17) The nitride semiconductor layer (20) further includes a gate layer (30) formed above the electron supply layer (26), and the gate layer (30) is composed of a third nitride semiconductor containing acceptor-type impurities. The nitride semiconductor device according to any one of Appendices 1 to 16.

[0145] (Appendix 18) The nitride semiconductor device according to Appendix 17, wherein the third nitride semiconductor contains GaN. (Appendix 19) The nitride semiconductor device according to any one of Appendices 1 to 18, wherein the first superlattice buffer layer (70; 72; 106) contains at least one of Fe, C, and Si as an impurity.

[0146] (Appendix 20) For the nitride semiconductor device according to any one of Appendices 1 to 19, x satisfies 0.35 < x < 0.9, and y satisfies 0.1 < y < 0.65.

[0147] (Appendix 21) In the second superlattice structure (SL2), the two-layer structure of the third layer (SL2A) and the fourth layer (SL2B) is repeated 2 or more times and 500 or less times. The nitride semiconductor device according to any one of Appendices 1 to 20.

[0148] (Appendix 22) For the nitride semiconductor device according to any one of Appendices 1 to 21, the thickness of the third layer (SL2A) is 5 nm or more and 7 nm or less, and the thickness of the fourth layer (SL2B) is 2 nm or more and 3 nm or less.

[0149] (Appendix 23) 23. The nitride semiconductor device according to any one of claims 1 to 22, wherein the second superlattice buffer layer (72; 74; 108) has a thickness of 100 nm or more.

[0150] (Appendix 24) 24. The nitride semiconductor device according to any one of claims 1 to 23, wherein the second superlattice buffer layer (72; 74; 108) contains at least one of Fe, C, and Si as an impurity.

[0151] (Appendix 25) 3. The nitride semiconductor device according to claim 2, wherein in the third superlattice structure (SL3), a two-layer structure of the fifth layer (SL3A) and the sixth layer (SL3B) is repeated 2 to 500 times.

[0152] (Appendix 26) The nitride semiconductor device according to claim 2 or 25, wherein the fifth layer (SL3A) has a thickness of 5 nm or more and 7 nm or less, and the sixth layer (SL3B) has a thickness of 2 nm or more and 3 nm or less.

[0153] (Appendix 27) 27. The nitride semiconductor device of claim 2, 25, or 26, wherein the third superlattice buffer layer (74) has a thickness of 100 nm or more.

[0154] (Appendix 28) 28. The nitride semiconductor device according to any one of appendix 2 or 25 to 27, wherein the third superlattice buffer layer (74) contains at least one of Fe, C, and Si as an impurity.

[0155] Various changes in form and details may be made to the above-described examples without departing from the scope of the claims and their equivalents. The above-described examples are illustrative and not limiting. The description of features in each example should be considered as applicable to similar features or aspects in other examples. Suitable results may be achieved if the sequence of events is performed in a different order and / or if the components in the described systems, architectures, devices, or circuits are combined in a different manner and / or are replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description but by the claims and their equivalents. All variations of the claims and their equivalents are included in the present disclosure. [Explanation of symbols]

[0156] 10,100...Nitride semiconductor device 10A…Top surface 12…Gate pad 14…Sauce Pad 16…Drain pad 18...Semiconductor substrate 20...Nitride semiconductor layer 20B…Bottom surface 22,102…Buffer layer 24...Electron transport layer 26…electron supply layer 28...Two-dimensional electron gas (2DEG) 30…Gate layer 30A…Top surface 30B…Bottom surface 32...Gate electrode 34…Passivation layer 34A…1st opening 34B…Second opening 36…Source electrode 38...Drain electrode 40...Field plate electrode 40A…End 42…Ridge 44...First extension part 46…Second extension part 48,52…Main body 50,54…Connection 56…Gate wiring 58…Source wiring 60…Drain wiring 62,64,66…Via 68,104…Base buffer layer 70…Lower buffer layer 72...Intermediate buffer layer 74…Upper buffer layer 106...First superlattice buffer layer 108...Second superlattice buffer layer SL1…first superlattice structure SL1A…1st layer SL1B…2nd layer SL2…Second superlattice structure SL2A…3rd layer SL2B…4th layer SL3…Third superlattice structure SL3A…5th layer SL3B…6th layer D1, D2, D3, D4, D5, D6...Dislocation lines

Claims

1. A semiconductor substrate; a nitride semiconductor layer formed above the semiconductor substrate; At least one electrode formed above the nitride semiconductor layer; Equipped with The nitride semiconductor layer is a first superlattice buffer layer; a second superlattice buffer layer formed above the first superlattice buffer layer; an electron transit layer formed above the second superlattice buffer layer and made of a first nitride semiconductor; an electron supply layer formed above the electron transit layer and made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; Including, The first superlattice buffer layer has a first superlattice structure including alternating first and second layers, the first layer being Al ｘ G １－ｘ N, where 0<x<1, and the second layer is composed of GaN; The second superlattice buffer layer has a second superlattice structure including alternating third and fourth layers, the third layer being Al ｙ G １－ｙ N, where 0<y<x, and the fourth layer is composed of GaN. Nitride semiconductor devices.

2. The nitride semiconductor layer further includes a third superlattice buffer layer formed above the second superlattice buffer layer, the third superlattice buffer layer having a third superlattice structure including a fifth layer and a sixth layer alternately arranged, the fifth layer being made of Al ｚ G １－ｚ 2. The nitride semiconductor device according to claim 1, wherein the sixth layer is made of GaN, where 0<z<y, and the electron transit layer is formed above the third superlattice buffer layer.

3. The nitride semiconductor layer further includes an upper buffer layer disposed between the second superlattice buffer layer and the electron transport layer, and the upper buffer layer is made of Al ｕ G １－ｕ 2. The nitride semiconductor device according to claim 1, wherein u is a junction between a first nitride semiconductor layer and a second nitride semiconductor layer, and wherein u is a junction between a first nitride semiconductor layer and a second nitride semiconductor layer.

4. The nitride semiconductor layer further includes an intermediate buffer layer disposed between the first superlattice buffer layer and the second superlattice buffer layer, the intermediate buffer layer being composed of Al ｉ G １－ｉ 2. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is composed of N, y<i<x.

5. The nitride semiconductor layer further includes a lower buffer layer disposed between the semiconductor substrate and the first superlattice buffer layer, the lower buffer layer being made of Al ｂ G １－ｂ 2. The nitride semiconductor device according to claim 1, wherein x<b<1.

6. 6. The nitride semiconductor device according to claim 1, wherein said nitride semiconductor layer further includes a base buffer layer in contact with said semiconductor substrate, said base buffer layer being made of AlN.

7. The nitride semiconductor device according to claim 1 , wherein said second superlattice buffer layer is in contact with said first superlattice buffer layer.

8. the nitride semiconductor layer has a bottom surface in contact with the semiconductor substrate and includes a plurality of dislocation lines; 6. The nitride semiconductor device according to claim 1, wherein in a region below the at least one electrode, a number of dislocation lines passing through an interface between the electron transit layer and the electron supply layer is smaller than a number of dislocation lines extending from the bottom surface of the nitride semiconductor layer.

9. 6. The nitride semiconductor device according to claim 1, wherein in said first superlattice structure, a two-layer structure of said first layer and said second layer is repeated 2 to 500 times.

10. 6. The nitride semiconductor device according to claim 1, wherein the first nitride semiconductor includes GaN, and the second nitride semiconductor includes AlGaN.

11. 6. The nitride semiconductor device according to claim 1, wherein the semiconductor substrate is made of a material different from that of the nitride semiconductor layer.

12. 6. The nitride semiconductor device according to claim 1, wherein the semiconductor substrate is a Si substrate having a (111) growth surface.

13. 6. The nitride semiconductor device according to claim 1, wherein an off-angle of said semiconductor substrate is greater than 0° and equal to or less than 1°.

14. 6. The nitride semiconductor device according to claim 1, wherein the first layer has a thickness of 5 nm or more and 7 nm or less, and the second layer has a thickness of 2 nm or more and 3 nm or less.

15. 6. The nitride semiconductor device according to claim 1, wherein said first superlattice buffer layer has a thickness of 100 nm or more.

16. 6. The nitride semiconductor device according to claim 1, wherein the electron transit layer has a thickness of 760 nm or less.

17. 6. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor layer further includes a gate layer formed above the electron supply layer, the gate layer being composed of a third nitride semiconductor containing an acceptor-type impurity.

18. The nitride semiconductor device according to claim 17 , wherein the third nitride semiconductor includes GaN.

19. 6. The nitride semiconductor device according to claim 1, wherein said first superlattice buffer layer contains at least one of Fe, C and Si as an impurity.

20. 6. The nitride semiconductor device according to claim 1, wherein x satisfies 0.35<x<0.9, and y satisfies 0.1<y<0.65.

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