Data processing device, data processing program, and data processing method

Abstract

To attain implementation of plural bit transition processing for a search for a solution of a combinatorial optimization problem with a restrictive condition.SOLUTION: A transition candidate determination circuit 13 determines, on the basis of a variation of a value of an evaluation function according to variation of a value of each of a plurality of state variables, calculated using a value of a first local field at a first time point, candidates which undergo value variation from the plurality of state variables one at a time. An update circuit 14 updates values of the candidates, the value of the first local field, and a value of a second local field used in determination of a restrictive violation amount each time each of the candidates is determined and, at a second time point, additionally updates the value of the first local field using the value of the second local field at the first and second time points. A determination circuit 16 determines, on the basis of a cumulative value of the variation at a time when the candidates undergo the value variation, whether or not to receive the value variation of the candidates of a first number of 2 or more and, if it is determined that the variation is not received, a control circuit 17 returns each of the value of the plurality of state variables and the values of the first and second local fields to the value at the first time point.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a data processing device, a data processing program, and a data processing method. [Background technology]

[0002] When searching for a solution to a combinatorial optimization problem, there is a method of converting the combinatorial optimization problem into an Ising model that represents the behavior of spin in a magnetic material. Then, using the Markov chain Monte Carlo method, a search is performed for the state of the Ising model where the value of the Ising-type evaluation function, that is, the value equivalent to the energy of the Ising model, is minimized. The state where the evaluation function has the smallest value among the minimum values ​​becomes the optimal solution. The state variables included in the Ising-type evaluation function are binary variables that take the value of 0 or 1. The state variables may be expressed as bits. Note that by changing the sign of the evaluation function, it is also possible to search for a state where the evaluation function has a maximum value.

[0003] Hereinafter, the Markov Chain Monte Carlo method will be abbreviated as the MCMC method. Processing using the MCMC method may also be called MCMC processing. In the MCMC processing, for example, a state transition is accepted with the acceptance probability of that state transition defined by the Metropolis method or the Gibbs method. Examples of the MCMC method include simulated annealing and replica exchange.

[0004] Conventionally, there is a process (hereinafter referred to as single-bit transition process) in which the number of bits allowed for a change in state variables (hereinafter referred to as transition) per trial of MCMC processing is 1. However, in single-bit transition process, when the solution gets stuck in a local solution, it becomes difficult to escape from the local solution, and the search speed may decrease.

[0005] For this reason, a process has been proposed in which, based on the calculation result of the amount of change in the value of the evaluation function when a multiple-bit transition occurs, it is determined whether or not the multiple-bit transition is possible, and if the transition is permitted, the multiple-bit transition is caused (see, for example, Patent Documents 1-4). Hereinafter, such a process is referred to as multiple-bit transition processing. Multiple-bit transition processing promotes the escape of the solution from a local solution, and makes it possible to widen the search range.

[0006] Some combinatorial optimization problems have constraints that the solution must satisfy. For example, the knapsack problem, a discrete optimization problem, has a constraint that the total volume of items that can be packed into a knapsack must be less than or equal to the capacity of the knapsack. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2020-021209 A [Patent Document 2] JP 2020-064536 A [Patent Document 3] JP 2021-157361 A [Patent Document 4] Patent Publication No. 2021-165965 Summary of the Invention [Problem to be solved by the invention]

[0008] Conventional multi-bit transition processing was not easy to implement because the configuration for calculating the amount of change in the value of the evaluation function when a multi-bit transition occurs and the configuration for propagating the data were complex.

[0009] In one aspect, the present invention aims to provide a data processing device, a data processing program, and a data processing method that are capable of implementing multiple bit transition processing for searching for a solution to a combinatorial optimization problem having constraints. [Means for solving the problem]

[0010] In one embodiment, the present invention includes a memory that stores values ​​at a first time point of a plurality of state variables included in an evaluation function of a combinatorial optimization problem having a constraint condition, a value at the first time point of a first local field used to specify an amount of change in the value of the evaluation function accompanying a change in each value of the plurality of state variables, and a value at the first time point of a second local field used to specify an amount of constraint violation to be added to the value of the evaluation function when the constraint condition is not satisfied; a transition candidate determination circuit that calculates the amount of change using the value of the first local field at the first time point and determines candidates for changing the values ​​of the plurality of state variables one by one based on the amount of change; and a transition candidate determination circuit that calculates the value of the candidate and is provided. A data processing device comprising: an updating circuit that updates values ​​of the first local field and the second local field, and at a second point in time, further updates the value of the first local field using the value of the second local field at the first point in time and the value of the second local field at the second point in time; an accumulation value calculation circuit that calculates an accumulation value of the amount of change when the value of the candidates is changed; a judgment circuit that judges whether or not to accept changes in the values ​​of a first number of the candidates (two or more) based on the accumulation value; and a control circuit that restores the values ​​of the plurality of state variables, the value of the first local field, and the value of the second local field to their values ​​at the first point in time, respectively, when the judgment circuit judges that the changes in the values ​​of the first number of the candidates are not accepted.

[0011] Also provided in one embodiment is a data processing program. Also provided in one embodiment is a method for processing data. Effect of the Invention

[0012] In one aspect, the present invention provides an implementation of a multi-bit transition process for searching for a solution to a combinatorial optimization problem with constraints. [Brief description of the drawings]

[0013] [Figure 1] FIG. 11 is a diagram illustrating an example of a relationship between a state variable and a second local field. [Diagram 2]FIG. 13 is a diagram illustrating an example of the amount of change in the value of a penalty function due to a change in the value of a state variable. [Diagram 3] FIG. 1 illustrates an example of a data processing device according to a first embodiment; [Figure 4] FIG. 13 is a diagram showing an example of updating the first local field and the second local field when the value of xj changes. [Diagram 5] FIG. 2 is a diagram illustrating an example of a memory, an update circuit, and a transition candidate determination circuit. [Figure 6] 4 is a flowchart showing the flow of an example of a data processing method according to the first embodiment. [Figure 7] 11 is a flowchart illustrating an example of a single bit transition process. [Figure 8] 11 is a flowchart showing a flow of an example of a multiple bit transition process of the data processing method according to the first embodiment. [Figure 9] 13 is a flowchart showing the flow of another example of the multiple bit transition process in the data processing method according to the first embodiment. [Figure 10] FIG. 1 illustrates a first example of pipeline processing of the data processing method according to the first embodiment (part 1); [Figure 11] FIG. 2 illustrates a first example of pipeline processing of the data processing method according to the first embodiment (part 2); [Figure 12] FIG. 11 illustrates a second example of pipeline processing in the data processing method according to the first embodiment (part 1); [Figure 13] FIG. 2 illustrates a second example of pipeline processing in the data processing method according to the first embodiment (part 2). [Figure 14] FIG. 1 illustrates an example of a data processing device according to a second embodiment (part 1); [Figure 15] FIG. 2 illustrates an example of a data processing device according to a second embodiment (part 2); [Figure 16] 13 is a flowchart showing a flow of an example of a multiple bit transition process of the data processing method according to the second embodiment. [Figure 17]13 is a flowchart showing the flow of another example of the multiple bit transition process of the data processing method according to the second embodiment. [Figure 18] FIG. 11 illustrates an example of pipeline processing of the data processing method according to the second embodiment (part 1); [Figure 19] FIG. 13 illustrates an example of pipeline processing of the data processing method according to the second embodiment (part 2); [Figure 20] FIG. 2 illustrates an example of hardware of an example of a data processing device. [Figure 21] FIG. 2 illustrates an example of computer hardware. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the invention will be described with reference to the drawings. A data processing device according to each of the following embodiments searches for a solution to a combinatorial optimization problem having constraints using an MCMC method such as simulated annealing or replica exchange, and outputs the searched solution.

[0015] An evaluation function for a combinatorial optimization problem with constraints is expressed, for example, by the following equation:

[0016]

number

[0017] The first and second terms on the right side are Ising-type evaluation functions. The first term on the right side is the sum of the products of the values ​​of the two state variables (0 or 1) and the weighting coefficient (which represents the strength of the interaction between the two state variables) for all combinations of state variables, without omissions or duplications. D represents a set of identification numbers for the state variables. x i is the state variable with identification number i, x j is the state variable with identification number j. ij is a weighting coefficient that indicates the magnitude of interaction between state variables with identification numbers i and j. The two terms on the right side are the sum of the products of the bias coefficient and the state variable for each identification number.i denotes the bias coefficient for identification number i.

[0018] The three items on the right side are constraint terms whose values ​​depend on whether the constraint conditions are violated. k is the identification number of the constraint conditions, and A is the set of identification numbers of the constraint terms. Also, γ k is the proportionality coefficient for the constraint condition of identification number = k. k represents the weight of the constraint term related to the constraint condition of identification number = k. γ k g(h k ) is a function according to the type of constraint. k ) is sometimes called the penalty function. k h is the local field (LF) used to determine the constraint violation amount added to the value of the evaluation function when the constraint condition of identification number = k is not satisfied. k is expressed by the following equation (2). In the following, the first local field (h i To distinguish it from the k is sometimes called the second local field.

[0019]

number

[0020] In equation (2), W ki is the x for the constraint with identification number k i is the weighting coefficient. k is a coefficient related to the constraint condition of identification number=k. FIG. 1 is a diagram showing an example of the relationship between the state variables and the second local field.

[0021] Figure 1 shows multiple state variables (in the example of Figure 1, x1, x i , x N ) and the interactions between each of the multiple state variables and multiple second local fields (h p , hk , h r ) are shown by arrows. The magnitude of these interactions is W ij or W ki is equivalent to.

[0022] If the constraint with identification number = k is an inequality constraint, g(h k ) can be expressed by the following equation (3).

[0023]

number

[0024] In formula (3), max[0,h k ] is 0 and h k If the constraint is an inequality constraint, h k can be expressed by the following equation (4).

[0025]

number

[0026] R k is the consumption (also called resource amount) of the constraint term with identification number k, U k represents the upper limit of the amount of resources. The term on the right side of the above formula (2) is R in formula (4). k This corresponds to +b in equation (2). k is the -U in equation (4). k Equivalent to R k and U k The difference between these is the constraint violation amount.

[0027] In addition, g(h k ) can also be another function (e.g., a step function, etc.). Hereinafter, the Ising-type evaluation function for the first and second terms on the right-hand side of formula (1) may be written as E(x). Also, the three constraint terms on the right-hand side of formula (1) may be written as P(x). Using E(x) and P(x), the evaluation function for a combinatorial optimization problem with constraints can be expressed as H(x) = E(x) + P(x).

[0028] Note that a certain state variable (x i The change in the evaluation function value when the value of ) changes (ΔH i ) can be expressed by the following equation (5) using a penalty function.

[0029]

number

[0030] g(h k +W ki Δx i )-g(h k ) is a state variable (x i It represents the change in the value of the penalty function (which can also be called the change in the constraint term) when the value of

[0031] FIG. 2 is a diagram showing an example of the amount of change in the value of the penalty function due to the change in the value of the state variable. k ) and the horizontal axis represents the magnitude of h k It represents. In Fig. 2, an example of a penalty function is g(h k )=max[0,h k ] is used. x i With the change in the value of h k h k +W ki Δx i When the value of the penalty function changes to g(h k +W ki Δx i )-g(h k )

[0032] The first local field used to determine the change in the value of the evaluation function expressed by equation (5) is the variable (h i ) can be used.

[0033]

number

[0034] In equation (6), Δg(h k ,W ki Δx i ) is expressed by the following equation (7).

[0035]

number

[0036] As shown in equation (7), Δg(h k ,W ki Δx i ) is x i , h k , W ki This is a quantity that can be calculated from h as in equation (6) i By using ΔH i is ΔH i =-h i Δx i It can be expressed as:

[0037] The data processing device of each embodiment described below calculates the first local field (h i ) is used to perform multiple bit transition processing to search for a solution to a combinatorial optimization problem with constraints. In the following explanation, the number of state variables included in the evaluation function shown in formula (1) is assumed to be N, and the number of constraints is assumed to be M.

[0038] (First embodiment) FIG. 3 illustrates an example of the data processing device according to the first embodiment. The data processing device 10 has a weighting coefficient memory 11, a memory 12, a transition candidate determination circuit 13, an update circuit 14, an accumulation value calculation circuit 15, a judgment circuit 16, a control circuit 17, an evaluation function value update and hold circuit 18, a comparison circuit 19, and a minimum value update and hold circuit 20.

[0039] The weighting coefficient memory 11 is h i The N × N W in formula (6), which is the calculation formula for ij And M × N W ki W ki =W ik Therefore, the weighting coefficient memory 11 has N×M W ik In addition, the weighting coefficient memory 11 does not need to store W ki It is not necessary to store the weighting coefficient memory 11. The weighting coefficient memory 11 can be realized by, for example, a volatile storage device that is an electronic circuit such as a dynamic random access memory (DRAM) or a non-volatile storage device that is an electronic circuit such as a flash memory. The weighting coefficient memory 11 may also be a storage device such as a hard disk drive (HDD).

[0040] The weighting coefficient memory 11 is ij Or W ki In addition to the bias coefficient (b i ), proportionality coefficient (γ k ), the coefficients for the constraints (b k ) and other calculation condition data may be stored.

[0041] The memory 12 stores N state variables (x1 to x N ) (hereinafter, sometimes called the state) and the first local field (h1 to h N The memory 12 also stores values ​​of N state variables at a first time point in the solution search and values ​​of N first local fields at a first time point. The memory 12 also stores values ​​of M second local fields (h k ) and the values ​​of the M second local fields at the first time point are stored.

[0042] Here, the first time point is, for example, a time point at which a multiple bit transition process starts (hereinafter, referred to as a start point). In Fig. 3, the values ​​of the N state variables at the start point are denoted as start point states, and the values ​​of the N first local fields at the start point are denoted as start point first local fields. Also, the values ​​of the M local fields at the start point are denoted as start point second local fields.

[0043] The memory 12 may have a smaller storage capacity than the weighting coefficient memory 11. The memory 12 may be realized by, for example, a volatile storage device that is an electronic circuit such as an SRAM (Static Random Access Memory) or a register. However, the memory 12 is not limited to these storage devices.

[0044] The transition candidate determination circuit 13 uses the values ​​of the N first local fields to calculate the amount of change in the value of the evaluation function associated with the change in each of the values ​​of the N state variables. i The amount of change (ΔH i ) is ΔH i =-h i Δx i Therefore, the transition candidate determination circuit 13 can be expressed as h i to -Δx i By multiplying by ΔH i The transition candidate determination circuit 13 can calculate N ΔH i In addition, the transition candidate determination circuit 13 can calculate N ΔH i Based on the starting point, x1 to x N Then, candidates for changing the value (hereinafter referred to as transition candidates) are determined one by one.

[0045] In the following example, the data processing device 10 will be described as performing multiple bit transition processing of n (an integer of 2 or more) bits. n can also be called a transition bit depth. The transition candidate determination circuit 13 determines the n transition candidates one by one.

[0046] The transition candidate determination circuit 13 outputs the identification number of the state variable determined as the transition candidate and the amount of change in the value of the evaluation function when the value of the transition candidate is changed. An example of a method for determining a transition candidate and an example of the transition candidate determination circuit 13 will be described later (see FIG. 5).

[0047] Each time a transition candidate is determined, the update circuit 14 updates the values ​​of the transition candidate stored in the memory 12, and also updates the N first local field values ​​and the M second local field values. In the following example, it is assumed that the update circuit 14 performs such updates until n transition candidates are determined.

[0048] For example, x j When is determined as a transition candidate, the update circuit 14 updates N h i For each of these, Δh i =W ij Δx j By adding h i In addition, when i=j, W ii = 0, and h i does not change, so no update is required.

[0049] Also, x j When is determined as a transition candidate, the update circuit 14 updates M h k For each of these, Δh k =W kj Δx j By adding h k Update the W kj h = 0 k does not change and therefore no update is required.

[0050] Figure 4 shows x j 4 is a diagram showing an example of updating the first local field and the second local field when the value of h1 to h2 changes. In the example of FIG. 4, N first local fields are h1 to h2. N and M second local fields are expressed by h N+1 ~h N+M Such a calculation can be performed by parallel computing with a parallelism degree of N+M.

[0051] Furthermore, at a second time point, the update circuit 14 further updates the value of the first local field using the value of the second local field at the first time point and the value at the second time point. The second time point may be when the second local field is updated. In other words, the N values ​​of the first local field may be updated using the updated second local field every time a transition candidate is determined. Alternatively, the second time point may be a time point when a transition candidate is determined multiple times. For example, the second time point may be a time point when a transition candidate is determined n-1 times.

[0052] h at the second time i h k The update using can be expressed, for example, by the following equation (8).

[0053]

number

[0054] In equation (8), h k (old) represents the second local field at the first time point stored in the memory 12. Note that, when i=j, h i Since does not change, no update is required. k [Δg(h k ,W ki Δx i )-Δg(h k (old) ,W ki Δx i )], δh i It is sometimes written as:

[0055] In the above-mentioned update process, the state (start point state), the value of the first local field (start point first local field), and the value of the second local field (start point second local field) at the first time point are not updated. The update here is a provisional update, and the updated state, the first local field, and the second local field values ​​may be returned to the values ​​of the start point state, the start point first local field, and the start point second local field by a process described later. The update circuit 14 performs the above-mentioned update process under the control of the control circuit 17.

[0056] The cumulative value calculation circuit 15 calculates a cumulative value of the amount of change in the value of the evaluation function when the value of the transition candidate is changed. The cumulative value calculation circuit 15 can be realized by using, for example, an adder, a register, or the like.

[0057] The decision circuit 16 decides whether or not to accept the change in the value of the n transition candidates based on the cumulative value of the change in the value of the evaluation function by the MCMC process. For example, the cumulative value of the change is ΔE i When written as ΔE i The acceptance probability A of accepting a change in the value of a state variable that causes i can be expressed by equation (9).

[0058]

number

[0059] β is the inverse (β=1 / T) of T (T>0), a parameter that represents temperature, and is called the inverse temperature. Below, β and T may also be called temperature values. The min operator indicates that the minimum value of the arguments is taken. The upper right-hand side of equation (8) corresponds to the Metropolis method. The lower right-hand side of equation (3) corresponds to the Gibbs method.

[0060] The decision circuit 16 determines, for example, the acceptance probability A i The decision circuit 16 for making such a decision uses, for example, a uniform random number having a value between 0 and 1, and A i This can be achieved by using a comparator that outputs a value based on the comparison result with

[0061] When the decision circuit 16 determines that the changes in the values ​​of the n transition candidates are acceptable, the control circuit 17 causes the update circuit 14 to update the values ​​of the N state variables and the first and second local fields stored in the memory 12 to values ​​when the value of the n-th transition candidate has changed. When the decision circuit 16 determines that the changes in the values ​​of the n transition candidates are not acceptable, the control circuit 17 returns the updated values ​​of the N state variables and the first and second local fields to their values ​​at the first time point.

[0062] 1. The control circuit 17 has a function of controlling the operation of each element shown in FIG. For example, the control circuit 17 may select a W corresponding to the identification number output by the transition candidate determination circuit 13. ij or W ki from the weighting coefficient memory 11 to the update circuit 14. Furthermore, the control circuit 17 controls the temperature value (T or β) used in the judgment process by the judgment circuit 16. When the simulated annealing method is used as the MCMC method, the control circuit 17, for example, gradually decreases the value of T according to a predetermined schedule. When the replica exchange method is used as the MCMC method, the control circuit 17 controls the above circuits so that processing is performed independently for each of the multiple replicas of the Ising model. The control circuit 17 sets a different temperature value for each of the multiple replicas, and exchanges temperature values ​​between the replicas at a predetermined exchange probability in a predetermined period.

[0063] Furthermore, the control circuit 17 may switch whether to cause the transition candidate determination circuit 13 to execute single-bit transition processing or multiple-bit transition processing, based on the determination result output by the determination circuit 16. For example, when a solution search is performed using the single-bit transition processing, if a determination result indicating that a change in value is not acceptable continues for a predetermined period of time, the control circuit 17 switches from the single-bit transition processing to the multiple-bit transition processing.

[0064] In the single-bit transition process, the transition candidate determination circuit 13 performs a process of determining whether or not a change in value is permitted for each of the N state variables based on the amount of change in the value of the evaluation function. The determination at this time is performed according to the MCMC method, similar to the determination circuit 16. In the multiple-bit transition process, the transition candidate determination circuit 13 performs a process of determining transition candidates one by one from the starting point.

[0065] When a determination result indicating that a value change is not accepted continues for a predetermined period during a solution search using the multi-bit transition process, the control circuit 17 may increase the value of n in the multi-bit transition process. When a determination result indicating that a value change is accepted is obtained during a solution search using the multi-bit transition process, or when such a determination result continues for a predetermined period, the control circuit 17 may switch from the multi-bit transition process to the single-bit transition process.

[0066] Furthermore, when the judgment circuit 16 judges that the changes in the values ​​of the n transition candidates are not accepted, the control circuit 17 may control the transition candidate determination circuit 13 so that the same n transition candidates are not selected again.

[0067] The evaluation function value update and retention circuit 18 has a retention circuit such as a register, and retains the value of the evaluation function. When the judgment circuit 16 judges that the changes in the values ​​of the n transition candidates are to be accepted, the evaluation function value update and retention circuit 18 obtains the accumulated value of the amount of change in the value of the evaluation function calculated by the accumulation value calculation circuit 15, updates the value of the evaluation function with the accumulated value, and outputs it.

[0068] The comparison circuit 19 compares the value of the evaluation function held in the evaluation function value update and hold circuit 18 with the minimum value of the evaluation function held in the minimum value update and hold circuit 20 . The minimum value updating and holding circuit 20 has a holding circuit such as a register, and holds the minimum value of the evaluation function obtained so far. When the comparison circuit 19 outputs a comparison result indicating that the value of the evaluation function held in the evaluation function value updating and holding circuit 18 is smaller than the minimum value obtained so far, the minimum value updating and holding circuit 20 updates the minimum value with the value of the evaluation function. The minimum value updating and holding circuit 20 also holds the values ​​of the N state variables when the minimum value was obtained. Then, for example, the values ​​of the N state variables held when a predetermined termination condition is satisfied are output as a solution to the combinatorial optimization problem.

[0069] FIG. 5 is a diagram showing an example of a memory, an update circuit, and a transition candidate determination circuit. Note that FIG. 5 shows the weighting coefficient (W ij,W ki ,W ik ) memory example is also shown.

[0070] The memory 12 has a state storage area 12a, a starting point state storage area 12b, a first local field storage area 12c, a starting point first local field storage area 12d, a second local field storage area 12e, a starting point second local field storage area 12f, and access control circuits 12g and 12h.

[0071] The state storage area 12a stores values ​​of N state variables, and the starting point state storage area 12b stores values ​​of N state variables at a first time point of the solution search (hereinafter referred to as the starting point). The first local field storage area 12c stores values ​​of N first local fields, and the starting point first local field storage area 12d stores values ​​of N first local fields at the starting point. The second local field storage area 12e stores values ​​of M second local fields, and the starting point second local field storage area 12f stores values ​​of M second local fields at the starting point.

[0072] The access control circuit 12g controls reading and writing of states between the state storage area 12a, the start point state storage area 12b, and the state update holding circuit 14a of the update circuit 14, based on the control of the control circuit 17 shown in Fig. 3. Based on the control of the control circuit 17, for example, the following operations are performed.

[0073] When a state variable is updated, the access control circuit 12g overwrites the value of the state variable stored in the state storage area 12a with the updated value of the state variable. 3 determines that the changes in the values ​​of the n transition candidates are acceptable, the access control circuit 12g overwrites the start point state of the start point state storage area 12b with the values ​​of the N state variables of the state storage area 12a. The values ​​of the N state variables of the state storage area 12a are the updated values ​​of n of the N state variables at the start point.

[0074] If the judgment circuit 16 determines that the changes in the values ​​of the n transition candidates are not accepted, the access control circuit 12g overwrites the values ​​of the N state variables in the state memory area 12a with the values ​​of the N state variables at the start point of the start point state memory area 12b.

[0075] The access control circuit 12h accesses the first local field storage area 12c, the starting point first local field storage area 12d, and the update circuit 14h under the control of the control circuit 17. i The access control circuit 12h controls the read and write of the first local field between the holding circuit 14f and the second local field storage area 12e, the starting point second local field storage area 12f, and the update circuit 14h under the control of the control circuit 17. k The control circuit 17 controls the reading and writing of the second local field between the holding circuit 14g and the control circuit 17. For example, the following operations are performed based on the control of the control circuit 17.

[0076] When the process of the transition candidate determination circuit 13 is performed, the access control circuit 12h calculates the N first local field values ​​in the first local field storage area 12c by i Write to the holding circuit 14f. When the value of the first local field is updated, the access control circuit 12h overwrites the value of the local field in the first local field storage area 12c with the updated value of the first local field.

[0077] If the judgment circuit 16 determines that the changes in the values ​​of the n transition candidates are to be accepted, the access control circuit 12h overwrites the N first local field values ​​at the start point of the start point first local field memory area 12d with the N first local field values ​​in the first local field memory area 12c.

[0078] If the judgment circuit 16 determines that the changes in the values ​​of the n transition candidates are not accepted, the access control circuit 12h overwrites the N first local field values ​​in the first local field memory area 12c with the N first local field values ​​at the start point of the start point first local field memory area 12d.

[0079] When the process of the transition candidate determination circuit 13 is performed, the access control circuit 12h updates the values ​​of M auxiliary variables in the second local field storage area 12e by h k Write to the holding circuit 14g. When the value of the second local field is updated, the access control circuit 12h overwrites the value of the second local field in the second local field storage area 12e with the updated value of the second local field.

[0080] If the judgment circuit 16 determines that the changes in the values ​​of the n transition candidates are to be accepted, the access control circuit 12h overwrites the M second local field values ​​at the start point of the start point second local field memory area 12f with the M second local field values ​​in the second local field memory area 12e.

[0081] If the judgment circuit 16 determines that the changes in the values ​​of the n transition candidates are not accepted, the access control circuit 12h overwrites the M second local field values ​​in the second local field memory area 12e with the M second local field values ​​at the start point of the start point second local field memory area 12f.

[0082] At a second time point when the first local field is updated using the values ​​of the second local field, the access control circuit 12h updates the M values ​​of the second local field in the start point second local field storage area 12f by, for example, h k Write to the holding circuit 14g.

[0083] The transition candidate determination circuit 13 includes a ΔH calculation circuit 13a, a ΔH holding circuit 13b, a FF (Flip-Flop) 13c, an acceptance determination circuit 13d, and a selection circuit 13e. The ΔH calculation circuit 13a uses the values ​​of the N first local fields to calculate the amount of change in the value of the evaluation function associated with the change in each of the values ​​of the N state variables. i The amount of change (ΔH i ) is ΔH i =-h i Δx i It can be expressed as Δx i is stored in the state storage area 12a. N It can be calculated from the value of

[0084] In addition, the ΔH calculation circuit 13a calculates ΔH for a state variable that has become a transition candidate once while n transition candidates are being determined. i This is to prevent a state variable that has once become a transition candidate from becoming a transition candidate again and returning to its original value.

[0085] The ΔH holding circuit 13b stores the N ΔHs calculated by the ΔH calculation circuit 13a. i Hold. FF13c is h k Hold the value of h k By delaying the timing of outputting h k (old) Update circuit 14 h k The result is supplied to the contribution calculation circuit 14e.

[0086] The acceptance judgment circuit 13d accepts a change in the value of at least one state variable. For example, the acceptance judgment circuit 13d judges whether the change in value is a ΔH i The identification number of the state variable that causes ΔH i The acceptance determination circuit 13d outputs, for example, ΔH i Identification numbers of multiple state variables that cause ΔH i The acceptance determination circuit 13d may be configured to accept changes in the values ​​of one or more state variables in accordance with a predetermined rule.

[0087] When single-bit transition processing is performed, the acceptance determination circuit 13d accepts a change in the value of each state variable with the acceptance probability shown in equation (9). When the acceptance determination circuit 13d accepts changes in the values ​​of a plurality of state variables, the selection circuit 13e selects one of the state variables whose value change has been accepted, and outputs the identification number of the selected state variable and the ΔH i For example, the selection circuit 13e may select one state variable randomly, or may select one state variable according to a predetermined rule.

[0088] The identification number of the state variable selected by the selection circuit 13e is supplied to the control circuit 17 shown in FIG. 3, and a ΔH i is supplied to the accumulation value calculation circuit 15. The update circuit 14 includes state update and hold circuits 14a, x k Holding circuit 14b, h i h k Update circuit 14c, h k Update detection circuit 14d, h k Contribution calculation circuit 14e, h i Holding circuit 14f, h k It has a holding circuit 14g.

[0089] The state update and hold circuit 14a holds the values ​​of N state variables. Under the control of the control circuit 17, the state update and hold circuit 14a updates the value of the state variable selected by the selection circuit 13e.

[0090] x k The holding circuit 14b holds M x k Holds the value of x k can be used, for example, to detect whether the constraint condition of the identification number = k is satisfied. In the case of inequality constraints, h k If >0, g(h k )>0, and the constraint is violated. For example, h k If >0 then x k =1, h k If ≦0, then x k =0 is x k However, the data processing device 10 of the present embodiment may be configured to hold x k In that case, x k The holding circuit 14b is not necessary.

[0091] h i h k The update circuit 14c, under the control of the control circuit 17, updates the first local field (h i ) and the second local field (h k) value. For example, x j If h is a transition candidate, i h i =h i +W ij Δx j The value is updated to h i h k The update circuit 14c is j If h is determined as a transition candidate, k h k =h k +W kj Δx j is updated to the value.

[0092] h k The update detection circuit 14d detects k Detects updates to W kj If =0, h for the constraint with identification number = k k Updates to the are not detected. h k The contribution calculation circuit 14e detects the update. k Changes in the value of h i The change in (δh i ) from the weighting coefficient memory 11. ki Read out h k The contribution calculation circuit 14e calculates h k h k Obtained from the holding circuit 14g, h k (old) Get from FF13c. And h k The contribution calculation circuit 14e calculates Δh i Calculate the original h i δh i By adding h i Update.

[0093] h k Based on the value of h i If the second time point at which the value of is updated is the time point at which n-1 transition candidates are determined, then h k (old) The value of the second local field at the starting point is used as h iThe holding circuit 14f holds the N values ​​of the first local field.

[0094] h k The holding circuit 14g holds the M values ​​of the second local field. Each circuit of the data processing device 10 as described above can be realized by using an electronic circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). At least a part of each circuit of the data processing device 10 can also be realized by software processing in which a processor executes a program. Processors include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and a DSP (Digital Signal Processor).

[0095] Next, the flow of the data processing method (solution search) by the data processing device 10 described above will be described with reference to a flowchart. FIG. 6 is a flowchart illustrating a flow of an example of the data processing method according to the first embodiment.

[0096] First, initialization is performed under the control of the control circuit 17 (step S10). In the process of step S10, the initial values ​​of the N state variables, the initial value of the evaluation function, the initial values ​​of the N first local fields, the initial values ​​of the M second local fields, and the end condition of the solution search are set. Furthermore, when the simulated annealing method is performed, for example, the start value and end value of the temperature value, and the value by which the temperature value is multiplied for each predetermined temperature change period are set. When the replica exchange method is performed, the temperature value for each replica, the replica exchange period, and the like are set.

[0097] The control circuit 17 judges whether or not to start the multi-bit transition process (step S11). For example, the control circuit 17 starts the single-bit transition process at the start of the solution search, and starts the multi-bit transition process if the judgment result indicating that the value change is not accepted continues for a predetermined period of time.

[0098] When the control circuit 17 determines not to start the multi-bit transition process, the process of step S12 is performed. In the process of step S12, a single-bit transition process is performed. The flow of the single-bit transition process will be described later (see FIG. 7). After the process of step S12, the process of step S18 is performed.

[0099] When the control circuit 17 determines to start the multi-bit transition process, the process of step S13 is performed. In the process of step S13, various multi-bit transition parameters used when performing the multi-bit transition process are set. The various multi-bit transition parameters include n, which is the aforementioned transition bit depth, and L, which is the number of repetition trials for repeating the multi-bit transition process. n and L may be input to the data processing device 10 by the user, or may be set in advance in a holding circuit such as a register in the data processing device 10. Further, the control circuit 17 sets the flag variable Mflip_flag, which becomes 1 when the change of the values of a plurality of transition candidates is allowed, to 0.

[0100] After the process of step S13, between k = 1 and k < L, the process of the multi-bit transition trial loop (steps S14 to S17) is repeated. In the multi-bit transition trial loop, a multi-bit transition process is performed (step S15). The flow of the multi-bit transition process will be described later (see FIG. 8).

[0101] After the process of step S15, the control circuit 17 determines whether Mflip_flag is 0 (step S16). When the control circuit 17 determines that Mflip_flag is 0, when k < L, k is incremented by 1 and the process from step S15 is repeated.

[0102] When the control circuit 17 determines that Mflip_flag is not 0, or when k reaches L, the process of step S18 is performed. In the process of step S18, the control circuit 17 judges whether or not to end the solution search. For example, when a predetermined end condition is satisfied, the control circuit 17 judges to end the solution search, outputs the solution to the combinatorial optimization problem that is the result of the solution search (step S19), and ends the process. In the process of step S19, for example, when it is judged to end the solution search, the values ​​of the N state variables held in the minimum value update holding circuit 20 are output as the solution to the combinatorial optimization problem. The control circuit 17 may display the solution on a display device (not shown), or may transmit the solution to an external device via a communication circuit (not shown).

[0103] When the control circuit 17 determines not to end the solution search, it repeats the process from step S11. FIG. 7 is a flow chart showing an example of a single bit transition process.

[0104] The transition candidate determination circuit 13 uses the current values ​​of the N first local fields to determine ΔH i is calculated (step S20). Then, the transition candidate determination circuit 13 performs an acceptance determination (step S21). The transition candidate determination circuit 13, for example, determines ΔH i Based on the temperature value supplied from the control circuit 17, the change in the value of each state variable is accepted with the acceptance probability shown in equation (9).

[0105] When changes in the values ​​of a plurality of state variables are accepted, the transition candidate determination circuit 13 selects one state variable to be updated (step S22). After that, the transition candidate determination circuit 13 judges whether or not the update is possible (step S23). For example, if the change in value of any of the state variables is not accepted in the process of step S21, it is judged that the update is not possible.

[0106] When the transition candidate determination circuit 13 determines that an update is possible, the update circuit 14 performs an update process (step S24). In the update process, the value of the state variable that has been made updatable changes. Then, based on this change, the values of the first and second local fields are updated.

[0107] At this time, the evaluation function value update and hold circuit 18 updates the held evaluation function value based on ΔH i associated with the change in the value of the state variable that has been made updatable. If the updated evaluation function value is smaller than the minimum value of the evaluation function held by the minimum value update and hold circuit 20, the minimum value is updated and held in the minimum value update and hold circuit 20 together with the current values of the N state variables.

[0108] If it is determined in the process of step S23 that an update is not possible, or after the process of step S24, the process of the data processing device 10 returns to the process of step S18 shown in FIG. 6. FIG. 8 is a flowchart showing the flow of an example of multi-bit transition processing of the data processing method according to the first embodiment.

[0109] The memory 12 stores the state, h i and h k values at the starting point (step S30). Thereafter, between i = 0 and i < n, the following processing of the n-bit transition trial loop (steps S31 to S48) is repeated.

[0110] In the n-bit transition trial loop, the transition candidate determination circuit 13 selects a calculation target for ΔH i . While n transition candidates are being determined, for the state variable that has once become a transition candidate, it is removed from the calculation target for ΔH i . The transition candidate determination circuit 13 uses h i stored in the memory 12 to calculate ΔH i selected as the calculation target (step S33).

[0111] Then, the transition candidate determination circuit 13 performs an acceptance determination (step S34). The transition candidate determination circuit 13 accepts the change in the value of at least one state variable. When the transition candidate determination circuit 13 receives changes in the values ​​of multiple state variables, it selects one of them and determines it as a transition candidate. The update circuit 14 updates the state by changing the value of the transition candidate (step S35). The state update here is a tentative update.

[0112] After the process of step S35, the cumulative value calculation circuit 15 calculates the ΔH i The accumulated value is calculated (step S36). After the process of step S36, the control circuit 17 judges whether i is n-1 or not (step S37). That is, it is judged whether n transition candidates are determined or not. If the control circuit 17 judges that i is n-1, the process of step S38 is performed. If the control circuit 17 judges that i is not n-1, the process of step S45 is performed.

[0113] In the process of step S38, the decision circuit 16 calculates ΔH i Based on the accumulated value, it is determined whether or not to accept the change in the value of the n transition candidates. The control circuit 17 judges whether the judgment circuit 16 has accepted the changes in the values ​​of the n transition candidates (step S39). If the judgment circuit 16 has accepted the changes in the values ​​of the n transition candidates, the control circuit 17 performs the process of step S40. If the judgment circuit 16 has not accepted the changes in the values ​​of the n transition candidates, the control circuit 17 performs the process of step S43.

[0114] In the process of step S40, the control circuit 17 sets the value of Mflip_flag to 1. After that, the update circuit 14 updates h i Update the value of h (step S41) k is updated (step S42).

[0115] In the process of step S43, the control circuit 17 sets the value of Mflip_flag to 0. After that, the control circuit 17 controls the state and i , h k The value of is restored to the stored state and value at the starting point (step S44).

[0116] After the processing of steps S42 and S44, i is incremented by 1 to become i=n, ​​so that the processing of the data processing device 10 leaves the n-bit transition trial loop and returns to the processing of step S18 shown in FIG.

[0117] The update circuit 14 updates h i Update the value of h (step S45) k Then, the update circuit 14 updates the value of h k And, h k (old) Using h i The value of is further updated (step S47).

[0118] After that, i is incremented by 1 and the n-bit transition trial loop is repeated. FIG. 9 is a flowchart showing the flow of another example of the multiple bit transition process of the data processing method according to the first embodiment.

[0119] The processing in steps S50 to S66 is the same as the processing in steps S30 to S46 shown in FIG. After the process of step S66, the control circuit 17 judges whether i is n-2 or not (step S67). That is, it is judged whether n-1 transition candidates have been determined or not. If the control circuit 17 judges that i is n-2, the process of step S68 is performed. If the control circuit 17 judges that i is not n-2, i is incremented by 1, and the n-bit transition trial loop (steps S51 to S69) is repeated.

[0120] In the process of step S68, the update circuit 14 k And the starting point h k h k (old) Using hi The value of i is then incremented by 1, and the n-bit transition trial loop (steps S51 to S69) is repeated.

[0121] In the examples of Figs. 8 and 9, ΔH i However, the present invention is not limited to the above example. For example, the ΔH calculated each time a transition candidate is determined may be used. i The acceptance decision may be made based on the cumulative value of .

[0122] Moreover, the order of the processes shown in FIGS. 6 to 9 is an example, and the order of the processes may be changed as appropriate. (Example of pipeline processing) The above processing can be performed in parallel for multiple replicas using pipeline processing. Memory 12 stores the values ​​of N state variables, the values ​​of N first local fields, and the values ​​of M second local fields for the number of replicas. Memory 12 may also store the values ​​of N state variables, N values ​​of the first local fields, and M values ​​of the second local fields at the start point for the number of replicas, or may store these values ​​common to all replicas. The weighting coefficients W stored in weighting coefficient memory 11 ij , W ki , W ik is common to all replicas.

[0123] The control circuit 17 causes the transition candidate determination circuit 13, the update circuit 14, the accumulation value calculation circuit 15, and the judgment circuit 16 to perform pipeline processing on a plurality of replicas. Note that the control circuit 17 may perform control so that single-bit transition processing is performed on some replicas.

[0124] Figures 10 and 11 are diagrams illustrating a first example of pipeline processing in the data processing method according to the first embodiment. Note that Figures 10 and 11 illustrate an example in which the multi-bit transition processing illustrated in Figure 8 is performed by pipeline processing.

[0125] In Fig. 10, the notation 0 to R-1 indicates replica numbers of R replicas. In the example of Fig. 10, trials with multiple bit transitions with a transition bit depth n of 3 bits are started at the same timing in all replicas. Note that the control circuit 17 can control each replica as an independent process, so the trial start timing and the value of n may differ among the multiple replicas. In addition, in pipeline processing, a FIFO is used to adjust the operation timing.

[0126] The process performed by each replica is divided into an update phase and a trial phase. ij and W kj Lead, W ij Δx j (=Δh i ), W kj Δx j (=Δh k ), δh i Calculation of h i and h k The trial phase includes updating the h i Read h from memory 12 k or h k (old) Leads, starting point state and h i , h k Store in memory 12, ΔH i Calculation of ΔH i This includes calculating the cumulative value and making an acceptance decision based on the cumulative value.

[0127] At time t1, the trial phase begins to determine the first transition candidate. For each replica, in turn, h i is read from memory 12, and h i It is held in the holding circuit 14f.

[0128] From time t2, for each replica, the starting state and h i , h k is stored in the memory 12. Also, from the timing t2, ΔH i The calculation is performed.

[0129] For each replica, from time t3 onwards, ΔH i In the example of FIG. 10, the cumulative value of ΔH i The acceptance decision based on the cumulative value of is not made until the third transition candidate is determined. Although not shown in the figure, from the timing t3, ΔH i 10, the process during the period (timing t3 to t9) during which the first transition candidate is determined for the R replicas is represented as 1st bit transition process.

[0130] When the first transition candidate is determined for each replica in turn from timing t3, the identification number of the state variable is supplied via the FIFO to the control circuit 17. After that, the update phase for the first transition candidate starts (timing t4).

[0131] The control circuit 17 sequentially calculates the W corresponding to the identification number of the transition candidate for each replica from the timing t4. ij and W kj is read from the weighting coefficient memory 11. Then, starting from timing t5, W ij Δx j (=Δh i ) and W kj Δx j (=Δh k ) is calculated. Furthermore, from timing t6, h i and h k The update process is performed.

[0132] At time t7, the trial phase begins to determine the second transition candidate. For each replica in turn, h i is read from memory 12, and h i It is held in the holding circuit 14f.

[0133] From time t8, for each replica, ΔH iAlso, from the timing t9, ΔH i 10, the process during the period (timing t9 to t13) during which the second transition candidate is determined for the R replicas is represented as a 2nd bit transition process.

[0134] From timing t10, an update phase associated with the determination of the second transition candidate starts, and the same processing as that from timing t4 to t6 is performed. From the timing t11, the first local field is updated using the second local field. From the timing t11, the first local field is updated for each replica in turn. k and k (old) One of the two is read from memory 12, and k The data is stored in the storage circuit 14g. From the timing t12, the data is stored in the storage circuit 14g. k and k (old) The other one is read from memory 12, and k The second local field values ​​are held in the holding circuit 14g. In the example of Fig. 10, for the replica with replica number = 1, two second local field values ​​change, so reading is performed in two cycles (a1, a2). In Fig. 10, the processing during the period (timings t13 to t18) during which the second local field values ​​are read for the R replicas is denoted as second local field processing.

[0135] From timing t14, the first local field is updated using the second local field. From timing t14, the value of h that has changed from the starting point is updated for each replica in turn. k W corresponding to the identification number k ki is read from the weighting coefficient memory 11. Then, from timing t15, Δh i Furthermore, from the timing t16, Δh is calculated for each replica in turn. i Using h i The update process is performed.

[0136] From timing t17, a trial phase for determining the third transition candidate starts, and the same process as that from timing t8 to t9 is performed. In Fig. 11, the process during the period (timing t18 to t23) during which the third transition candidate is determined for the R replicas is represented as the third bit transition process.

[0137] From timing t19, ΔH i 11, a white circle indicates that the application is determined to be acceptable, and a black square indicates that the application is rejected.

[0138] In the example of FIG. 11, the replica with replica number = 0, R-1 is judged as acceptable, and the other replicas are rejected. Therefore, the update phase is executed for the replica with replica number = 0, R-1 (timing t20 to t26). The update phase is not executed for the other replicas, and the state at the start point is the same as h i ,h k is read and the current state and h i ,h k is written to the memory 12.

[0139] From timing t21, the first local field is updated using the second local field. For replicas with replica numbers = 0 and R-1, at the processing timing of each replica, h k and k (old) One of the two is read from memory 12, and k The data is stored in the storage circuit 14g. From the timing t22, for the replicas with replica numbers 0 and R-1, at the processing timing of each replica, h k and k (old) The other one is read from memory 12, and k It is held in the holding circuit 14g.

[0140] From timing t24, the first local field is updated using the second local field. From timing t14, the replicas with replica numbers = 0, R-1 are updated by calculating the change in h from the starting point at the processing timing of each replica. k W corresponding to the identification number k ki are read from the weighting coefficient memory 11. Then, from timing t25, δh i Furthermore, from the timing t26, δh i Using h i The update process of h at the starting point is performed for other replicas. i ,h k Using h i ,h k will be updated.

[0141] After that, from timing t27, a trial phase for determining the first transition candidate starts again, and the same process as that from timing t1 is performed. When the above-mentioned pipeline processing is performed, for example, the state showing the minimum value among the values ​​of the evaluation function obtained while the processing of each replica is repeated a predetermined number of times is output as a solution. Note that the above-mentioned pipeline processing can be applied to a solution search using the simulated annealing method, and can also be applied to a solution search using the replica exchange method.

[0142] The control circuit 17 controls multiple replicas so that different processes are performed by the different replicas during the same period through pipeline processing, thereby enabling multiple replicas to be processed simultaneously in parallel. As shown in Figures 10 and 11, one step of each replica process (each process in the trial phase + update phase) has the same duration for each process that changes the value of one transition candidate (1st bit transition process, 2nd bit transition process, 3rd bit transition process). This makes it possible to hide the pipeline delay of each replica process.

[0143] Figures 12 and 13 are diagrams showing a second example of the pipeline processing of the data processing method according to the first embodiment. Note that Figures 12 and 13 show an example in which the multi-bit transition processing shown in Figure 9 is performed by pipeline processing.

[0144] The process from timing t30 to timing t36 is the same as the process from timing t1 to t7 shown in FIG. From timing t36, the first local field is updated using the second local field. The process from timing t36 to one cycle before timing t43 is the same as the process from timing t11 to timing t18 shown in Figs. 10 and 11.

[0145] The process from one cycle before timing t43 to timing t47 is the same as the process from timing t19 to timing t23 shown in FIG. The process from timing t47 to timing t51 is the same as the process from timing t23 to timing t27 shown in FIG.

[0146] 12 and 13, the difference from the value at the start point of the second local field is reflected in the first local field every time a transition candidate is determined. After it is determined whether or not to accept the transitions of the n transition candidates, the above-mentioned difference of the second local field does not need to be reflected in the first local field for replicas other than the accepted replicas, so that the pipeline processing period can be shortened.

[0147] According to the data processing device 10 and the data processing method of the first embodiment described above, the state and the values ​​of the first and second local fields at the first time point (the starting point in the above example) are stored. Then, from that time point, the values ​​of the transition candidates determined one by one are changed to update the first and second local fields, and ΔH iWhether or not to accept the change in the value of the transition candidates is determined based on the cumulative value of n. Even if the state and the values ​​of the first and second local fields are updated based on the change in the value of the transition candidates, at the time of the above-mentioned acceptance or rejection, they are returned to the state and the values ​​of the first and second local fields stored in advance at the first time point. In this way, a complex propagation mechanism of the local field for realizing a multi-bit transition is not required. This makes it possible to increase the independence of the arithmetic unit for each bit, simplifies the circuit configuration, and makes it easier to implement multi-bit transition processing. This also makes it possible to achieve large-scale parallelization. Furthermore, since processing can be performed using the same circuit even if the number (n) of transition candidates changes, there is a high degree of freedom in searching.

[0148] Furthermore, since single-bit transition processing and multiple-bit transition processing can be realized in the same circuit, switching of operation modes is easy. Furthermore, it is possible to realize pipeline processing using multiple replicas as shown in FIGS. 10 to 13 without complicating the circuit configuration, and high performance can be expected.

[0149] Moreover, according to the data processing device 10 and the data processing method of the first embodiment, the second local field is used to identify the constraint violation amount added to the value of the evaluation function when the constraint condition is not satisfied. The second local field has a value stored in the memory 12 at the first time point as described above. The second local field is updated every time a transition candidate is determined. Then, at the second time point, the value of the first local field is further updated using the value of the second local field at the first time point and the value of the second local field at the second time point. Furthermore, when it is determined that the change in the value of the n transition candidates is not accepted, the value of the second local field is returned to the value at the first time point. This makes it possible to apply the above-mentioned multi-bit transition processing to a combinatorial optimization problem having constraint conditions.

[0150] 9 to 11, the data processing device 10 may update the first local field using the values ​​of the second local field at the first and second time points when a plurality of transition candidates are determined (in the above example, when n-1 transition candidates are determined). This makes it possible to reflect the changes in the second local field collectively, as compared with the case where the changes in the second local field are reflected in the first local field every time, thereby reducing the number of calculations.

[0151] Such a data processing device 10 is expected to be useful as a means for quickly obtaining accurate solutions when solving various problems in modern society that can be converted into combinatorial optimization problems with constraints.

[0152] (Second embodiment) A data processing device according to a second embodiment described below divides N state variables into a plurality of state variable groups, and executes, in parallel, determination of n transition candidates, update processing, calculation of cumulative values, etc., for each state variable group using a plurality of modules. Note that, in the following, an example is shown in which N state variables are divided into three state variable groups and processing is performed using three modules, but the number is not limited to this.

[0153] Figures 14 and 15 are diagrams illustrating an example of a data processing device according to the second embodiment. In Figures 14 and 15, the same elements as those illustrated in Figures 3 and 5 are denoted by the same reference numerals.

[0154] In the data processing device 30 according to the second embodiment, the transition candidate determination circuit 31 includes modules 31a1, 31a2, and 31a3. N Then, n transition candidates are determined one by one within the ranges of the mutually different state variable groups.

[0155] For example, the module 31a1 is x1 to x k-1 The state variable group of module 31a2 is x k ~x l-1 The state variable group of module 31a3 is x l ~x NWe deal with a set of state variables.

[0156] Each of modules 31a1 to 31a3 is provided with ΔH calculation circuit 13a, ΔH holding circuit 13b, acceptance judgment circuit 13d, and selection circuit 13e shown in Fig. 5. In Fig. 14, ΔH calculation circuit 13a and ΔH holding circuit 13b are collectively written as "ΔH calculation", acceptance judgment circuit 13d is written as "acceptance", and selection circuit 13e is written as "selection".

[0157] Further, the transition candidate determination circuit 31 includes a selection circuit 31b and an FF unit 31c. The selection circuit 31b, under the control of the control circuit 17, determines whether a ΔH i The transition candidate identification number is similarly selected and supplied to one of the holding circuits 33b1, 33b2, 33b3 for the modules 31a1 to 31a3. The FF unit 31c has the FF 13c shown in FIG. 5, which is the number of the modules 31a1 to 31a3, that is, three. As a result, k (old) It is possible to output three in parallel.

[0158] The identification number and ΔH of the first transition candidate output from each of the modules 31a1 to 31a3 i The identification numbers and ΔH of the second and subsequent transition candidates output from each of the modules 31a1 to 31a3 may be supplied to the calculation circuits 33a1 to 33a3 and the holding circuits 33b1 to 33b3 for any of the modules. i are supplied to the calculation circuits 33a1 to 33a3 and the holding circuits 33b1 to 33b3 for the corresponding modules, respectively.

[0159] As the selection circuit 31b that performs such a selection, for example, a 3-lane 3-1 selector can be used. In the update circuit 32, the state update and hold circuit 32a holds three state variable groups. The three state variable groups are obtained by dividing the values ​​of N state variables into three. The state update and hold circuit 32a can update in parallel the values ​​of the state variables selected by the selection circuit 31b from each state variable group under the control of the control circuit 17. The state update and hold circuit 32a also selects, in parallel, Δx j can be output in parallel.

[0160] In addition, in the update circuit 32, h i h k Under the control of the control circuit 17, the update circuit 32b updates the first local field (h i ) and the second local field (h k ) value. For example, x j If h is a transition candidate, i h i =h i +W ij Δx j Also, the value is updated to x j If h is determined as a transition candidate, k h k =h k +W kj Δx j is updated to the value.

[0161] h k The update detection circuit 32d detects the x j Three sets of h with changing values ​​of k Detects updates to W kj If =0, h for the constraint with identification number = k k Updates to the .

[0162] h k The contribution calculation circuit 32c calculates three sets of h k Updates were detected in k Changes in the value of h i The change in (δh i ) used to calculate nonzero W kiis read from the weighting coefficient memory 11. Furthermore, h k The contribution calculation circuit 32c calculates three sets of h k h k Obtained from holding circuit 32f, h k (old) is obtained from the FF unit 31c. k The contribution calculation circuit 32c calculates three sets of h k δh with each change i Calculate h in the first local field group corresponding to each pair. i δh i By adding h i Update.

[0163] h i The holding circuit 32e has N h i is divided into three parts corresponding to the three sets of state variables. N / 3 h i is selected from the corresponding set of state variables x j The change in (Δx j ) is used to update the

[0164] h k The holding circuit 32f has M h k Three sets of these are stored corresponding to the three modules 31a1 to 31a3. The cumulative value calculation circuit 33 in FIG. 15 calculates ΔH i The cumulative value calculation circuit 33 further includes holding circuits 33b1-33b3 that hold identification numbers of n transition candidates for the modules 31a1-31a3, respectively, and a selection circuit 33c.

[0165] The selection circuit 33c selects three ΔH i For example, the selection circuit 33c selects one of the accumulated values ​​of ΔH i The selection circuit 33c selects the accumulated value of n, and outputs the selected accumulated value together with the indices of the n transition candidates corresponding to the accumulated value.

[0166] The decision circuit 16 decides, based on the selected cumulative value, whether or not to accept changes in the values ​​of the n transition candidates corresponding to the selected cumulative value. Next, the flow of a data processing method (solution search) by the data processing device 30 of the second embodiment will be described with reference to a flowchart.

[0167] The overall process and the flow of the single bit transition process are similar to the process flows shown in FIG. 6 and FIG. 7, and therefore a description thereof will be omitted. FIG. 16 is a flowchart illustrating an example of a multiple bit transition process of the data processing method according to the second embodiment.

[0168] The processing in steps S70 to S88 in FIG. 16 is substantially the same as the processing in steps S30 to S48 shown in FIG. However, the processes of steps S72 to S76 and steps S85 to S87 are performed for each module. Also, in the process of step S78, the decision circuit 16 selects three ΔH i Using one cumulative value selected from the cumulative values, it is determined whether or not to accept changes in the values ​​of the n transition candidates corresponding to that cumulative value.

[0169] Furthermore, in the process of step S81, first, a process is performed to restore the state and the value of the first local field for each module to the state and the value of the first local field at the stored start point. This is because the held state and the first local field are different for each module. Then, the control circuit 17 causes the update circuit 32 to update the state and the value of the first local field for each module based on the identification numbers of the n transition candidates held in any of the holding circuits 33b1 to 33b3.

[0170] In the process of step S82, the second auxiliary variable (h k The values ​​of the second local fields held corresponding to the other modules are also updated so that the value of

[0171] Furthermore, in the processing of step S84, the control circuit 17 restores the values ​​of the N / 3 state variables, the N / 3 values ​​of the first local field, and the M values ​​of the second local field held corresponding to the three modules 31a1 to 31a3 to the values ​​stored at the starting point.

[0172] FIG. 17 is a flowchart showing the flow of another example of the multiple bit transition process of the data processing method according to the second embodiment. The processing in steps S90 to S109 in FIG. 17 is almost the same as the processing in steps S50 to S69 shown in FIG.

[0173] However, the processes of steps S92 to S96 and steps S105 to S108 are performed for each module. Also, in the process of step S98, the decision circuit 16 selects three ΔH i Using one cumulative value selected from the cumulative values, it is determined whether or not to accept changes in the values ​​of the n transition candidates corresponding to that cumulative value.

[0174] Furthermore, in the process of step S101, first, a process is performed to restore the state and the value of the first local field for each module to the state and the value of the first local field at the stored start point. After that, the control circuit 17 causes the update circuit 32 to update the state and the value of the first local field for each module based on the identification numbers of the n transition candidates held in any of the holding circuits 33b1 to 33b3.

[0175] In the process of step S102, the second local field (h k The values ​​of the second local fields held corresponding to the other modules are also updated so that the value of

[0176] Furthermore, in the processing of step S104, the control circuit 17 restores the values ​​of the N / 3 state variables, the N / 3 values ​​of the first local field, and the M values ​​of the second local field held corresponding to the three modules 31a1 to 31a3 to the values ​​stored at the starting point.

[0177] It should be noted that the order of the processes shown in FIGS. 16 and 17 is merely an example, and the order of the processes may be changed as appropriate. (Example of pipeline processing) As with the data processing of the data processing device 10 of the first embodiment, the above processing can be performed in parallel for multiple replicas of the Ising model using pipeline processing. The memory 12 stores the values ​​of N state variables, N values ​​of the first local field, and M values ​​of the second local field for each module, for the number of replicas. The memory 12 may also store the values ​​of N state variables, N values ​​of the first local field, and M values ​​of the second local field at the start point, for the number of replicas, or may be common to all replicas. In that case, however, in order to prevent multiple replicas from using the memory 12 at the same time, control is performed so that multiple bit transition processing does not occur in any replica other than one replica in the pipeline processing. The weight coefficient W stored in the weight coefficient memory 11 ij , W ki , W ik is common to all replicas.

[0178] The control circuit 17 causes the transition candidate determination circuit 31, the update circuit 32, the accumulation value calculation circuit 33, and the judgment circuit 16 to perform pipeline processing on a plurality of replicas. Note that the control circuit 17 may perform control so that single-bit transition processing is performed on some replicas.

[0179] Figures 18 and 19 are diagrams showing an example of pipeline processing of the data processing method of the second embodiment. Note that Figures 18 and 19 show an example in which the multi-bit transition processing shown in Figure 16 is performed by pipeline processing. It is also possible to perform the multi-bit transition processing shown in Figure 17 by pipeline processing. Below, differences from the timing chart shown in Figure 12 will be mainly described.

[0180] Each process in the update phase is performed for each module. In the trial phase, all processes except the acceptance determination based on the accumulated value by the determination circuit 16 are performed for each module. From timing t60 to t74, the process is the same as that from timing t30 to t44 shown in Fig. 12, except that the above process is performed for each module. From timing t75 to t76, the process of step S81 shown in Fig. 16 is performed to restore the state and the value of the first local field for each module of the replica with replica number = 0 to the state and the value of the first local field stored at the starting point. From timing t76 to t77, the process of updating the state and the value of the first local field for each module in the process of step S81 shown in Fig. 16 and the process of step S82 are performed.

[0181] By such processing, the timing t77 and the h used for updating the first local field using the second local field are obtained. k or h k (old) A waiting time occurs between the start timing of the read (timing t78) etc. The control circuit 17 may vary the processing cycle to reduce the waiting time.

[0182] The second bit transition process ends at timing t79. After that, from timing t80 to t81, the process of step S81 shown in Fig. 16 is performed to restore the state and the value of the first local field for each module of the replica with replica number = R-1 to the state and the value of the first local field stored at the starting point. From timing t81 to t82, the process of updating the state and the value of the first local field for each module in the process of step S81 shown in Fig. 16 and the process of step S82 are performed.

[0183] According to the data processing device 30 and the data processing method of the second embodiment as described above, the same effects as those of the data processing device 10 and the data processing method of the first embodiment can be obtained. Furthermore, the data processing device 30 of the second embodiment can perform parallel processing using multiple modules, so that a solution search can be performed more efficiently. As described above, in the data processing device 10 of the first embodiment, the circuit configuration for realizing multiple bit transition processing can be simplified. Therefore, even in a configuration for performing a parallel search using multiple modules like the data processing device 30 of the second embodiment, it is possible to prevent the circuit configuration from becoming complicated.

[0184] (Hardware configuration example) FIG. 20 is a diagram illustrating an example of hardware of an example of a data processing device. The data processing device 40 is, for example, a computer, and includes a processor 41, a RAM (Random Access Memory) 42, a HDD 43, a GPU 44, an input interface 45, a media reader 46, a communication interface 47, and an accelerator card 48. The above units are connected to a bus.

[0185] The processor 41 loads at least a part of the programs and data stored in the HDD 43 into the RAM 42 and executes the programs. The processor 41 may include, for example, multiple processor cores. The data processing device 40 may include multiple processors. A set of multiple processors (multiprocessor) may be called a "processor." A CPU, a GPU, a DSP, or the like may be used as the processor 41.

[0186] The RAM 42 is a volatile semiconductor memory that temporarily stores programs executed by the processor 41 and data used in calculations by the processor 41. Note that the data processing device 40 may include a type of memory other than the RAM 42, or may include multiple memories.

[0187] The HDD 43 is a non-volatile storage device that stores software programs such as an OS (Operating System), middleware, and application software, as well as data. The programs include, for example, a program that causes the data processing device 40 to execute a process of searching for a solution to combinatorial optimization. Note that the data processing device 40 may be provided with other types of storage devices, such as a flash memory or an SSD (Solid State Drive), or may be provided with multiple non-volatile storage devices.

[0188] The GPU 44 outputs an image to a display 44a connected to the data processing device 40 in accordance with an instruction from the processor 41. As the display 44a, a CRT (Cathode Ray Tube) display, a liquid crystal display (LCD: Liquid Crystal Display), a plasma display (PDP: Plasma Display Panel), an organic EL (OEL: Organic Electro-Luminescence) display, or the like can be used.

[0189] The input interface 45 acquires an input signal from an input device 45a connected to the data processing device 40, and outputs the signal to the processor 41. As the input device 45a, a pointing device such as a mouse, a touch panel, a touch pad, or a trackball, a keyboard, a remote controller, a button switch, etc. may be used. In addition, a plurality of types of input devices may be connected to the data processing device 40.

[0190] The medium reader 46 is a reading device that reads programs and data recorded on a recording medium 46a. For example, a magnetic disk, an optical disk, a magneto-optical disk (MO: Magneto-Optical disk), a semiconductor memory, etc. can be used as the recording medium 46a. Magnetic disks include flexible disks (FD: Flexible Disks) and HDDs. Optical disks include compact discs (CDs) and digital versatile discs (DVDs).

[0191] The medium reader 46 copies the program and data read from the recording medium 46a to another recording medium such as the RAM 42 or the HDD 43. The read program is executed by the processor 41, for example. The recording medium 46a may be a portable recording medium, and may be used for distributing the program and data. The recording medium 46a and the HDD 43 may also be referred to as computer-readable recording media.

[0192] The communication interface 47 is an interface that is connected to a network 47a and communicates with other information processing devices via the network 47a. The communication interface 47 may be a wired communication interface that is connected to a communication device such as a switch by a cable, or may be a wireless communication interface that is connected to a base station by a wireless link.

[0193] The accelerator card 48 is a hardware accelerator that searches for a solution to a combinatorial optimization problem and includes an FPGA 48a and a DRAM 48b.

[0194] 3, 14, and 15 can be realized by an FPGA 48a and a DRAM 48b. For example, the weighting coefficient memory 11 can be realized by the DRAM 48b, and the other circuits and the memory 12 can be realized by the FPGA 48a.

[0195] It should be noted that there may be multiple accelerator cards 48. Moreover, the above-described processing contents (eg, FIGS. 6 to 9, 16, 17, etc.) performed by the data processing devices 10 and 30 can be realized by software by making a computer execute a program.

[0196] The program may be recorded on a computer-readable recording medium. For example, a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory may be used as the recording medium. Magnetic disks include flexible disks and HDDs. Optical disks include CDs, CD-R (Recordable) / RW (Rewritable), DVDs, and DVD-R / RWs. The program may be recorded on a portable recording medium and distributed. In that case, the program may be copied from the portable recording medium to another recording medium and executed.

[0197] Fig. 21 is a diagram showing an example of computer hardware, in which the same elements as those shown in Fig. 20 are denoted by the same reference numerals. The computer 50 is not provided with the accelerator card 48 shown in FIG.

[0198] In the computer 50, the processor 41 executes the above-mentioned processing contents (for example, FIG. 6 to FIG. 9, FIG. 16, FIG. 17, etc.) by executing a program. The processor 41 may include a plurality of processor cores in order to execute the processing of a plurality of replicas in parallel. Also, the HDD 43 can be used as the weighting coefficient memory 11 shown in FIG. 3, etc., and the RAM 42 can be used as the memory 12.

[0199] While one aspect of the data processing device, data processing program, and data processing method of the present invention has been described above based on the embodiment, these are merely examples and the present invention is not limited to the above description. [Explanation of symbols]

[0200] 10 Data Processing Device 11 Weighting coefficient memory 12. Memory 13 Transition candidate determination circuit 14 Update circuit 15 Accumulation value calculation circuit 16 Judgment circuit 17 Control circuit 18 Evaluation function value update and retention circuit 19 Comparison circuit 20 Minimum value update and hold circuit

Claims

1. a memory that stores values ​​at a first time point of a plurality of state variables included in an evaluation function of a combinatorial optimization problem having a constraint condition, the values ​​at the first time point of a first local field used to specify an amount of change in a value of the evaluation function accompanying a change in each of the values ​​of the plurality of state variables, and the values ​​at the first time point of a second local field used to specify an amount of constraint violation to be added to the value of the evaluation function when the constraint condition is not satisfied; a transition candidate determination circuit that calculates the amount of change by using a value of the first local field at the first time point, and determines candidates for changing values ​​of the plurality of state variables one by one based on the amount of change; an update circuit that updates a value of the candidate and values ​​of the first local field and the second local field each time the candidate is determined, and further updates, at a second time point, the value of the first local field using the value of the second local field at the first time point and the value of the second local field at the second time point; an accumulation value calculation circuit for calculating an accumulation value of the amount of change when the value of the candidate is changed; a determination circuit that determines whether or not to accept a change in the value of the first number of candidates, which is two or more, based on the cumulative value; a control circuit that returns the values ​​of the state variables, the first local field, and the second local field to their values ​​at the first time point when the determination circuit determines that the changes in the values ​​of the first number of candidates are not acceptable; A data processing device comprising:

2. the control circuit switches between performing a first process of determining whether or not a change in the value of each of the plurality of state variables is permitted based on the amount of change and performing a second process of determining the candidates one by one; The first time point is a time point at which the second process starts.

2. A data processing apparatus according to claim 1.

3. The data processing apparatus according to claim 1 , wherein the second point in time is a point in time at which the candidate has been determined a plurality of times.

4. the memory stores values ​​of the plurality of state variables and values ​​of the first local field and the second local field for a number of replicas; the control circuit causes the transition candidate determination circuit, the update circuit, the accumulation value calculation circuit, and the judgment circuit to perform pipeline processing on the plurality of replicas; 2. A data processing apparatus according to claim 1.

5. the transition candidate determination circuit includes a plurality of modules, the plurality of modules determining the first number of candidates one by one within a range of mutually different state variable groups among the plurality of state variables; the update circuit updates the values ​​of the state variables, the first local field, and the second local field corresponding to each of the plurality of modules according to the candidates determined by each of the plurality of modules; the cumulative value calculation circuit calculates the cumulative value for each of the plurality of modules, and selects one of the cumulative values ​​calculated for each of the plurality of modules; the determination circuit determines, based on the selected cumulative value, whether or not to accept a change in the value of the first number of the candidates corresponding to the selected cumulative value; 2. A data processing apparatus according to claim 1.

6. storing in a memory values ​​of a plurality of state variables included in an evaluation function of a combinatorial optimization problem having a constraint condition, values ​​of a first local field used for specifying an amount of change in a value of the evaluation function accompanying changes in the values ​​of the plurality of state variables, and values ​​of a second local field used for specifying an amount of constraint violation to be added to the value of the evaluation function when the constraint condition is not satisfied; calculating the amount of change by using a value of the first local field at the first time point, and determining candidates for changing values ​​of the plurality of state variables one by one based on the amount of change; updating a value of the candidate and values ​​of the first local field and the second local field each time the candidate is determined, and further updating the value of the first local field at a second time point using the value of the second local field at the first time point and the value of the second local field at the second time point; calculating an accumulated value of the amount of change when the value of the candidate is changed; determining whether to accept a change in the value of the candidate of two or more first numbers based on the cumulative value; when it is determined that the changes in the values ​​of the first number of candidates are not to be accepted, the values ​​of the plurality of state variables, the value of the first local field, and the value of the second local field are restored to their values ​​at the first time point. A data processing program that causes a computer to carry out processing.

7. a memory stores values ​​at a first time point of a plurality of state variables included in an evaluation function of a combinatorial optimization problem having a constraint condition, a value at the first time point of a first local field used to specify an amount of change in a value of the evaluation function accompanying a change in each value of the plurality of state variables, and a value at the first time point of a second local field used to specify an amount of constraint violation to be added to the value of the evaluation function when the constraint condition is not satisfied; a transition candidate determination circuit that calculates the amount of change by using a value of the first local field at the first time point, and determines candidates for changing values ​​of the plurality of state variables one by one based on the amount of change; an update circuit updates the value of the candidate and the values ​​of the first local field and the second local field each time the candidate is determined, and further updates the value of the first local field at a second time point using the value of the second local field at the first time point and the value of the second local field at the second time point; an accumulation value calculation circuit calculates an accumulation value of the amount of change when the value of the candidate is changed; a determination circuit determines whether or not to accept a change in the value of the first number of candidates, which is two or more, based on the cumulative value; and when the control circuit determines that the determination circuit does not accept the change in the values ​​of the first number of the candidates, the control circuit restores the values ​​of the plurality of state variables, the value of the first local field, and the value of the second local field to their values ​​at the first time point. Data processing methods.

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