Photoelectric conversion device and device

Abstract

To solve the problem in a correlation detection of higher time resolution.SOLUTION: A photoelectric conversion device comprises: an avalanche photodiode; and an integration circuit that performs an integration of an output signal of the avalanche photodiode by using a predetermined weight corresponded to an acquisition of an optical flow.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a photoelectric conversion device and an apparatus including the photoelectric conversion device. [Background technology]

[0002] A time-correlated image sensor is known as one type of imaging sensor.

[0003] Non-Patent Document 1 discloses a structure in which a correlation detection structure is embedded in a pixel as a time correlation image sensor. By providing this structure, it becomes possible to detect a time variation pattern with a wider band than the frame rate. As this correlation detection structure, a structure is disclosed in which a photodiode that generates a photocurrent and multiple capacitors that accumulate this photocurrent are provided. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Shigeru Ando and Akira Kurumi, "Time Correlated Imaging and Its Applications", Transactions of the Institute of Electrical Engineers of Japan, Vol. 129, No. 5, May 1, 2009, pp. 129-137 Summary of the Invention [Problem to be solved by the invention]

[0005] The structure described in Non-Patent Document 1 has a problem in performing correlation detection with higher time resolution. [Means for solving the problem]

[0006] The technology disclosed herein is a photoelectric conversion device characterized by including an avalanche photodiode and an integrating circuit that integrates an output signal of the avalanche photodiode using a predetermined weighting corresponding to the acquisition of optical flow.

[0007] The technology disclosed herein is also a photoelectric conversion device comprising an avalanche photodiode, a first integrating circuit that integrates an output signal of the avalanche photodiode, and a second integrating circuit that integrates the output signal, wherein a weighting amount for the integration by the first integrating circuit for the output signal is different from a weighting amount for the integration by the second integrating circuit for the output signal. Effect of the Invention

[0008] The technique of the present disclosure enables correlation detection with higher time resolution. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram showing a configuration of a photoelectric conversion device; [Diagram 2] A diagram showing the relationship between the main frame, subframe, and weighting amount [Diagram 3] A diagram showing the configuration of a pixel [Figure 4] Diagram showing the structure of a stacked sensor [Diagram 5] FIG. 1 shows the configuration and operation of a pixel having an avalanche photodiode. [Figure 6] A diagram showing the configuration of a pixel [Figure 7] A diagram showing the configuration of a pixel [Figure 8] A diagram showing the configuration of a pixel [Figure 9] A diagram showing the configuration of a pixel [Figure 10] 1 is a diagram showing a configuration of a photoelectric conversion device; [Figure 11] Timing diagram showing driving of pixels [Figure 12] FIG. 1 shows the configuration of a weight control unit. [Figure 13] Timing diagram showing the driving of the weight control unit [Figure 14] FIG. 1 shows the configuration of a weight control unit. [Figure 15] Timing diagram showing the driving of the weight control unit [Figure 16] FIG. 1 shows the configuration of a weight control unit. [Figure 17] Timing diagram showing the driving of the weight control unit [Figure 18] A diagram showing the relationship between the memory configuration in the weight control unit and the weighting amount. [Figure 19] Equipment configuration diagram DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Each embodiment will be described below with reference to the drawings.

[0011] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an image pickup device, and can be applied to other examples of photoelectric conversion devices. For example, a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device for measuring the amount of incident light) may be used.

[0012] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors are changed as appropriate.

[0013] For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type, as compared to the description in the embodiment. The conductivity type of the semiconductor region described in the embodiment described below is also merely an example, and is not limited to the conductivity type described in the embodiment. The conductivity type may be changed as appropriate from the conductivity type described in the embodiment, and the potential of the semiconductor region may be changed as appropriate in accordance with this change.

[0014] In the following examples, the connections between elements of a circuit may be described. In this case, even if another element is present between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, elements A and B are treated as being connected, unless otherwise specified.

[0015] (First embodiment) The present embodiment will be described with reference to the drawings.

[0016] A sensor that performs time-correlated imaging can be configured to include a photodiode and a configuration for distributing the signal output by the photodiode. This distribution can be expressed by the following formula (1) for the signal for each pixel that generates an image.

number

[0017] Here, f(x, y, t) is the brightness of pixel (x, y) at time t, and v is the velocity of pixel (x, y).

[0018] The exposure time for acquiring one frame of an image is defined as T. Furthermore, the image g(x, y) is expressed as the following formula (2).

number

[0019] As shown in formula (2), an image is expressed as a complex number e -inΔwt The integral over one frame time is calculated by multiplying the reference signal by the reference signal. The captured image g(x, y) is assumed to satisfy the following formula (3).

number

[0020] The second term of Equation (3) is the boundary value of the integral. Since Equation (3) is a simultaneous equation, for example, by solving the simultaneous equation using two images g0(x,y) and g1(x,y), the boundary value of the integral can be eliminated. The time correlation image sensor can output an intensity image g0(x,y) consisting of only the real part, and the real and imaginary parts of a complex correlation image gn(x,y) (hereinafter, the complex correlation image is also called a time correlation signal). Therefore, by substituting the sensor detection results into the simultaneous equation of Equation (3) and solving it, the velocity v at each pixel, that is, the optical flow, can be obtained.

[0021] In a time-correlated image sensor, it is necessary to calculate the integral over one frame time, as shown in formula (2). Therefore, the output timing of the correlation image is limited to one frame time unit. In a time-correlated image sensor, the period of the reference signal and the opening time of the shutter are made to coincide. Therefore, the output of the correlation image is output according to the periodic timing of the opening time of the shutter.

[0022] Here, an overview of event-based sensors will be given.

[0023] The event-based sensor detects a change in luminance within the shooting range and outputs an event signal for each detection. The event-based sensor is formed, for example, including a plurality of pixels arranged in a matrix. The event signal is a signal associated with an event. An event is a change in luminance of a pixel. As an example, the event signal includes the detection time when the event is detected, the pixel position where the event occurs, and the change in pixel value. The time when the event is detected can be measured based on the internal clock of the event-based sensor (event camera time).

[0024] The reference time when an event is detected may be reset as necessary. The change in pixel value may be, for example, a change in luminance. The change in pixel value may be the amount of change itself, or may be information indicating whether the luminance change is positive or negative.

[0025] An event-based sensor outputs an event signal only when a luminance change occurs. In other words, the event-based sensor outputs the event signal asynchronously. Note that asynchronous output here means that the output is independent in time for each pixel.

[0026] The operation of the event-based sensor can be expressed mathematically as follows:

number

[0027] This Y(x,y,t) is the image at time t. Time t0 is the time when measurement started. Image Y(x,y,t0) is the initial image stored at time t0. In general, image Y(x,y,t0) can be set to 0. ΔY is the threshold for event occurrence (absolute value of brightness change). p(x,y,si) is the i-th event signal that occurred at pixel (x,y), and p(x,y,si)=±1.

[0028] The event-based sensor can be given a function to output a time-correlated signal like a time-correlated image sensor. When the time t is the end point of a frame, the signal of the time-correlated image sensor can be expressed as the following formulas (5) to (7) with the angular velocity ω=2π / T.

number

[0029] A time-correlated image sensor represents brightness by accumulating the current output by the photodiode in a capacitor. On the other hand, an event-based sensor represents the change in current from the photodiode by quantizing it. For this reason, in an event-based sensor, the current from the photodiode at time s can be divided into a term that is a constant value during the measurement period and a displacement term from that, as shown in the following equation (8).

number

[0030] Moreover, taking into consideration the properties of the reference signal, the following formulas (9) and (10) are satisfied.

number

[0031] This can be expressed as the following equations (11) to (13).

number

[0032] In the event-based sensor, the current output by the photodiode of the time correlation image sensor is converted into an event signal of the event-based sensor as shown in the following formula (14).

number

[0033] As a result, formulas (11) to (13) can be transformed into the following formulas (15) to (17).

number

[0034] As shown in formulas (15) to (17), a time correlation signal can be output by using events occurring during the period (cycle T) for acquiring the correlation.

[0035] (Configuration of photoelectric conversion device) FIG. 1 is a diagram showing the configuration of a photoelectric conversion device according to this embodiment.

[0036] The photoelectric conversion device of this embodiment has a pixel array 51. The pixel array 51 has a plurality of pixels 110 arranged across a plurality of rows and a plurality of columns. A control unit 52 controls the reset operation and signal output operation of the plurality of pixels 110.

[0037] The weight control unit 53 controls weighting (weighting amount) for signals generated by the pixels 110. The readout unit 54 reads out signals output by the pixels 110 that have been instructed by the control unit 52 to output signals. The readout unit 54 outputs the signals to the outside of the photoelectric conversion device after performing various types of arithmetic processing. The various types of arithmetic processing may include processing related to time-correlated imaging.

[0038] FIG. 2 shows an example of the control of the weighting amount by the weighting control unit 53. A unit exposure period is divided into a plurality of sub-exposure periods. The weighting amount (a coefficient for a signal generated by the pixel 110) in this sub-exposure period is changed, for example, along a sine waveform. By changing the weighting amount in this manner, a signal corresponding to the above-mentioned formula (17) can be generated. On the other hand, the weighting amount may be changed to a cosine waveform. In this case, a signal corresponding to formula (16) can be generated.

[0039] FIG. 3 shows a configuration of an APD pixel 110 (also written as pixel 110), which is an example of the pixel 110 shown in FIG. 1. APD is an abbreviation of Avalanche Photo Diode. The APD 201 (avalanche photodiode) generates a pair of charges according to incident light by photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage that causes the APD 201 to perform avalanche multiplication is supplied to the anode and cathode. By supplying such a voltage, avalanche multiplication of charges generated by incident light occurs, and an avalanche current is generated. As shown in FIG. 4, the pixel 110 has a structure in which a first chip 11 and a second chip 21 are stacked. The first chip 11 is provided with the APD 201 shown in FIG. 3. 3 are provided on a second chip 21. The photoelectric conversion device of this embodiment has a so-called stacked sensor structure in which a first chip 11 and a second chip 21 are stacked.

[0040] When a reverse bias voltage is supplied, there are two modes: Geiger mode, which operates with the potential difference between the anode and cathode greater than the breakdown voltage, and linear mode, which operates with the potential difference between the anode and cathode close to or less than the breakdown voltage. An APD that operates in Geiger mode is called a SPAD. For example, the voltage VL (first voltage) is -30V, and the voltage VH (second voltage) is 1V.

[0041] The quench unit 202 is connected to a power supply that supplies a voltage VH and the APD 201. The quench unit 202 has a function of converting a change in avalanche current occurring in the APD 201 into a voltage signal. The quench unit 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has a function of suppressing avalanche multiplication by suppressing the voltage supplied to the APD 201 (quench operation).

[0042] The signal processing section 103 has a waveform shaping section 210, a counter section 211, and a selection circuit 212. In this specification, it is sufficient that the signal processing section 103 has any one of the waveform shaping section 210, the counter section 211, and the selection circuit 212.

[0043] The waveform shaping unit 210 shapes the potential change of the cathode of the APD 201 obtained when a photon is detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 210. Although an example in which one inverter is used as the waveform shaping unit 210 is shown in Fig. 3, a circuit in which a plurality of inverters are connected in series may be used, or another circuit having a waveform shaping effect may be used.

[0044] The counter unit 211 counts the pulse signal output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via a drive line 213, the signal held in the counter unit 211 is reset.

[0045] A control pulse pSEL is supplied to the selection circuit 212 from the vertical scanning circuit unit 110 in Fig. 1 via a drive line 214 in Fig. 3, and switches between electrical connection and non-connection between the counter unit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0046] The electrical connection may be switched by disposing a switch such as a transistor between the quench unit 202 and the APD 201 or between the photoelectric conversion unit 102 and the signal processing unit 103. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion unit 102 may be electrically switched using a switch such as a transistor.

[0047] Fig. 5 is a diagram showing a schematic diagram of the relationship between the operation of the APD 201 and the output signal. Note that the explanation will be given here assuming that the weighting amount by the weighting control unit 53 is 1. Fig. 5(a) is a diagram showing the APD 201, the quenching unit 202, and the waveform shaping unit 210 of Fig. 2. Here, the input side of the waveform shaping unit 210 is nodeA, and the output side is nodeB. Fig. 5(b) shows the waveform change of nodeA in Fig. 5(a), and Fig. 5(c) shows the waveform change of nodeB in Fig. 5(a).

[0048] Between times t0 and t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5(a).

[0049] When a photon is incident at time t1, an avalanche multiplication current flows through the quench section 202, and the voltage at nodeA drops. When the voltage drop increases further and the potential difference applied to the APD 201 decreases, avalanche multiplication in the APD 201 stops, and the voltage level at nodeA does not drop below a certain value. After that, a current that compensates for the voltage drop from the voltage VL flows through nodeA, and at time t3, nodeA is stabilized to its original potential level.

[0050] At this time, the portion of the output waveform at nodeA that exceeds a certain threshold value is waveform-shaped by the waveform shaping section 210 and is output as a signal at nodeB.

[0051] Fig. 6 is a diagram showing in more detail the configuration of the pixel 110 of this embodiment. In Fig. 6, the same reference numerals as those in Fig. 2 are used for components having the same functions as those in Fig. 2.

[0052] The quench unit 202 includes a quench element 202-1. The quench element 202-2 is a P-type MOS transistor. A signal PCLKB is input to this quench element 202-2 from the control unit 52 shown in FIG. 1. This signal PCLKB is a clock signal, for example, a pulse signal with a frequency of 1 MHz to 200 MHz. The number of pulses in one main frame can be set according to the number of bits of the counter unit 211 described later, and is 2048 pulses when the counter unit 211 counts with 11 bits.

[0053] The counter unit 211 has a third integrator circuit 211-3, a first integrator circuit 211-1, and a second integrator circuit 211-2. It also has a multiplexer (MUX) 320-1, MUX320-2, and an AND circuit 330. The AND circuit 330 outputs a signal of the logical product of the output of the waveform shaping circuit 210 and the signal PCLKB to the third integrator circuit 211-3, MUX320-1, and MUX320-2. The third integrator circuit 211-3 counts the signal of the AND circuit 330 with a weighting amount of 1. In other words, a counting result corresponding to the number of photons incident on the avalanche photodiode 211 is generated.

[0054] 1 includes a sine waveform generator 311 (first waveform generator) and a cosine waveform generator 313 (second waveform generator). The sine waveform generator 311 outputs a plurality of pulse signals as bus signals to the input node of the MUX 320-1.

[0055] When the output of the AND circuit 330 is at a high level, the MUX 320-1 outputs the output of the sine waveform generating unit 311 to the first integrating circuit 211-1. On the other hand, when the output of the AND circuit 330 is at a low level, the MUX 320-1 outputs an output of 0 (ground voltage) to the first integrating circuit 211-1. When an output of 0 is given, the first integrating circuit 211-1 does not count up. The signal output by the sine waveform generating unit 311 is set so that the counting operation of the first integrating circuit 211-1 becomes the weighting amount shown in FIG. 2.

[0056] In this way, the first integrator circuit 211-1 counts up when the output of the AND circuit 330 is at a high level, according to the value of the bus signal output by the sine waveform generator 311. This allows the first integrator circuit 211-1 to generate a signal with a sine component expressed by equation (17).

[0057] The cosine waveform generating unit 313 outputs a bus signal, which is a plurality of pulse signals, to the input node of the MUX 320-2.

[0058] When the output of the AND circuit 330 is at a high level, the MUX320-2 outputs the output of the cosine waveform generating unit 313 to the second integrating circuit 211-2. On the other hand, when the output of the AND circuit 330 is at a low level, the MUX320-2 outputs an output of 0 (ground voltage) to the second integrating circuit 211-2. When the output of 0 is given, the second integrating circuit 211-2 does not count up. The signal output by the cosine waveform generating unit 313 is set so that the counting operation of the second integrating circuit 211-2 is weighted to a waveform in which the weighting of the sine waveform shown in FIG. 2 is made into a cosine waveform. That is, at a given time (timing), the weighting amounts of the first integrating circuit 211-1 and the second integrating circuit 211-2 are different amounts. This is because one is a weighting amount corresponding to a sine waveform and the other is a weighting amount corresponding to a cosine waveform. It is not necessary that the weighting amounts of the first integrator circuit 211-1 and the second integrator circuit 211-2 are different at all times. At a certain predetermined time (timing), the weighting amounts of the first integrator circuit 211-1 and the second integrator circuit 211-2 may be the same.

[0059] In this manner, the second integrator circuit 211-2 counts up according to the value of the bus signal, which is a plurality of pulse signals output by the cosine waveform generator 313, when the output of the AND circuit 330 is at a high level. This allows the second integrator circuit 211-2 to generate a signal of the cosine component expressed by equation (16).

[0060] The control unit 52 shown in Fig. 1 outputs a signal P_RES to the first integrator circuit 211-1, the second integrator circuit 211-2, and the third integrator circuit 211-3. When the signal P_RES goes high, the signals held in the first integrator circuit 211-1, the second integrator circuit 211-2, and the third integrator circuit 211-3 are reset to their initial values. At the timing of starting the main frame shown in Fig. 2, the signal P_RES goes high and then goes low. This starts the counting operation in the main frame by the count unit 211. Note that one main frame corresponds to one image.

[0061] The weighting amount of the third integrating circuit 211-3 for the output of the APD 201 is 1, and is constant throughout the period during which the first integrating circuit and the second integrating circuit perform the integration operation with weighting. The weighting of the output of the APD 201 of the first integrating circuit 211-1 is a predetermined weighting corresponding to a sine waveform. The weighting of the output of the APD 201 of the second integrating circuit 211-2 is a predetermined weighting corresponding to a cosine waveform. That is, the weighting of the output of the APD 201 of each of the third integrating circuit 211-3, the first integrating circuit 211-1, and the second integrating circuit 211-2 is different from each other. That is, it can be said that among the multiple integrating circuits, some integrating circuits and other some integrating circuits have different weightings for the output of the APD 201. By providing this configuration, the photoelectric conversion device of this embodiment can realize time-correlated imaging. In addition, the photoelectric conversion device of this embodiment performs time-correlated imaging using the APD 201. This makes it possible to suitably perform time-correlated imaging even in low-luminance shooting scenes.

[0062] The sine waveform generating unit 311 and the cosine waveform generating unit 313 may be provided for each of the multiple pixels 110. Alternatively, the multiple pixels 110 may be divided into multiple blocks, each of which has a portion of the multiple pixels 110, and the sine waveform generating unit 311 and the cosine waveform generating unit 313 may be provided for each of the multiple blocks.

[0063] Second embodiment The photoelectric conversion device of this embodiment will be described, focusing on the differences from the first embodiment.

[0064] In the first embodiment, the pixel includes an integrating circuit for obtaining a cosine component and a sine component. In the present embodiment, the signal input to the quenching unit 202 is a signal corresponding to a sine component and a cosine component. This makes it possible to perform time-correlated imaging using the APD 201 without providing two integrating circuits, an integrating circuit for a cosine component and an integrating circuit for a sine component.

[0065] Fig. 7 is a diagram showing the configuration of a pixel 110 of this embodiment. In Fig. 7, members having the same functions as those shown in Fig. 6 are denoted by the same reference numerals as those in Fig. 6.

[0066] In the pixel 110 of this embodiment, the quench unit 202 has a quench element 202-2. The output (signal PCLKB, which is a first pulse signal) of the NAND circuit 411 (first logic circuit) is input to the quench element 202-2. A plurality of pulse signals are input to the NAND circuit 411. The plurality of pulse signals are the signal P_DECI_CLK and the signal P_RCH_TRG shown in FIG. 1. The signal P_RCH_TRG output by the control unit 52 is also input to the logic circuit 401. The output of the logic circuit 401 is shown as a signal TCLK. The signal P_DECI_CLK is generated by thinning out some of the pulse signals from the clock signal input to the weight control unit 53. This thinning out process of the clock signal is performed so that the integrating circuit 460 integrates at a period corresponding to the weighting corresponding to the sine component or the cosine component. Details will be described later. The signal P_RCH_TRG becomes high level at the start of a subframe. Furthermore, the signal P_RCH_TRG maintains a low level during one subframe. When both the signal P_RCH_TRG and the signal P_DECI_CLK are at a high level, the output of the NAND circuit 411 becomes a low level. This causes the quench element 202-2, which is a P-type MOS transistor, to be turned on, and a recharge operation is performed on the APD 201. This recharge operation is performed only once in one subframe.

[0067] An output signal of the waveform shaping circuit 210 is input to an input terminal D of the flip-flop circuit 450 (second logic circuit). A signal P_RES output by the control unit 52 is input to a reset terminal R. A signal P_RCH_TRG is input to a clock input terminal. An AND circuit 455 (third logic circuit) generates a second pulse signal which is a logical product of the outputs of the logic circuit 401 and the flip-flop circuit 450. The second pulse signal obtained by this logical product is input to an integrator circuit 460. The signal P_RES goes high at the start of one main frame. This resets the flip-flop circuit 450 and the integrator circuit 460.

[0068] In the pixel 110 of this embodiment, when a photon is incident on the APD 201, the output of the waveform shaping circuit 210 becomes high level. This change in the output of the waveform shaping circuit 210 causes the output Q of the flip-flop circuit 450 to become high level. Then, every time the pulse signal of the signal P_DECI_CLK transitions from low level to high level (i.e., every time the signal TCLK transitions to high level), the output of the AND circuit 455 transitions from low level to high level. As a result, the integrator circuit 460 performs integration for the number of transitions of TCLK from low level to high level after the output Q of the flip-flop circuit 450 changes to high level.

[0069] In other words, the signal generated by the integrator circuit 460 when one photon is incident is weighted by the signal TCLK, allowing the integrator circuit 460 to perform weighted integration for the incidence of one photon.

[0070] Furthermore, when the integration circuit 460 is caused to generate a signal corresponding to a sine component, the weighting for one subframe is set as shown in Fig. 2. The control unit 52 sets the period of the signal P_DECI_CLK so as to correspond to the weighting assigned to one subframe. This allows the integration circuit 460 to generate a signal corresponding to the weighting of the subframe shown in Fig. 2.

[0071] Similarly, when the integration circuit 460 generates a signal corresponding to the cosine component, the control unit 52 may set the period of the signal P_DECI_CLK so as to weight the subframe corresponding to the cosine component.

[0072] As a result, in this embodiment as well, time-correlated imaging using the APD 201 can be performed.

[0073] A modified example will now be described.

[0074] 8 is a diagram showing the configuration of a pixel 110 according to a modification of the present embodiment. This modification includes an integrating circuit 470 and an integrating circuit 480. The integrating circuit 480 performs weighted integration, similar to the integrating circuit 460 shown in FIG. 7. On the other hand, the integrating circuit 470 does not perform weighting, and performs integration in response to changes in the output of the APD 201. In other words, this is an integrating circuit that acquires components of normal imaging.

[0075] The pixel 110 of FIG. 8 further includes an OR circuit 415 and a logic circuit 421. The NAND circuit 412 receives the output of the OR circuit 415 and the output of the signal P_RCH_TRG. The logic circuit 402 receives the signal P_DECI_CLK and an inverted signal of the signal P_RCH_TRG. The logic circuit 421 receives the signal P_DECI_CLK2 and an inverted signal of the signal P_RCH_TRG. The signal P_DECI_CLK2 is a signal that becomes high level only once at the end of one subframe period. The AND circuit 458 (fourth logic circuit) outputs a third pulse signal using the output of the logic circuit 421 and the output of the flip-flop circuit 450. If the output Q of the flip-flop 450 changes to a high level during one subframe period (i.e., if a photon is incident on the APD 201), the integrator circuit 470 counts up. On the other hand, if the output Q of the flip-flop 450 remains at a low level during one subframe period (i.e., if no photons are incident on the APD 201), the integrating circuit 470 does not count up. As a result, the integrating circuit 470 performs an integrating operation without weighting.

[0076] In this modification, integration circuits 470 and 480 can perform integration with different weights for the detection of the incidence of one photon.

[0077] Third embodiment The photoelectric conversion device of this embodiment will be described, focusing on the differences from the modified example of the second embodiment.

[0078] The photoelectric conversion device of this embodiment divides the pulse signal of the signal P_DECI_CLK shown in Fig. 7 into a plurality of signals P_DECI_CLK3 and P_DECI_CLK4. Compared with the case where the signal P_DECI_CLK is transmitted in a single phase as in Fig. 7, this embodiment has the effect of being able to handle higher frequencies. Furthermore, signals P_DECI_CLK3 and P_DECI_CLK4 are generated so that the integration process of the integration circuit 490 corresponds to the upper bits and lower bits of the count signal generated by the integration circuit 490. This allows the integration circuit 490 to perform integration process divided by the upper bits and lower bits.

[0079] Fig. 9 is a diagram showing the configuration of a pixel 110 of the photoelectric conversion device of this embodiment. In Fig. 9, components having the same functions as those shown in Fig. 8 are denoted by the same reference numerals as those in Fig. 8.

[0080] In the pixel 110 of this embodiment, the weight control unit 53 inputs the signals P_DECI_CLK3 and P_DECI_CLK4 to the OR circuit 415. The signal P_DECI_CLK3 is generated as a signal corresponding to the higher bits, and the signal P_DECI_CLK4 is generated as a signal corresponding to the lower bits. The signals P_DECI_CLK3 and P_DECI_CLK4 can be pulse signals that are each a part of the signal P_DECI_CLK shown in FIG. 7. The OR circuit 415 outputs a signal equivalent to the signal P_DECI_CLK shown in FIG. 7 to the NAND circuit 412. With this configuration, the signal P_DECI_CLK is divided into the signals P_DECI_CLK3 and P_DECI_CLK4 and transmitted, which makes it easier to increase the frequency of the signal output to the NAND circuit 412 compared to the case where the signal P_DECI_CLK is output in a single phase. Since the signal P_DECI_CLK is transmitted from the weight control unit 53 to a plurality of pixels 110, there are limitations on increasing the frequency of the signal due to the presence of parasitic capacitance of the signal line that transmits the signal. On the other hand, in this embodiment, the OR circuit 415 is provided inside the pixel 110, and the signal P_DECI_DLK is generated inside the pixel 110, which makes it easier to improve the frequency of the signal.

[0081] The pixel 110 of this embodiment includes a shift calculator 485. The shift calculator 485 receives the output result of the AND circuit 458 and performs a process of bit-shifting the signal generated by the integrator circuit 490. The signal P_DECI_CLK4 is a signal corresponding to the signal for the higher bits. Therefore, when the output Q of the flip-flop circuit 450 is at a high level at the timing when the signal P_DECI_CLK4 becomes high level, the integrator circuit 490 performs an arithmetic process to integrate the signal for the higher bits. For example, the signal P_DECI_CLK4 is used to generate a signal that is two bits higher than the signal P_DECI_CLK3. In this case, when the output Q of the flip-flop circuit 450 is at a high level at the timing when the signal P_DECI_CLK4 becomes high level, the integrator circuit 490 is made to count the two bits higher. In other words, when the signal P_DECI_CLK4 is at a low level, the integration circuit 490 is caused to perform an integration process that is four times (a bit shift of two bits) the integration of the signal P_DECI_CLK3. This allows the integration circuit 490 to perform integration processes corresponding to the higher and lower bits, respectively, using the signal P_DECI_CLK4 for the higher bits and the signal P_DECI_CLK3 for the lower bits.

[0082] In this embodiment, the signals P_DECI_CLK3 and P_DECI_CLK4 have been described as pulse signals corresponding to the upper and lower bits of the integrator circuit 490. The present invention is not limited to this example, and for example, the signal P_DECI_CLK shown in FIG. 7 may be equally divided into the signals P_DECI_CLK3 and P_DECI_CLK4. In this configuration, the logic circuit 421, the logic circuit 459, and the shift calculator 485 may be omitted. This configuration also has the effect of making it easier to make the signal PCLKB a high frequency, compared to the configuration in FIG. 7.

[0083] It is also possible to combine the first to third embodiments. For example, in the configuration described in the first embodiment, the weighting amounts of the second integrator circuit 211-2 and the third integrator circuit 211-3 may be made different as described in Fig. 7 and Fig. 8 of the second embodiment. That is, in the second integrator circuit 211-2 of the first embodiment, a signal corresponding to a sine component may be integrated with a first weighting during the first subframe period, and may be integrated with a second weighting during the second subframe period.

[0084] In addition, the integrating circuit described in each embodiment reads out a signal for each mainframe, but the present invention is not limited to this. The integrating circuit may continuously perform integration for multiple mainframes.

[0085] (Fourth embodiment) FIG. 10 is a diagram showing the configuration of a photoelectric conversion device according to this embodiment.

[0086] The differences from FIG. 1 mentioned above will be explained.

[0087] Weighting signal lines 61 to 64 output from weight control unit 53 are alternately connected to pixels 110 in a two-by-two matrix. That is, of the two-by-two pixels 110, the upper left pixel 110 is connected to weighting signal line 61, and the lower left pixel 110 is connected to weighting signal line 62. The upper right pixel 110 is connected to weighting signal line 63, and the lower right pixel 110 is connected to weighting signal line 64. The connection configuration within pixel array 51 is repeated as described above.

[0088] The weighting signal lines 61 to 64 are controlled only by the weighting control section 55 in the weighting control section 53, or are controlled by two blocks, the weighting control section 55 and the pulse generating section 56. Details will be described later.

[0089] The pixel 110 used in FIG. 10 is that shown in FIG.

[0090] The timing diagram of FIG. 11 illustrates the operation of the pixel 110 configuration illustrated in FIG.

[0091] At time t10, the signal P_RCH_TRG goes High. This starts a subframe. Next, at time t11, the signal P_DECI_CLK also goes High. At this time, the output PCLKB of the NAND circuit 411 goes Low. This turns on the quench element 202-2, which is a P-type MOS transistor, and a recharge operation is performed on the APD 201. This recharge operation is performed only once in one subframe.

[0092] Time t12 is the time when a photon is first incident on the APD 201 in this subframe. As a result, at time t13, the output of the waveform shaping circuit 210 becomes High, and the D input of the connected flip-flop circuit 450 also becomes High. Thereafter, even if subsequent photons arrive within this subframe, no change is observed in the circuit operation, and the state is maintained until time t14.

[0093] Next, at time t14, the signal P_RCH_TRG goes High. This starts the next subframe. This signal is also connected to the clock input terminal of the flip-flop circuit 450, so the Q output of the flip-flop circuit 450 goes High. At time t15, the signal P_DECI_CLK also goes High, so the output PCLKB goes Low. This causes a recharge operation for the APD 201, and the output of the waveform shaping circuit 210, i.e., the D input of the flip-flop circuit 450, goes Low.

[0094] Meanwhile, a pulse signal is input to the signal P_DECI_CLK from time t18 to t23. At this time, since the signal P_RCH_TRG is Low, the same pulse signal is output from the logic circuit 401 as the signal TCLK from time t18 to t23. Also, since the Q output of the flip-flop circuit 450 is High at these times, the signal TCLK is output as is from the AND circuit 455. The signal TCLK from time t18 to t23 is integrated in the integration circuit 460.

[0095] Similarly to time t12, time t16 is the time when a photon is first incident on the APD 201 in this subframe. As a result, at time t17, the output of the waveform shaping circuit 210 becomes High, and the D input of the connected flip-flop circuit 450 also becomes High.

[0096] Then, at time t24, the signal P_RCH_TRG goes high, just like at time t14. This starts the next subframe. The subsequent operations are similar, so a description thereof will be omitted.

[0097] In this way, it is possible to weight the detection of a photon in the previous subframe by the number of signals TCLK in the current subframe.

[0098] 12 shows the internal configuration of the weight control unit 53. In this embodiment, the inside is controlled only by the weight amount control unit 55.

[0099] Here, there are four memories (holding units), memory 501 to memory 504. In this diagram, the address is shown moving vertically in each memory. Reading from these four memories is controlled by read control unit 513, and the same address is specified for each of the four memories to read. For example, when the top address is specified and read, data 16 is read from memory 501 to memory 503, and data 32 is read from memory 504. Next, when the address is advanced by one, data 21 is read from memory 501, data 16 from memories 502 and 503, and data 31 from memory 504. These data are the weights output from weight control unit 55.

[0100] Prior to the main driving of the photoelectric conversion device, setting information is written in the memory through communication from outside the photoelectric conversion device.

[0101] Data read from memory 501 is output to counter 505 , and similarly, data from memory 502 is output to counter 506 , data from memory 503 is output to counter 507 , and data from memory 504 is output to counter 508 .

[0102] A common signal CLK is input to these counters 505 to 508. Each of the counters 505 to 508 performs a counting operation using this signal CLK. Furthermore, each of the counters 505 to 508 outputs a signal (signals en1 to en4 in FIG. 12) that becomes High when the counters are in a counting operation.

[0103] The counters 505-508 are an embodiment of a measurement unit that measures the data (weights) read from the memories 501-504.

[0104] Next, signals en1 to en4 and the signal CLK from counters 505 to 508 are input to AND circuits 509 to 512. Each of AND circuits 505 to 508 outputs signals P_DECI_CLK1 to P_DECI_CLK4 as the logical product of the two input signals. As a result, the weights held in memories 501 to 504 are converted into pulse numbers and output as signals P_DECI_CLK1 to P_DECI_CLK4.

[0105] The timing diagram in FIG. 13 illustrates the operation of the weight control unit 53 in FIG.

[0106] 13 shows the operation timing of counter 505 from reading memory 501 in weight control unit 55. The operations of other memories 502 to 504 and counters 506 to 508 can be similar to those of memory 501 and counter 505, and therefore are omitted here.

[0107] At time t10, signal P_RCH_TRG goes High, as in FIG. 11. This starts the subframe operation. At time t11 in FIG. 11, signal P_DECI_CLK also goes High. In the operation in FIG. 11, while signal P_RCH_TRG is High, the rising pulses of signal P_DECI_CLK are individually controlled within weight control unit 53. Furthermore, OR circuit 415OR circuit 415 outputs a signal that is the logical sum of one of signals P_DECI_CLK1-4 and signal P_DECI_CLK.

[0108] Next, at time t30, the signal rd_str goes High. This starts read control from the memory read control unit 513. This causes addressing of the memory 501 to be performed at time t31. Here, the top address of the memory 501 is specified. Furthermore, this addressing causes the data 16 held in the memory 501 to be output at time t32.

[0109] Time 33 is the start timing of the counting operation of the counter 505. Here, the counter 505 starts the counting operation after a predetermined delay has elapsed since the signal rd_str went High in order to wait for a series of operations from addressing the memory 501 to reading out a signal from the memory 501. Also, the signal en1 output from the counter 505 is set to High.

[0110] The counter 505 performs a count-up operation using the input signal CLK, and counts up to 15, which is the data 16 read from the memory 501 minus 1. At time t34, the signal en1 of the counter 505 is changed from High to Low. This makes it possible to output 16 pulses as the signal P_DICE_CLK1. This means that control is performed to output the same number of pulses as the data 16 held in the memory 501. Also, at this time t34, the internal counter of the counter 505 sets the count value to a predetermined value (maximum value) in preparation for the next operation. This state can also be said to be the reset state of the counter 505.

[0111] Next, the signal P_RCH_TRG goes high again and operation proceeds to the next subframe.

[0112] At time t35, similarly to time t30, a start signal is again provided to signal rd_str, and the subframe operation begins.

[0113] Next, at time t36, the next address is designated in memory 501. Then, at time t37, data 21 held in memory 501 is read out.

[0114] At time t38, the operation of the counter 505 starts in the same manner as at time t33. The counter 505 starts counting up in response to the signal CLK input to the counter 505. The counter 505 also counts up to 20, which is the data 21 read from the memory 501 minus 1.

[0115] At time t39, the signal en1 of the counter 505 is set to Low, which enables the signal P_DICE_CLK1 to output 21 pulses.

[0116] This operation makes it possible to change the number of pulses of the signal P_DECI_CLK on a subframe basis, thereby changing the amount of weighting.

[0117] In addition, since the data held in memories 501 to 504 can be changed, it is possible to change signals P_DECI_CLK1 to P_DECI_CLK4 individually. For example, memory 501 holds data that results in a sine waveform as shown in Fig. 2, memory 504 holds data that results in a cosine waveform, and memories 502 and 503 are weighted to a certain extent. This makes it possible to obtain optical flow signals from 2 rows x 2 columns of pixels.

[0118] Also in this embodiment, the effects described in the first to third embodiments can be obtained in the same manner.

[0119] Furthermore, in this embodiment, the signals P_DECI_CLK1 to P_DECI_CLK4 are connected to different pixels 110, respectively. However, this embodiment can also be applied to the pixel shown in FIG.

[0120] Fifth embodiment The present embodiment will be described focusing on the differences from the fourth embodiment. The parts of the present embodiment that are not described can be the same as those of the fourth embodiment.

[0121] Fig. 14 shows the internal configuration of the weight control unit 53. In this embodiment, the signals P_DECI_CLK1 to P_DECI_CLK4 are controlled by two units, a weight control unit 55 and a pulse generation unit 56. The weight control unit 55, counters 505 to 508, and AND circuits 509 to 512 are the same as those shown in Fig. 12, so their description will be omitted.

[0122] The pulse generating unit 56 of FIG. 14 of this embodiment includes counters 514 to 517 and AND circuits 518 to 521. First, a common signal CLK is input to the counters 514 to 517. Each of the counters 514 to 517 performs a count-up operation using this signal CLK. Furthermore, each of the counters 514 to 517 can set a maximum count value. After reaching the maximum count value, the counters 514 to 517 can return to the initial count value and repeatedly perform the count-up operation. As this periodic signal, the counters 514 to 517 output signals en5 to en8.

[0123] Next, these signals en5 to en8 and the signal CLK are input to the AND circuits 518 to 521. Then, the AND circuits 518 to 521 output signals which are logical products of the signals en5 to en8 and the signal CLK as signal pulses 5 to 8 shown in FIG.

[0124] Signal pulses 5 to 8 output from the pulse generating unit 56 are input to counters 505 to 508 in the same manner as in FIG.

[0125] The counters 505 to 508 perform a count-up operation using the signal pulses 5 to 8. Then, the counters 505 to 508 continue the count-up operation until they reach a value obtained by subtracting 1 from the value of the data read from the memories 501 to 504, and then the signals en1 to en4 go Low.

[0126] Subsequently, AND circuits 509 to 512 generate signals which are the logical products of signals en1 to en4 and signal pulse 5 to pulse 8, respectively, and output them as signals P_DECI_CLK1 to P_DECI_CLK4.

[0127] FIG. 15 is a timing chart for explaining the operation of each circuit block shown in FIG.

[0128] FIG. 15(A) shows a pulse signal output from a pulse generating unit that oscillates continuously, and FIG. 15(B) shows a pulse signal that oscillates at periodic intervals.

[0129] Also, as in Fig. 13, this timing diagram describes the operation timing of the memory 501 to the counter 505 in the weight control unit 55, and the other three components with the same circuit configuration operate in the same manner, so their explanations are omitted. Also, the same contents as those explained in Fig. 13 are omitted, and the explanation focuses on the differences. At time t10 in Fig. 15(A), a subframe is started when the signal P_RCH_TRG goes High, as in Fig. 13. Also, at time t30, the signal rd_str goes High, as in Fig. 13, and read control by the memory read control unit 513 is started. At time t31, the memory 501 is addressed, and at time t32, data 16 is output from the memory 501.

[0130] Next, at time t40, the operation of counter 514 in pulse generating unit 56 is started. This is because the count-up operation of counter 505 uses data read from memory 501 and an output pulse from counter 514. Therefore, counter 514 starts operating before count 505. Also, counter 514 is set to perform continuous oscillation with period setting 1 set to 0. Therefore, although the internal counter value of counter 514 starts from 0, it does not count up and remains at 0.

[0131] At the next time t33, the counter 514 sees the internal counter value 0 and sets the signal en5 to High at the next clock. The AND circuit 518 generates a logical AND of the signal en5 and the signal CLK, so that the signal pulse 5 becomes a continuous oscillation pulse.

[0132] Next, the counter 505 performs a count-up operation at time t33 by the continuously oscillated signal pulse 5. The signal en1 output from the counter 505 goes High during the count operation. The signal P_DECI_CLK1 output from the AND circuit 509 is output as a signal of the logical AND of the signal pulse 5 and the signal en1.

[0133] At the next time t34, the counter 505 sets the signal en1 to Low when the data read from the memory 501 becomes 15, which is obtained by subtracting 1 from 16. This enables the signal P_DICE_CLK1 to output 16 pulses.

[0134] The same operation can be repeated in subsequent subframes.

[0135] FIG. 15(B) will be further described, focusing on the differences from FIG. 15(A).

[0136] Counter 514 counts up to the value set in Cycle Setting 1, and when it reaches that value, it returns to 0. In this diagram, cycle setting 1 of counter 514 is set to 1, and as a result, the internal count value of counter 514 performs a cyclic operation of repeating 0 and 1.

[0137] As a result, at time t33, counter 514 sees the internal counter value of 0 and sets signal en5 to High at the next signal CLK, so that the cyclic counting operation of 0s and 1s results in a pulse output of one clock every two clocks.

[0138] As a result, the signal P_DECI_CLK1 also outputs a pulse such that one clock is output for every two clocks of the signal CLK, and this operation is repeated 16 times, that is, 16 pulses are output.

[0139] The same operation can be repeated in subsequent subframes.

[0140] In addition, the pulse generating unit 56 in this embodiment is shown configured as the logical product of the counter output and the signal CLK, but this is just one example and other configurations are also possible. For example, the counter output, the count value at which the pulse signal becomes High, and the count value at which the pulse signal becomes Low are stored as setting values, and a pulse signal is output according to the setting. A signal obtained by logically multiplying the pulse signal and the signal CLK is output from the pulse generating unit 56. Even with this configuration, the timing of issuing the signal P_DECI_CLK can be controlled between a plurality of pixels 110 (between adjacent pixels 110).

[0141] As described above, by using the pulse generating unit 56, it becomes possible to adjust the pulse interval for data with the same weighting amount. In addition to the effects of the first to fourth embodiments, this makes it possible to set the operation speeds of the internal counts from the counters 505 to 508 individually, so that it becomes possible to distribute the current peaks among a plurality of pixels (adjacent pixels) 110.

[0142] Sixth embodiment This embodiment is a modification of the fifth embodiment.

[0143] 16 shows the internal configuration of the weight control unit 53, and in this embodiment, P_DECI_CLK1 to P_DECI_CLK4 are controlled by two units, a weight control unit 55 and a pulse generation unit 56. The difference from FIG. 14 is the configuration of the pulse generation unit 56. The pulse generating unit 56 in FIG. 16 has a memory read control 522, four memories 523 to 526, and PS527 to PS530 which are parallel-serial circuits.

[0144] Here, the four memories 523 to 526 are described as having addresses proceed vertically in each memory. Reading from these four memories is controlled by the read control unit 522, and the same address is specified for each of the four memories to read. For example, when the top address is specified and read, 8-bit data 8'b0101_0101 is read from memories 523 to 526.

[0145] Next, when the address is advanced by one, the same 8-bit data 8'b0101_0101 is read out from the memories 523 to 526.

[0146] This 8-bit data is converted into parallel-serial data by the PS527 at the timing of a signal load from the memory read control 522. As a result, the data is output from the pulse generating unit 56 as PS527 to PS530 (denoted as ps5 to ps8 in the drawing).

[0147] The signals ps5 to ps8 output from the pulse generating unit 56 are input to counters 505 to 508 as in FIGS.

[0148] The counters 505 to 508 perform counting operations using the signals ps5 to ps8, and operate until they reach a value obtained by subtracting 1 from the value of the data read from the memories 501 to 504, and then set the signals en1 to en4 to Low.

[0149] Then, AND circuits 509 to 512 respectively take the logical products of these signals en1 to en4 and signals ps5 to ps8 and output the products as signals P_DECI_CLK1 to P_DECI_CLK4.

[0150] FIG. 17 is a timing diagram of the configuration shown in FIG.

[0151] FIG. 17(A) shows a pulse signal output from a pulse generating unit that oscillates continuously, and FIG. 17(B) shows a pulse signal that oscillates at periodic intervals.

[0152] 13 and 15, this timing diagram describes the operation timing of memory 501 to counter 505 in weight control unit 55, and the other three components with the same circuit configuration operate in the same way, so their explanations are omitted. Also, the same content as that explained in Figures 13 and 15 is omitted, and the explanation focuses on the differences.

[0153] At time t10 in Fig. 17A, the signal P_RCH_TRG goes High and a subframe starts, as in Fig. 13 and Fig. 15. Also, at time t30, the signal rd_str starts read control from the memory read control 513 and the memory read control 522.

[0154] Next, at time t31, the addresses of memory 501 and memory 523 are specified, and at time t32, data 16 is output from memory 501, and 8-bit binary data 8'b0101_0101 is output from memory 523.

[0155] Next, at time t41, a signal load is issued during the data output period of the memory 523. Here, the signal load is output once every 8 clocks in accordance with 8 bits of data.

[0156] This signal load causes ps527 to take in parallel data and convert it to a serial signal. This conversion causes the signal ps5 to output a low signal when the 8-bit data is low, and a high signal when the 8-bit data is high.

[0157] At time t33, the counter 505 performs a count-up operation using the Low / High signal from the signal ps5. The signal en1, which is the output of the counter 505, is a signal that becomes High during the count operation. The signal P_DECI_CLK1 output from the AND circuit 509 is output by taking the logical AND of the signals ps5 and en1.

[0158] Next, at time t42, the memory 523 is again addressed, and at time t43, the same 8-bit binary data 8'b0101_0101 is read out. This read operation is performed every 8 clocks, so that 8-bit data is successively read out and a continuous pulse signal ps5 is output.

[0159] At the next time t34, the counter 505 changes the signal en1 to Low when the data read from the memory 501 becomes 15, which is obtained by subtracting 1 from 16. This enables the signal P_DICE_CLK1 to output 16 pulses.

[0160] Thereafter, the same content is repeated in the next subframe, so the description will be omitted.

[0161] The explanation of FIG. 17(B) will be further made with reference to the difference from FIG. 17(A).

[0162] In this figure, 8'b0100_0100 is held as 8-bit binary data in the memory 523. Therefore, when parallel-serial conversion is performed with the signal load at time t41, a pulse output is generated at time t33, where one clock is output every two clocks.

[0163] As a result, the signal P_DECI_CLK1 also outputs a pulse such that one clock is output every two clocks, and this operation is repeated 16 times, that is, 16 pulses are output.

[0164] The operations in the next subframe and thereafter can be a repetition of the operations in the above subframes.

[0165] As described above, it is possible to adjust the pulse interval for data with the same weighting amount by using the pulse generating unit 56. In addition to the effects of the first to fourth embodiments, this makes it possible to set the operation speeds of the internal counters 505 to 508 individually, so that it becomes possible to distribute the current peaks among a plurality of pixels (adjacent pixels) 110.

[0166] Furthermore, since the operation speed of counters 505 to 504 can be slowed down depending on the weighting amount, the effect of reducing power consumption can be obtained.

[0167] Seventh embodiment This embodiment is a modification of the fourth to sixth embodiments.

[0168] In this embodiment, the weight control unit 55 is configured as a circuit rather than a memory.

[0169] Moreover, in order to correspond to the acquisition of optical flows in the present invention, it is necessary to generate a sine waveform and a cosine waveform as the weighting settings. Therefore, in this embodiment, a sine waveform is output as the data to be output to counter 505, and a cosine waveform is output as the data to be output to counter 508 (not shown).

[0170] Next, an example of generating the sine and cosine waveforms will be explained using the following equations (18), (19), (20), and (21).

[0171]

number

[0172] Here, f(n) represents the sine function and g(n) represents the cosine function.

[0173] In this formula (18), it is meant that the derivative of a sine function is a cosine function, and in formula (19), it is meant that the derivative of a cosine function is a -sine function.

[0174] Transform these

[0175]

number

[0176] Here, f(0) is set to 0 as an initial value, g(0) is set to, for example, 30, and the coefficient k is multiplied by dividing one period of the sin and cos waveforms by n, where 2π is the value. In other words, if one period of the sin and cos waveforms is realized with 1024 data, it becomes 2π / 1024. When these calculations are performed, decimals appear, but these are rounded to integers and output to counters 505 and 508. As described above, even if weighting control unit 55 uses these circuits, it is possible to obtain the same effects as those of the fourth to sixth embodiments.

[0177] Eighth embodiment The present embodiment will be described focusing on the differences from the seventh embodiment.

[0178] In this embodiment, a method for reducing the capacity of the memory configured in the weight control unit 55 will be described.

[0179] Moreover, in order to accommodate the acquisition of optical flow in the present invention, it is necessary to generate sine and cosine waveforms as weighting factors.

[0180] Since these sine and cosine waveforms are periodic functions, they can be realized by having only 1 / 2 or 1 / 4 of the period without having to have memory for one period.

[0181] Figure 18(A) shows the case where only 1 / 2 cycle data of sine and cosine functions is stored in memory. The horizontal axis is the memory address, which is shown as the vertical axis in Figure 12. The vertical axis in Figure 18(A) shows the data value stored in memory.

[0182] When generating a sine waveform using these data, this is achieved by address control only, as shown in Figure 18(A). That is, starting from the center of the address, decrementing is performed until the top address is reached. Once the top address is reached, incrementing is performed and control is continued up to the maximum address in Figure 18. Once the maximum address is reached, decrementing is performed again and the process is continued up to the center of the address.

[0183] Similarly, when generating a cosine waveform, this can be achieved by address control alone. That is, the address is incremented from the starting address, and when the maximum address is reached, the address is decremented again up to the starting address.

[0184] By performing this type of address control, it is possible to generate sine and cosine waveforms, thereby achieving the effect of reducing memory capacity.

[0185] Next, Figure 18(B) shows the case where only 1 / 4 cycle data of sine and cosine functions is stored in memory. The horizontal axis is the memory address, which is represented as the vertical axis in Figure 12. The vertical axis in Figure 18(B) shows the data value stored in memory.

[0186] When using these data to generate a sine waveform, this is achieved by controlling the address while performing data calculations as shown in Figure 18(B). In other words, the address is decremented from the maximum address, and then incremented when it reaches the first address. Also, when the first address is read, this data is stored separately. Up to this point, control is performed using only the address. Next, decrement is performed again, but this time the read data is subtracted from the maximum value previously stored while the address is decremented. When it reaches the first address in this state, increment is performed again. Here too, the read data is subtracted from the maximum value previously stored while the address is incremented. The above operations make it possible to generate a sine waveform.

[0187] Similarly, when generating a cosine waveform, this is achieved by address control and data calculation. In other words, the address is incremented from the starting address to the maximum address. In this case, only the address is controlled. Also, when the starting address is read, this data is stored separately.

[0188] Next, the address is decremented to the starting address 0, but at this time the read data is subtracted from the maximum value previously stored while the address is decremented. When it reaches the starting address in this state, it is incremented again. Here too, the address is incremented while the read data is subtracted from the maximum value previously stored.

[0189] When the maximum address is reached, the counter is decremented again, but here only the address is controlled. The above operation makes it possible to generate a cosine waveform.

[0190] By performing address control while performing such data calculations, it is possible to generate sine and cosine waveforms, which has the effect of reducing memory capacity.

[0191] Ninth embodiment This embodiment is applicable to any of the first to eighth embodiments. FIG. 19(a) is a schematic diagram for explaining a device 9191 including a semiconductor device 930 of this embodiment. The semiconductor device 930 can be any of the semiconductor devices explained in the first to third embodiments, or a semiconductor device that combines a plurality of the embodiments. The device 9191 including the semiconductor device 930 will be explained in detail. The semiconductor device 930 can include a semiconductor device 910. The semiconductor device 930 can include a package 920 that houses the semiconductor device 910 in addition to the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed, and a cover such as glass that faces the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal provided on the semiconductor device 910.

[0192] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and is an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0193] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The processing device 960 may also acquire an optical flow using a signal output by the photoelectric conversion device of each of the above-mentioned embodiments. That is, the processing device 960 may generate three images, an image based on a sine component, an image based on a cosine component, and a normal image, and acquire an optical flow from these three images.

[0194] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0195] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0196] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft, etc.). The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0197] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0198] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0199] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 19(b) and 19(c).

[0200] FIG. 19(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 80, such as a lens, a shutter, or a mirror. In addition, a plurality of photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in the pixel of the photoelectric conversion device 80. For example, a plurality of photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The photoelectric conversion units receive light beams that have passed through different positions of the pupil of the optical system, and the photoelectric conversion device 80 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may calculate the parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of these distance information to determine the possibility of collision. The distance information may be acquired using a ToF (Time of Flight) technique. The distance information acquisition means may be realized by dedicated hardware or by a software module. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or may be realized by a combination of these.

[0201] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0202] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the photoelectric conversion system 8. Fig. 19(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0203] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0204] The above-described embodiments can be modified as appropriate without departing from the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is greater than B," for example, this specification can be said to disclose that "A is not greater than B" even if the statement that "A is not greater than B" is omitted. This is because when it is stated that "A is greater than B," it is assumed that the case in which "A is not greater than B" is taken into consideration.

[0205] The technology of the present disclosure has the following configuration.

[0206] (Configuration 1) an avalanche photodiode; and an integrating circuit that integrates the output signals of the avalanche photodiodes using a predetermined weighting corresponding to the acquisition of an optical flow.

[0207] (Configuration 2) an avalanche photodiode; a first integrating circuit that integrates the output signal of the avalanche photodiode; a second integrating circuit for integrating the output signal; 13. A photoelectric conversion device, comprising: a first integrating circuit and a second integrating circuit, the first integrating circuit and the second integrating circuit each having a different weighting for integrating the output signal.

[0208] (Configuration 3) The photoelectric conversion device according to configuration 2, characterized in that a weighting amount used in the integration of the output signal by the first integration circuit at a given time is different from a weighting amount used in the integration of the output signal by the second integration circuit.

[0209] (Configuration 4) the first integrating circuit integrates the output signal by a coefficient corresponding to a sine component; 4. The photoelectric conversion device according to claim 2, wherein the second integrating circuit integrates the output signal using a coefficient corresponding to a cosine component.

[0210] (Configuration 5) a third integrating circuit for integrating the output signal; 5. The photoelectric conversion device according to any one of configurations 2 to 4, wherein the third integrating circuit performs integration using a constant coefficient during a period in which the first integrating circuit performs integration.

[0211] (Configuration 6) A waveform shaping unit connected to the avalanche photodiode, 6. The photoelectric conversion device according to any one of configurations 1 to 5, wherein the output signal is an output from the waveform shaping section.

[0212] (Configuration 7) a first waveform generating unit that outputs a pulse signal that goes high at a period corresponding to the sine component; 7. The photoelectric conversion device according to any one of configurations 2 to 6, wherein the first integrating circuit integrates the output signal using the first waveform generating section and the output signal.

[0213] (Configuration 8) a second waveform generating unit that outputs a pulse signal that goes high in a period corresponding to the cosine component; 8. The photoelectric conversion device according to configuration 7, wherein the second integrating circuit integrates the output signal using the second waveform generating section and the output signal.

[0214] (Configuration 9) a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; 2. The photoelectric conversion device according to configuration 1, wherein the integrating circuit performs the integrating operation using an output of the third logic circuit.

[0215] (Configuration 10) a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; 9. The photoelectric conversion device according to any one of configurations 2 to 8, wherein the first integrating circuit performs the integrating operation using an output from the third logic circuit.

[0216] (Configuration 11) a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; a fourth logic circuit that generates a third pulse signal using a part of the plurality of pulse signals and an output of the second logic circuit; the first integrating circuit performs the integration using an output of the third logic circuit; 6. The photoelectric conversion device according to configuration 5, wherein the third integrating circuit performs the integrating operation using an output from the fourth logic circuit.

[0217] (Configuration 12) a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; a fourth logic circuit that generates a third pulse signal using a part of the plurality of pulse signals and an output of the second logic circuit; A computing unit; the integrating circuit performs the integration using an output of the third logic circuit; 2. The photoelectric conversion device according to configuration 1, wherein the arithmetic unit multiplies the signal held by the integrating circuit by using an output of the fourth logic circuit.

[0218] (Configuration 13) The photoelectric conversion device according to configuration 2, further comprising a weighting control unit which outputs a weighting amount, and a measurement unit which measures the weighting amount, and provides weighting amounts to the first integrating circuit and the second integrating circuit by a signal converted from the weighting amount to a pulse number.

[0219] (Configuration 14) The photoelectric conversion device according to configuration 2, further comprising a weighting amount control unit that outputs a weighting amount, a measurement unit that measures the weighting amount, and a pulse generating unit that provides a pulse to the measurement unit, wherein a pulse signal that is output at the pulse issuance timing is converted into a pulse number that corresponds to the number of times that a pulse is continuously issued until the weighting amount is reached, and a weighting amount is provided to the first integrating circuit and the second integrating circuit by a signal of the pulse number.

[0220] (Configuration 15) The photoelectric conversion device described in configuration 13, characterized in that the weighting control unit has a holding unit that holds a predetermined value of the measurement unit, and provides weighting amounts to the first integrator circuit and the second integrator circuit by reading out the predetermined value held in the holding unit.

[0221] (Configuration 16) The photoelectric conversion device according to configuration 13, characterized in that the weight control unit has a holding unit that holds a predetermined value of the measurement unit, the holding unit holds a signal of a first value and a signal of a second value, a pulse signal is generated by reading out the signal of the first value and the signal of the second value from the holding unit, and a weight is applied to the first integrator circuit and the second integrator circuit by the measurement unit driven by the pulse signal.

[0222] (Configuration 17) The photoelectric conversion device according to configuration 13, wherein the weighting control unit has an arithmetic circuit that generates a calculated value by calculating a coefficient corresponding to a sine component and a coefficient corresponding to a cosine component, and the measurement unit is driven with the calculated value as a maximum value to provide weighting amounts to the first integrating circuit and the second integrating circuit.

[0223] (Configuration 18) The photoelectric conversion device according to configuration 14, wherein the measurement unit generates a periodic pulse signal based on a set value, and the measurement unit measures the weighting amount using the periodic pulse signal, thereby providing weighting amounts to the first integrating circuit and the second integrating circuit.

[0224] (Configuration 19) The photoelectric conversion device according to configuration 13, characterized in that the maximum value is 1 / 2 period of a coefficient corresponding to a sine component and 1 / 2 period of a coefficient corresponding to a cosine component, and the measurement unit driven by setting it to a weighting amount for one period provides weighting amounts to the first integrating circuit and the second integrating circuit.

[0225] (Configuration 20) The photoelectric conversion device according to configuration 13, characterized in that the maximum value is a 1 / 4 period of a coefficient corresponding to a sine component and a 1 / 4 period of a coefficient corresponding to a cosine component, and the measurement unit driven by setting it to a weighting amount for one period provides weighting amounts to the first integrating circuit and the second integrating circuit.

[0226] (Configuration 21) An apparatus including the photoelectric conversion device according to any one of configurations 1 to 20, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

[0227] (Configuration 22) An apparatus including the photoelectric conversion device according to any one of configurations 1 to 21, a processing device for processing a signal output from the photoelectric conversion device, The processing device is configured to obtain optical flow using a signal output from the photoelectric conversion device. [Explanation of symbols]

[0228] 201 Avalanche photodiode 202 Quench Department 210 Waveform shaping section 211 Estimation Department 211-1 First integrating circuit 211-2 Second integration circuit 211-3 3rd integrator circuit 212 Selection circuit 311 sin waveform generator 313 cos waveform generator

Claims

1. an avalanche photodiode; and an integrating circuit that integrates the output signals of the avalanche photodiodes using a predetermined weighting corresponding to the acquisition of an optical flow.

2. an avalanche photodiode; a first integrating circuit that integrates an output signal of the avalanche photodiode; a second integrating circuit for integrating the output signal; a weighting amount used in the integration of said output signal by said first integration circuit and a weighting amount used in the integration of said output signal by said second integration circuit being different from each other;

3. 3. The photoelectric conversion device according to claim 2, wherein a weighting amount used in the integration of the output signal by the first integration circuit at a given time is different from a weighting amount used in the integration of the output signal by the second integration circuit.

4. the first integrating circuit integrates the output signal by a coefficient corresponding to a sine component; 3. The photoelectric conversion device according to claim 2, wherein the second integrating circuit integrates the output signal with a coefficient corresponding to a cosine component.

5. a third integrating circuit for integrating the output signal; 3. The photoelectric conversion device according to claim 2, wherein the third integrating circuit performs integration using a constant coefficient during a period in which the first integrating circuit performs integration.

6. A waveform shaping unit connected to the avalanche photodiode, 2. The photoelectric conversion device according to claim 1, wherein the output signal is an output from the waveform shaping section.

7. A waveform shaping unit connected to the avalanche photodiode, 3. The photoelectric conversion device according to claim 2, wherein the output signal is an output from the waveform shaping section.

8. a first waveform generating unit that outputs a pulse signal that goes high in a period corresponding to a sine component; 3. The photoelectric conversion device according to claim 2, wherein the first integrating circuit integrates the output signal using the first waveform generating section and the output signal.

9. a second waveform generating unit that outputs a pulse signal that goes high in a period corresponding to the cosine component; 9. The photoelectric conversion device according to claim 8, wherein the second integrating circuit integrates the output signal using the second waveform generating section and the output signal.

10. a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; 2. The photoelectric conversion device according to claim 1, wherein the integration circuit performs the integration using an output from the third logic circuit.

11. a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; 3. The photoelectric conversion device according to claim 2, wherein the first integrating circuit performs the integrating operation using an output from the third logic circuit.

12. a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; a fourth logic circuit that generates a third pulse signal using a part of the plurality of pulse signals and an output of the second logic circuit; the first integrating circuit performs the integration using an output of the third logic circuit; 6. The photoelectric conversion device according to claim 5, wherein the third integrating circuit performs the integrating operation using an output from the fourth logic circuit.

13. a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals; a quench element connected to the avalanche photodiode and receiving the first pulse signal; a waveform shaping unit connected to the avalanche photodiode; A second logic circuit connected to the waveform shaping unit; a third logic circuit that outputs a second pulse signal using an output of the second logic circuit and a part of the plurality of pulse signals; a fourth logic circuit that generates a third pulse signal using a part of the plurality of pulse signals and an output of the second logic circuit; A computing unit; the integrating circuit performs the integration using an output of the third logic circuit; 2. The photoelectric conversion device according to claim 1, wherein the arithmetic unit multiplies the signal held by the integration circuit by using an output from the fourth logic circuit.

14. 3. The photoelectric conversion device according to claim 2, further comprising a weighting control unit which outputs a weighting amount, and a measurement unit which measures the weighting amount, and provides weighting amounts to the first integrating circuit and the second integrating circuit by a signal converted from the weighting amount to a pulse number.

15. 3. The photoelectric conversion device according to claim 2, further comprising a weighting amount control unit which outputs a weighting amount, a measurement unit which measures the weighting amount, and a pulse generating unit which gives a pulse to the measurement unit, wherein a pulse signal output at the pulse issuance timing is converted into a pulse number corresponding to the number of times a pulse is issued until the weighting amount is reached, and a weighting amount is given to the first integrating circuit and the second integrating circuit by a signal of the pulse number.

16. The photoelectric conversion device according to claim 14, characterized in that the weighting control unit has a holding unit that holds a predetermined value of the measurement unit, and provides weighting amounts to the first integrator circuit and the second integrator circuit by reading out the predetermined value held in the holding unit.

17. The photoelectric conversion device described in claim 14, characterized in that the weighting control unit has a holding unit that holds a predetermined value of the measurement unit, the holding unit respectively holds a first value signal and a second value signal, a pulse signal is generated by reading out the first value signal and the second value signal from the holding unit, and a weighting amount is provided to the first integrator circuit and the second integrator circuit by the measurement unit driven by the pulse signal.

18. The photoelectric conversion device according to claim 14, characterized in that the weighting control unit has an arithmetic circuit that generates a calculated value by calculating a coefficient corresponding to a sine component and a coefficient corresponding to a cosine component, and the measurement unit is driven with the calculated value as a maximum value to provide weighting amounts to the first integrator circuit and the second integrator circuit.

19. The photoelectric conversion device according to claim 15, characterized in that the measurement unit generates a periodic pulse signal based on a set value, and the measurement unit measures the weighting amount using the periodic pulse signal, thereby providing weighting amounts to the first integrator circuit and the second integrator circuit.

20. The photoelectric conversion device according to claim 18, characterized in that the maximum value is 1 / 2 period of a coefficient corresponding to a sine component and 1 / 2 period of a coefficient corresponding to a cosine component, and a weighting amount is applied to the first integrating circuit and the second integrating circuit by the measuring unit driven by setting the weighting amount to one period.

21. The photoelectric conversion device according to claim 18, characterized in that the maximum value is a quarter period of a coefficient corresponding to a sine component and a quarter period of a coefficient corresponding to a cosine component, and a weighting amount is applied to the first integrating circuit and the second integrating circuit by the measuring unit driven by setting the weighting amount to one period.

22. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 21, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

23. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 21, a processing device for processing a signal output from the photoelectric conversion device, The processing device is configured to obtain optical flow using a signal output from the photoelectric conversion device.

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