Storage device

Abstract

To provide a novel storage device.SOLUTION: A plurality of memory cells containing two vertical transistors is serially connected. One of the two vertical transistors functions as a transistor for writing information, and the other one functions as a transistor for reading the information to be written to each memory cell. The information to be written to each memory cell is held into a gate of the transistor for reading. The transistor of which an off current is smaller is used for the transistor for writing.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, and a driving method or a manufacturing method thereof. [Background technology]

[0003] In recent years, with an increase in the amount of data handled, there is a demand for semiconductor devices with larger storage capacity. In order to increase the storage capacity per unit area, it is effective to form memory cells in a stacked manner (see Patent Documents 1 and 2). By providing memory cells in a stacked manner, the storage capacity per unit area can be increased according to the number of stacked memory cells. Patent Documents 3 and 4 disclose memory devices using an oxide semiconductor.

[0004] In Patent Documents 1 and 2, a plurality of storage elements (also called memory cells) are stacked and connected in series to form a three-dimensional memory cell array (also called a memory string). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2011 / 0065270 [Patent Document 2] US Patent Application Publication No. 2016 / 0149004 [Patent Document 3] JP 2018-207038 A [Patent Document 4] JP 2019-008862 A Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1, a semiconductor provided in a columnar shape is in contact with an insulator having a charge storage layer. In Patent Document 2, a semiconductor provided in a columnar shape is in contact with an insulator that functions as a tunnel dielectric. In both Patent Documents 1 and 2, writing information to a memory cell is performed by extracting and injecting charges through the insulator. In this case, a trap center may be formed at the interface where the semiconductor and the insulator are in contact. The trap center may capture electrons and cause the threshold voltage (also called "Vth") of the transistor to fluctuate. This may have an adverse effect on the reliability of the memory device.

[0007] An object of one embodiment of the present invention is to provide a highly reliable storage device. Another object of one embodiment of the present invention is to provide a storage device with a large storage capacity. Another object of one embodiment of the present invention is to provide a storage device with a small occupation area. Another object of one embodiment of the present invention is to provide a storage device with high storage density. Another object of one embodiment of the present invention is to provide a storage device with low manufacturing costs. Another object of one embodiment of the present invention is to provide a novel storage device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low manufacturing costs. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0008] Note that the description of these problems does not preclude the existence of other problems. Other problems can be extracted from the description of the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these and other problems. One embodiment of the present invention solves at least one of the above problems and other problems. [Means for solving the problem]

[0009] One aspect of the present invention is a memory cell having n (n is an integer of 3 or more) memory cells, a first wiring, n second wirings, n third wirings, and n fourth wirings, each of the n memory cells having a first transistor and a second transistor, each of the first transistor and the second transistor having a first conductive layer, a first insulating layer on the first conductive layer, a fourth conductive layer on the first insulating layer, a second insulating layer on the fourth conductive layer, a second conductive layer on the second insulating layer, a semiconductor layer having a region along a side surface of the fourth conductive layer, and a third conductive layer having a region along the side surface of the fourth conductive layer via the semiconductor layer, and the second conductive layer of the first transistor [i] included in the i-th (i is an integer of 2 or more and n-1 or less) memory cell is electrically connected to the first wiring, a first conductive layer of the first transistor [i] electrically connected to the third conductive layer of a second transistor [i] included in the i-th memory cell, a third conductive layer of the first transistor [i] electrically connected to the i-th second wiring, a fourth conductive layer of the first transistor [i] electrically connected to the i-th third wiring, a fourth conductive layer of the second transistor [i] electrically connected to the i-th fourth wiring, a first conductive layer of the second transistor [i] electrically connected to the second conductive layer of a second transistor [i-1] included in the i-1th memory cell, and a second conductive layer of the second transistor [i] electrically connected to the first conductive layer of a second transistor [i+1] included in the i+1th memory cell.

[0010] The first transistor [i] and the second transistor [i] preferably have an overlapping region in a plan view. The first conductive layer of the first transistor [i] can function as the third conductive layer of the second transistor [i]. By providing a capacitance element electrically connected to the third conductive layer of the second transistor [i] in each of the n memory cells, information written in the memory cells can be more stably held. Effect of the Invention

[0011] According to one embodiment of the present invention, a highly reliable storage device can be provided. According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device with a small occupation area can be provided. According to one embodiment of the present invention, a storage device with high storage density can be provided. According to one embodiment of the present invention, a storage device with low manufacturing costs can be provided. According to one embodiment of the present invention, a novel storage device can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low manufacturing costs can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0012] Note that the description of these effects does not preclude the existence of other effects. The other effects can be extracted from the description of the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have to achieve all of these effects and other effects. One embodiment of the present invention achieves at least one of these effects and other effects. [Brief description of the drawings]

[0013] [Figure 1] 1A to 1C are diagrams illustrating an example of a circuit configuration of a semiconductor device. [Diagram 2] FIG. 2 is a schematic perspective view of the semiconductor device. [Diagram 3] FIG. 3 is a view of the semiconductor device as viewed from the X direction. [Figure 4] Fig. 4A is a plan view showing an example of a semiconductor device, and Figs. 4B to 4E are cross-sectional views showing an example of the semiconductor device. [Diagram 5] FIG. 5 is a cross-sectional view showing an example of a semiconductor device. [Figure 6] Fig. 6(A) is a diagram showing an example of a circuit configuration of a semiconductor device. Fig. 6(B) is a plan view showing an example of a semiconductor device. Fig. 6(C) is a perspective schematic view showing an example of a semiconductor device. Fig. 6(D) is a diagram showing the semiconductor device in the Y direction. Fig. 6(E) is a diagram showing the semiconductor device in the X direction. [Figure 7]7(A) and (B) are cross-sectional views showing an example of a semiconductor device. [Figure 8] FIG. 8 is a cross-sectional view showing an example of a semiconductor device. [Figure 9] Fig. 9(A) is a diagram showing an example of a circuit configuration of a semiconductor device. Fig. 9(B) is a plan view showing an example of a semiconductor device. Fig. 9(C) is a perspective schematic view showing an example of a semiconductor device. Fig. 9(D) is a diagram showing the semiconductor device as viewed in the Y direction. Fig. 9(E) is a diagram showing the semiconductor device as viewed in the X direction. [Figure 10] 10(A) and 10(B) are plan views showing an example of a semiconductor device. [Figure 11] Fig. 11(A) is a diagram showing an example of a circuit configuration of a semiconductor device. Fig. 11(B) is a plan view showing an example of a semiconductor device. Fig. 11(C) is a schematic perspective view showing an example of a semiconductor device. Fig. 11(D) is a diagram showing the semiconductor device as viewed in the Y direction. Fig. 11(E) is a diagram showing the semiconductor device as viewed in the X direction. [Figure 12] Fig. 12(A) is a plan view showing an example of a semiconductor device, Fig. 12(B) is a cross-sectional view showing an example of the semiconductor device, and Fig. 12(C) is a diagram showing an example of a circuit configuration of the semiconductor device. [Figure 13] 13A to 13D are diagrams illustrating examples of circuit configurations of a semiconductor device. [Figure 14] FIG. 14 is a timing chart showing an example of the operation of the semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 16] FIG. 16 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 18] FIG. 18 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 19] FIG. 19 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 20] FIG. 20 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 21]FIG. 21 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 22] 22A to 22D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Diagram 23] 23A to 23D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 24] 24A and 24B are diagrams illustrating an example of a semiconductor device. [Diagram 25] FIG. 25 is a cross-sectional view showing an example of a semiconductor device. [Figure 26] 26(A) and (B) are diagrams showing various storage devices by hierarchical level. [Figure 27] 27(A) and 27(B) are diagrams showing an example of an electronic component. [Figure 28] Fig. 28(A) to Fig. 28(C) are diagrams showing an example of a mainframe computer. Fig. 28(D) is a diagram showing an example of space equipment. Fig. 28(E) is a diagram showing an example of a storage system applicable to a data center. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0015] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may have semiconductor devices.

[0016] In the drawings and the like relating to this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0017] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are commonly used with the same reference numerals in different drawings, and the repeated explanation may be omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be given. In addition, in order to make the drawings easier to understand, the description of some components may be omitted in perspective views or plan views.

[0018] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0019] In this specification, the terms "above," "below," "upward," or "below" indicating the position of the components may be used for convenience in describing the positional relationship between the components with reference to the drawings. The positional relationship between the components may change as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0020] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0021] In this specification, the term "overlap" does not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0022] In this specification, the terms "adjacent" and "close to" do not limit the components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0023] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". For example, the term "insulating film" may be changed to the term "insulating layer". Alternatively, depending on the situation or the circumstances, it is possible to replace the terms "film" and "layer" with other terms without using them. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film". For example, the term "insulating layer" or "insulating film" may be changed to the term "insulator". Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film".

[0024] Voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point. Generally, however, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is simply called potential or voltage, and potential and voltage are often used as synonyms. For this reason, in this specification and elsewhere, potential may be read as voltage, and voltage may be read as potential, unless otherwise specified.

[0025] In the present specification, terms such as "electrode", "wiring", and "terminal" do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" or "wirings" are formed integrally. Furthermore, for example, "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wiring", "terminals", and the like are formed integrally. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, terms such as "electrode", "wiring", and "terminal" may be replaced with terms such as "region", "conductive layer", and the like, depending on the circumstances.

[0026] In this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". Also, for example, the term "wiring" may be changed to the term "power line". Also, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". Terms such as "power line" may be changed to the term "signal line". Also, the reverse is also true, and terms such as "signal line" may be changed to the term "power line". Also, the term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. Also, the reverse is also true, and terms such as "signal" may be changed to the term "potential".

[0027] In this specification, the term "source" refers to a source region or a source electrode. The source region refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The source electrode refers to a conductive layer including a portion connected to the source region.

[0028] In this specification, "drain" refers to a drain region or a drain electrode. The drain region refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The drain electrode refers to a conductive layer including a portion connected to the drain region.

[0029] In this specification, when it is explicitly stated that X and Y are connected, this includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, but also includes connection relationships other than those shown in a figure or text.

[0030] An example of a case where X and Y are electrically connected is a case where one or more elements (e.g., switches, transistors, inductors, resistive elements, etc.) that enable the electrical connection between X and Y are connected between X and Y.

[0031] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude, current amount, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) may be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0032] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0033] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, a ground potential or a source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0034] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as a "conductive state"), and the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as a "non-conductive state").

[0035] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0036] In addition, unless otherwise specified, the transistors described in this specification are enhancement-type (normally-off) n-channel field-effect transistors. Therefore, the threshold voltage is assumed to be higher than 0 V. In addition, unless otherwise specified, "supplying a potential H to the gate of a transistor" may be synonymous with "turning the transistor on." In addition, unless otherwise specified, "supplying a potential L to the gate of a transistor" may be synonymous with "turning the transistor off."

[0037] In this specification, potential H is a potential that turns an n-channel field effect transistor (also called an "n-type transistor") into an on state, and a potential that turns a p-channel field effect transistor (also called a "p-type transistor") into an off state. Moreover, potential L is a potential that turns an n-type transistor into an off state, and a potential that turns a p-type transistor into an on state. Therefore, potential H is a potential higher than potential L.

[0038] In addition, in drawings and the like, in order to clearly show the potential of wiring, electrodes, etc., an "H" indicating a potential H or an "L" indicating a potential L may be added next to the wiring, electrode, etc. Also, wiring, electrodes, etc. where a potential change has occurred may be added with "H" or "L" enclosed in letters. Also, when a transistor is in an off state, an "x" symbol may be added over the transistor. Also, an arrow may be added to show the direction of current flow.

[0039] In this specification, when referring to counting values ​​and measurement values, "same," "equal," "uniform" (including synonyms thereof) are used, they are assumed to include an error of plus or minus 10%, unless otherwise specified.

[0040] In addition, in the drawings and the like related to this specification, arrows indicating the X direction, the Y direction, and the Z direction may be attached. In this specification, the "X direction" is a direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect with each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, the Y direction, and the Z direction may be called the "first direction" or the "first direction". In addition, the other one may be called the "second direction" or the "second direction". In addition, the remaining one may be called the "third direction" or the "third direction".

[0041] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., a "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., a "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0042] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, "[m,n]” may be added to the symbol.

[0043] In addition, ordinal numbers such as "first" and "second" are used in this specification to avoid confusion of components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims, etc.

[0044] Note that in this specification, one of the source and the drain of a transistor may be referred to as a "first terminal," and the other of the source and the drain of a transistor may be referred to as a "second terminal."

[0045] (Embodiment 1) A memory cell 10 according to one embodiment of the present invention and a memory string 100 including the memory cell 10 will be described.

[0046] <Memory string configuration example> FIG. 1(A) shows an example of a circuit configuration of a memory string 100 including n (n is an integer equal to or greater than 2) memory cells 10. FIG. 2 shows a schematic perspective view of a memory string 100 where n is 3. The memory string 100 extends in the Z direction. The Z direction is, for example, a direction perpendicular to a substrate (not shown). FIG. 3 is a schematic view of the memory string 100 shown in FIG. 2 as viewed from the X direction.

[0047] The memory string 100 has n (n is an integer greater than or equal to 3) memory cells 10, n wirings WWL, n wirings COM, n wirings WBG, n wirings RBG, wiring RBL, wiring WBL, wiring SL, a transistor 121, and a transistor 122.

[0048] The n memory cells 10 are provided between the transistor 121 and the transistor 122. In this specification, the first (also referred to as the "first stage") memory cell 10 is indicated as memory cell 10[1], the second stage memory cell 10 is indicated as memory cell 10[2], and the nth stage memory cell 10 is indicated as memory cell 10[n]. Also, the i-th stage (i is an integer between 2 and n-1) memory cell 10 is indicated as memory cell 10[i]. Other components are indicated in the same manner.

[0049] 1, the transistor WTr included in the memory cell 10[1] is shown as a transistor WTr[1], the transistor RTr included in the memory cell 10[1] is shown as a transistor RTr[1], and the capacitance element Cs included in the memory cell 10[1] is shown as a capacitance element Cs[1].

[0050] Moreover, the wiring COM, the wiring RBG, and the wiring WWL connected to the memory cell 10[1] are respectively indicated as the wiring COM[1], the wiring RBG[1], and the wiring WWL[1].

[0051] The transistor WTr included in the memory cell 10[i] is denoted as the transistor WTr[i], the transistor RTr included in the memory cell 10[i] is denoted as the transistor RTr[i], and the capacitive element Cs included in the memory cell 10[i] is denoted as the capacitive element Cs[i]. The wiring WBL, wiring COM, wiring RBG, and wiring WWL connected to the memory cell 10[i] are denoted as the wiring WBL[i], wiring COM[i], wiring RBG[i], and wiring WWL[i], respectively.

[0052] Similarly, the transistor WTr included in the memory cell 10[n] is indicated as a transistor WTr[n], the transistor RTr included in the memory cell 10[n] is indicated as a transistor RTr[n], and the capacitance element Cs included in the memory cell 10[n] is indicated as a capacitance element Cs[n]. In addition, the wiring COM, wiring RBG, and wiring WWL connected to the memory cell 10[n] are indicated as wiring COM[n], wiring RBG[n], and wiring WWL[n], respectively.

[0053] As the transistor WTr and the transistor RTr, a transistor having a gate and a backgate is used. The gate and the backgate are arranged to sandwich a channel formation region of the semiconductor layer. In addition, both the gate and the backgate are formed of a conductive layer or a semiconductor layer with low resistivity. The backgate can function in the same manner as the gate. When the gate is used to control the on-state and off-state of the transistor, the potential of the backgate may be the same potential as the gate, or may be ground potential (GND) or an arbitrary potential. In addition, when the transistor is turned on, by supplying a potential H to both the gate and the backgate, the on-current can be increased more than when the potential H is supplied to only one of them. In addition, by changing the potential of the backgate independently without linking it with the gate, the threshold voltage of the transistor can be changed. In addition, since the gate and the backgate are formed of a conductive layer or a semiconductor layer with low resistivity, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly, an electric field shielding function against static electricity, etc.). By providing a backgate in addition to the gate, the characteristic variation between transistors can be reduced.

[0054] In the memory cell 10, the first terminal of the transistor WTr is connected to the gate of the transistor RTr and one electrode of the capacitance element Cs, and the second terminal is connected to the wiring WBL. The gate of the transistor WTr is connected to the wiring WWL, and the back gate of the transistor WTr is connected to the wiring WBG. The back gate of the transistor RTr is connected to the wiring RBG. The other electrode of the capacitance element Cs is connected to the wiring COM. The region where the first terminal of the transistor WTr, the gate of the transistor RTr, and one electrode of the capacitance element Cs are connected functions as a retention node SN.

[0055] The first terminal of the transistor RTr in the memory cell 10 is connected to a different destination depending on which stage the transistor RTr is included in the memory cell 10. The first terminal of the transistor RTr (transistor RTr[1]) in the memory cell 10[1] is connected to the transistor 121, and the first terminal of the transistor RTr (transistor RTr[n]) in the memory cell 10[n] is connected to the transistor 122.

[0056] Specifically, a first terminal of the transistor 121 is connected to the wiring SL, and a second terminal of the transistor 121 is connected to the wiring WBL and the first terminal of the transistor RTr[1]. A first terminal of the transistor RTr[n] is connected to a second terminal of the transistor RTr (transistor RTr[n-1]) included in the memory cell 10[n-1], and the second terminal of the transistor RTr[n] is connected to a first terminal of the transistor 122. A second terminal of the transistor 122 is connected to the wiring RBL.

[0057] The first terminal of the transistor RTr (transistor RTr[i]) in the memory cell 10[i] is connected to the second terminal of the transistor RTr[i-1]. The second terminal of the transistor RTr[i] is connected to the first terminal of the transistor RTr[i+1].

[0058] 1A shows an example in which transistors each having a back gate are used as the transistor 121 and the transistor 122. The back gate may be used independently of the gate, or the gate and the back gate of the transistor 121 may be connected as shown in FIG 1B. Alternatively, a transistor without a back gate may be used as shown in FIG 1C.

[0059] 2 and 3, the second terminal of the transistor 121 and the first terminal of the transistor RTr[1] (conductive layer 220R[1]) are connected via the conductive layer 246[0], the second terminal of the transistor RTr[1] (conductive layer 240R[1]) and the first terminal of the transistor RTr[2] (conductive layer 220R[2]) are connected via the conductive layer 246[1], and the second terminal of the transistor RTr[2] (conductive layer 240R[2]) and the first terminal of the transistor RTr[3] (conductive layer 220R[3]) are connected via the conductive layer 246[2]. In addition, since the memory string 100 shown in FIG. 2 and FIG. 3 is a case where n=3, the second terminal of the transistor RTr[3] (conductive layer 240R[3]) is connected to the first terminal of the transistor 122 via the conductive layer 246[3].

[0060] The first terminal of the transistor 122 and the second terminal of the transistor 121 are connected via the channel formation regions of the transistors RTr[1] to RTr[n]. Thus, the transistors 121, 122, and the transistors RTr[1] to RTr[n] are connected in series.

[0061] In addition, the second terminals of the transistors WTr[1] to WTr[n] are connected to each other. In FIG. 2 and FIG. 3, the second terminal (conductive layer 240W[1]) of the transistor WTr[1] and the second terminal (conductive layer 240W[2]) of the transistor WTr[2] are connected via the conductive layer 245[2], and the second terminal (conductive layer 240W[2]) of the transistor WTr[2] and the second terminal (conductive layer 240W[3]) of the transistor WTr[3] are connected via the conductive layer 245[3]. In addition, in FIG. 2 and FIG. 3, the second terminal of the transistor WTr[1] is connected to the second terminal of the transistor 121 via the conductive layer 245[1].

[0062] Each of the conductive layers 245 functions as a part of the wiring WBL. Also, a part of the second terminal of each of the transistors WTr functions as a part of the wiring WBL.

[0063] The memory string 100 functions as a NAND type storage device in which a plurality of memory cells 10 are connected in series.

[0064] <Example of transistor configuration> A configuration example of a transistor 200 that can be used as the transistor WTr and the transistor RTr in the memory cell 10 will be described with reference to FIGS.

[0065] FIG. 4(A) is a plan view of the transistor 200. FIG. 4(B) and FIG. 5 are cross-sectional views of the A1-A2 area indicated by the dashed line in FIG. 4(A). FIG. 5 is an enlarged view of FIG. 4(B), showing a configuration example of each layer in more detail. FIG. 4(C) is a cross-sectional view of the dashed line A3-A4 area indicated in FIG. 4(A). FIG. 4(D) is a cross-sectional view of the dashed line A5-A6 area indicated in FIG. 4(B) and FIG. 4(C). FIG. 4(D) can also be said to be a cross-sectional view of the XY plane including the insulating layer 280a. FIG. 4(E) is a cross-sectional view of the dashed line A7-A8 area indicated in FIG. 4(B) and FIG. 4(C). FIG. 4(E) can also be said to be a cross-sectional view of the XY plane including the conductive layer 255. In the plan view of FIG. 4(A), some elements are omitted for clarity. In the plan views below, some elements may also be omitted.

[0066] 4A to 4E and 5 includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, and an insulating layer 280b over the insulating layer 280a. The insulating layer 210, the insulating layer 280a, and the insulating layer 280b function as interlayer films.

[0067] Transistor 200 includes a conductive layer 220a, a conductive layer 220b on conductive layer 220a, a conductive layer 255 on insulating layer 280a, a conductive layer 240a on insulating layer 280b, a conductive layer 240b on conductive layer 240a, an insulating layer 235, a semiconductor layer 230, an insulating layer 250 on semiconductor layer 230, a conductive layer 265a on insulating layer 250, and a conductive layer 265b on conductive layer 265a.

[0068] In this specification, the conductive layer 220a and the conductive layer 220b may be collectively referred to as the conductive layer 220. Moreover, the conductive layer 240a and the conductive layer 240b may be collectively referred to as the conductive layer 240. Moreover, the conductive layer 265a and the conductive layer 265b may be collectively referred to as the conductive layer 265.

[0069] In the transistor 200, the semiconductor layer 230 functions as a semiconductor layer, the conductive layer 265 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 235 functions as a second gate insulating layer. The conductive layer 265 also functions as a gate wiring.

[0070] When the conductive layer 265 is used as a gate electrode, the conductive layer 255 functions as a backgate electrode. In this case, the insulating layer 250 functions as a gate insulating layer, and the insulating layer 235 functions as a backgate insulating layer. Note that when the conductive layer 265 is used as a backgate electrode, the conductive layer 255 functions as a gate electrode.

[0071] In addition, the transistor 200 has a structure in which the channel formation region is electrically surrounded by the electric field of the conductive layer 255 that can function as a gate electrode, and therefore can be said to have a type of GAA (Gate All Around) structure.

[0072] The semiconductor layer 230 has a region overlapping with the conductive layer 255 with the insulating layer 235 interposed therebetween and a region overlapping with the conductive layer 265 with the insulating layer 250 interposed therebetween. At least one of these regions functions as a channel formation region of the transistor 200. One of the region of the semiconductor layer 230 in contact with the conductive layer 220 and the region of the semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0073] As shown in FIGS. 4B and 4C, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b.

[0074] The conductive layer 220 has a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, and a recess is provided in the conductive layer 220b. In other words, the conductive layer 220 has a recess, the bottom surface of which corresponds to the bottom surface of the recess in the conductive layer 220b, and the side surface of which corresponds to the side surface of the recess in the conductive layer 220b. Specifically, the conductive layer 220b has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. When the opening 290 is formed, the second recess is provided in the conductive layer 220b, and then, when the insulating layer 235 is processed, the first recess is provided in the conductive layer 220b. 4(B) and the like, the side surface of the first recess is aligned with the surface of the insulating layer 235 facing the semiconductor layer 230, and the side surface of the second recess is aligned with the side surface of the insulating layer 280a and the like facing the opening 290. Hereinafter, the first recess and the second recess may be collectively referred to as the recess.

[0075] The opening 290 overlaps with the recess of the conductive layer 220b. Here, the bottom of the opening 290 includes the bottom surface of the recess of the conductive layer 220b, and the sidewall of the opening 290 includes the side surface of the recess of the conductive layer 220b, the side surface of the insulating layer 280a, the side surface of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b.

[0076] The opening 290 includes an opening in the insulating layer 280a, an opening in the conductive layer 255, an opening in the insulating layer 280b, an opening in the conductive layer 240a, and an opening in the conductive layer 240b. In other words, an opening in a region where the insulating layer 280a overlaps with the conductive layer 220a is a part of the opening 290, an opening in a region where the conductive layer 255 overlaps with the conductive layer 220a is another part of the opening 290, an opening in a region where the insulating layer 280b overlaps with the conductive layer 220a is another part of the opening 290, an opening in a region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290, and an opening in a region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290. The shape and size of the opening 290 in a plan view may differ depending on each layer. When the upper surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0077] At least some of the components of the transistor 200 are disposed within the opening 290. Specifically, each of the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265 is disposed such that at least a portion of the insulating layer 235 is located within the opening 290.

[0078] The insulating layer 235 has a region located between the semiconductor layer 230 and the conductive layer 255. The semiconductor layer 230 has a region in contact with the insulating layer 235 within the opening 290.

[0079] 4(B) and the like, the insulating layer 235 has a region in contact with the bottom surface of the second recess of the conductive layer 220 and a region in contact with the side surface of the second recess of the conductive layer 220. In addition, the insulating layer 235 has a region in contact with the side surface of the insulating layer 280a, a region in contact with the side surface of the conductive layer 255, a region in contact with the side surface of the insulating layer 280b, a region in contact with the side surface of the conductive layer 240a, and a region in contact with the side surface of the conductive layer 240b in the opening 290. The semiconductor layer 230 has a region in contact with the bottom surface of the first recess of the conductive layer 220, a region in contact with the side surface of the first recess of the conductive layer 220, a region in contact with the insulating layer 235, and a region in contact with the upper surface of the conductive layer 240b. The insulating layer 250 is located inside the semiconductor layer 230 within the opening 290, and the conductive layer 265a is located inside the insulating layer 250 within the opening 290.

[0080] The insulating layer 235 is provided along at least a part of the sidewall of the opening 290. Furthermore, the portions of the semiconductor layer 230 and the insulating layer 250 that are disposed within the opening 290 are provided so as to reflect the shape of the opening 290. Specifically, the semiconductor layer 230 is provided so as to cover the bottom and sidewall of the opening 290, and the insulating layer 250 is provided so as to cover the semiconductor layer 230. Then, the conductive layer 265a is provided so as to fill at least a part of the recess of the insulating layer 250 that reflects the shape of the opening 290.

[0081] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is provided in the opening 290. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all layers constituting the conductive layer 265 in the opening 290 as the transistor 200 is miniaturized and the diameter of the opening 290 becomes smaller. FIGS. 4B and 4C show an example in which the conductive layer 265 has a two-layer structure, in which only the conductive layer 265a is provided in the opening 290, and the conductive layer 265b over the conductive layer 265a is provided so as to overlap with the opening 290. Note that both the conductive layer 265a and the conductive layer 265b may be located in the opening 290 depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like.

[0082] By providing a recess in a position where the conductive layer 220b overlaps with the opening 290, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 265a in the opening 290 can be made lower than the height of the upper surface of the conductive layer 220b in contact with the insulating layer 280a, with the upper surface of the insulating layer 210 as a reference, as compared to a case where the conductive layer 220b does not have the recess. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the upper surface of the insulating layer 210 is used as a reference. The surface used as a reference is not limited to the surface on which the transistor is to be formed. For example, the upper surface of a substrate on which the transistor or semiconductor device is provided may be used as a reference.

[0083] 5, the shortest distance Tc from the upper surface of the insulating layer 210 to the upper surface of the conductive layer 220b that contacts the insulating layer 280a is preferably longer than the shortest distance Ta from the upper surface of the insulating layer 210 to the lower surface of the insulating layer 250. This makes it possible to increase the contact area between the side surface of the conductive layer 220b and the semiconductor layer 230, and to reduce the contact resistance between the conductive layer 220b and the semiconductor layer 230. Therefore, it is possible to suppress a decrease in the on-current of the transistor 200 caused by the contact resistance between the conductive layer 220b and the semiconductor layer 230. The shortest distance Ta can be determined based on the lower surface of the insulating layer 250 in the opening 290.

[0084] As shown in FIG. 5, the shortest distance Tc is more preferably equal to or greater than the shortest distance Tb from the upper surface of the insulating layer 210 to the lower surface of the conductive layer 265a, and is even more preferably longer than the shortest distance Tb. This allows an electric field from the conductive layer 265a to be applied to the entire region between the source region and the drain region of the semiconductor layer 230. That is, an electric field from the conductive layer 265a is applied to the entire channel formation region of the semiconductor layer 230, and the on-current of the transistor 200 can be increased. This allows the electrical characteristics of the transistor 200 to be improved. Furthermore, the gate electric field is also easily applied to the region of the semiconductor layer 230 that is in contact with the conductive layer 220b, so that the on-current of the transistor 200 can be further increased. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved. The shortest distance Tb can be determined based on the lower surface of the conductive layer 265a in the opening 290.

[0085] The semiconductor layer 230 contacts the bottom and side surfaces of the recess of the conductive layer 220b and the upper surface of the conductive layer 240b. The conductive layer 220b has a recess, so that the area of ​​contact between the semiconductor layer 230 and the conductive layer 220b can be increased. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.

[0086] When an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 230, a conductive material containing oxygen is preferably used for the conductive layer 220b, which can reduce contact resistance between the semiconductor layer 230, which is an oxide semiconductor, and the conductive layer 220b.

[0087] Since a conductive material containing oxygen has low contact resistance with an oxide semiconductor, when the conductive layer 220 and the conductive layer 240 have a stacked structure, a conductive material containing oxygen is preferably used for a layer in the stacked structure that has the largest contact area with the semiconductor layer 230, which is an oxide semiconductor. For this reason, for example, a conductive material containing oxygen is preferably used for the conductive layer 220b and the conductive layer 240b.

[0088] Alternatively, when the conductive layer 220 and the conductive layer 240 have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that is closest to a channel formation region, the on-state current of a transistor in which an oxide semiconductor is used for the semiconductor layer 230 can be increased. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240a, for example.

[0089] As the oxygen-containing conductive material, it is preferable to use a metal oxide having electrical conductivity (also called an "oxide conductor").

[0090] 4B shows a structure in which the end of the conductive layer 240a, the end of the conductive layer 240b, and the end of the semiconductor layer 230 are aligned outside the opening 290. The conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 can be manufactured in the same process using the same mask. Therefore, the number of masks required to manufacture a semiconductor device can be reduced. Note that any one of the end of the semiconductor layer 230, the end of the conductive layer 240a, and the end of the conductive layer 240b may be located inside or outside the other in the X direction or Y direction.

[0091] The conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220. In addition, it is preferable that the conductive layer 240 is not located inside the opening 290 of the insulating layer 280b, etc. In other words, it is preferable that the conductive layer 240 does not have a region in contact with the side surface of the insulating layer 280b in the opening 290. With this configuration, the opening 290 can be formed in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a at once. In addition, if the side surface of the conductive layer 240, the side surface of the insulating layer 280b, the side surface of the conductive layer 255, and the side surface of the insulating layer 280a are aligned in the opening 290, the film thickness distribution of the insulating layer 235, the semiconductor layer 230, etc. provided inside the opening 290 can be made uniform. In addition, it is possible to suppress the insulating layer 235, the semiconductor layer 230, etc. from being divided by a step between the conductive layer 240 and the insulating layer 280b, etc.

[0092] In addition, in FIG. 4(B) and FIG. 4(C), a configuration is shown in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 are flush (aligned, or approximately aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 may be discontinuous. Also, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280b in the opening 290 may be different from each other. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280b in the opening 290. By adopting such a configuration, the coverage of the semiconductor layer 230 on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when insulating layer 280a and insulating layer 280b each have a multilayer structure, the inclination of the side surface of each layer may be different within opening 290. Similarly, when conductive layer 240 has a multilayer structure, the inclination of the side surface of each layer within opening 290 may be different.

[0093] An oxide semiconductor may be used as the semiconductor layer 230 in which a channel is formed. In this specification, a transistor using an oxide semiconductor for a semiconductor layer in which a channel is formed is also referred to as an "OS transistor." An oxide semiconductor has a band gap of 2 eV or more and therefore has an extremely low off-state current. Therefore, by using an OS transistor as the transistor WTr, data written to the retention node SN can be held for a long period of time.

[0094] Moreover, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-current hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200° C. or less. The on-current is also unlikely to decrease even in a high-temperature environment. Furthermore, the OS transistor has a high withstand voltage between the source and drain. Thus, a memory circuit or memory element (also referred to as an "OS memory") using an OS transistor operates stably even in a high-temperature environment, and has high reliability.

[0095] In addition, the electrical characteristics of OS memory are less susceptible to change when exposed to radiation such as cosmic rays. In other words, OS memory is less susceptible to soft errors caused by radiation and is highly reliable.

[0096] When OS transistors are used for both the transistors WTr and RTr, a highly reliable memory element can be realized.

[0097] On the other hand, in an OS transistor, oxygen vacancies (V O ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. In addition, hydrogen near the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H) and generate electrons that serve as carriers. For this reason, when oxygen vacancies are contained in the channel formation region in the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0098] On the other hand, the source and drain regions of the OS transistor have more oxygen vacancies than the channel formation region. O It is preferable that the region has a high carrier concentration and low resistance due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, or a metal element. That is, the source and drain regions of the OS transistor are preferably n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0099] As described above, the semiconductor layer 230 is provided inside the opening 290. In addition, the transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located above, so that a current flows in the vertical direction. In other words, a channel is formed along the side surface of the opening 290.

[0100] That is, the transistor 200 is a transistor in which the source electrode and the drain electrode are disposed in the Z direction. The source region and the drain region of the transistor 200 are disposed at different heights. In other words, the source region and the drain region of the transistor 200 are disposed at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0101] A vertical transistor can occupy a smaller area than a conventional transistor (e.g., a planar transistor) in which a channel formation region, a source region, and a drain region are provided separately on the XY plane. Thus, by using a vertical channel transistor, the area occupied by the memory cell 10 can be reduced. Thus, the area occupied by a storage device including the memory cell 10 can be reduced. Furthermore, the memory density of the storage device including the memory cell 10 can be increased. Furthermore, the storage capacity per unit area of ​​a semiconductor device using the memory cell 10 can be increased. Furthermore, by using a vertical channel transistor in a semiconductor device, the area of ​​the semiconductor device can be reduced and the semiconductor device can be highly integrated.

[0102] The positional relationship of each layer in the opening 290 will be described with reference to FIG. 4(D) and FIG. 4(E). The insulating layer 235 is in contact with the outer surface of the semiconductor layer 230. The conductive layer 255 surrounds the entire periphery of the semiconductor layer 230 via the insulating layer 235. The insulating layer 250 is in contact with the outer surface of the conductive layer 265a. The semiconductor layer 230 surrounds the entire periphery of the conductive layer 265a via the insulating layer 250. Thus, the channel formation region of the transistor 200 can be formed on the entire outer surface of the semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 235). Note that FIG. 4(E) can also be said to be a cross-sectional view in the XY plane including the channel formation region of the semiconductor layer 230.

[0103] The channel length of the transistor 200 can be regarded as the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thicknesses of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, and the like on the conductive layer 220. In other words, it can be said that the channel formation region of the semiconductor layer 230 has a region overlapping with a side surface of the insulating layer 280a, a region overlapping with a side surface of the conductive layer 255, and a region overlapping with a side surface of the insulating layer 280b.

[0104] Since the transistor 200 has the conductive layer 255 functioning as a back gate, the threshold voltage of the transistor 200 can be controlled by the potential applied to the conductive layer 255. At this time, a portion of the semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween is most susceptible to the influence of the conductive layer 255. Thus, in FIG. 5, the semiconductor layer 230 is shown divided into three regions, a region 230n+, a region 230n-, and a region 230i. The region 230i corresponds to the portion of the semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween.

[0105] The region 230n+ is formed in the semiconductor layer 230 in a region in contact with the conductive layer 240b or the conductive layer 220b and in its vicinity, and can be called a source region or a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.

[0106] The region 230i is a region in the semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and overlaps with the conductive layer 265a with the insulating layer 250 interposed therebetween. The region 230i functions as a channel formation region. The channel formation region is preferably controlled to be i-type (intrinsic) or substantially i-type by a potential applied to the conductive layer 255.

[0107] The region 230n- is preferably a region having a higher resistance than the region 230n+ and a lower resistance than the region 230i. However, if there is a high resistance region between the region 230i and the region 230n+, the on-current of the transistor 200 may decrease. By making the region 230n- a relatively low resistance region, the on-current of the transistor 200 may be increased. Note that the region 230n- may also function as a channel formation region.

[0108] As described above, when the channel length of the transistor 200 is regarded as the distance between the source region and the drain region, the channel length of the transistor 200 can be regarded as the length L1. On the other hand, since the region 230n- is a region with a lower resistance than the region 230i, the channel formation region of the transistor 200 can also be regarded as the region 230i that is controlled by the conductive layer 255 to become a high resistance region. In this case, the channel length of the transistor 200 can be regarded as the length L0 of the region 230i, which is shorter than the length L1. In this case, the length L0 can also be regarded as the effective channel length of the transistor 200.

[0109] When the resistance of the region 230n- is low and the effective channel length of the transistor 200 is short, the transistor 200 tends to have normally-on characteristics. On the other hand, the transistor of one embodiment of the present invention has a backgate. By supplying a potential that is lower than or equal to the source potential or a potential that is lower than or equal to 0 V (preferably a negative potential) to the backgate, the threshold voltage of the transistor can be shifted in the positive direction, thereby making the transistor normally-off. As a result, the transistor of one embodiment of the present invention can have both a large on-current and normally-off characteristics.

[0110] Note that in the transistor of one embodiment of the present invention, either the conductive layer 255 or the conductive layer 265 may be used as a gate, and either may be used as a back gate. In particular, in the transistor of one embodiment of the present invention, it is preferable to use the conductive layer 265 as a gate and the conductive layer 255 as a back gate. When the conductive layer 265, which has a wider region facing the semiconductor layer 230 than the conductive layer 255, is used as the gate, a gate electric field can be applied to the semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor.

[0111] In a planar transistor, the channel length is limited by the exposure limit of photolithography. In one embodiment of the present invention, however, the channel length can be set by the film thickness of the insulating layer 280a and the insulating layer 280b. Thus, the channel length of the transistor 200 can be made to be an extremely fine structure equal to or less than the exposure limit of photolithography (for example, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm). This increases the on-state current of the transistor 200, and improves the frequency characteristics. A vertical transistor has a structure that makes it easy to reduce the channel length, and therefore can easily increase the on-state current (reduce the on-state resistance). By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0112] As shown in FIG. 4D, the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. Therefore, the side surface of the conductive layer 265a provided at the center faces the side surface of the semiconductor layer 230 through the insulating layer 250. That is, in a plan view, the entire circumference of the semiconductor layer 230 becomes a channel formation region. At this time, for example, the channel width of the transistor 200 is determined by the length of the outer circumference of the semiconductor layer 230. That is, it can be said that the channel width of the transistor 200 is determined by the width of the opening 290 (the diameter when the opening 290 is circular in a plan view). In FIG. 4B to FIG. 4E, the width D of the opening 290 is shown, and in FIG. 4E, the channel width W of the transistor 200 is shown. By increasing the width D of the opening 290, the channel width per unit area can be increased, and the on-current can be increased.

[0113] The width D of the opening 290 may vary in the depth direction. Here, in particular, the shortest distance between two side surfaces facing each other through the opening 290 of the conductive layer 255 in a cross-sectional view perpendicular to the Z direction (for example, FIG. 4B or FIG. 4C) is used as the width D. In other words, the minimum value of the width of the opening 290 in the conductive layer 255 as viewed from the Z direction is used as the width D of the opening 290. In addition, the width of the opening 290 at the highest position in the conductive layer 255, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290 in the conductive layer 255, but the method of determining the width D is not particularly limited. For example, the shortest distance of the width of the opening 290 in any of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b as viewed from the Z direction can be used as the width D. Furthermore, width D may be the width of opening 290 at the highest position, the width of opening 290 at the lowest position, the width of opening 290 at the midpoint between these positions in either insulating layer 280a, insulating layer 280b, conductive layer 240a or conductive layer 240b, or the average value of these three widths.

[0114] When the opening 290 is formed using a photolithography method, the width D of the opening 290 is limited by the exposure limit of the photolithography. The width D of the opening 290 is also limited by the film thickness of each of the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265a provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π".

[0115] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, and more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0116] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. As a result, the distance between the conductive layer 255 and the semiconductor layer 230 and the distance between the conductive layer 265a and the semiconductor layer 230 are each approximately uniform, so that a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0117] In the present embodiment, the opening 290 is circular in plan view, but the present invention is not limited to this. In plan view, the opening 290 may be, for example, a circle, an ellipse, or other nearly circular shape, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, a star-shaped polygon, or other polygon with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIG. 4(A) and the like, the opening 290 is preferably circular in plan view. By making the opening circular, the processing accuracy when forming the opening can be improved, and an opening of a fine size can be formed. In this specification and the like, the circle is not limited to a perfect circle.

[0118] <Materials for semiconductor devices> Materials that can be used for a semiconductor device such as a transistor, a memory cell, a memory string, or a memory device according to one embodiment of the present invention will be described below. Note that each layer constituting a semiconductor device according to one embodiment of the present invention may have a single-layer structure or a stacked-layer structure. FIGS. 4B and 4C show an example in which the conductive layer 220a has a single-layer structure. FIG. 5 shows an example in which the conductive layer 220a has a stacked-layer structure.

[0119] [Semiconductor layer 230] As described above, the semiconductor layer 230 has a channel formation region. The semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low resistance regions) having a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a stacked structure of two or more layers.

[0120] The crystallinity of a semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0121] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 230, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a large band gap for the semiconductor layer 230, the off-state current of the transistor can be reduced. Since the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, since the frequency characteristics of the OS transistor are high, the semiconductor device can operate at high speed.

[0122] For an oxide semiconductor that can be used for a semiconductor layer of a transistor of one embodiment of the present invention, the description in Embodiment 3 can be referred to. Detailed description thereof is omitted here.

[0123] In addition, the semiconductor device of this embodiment may be applied to a transistor using another semiconductor material in the channel formation region. Examples of the other semiconductor material include a semiconductor made of a single element or a compound semiconductor. Examples of the semiconductor made of a single element include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Other examples of the compound semiconductor include organic semiconductors and nitride semiconductors. The above-mentioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may include impurities as dopants.

[0124] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0125] The semiconductor layer of the transistor may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0126] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to group 16). Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0127] [Insulation layer] For the insulating layers (insulating layer 210, insulating layer 235, insulating layer 250, insulating layer 280a, insulating layer 280b, etc.), an inorganic insulating film is preferably used. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may be used for the insulating layer of the semiconductor device.

[0128] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the insulating layers that function as gate insulating layers, such as the insulating layer 235 and the insulating layer 250, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low relative dielectric constant for the insulating layer that functions as an interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings. Therefore, materials can be selected according to the function of the insulating layer. Note that materials with a low relative dielectric constant also have high dielectric strength.

[0129] Examples of materials having a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0130] Examples of materials with low relative dielectric constants include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Examples of other inorganic insulating materials with low relative dielectric constants include silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.

[0131] Furthermore, a material that can have ferroelectricity may be used for the insulating layer 235, the insulating layer 250, etc. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO X(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0132] In addition, examples of materials that can have ferroelectricity include metal nitrides having an element M1, an element M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be set appropriately. In addition, a metal oxide having the element M1 and nitrogen may have ferroelectricity even if it does not contain the element M2. In addition, examples of materials that can have ferroelectricity include materials in which the element M3 is added to the above metal nitride. In addition, the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0133] Moreover, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0134] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxide nitrides in which nitrogen is added to the above-mentioned metal oxides, or metal nitride oxides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0135] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of having ferroelectricity.

[0136] Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a thin film of a few nm. Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a small area. Therefore, by using metal oxides containing hafnium and / or zirconium, it is possible to miniaturize semiconductor devices.

[0137] In this specification, etc., a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, etc., a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0138] It is said that ferroelectricity is expressed by displacing oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to express ferroelectricity, the insulating layer needs to contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.

[0139] In addition, by adding a Group 3 element (also called IIIa element) in the periodic table to an oxide having one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, and crystals having an orthorhombic crystal structure are easily formed. This is preferable because the proportion of crystals having an orthorhombic crystal structure increases, and the remanent polarization can be increased. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide decreases, and ferroelectricity may not be easily expressed. Therefore, the content of the Group 3 element in the oxide having one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0140] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer having a function of suppressing the transmission of impurities and oxygen. As the insulating layer having a function of suppressing the transmission of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as a material for the insulating layer having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0141] Specifically, examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0142] Furthermore, an insulating layer provided in contact with an oxide semiconductor layer or in the vicinity of the oxide semiconductor layer, such as the insulating layer 235 or the insulating layer 250, is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located in the vicinity of the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of an insulating layer in which a region containing excess oxygen is easily formed include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0143] Since the insulating layer 210 functions as an interlayer film, it is preferable that the insulating layer 210 has a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 210.

[0144] In addition, it is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 210. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 230.

[0145] Moreover, it is preferable to use a barrier insulating layer against hydrogen as the insulating layer 210. When the insulating layer 210 provided on the outer side of the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen into the semiconductor layer 230 can be suppressed.

[0146] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0147] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that has low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - In addition, impurities when described as a corresponding substance refer to impurities in the channel formation region or semiconductor layer unless otherwise specified, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, oxygen atoms, oxygen molecules, etc.

[0148] For example, it is preferable to use a silicon nitride film as the insulating layer 210.

[0149] When an oxide semiconductor is used as the semiconductor layer 230, the insulating layer 280a and the insulating layer 280b each preferably have the above-mentioned barrier insulating layer against hydrogen. The insulating layer 280a and the insulating layer 280b are provided so as to surround the semiconductor layer 230. The insulating layer 280a and the insulating layer 280b provided on the outside of the semiconductor layer 230 have a barrier property against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 230 can be suppressed. For example, the insulating layer 280a and the insulating layer 280b each preferably have one or both of an aluminum oxide film and a silicon nitride film.

[0150] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280a and the insulating layer 280b, oxygen can be extracted from the semiconductor layer 230, and the formation of an excessive amount of oxygen vacancies in the semiconductor layer 230 can be suppressed.

[0151] When an oxide semiconductor is used for the semiconductor layer 230, using silicon nitride for the insulating layers 280a and 280b can prevent excess oxygen from being supplied to the semiconductor layer 230. Thus, excess oxygen can be prevented from being contained in the channel formation region of the semiconductor layer 230, which can improve the reliability of the transistor 200.

[0152] The insulating layer 280a and the insulating layer 280b each preferably include the above-described insulating oxide insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen.

[0153] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an atmosphere containing oxygen. In addition, by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulating layer 280a and the insulating layer 280b can be reduced. By depositing at least some of the layers constituting the insulating layer 280a and the insulating layer 280b in this manner, oxygen can be supplied from the insulating layer 280a and the insulating layer 280b to the channel formation region of the semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0154] When an oxide semiconductor is used for the semiconductor layer 230, the concentrations of impurities such as water and hydrogen in the insulating layers 280a and 280b are preferably reduced, which can prevent impurities such as water and hydrogen from entering a channel formation region of the semiconductor layer 230.

[0155] Note that the thicknesses of the insulating layers 280a and 280b on the conductive layer 220 affect the channel length of the transistor 200, so the thicknesses of the insulating layers 280a and 280b are set appropriately according to the design value of the channel length of the transistor 200.

[0156] For example, it is preferable to use a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film as the insulating layer 280a and the insulating layer 280b, respectively. Alternatively, it is preferable to use a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order as the insulating layer 280a and the insulating layer 280b, respectively. For example, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order as the insulating layer 280a and the insulating layer 280b, respectively.

[0157] In the case where an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a function of capturing hydrogen and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0158] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, and examples include oxides containing hafnium and zirconium. Here, in metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, so that they have a high ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, the amorphous structure may be realized by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Note that the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.

[0159] The function of capturing or fixing a corresponding substance can also be said to have a property that makes it difficult for the corresponding substance to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.

[0160] When an oxide semiconductor is used as the semiconductor layer 230 and the gate insulating layer has a stacked structure, a layer in contact with the semiconductor layer 230 preferably has a function of capturing and fixing hydrogen. This makes it possible to more effectively capture or fix hydrogen contained in the semiconductor layer 230. Thus, the hydrogen concentration in the semiconductor layer 230 can be reduced. For example, hafnium silicate or the like may be used as the layer of the insulating layer 250 in contact with the semiconductor layer 230. In addition, the layer preferably has an amorphous structure.

[0161] By making the layer have an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the layer. This makes the film thickness distribution of the insulating layer 250 uniform, and it is possible to reduce portions with an extremely thin film thickness, thereby improving the withstand voltage of the insulating layer 250. In addition, it is possible to make the film thickness distribution of the film provided on the insulating layer 250 uniform.

[0162] Moreover, by suppressing the formation of grain boundaries in the layer, leakage current caused by defect levels in the grain boundaries can be reduced, and the insulating layer 250 can function as an insulating film with low leakage current.

[0163] In addition, hafnium oxide is a high-k material, and hafnium silicate can be a high-k material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In addition, it is possible to reduce the EOT of the gate insulating layer.

[0164] In view of the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0165] Furthermore, when an oxide semiconductor is used as the semiconductor layer 230, it is preferable to use the above-mentioned barrier insulating layer against hydrogen as the insulating layer 250. By using a barrier insulating layer against hydrogen as the insulating layer 250, it is possible to suppress the diffusion of impurities contained in the conductive layer 265 into the semiconductor layer 230. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable as the insulating layer 250. Furthermore, the insulating layer 250 may have an insulating layer having a structure that is stable against heat, such as silicon oxide or silicon oxynitride.

[0166] With such a structure, a semiconductor device having good electrical characteristics, a highly reliable semiconductor device, a semiconductor device with less variation in the electrical characteristics of the transistors, and a semiconductor device with a large on-current can be provided.

[0167] Additionally, insulating layer 250 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0168] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0169] The insulating layer 250 preferably has a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 240, the conductive layer 265, and the like. When the insulating layer 250 has a stacked structure, a layer in contact with the conductive layer 240 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 250, a layer in contact with the conductive layer 240 and a layer in contact with the conductive layer 265 are preferably barrier insulating layers against oxygen.

[0170] By using a barrier insulating layer against hydrogen and oxygen for a layer of the insulating layer 250 that is in contact with the conductive layer 265, oxidation of the conductive layer 265 can be suppressed. When an oxide semiconductor is used for the semiconductor layer 230, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 265 and oxygen vacancies can be suppressed in the semiconductor layer 230.

[0171] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0172] The layer in the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280b. When the layer has a barrier property against oxygen, the side surface of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surface. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0173] Moreover, each layer constituting the insulating layer 250 is preferably a thin film. For example, each layer constituting the insulating layer 250 is set to a thickness of 1 nm to 20 nm, preferably 3 nm to 10 nm, so that the subthreshold swing value (also called S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage being constant in the subthreshold region.

[0174] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Each layer constituting the insulating layer 250 may have a region with the above thickness at least in a part thereof.

[0175] In addition, when an oxide semiconductor is used as the semiconductor layer 230, it is preferable to use a three-layer structure in which a first insulating layer having a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 230 side as the insulating layer 250. As a material having a low relative dielectric constant of the first insulating layer, it is preferable to use silicon oxide or silicon oxynitride. The first insulating layer is a layer in contact with the semiconductor layer 230. By using an oxide for the first insulating layer, oxygen can be supplied to the semiconductor layer 230. In addition, by providing the third insulating layer, it is possible to suppress the diffusion of oxygen contained in the first insulating layer to the conductive layer 265, and thus to suppress the oxidation of the conductive layer 265. In addition, it is possible to suppress a decrease in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 230.

[0176] When an oxide semiconductor is used for the semiconductor layer 230, it is preferable to use a four-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 230 side. The first insulating layer to the third insulating layer can have a similar structure to the layers used in the above-mentioned three-layer structure. The fourth insulating layer is a layer in contact with the semiconductor layer 230. The fourth insulating layer has a barrier property against oxygen, which can suppress oxygen from being released from the semiconductor layer 230. For example, aluminum oxide may be used as the fourth insulating layer. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230. Specifically, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are laminated in this order from the semiconductor layer 230 side.

[0177] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0178] In addition, it is preferable to use a three-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked in this order from the semiconductor layer 230 side as the insulating layer 250. Specifically, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0179] Note that the insulating layer 210 may be an insulating layer having the above-mentioned function of trapping or fixing hydrogen. This allows hydrogen in the semiconductor layer 230 to diffuse into the insulating layer 210 through the conductive layers 220a and 220b, and the hydrogen can be trapped or fixed. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230. For example, the insulating layer 210 may have a two-layer structure of a silicon nitride film and a hafnium silicate film on the silicon nitride film.

[0180] The insulating layer 235 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0181] In the case where an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 235 preferably has an insulating layer having a region containing oxygen that is desorbed by heating. This allows oxygen to be supplied from the insulating layer 235 to the semiconductor layer 230. For example, the insulating layer 235 is preferably made of silicon oxide or silicon oxynitride.

[0182] The insulating layer 235 preferably has a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the semiconductor layer 230 and improve the reliability of the transistor 200. For example, the insulating layer 235 is preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0183] Moreover, the insulating layer 235 may be made of the above-mentioned material that may have ferroelectric properties.

[0184] For example, the insulating layer 235 may be a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film and a silicon nitride film. In the case of a two-layer structure of a silicon oxide film and a silicon nitride film, for example, it is preferable to provide a silicon oxide film on the semiconductor layer 230 side and a silicon nitride film on the conductive layer 255 side. This makes it possible to efficiently supply oxygen to the semiconductor layer 230 and to suppress the diffusion of impurities such as hydrogen into the semiconductor layer 230. Alternatively, a silicon nitride film may be provided on the semiconductor layer 230 side and a silicon oxide film may be provided on the conductive layer 255 side.

[0185] [Conductive layer] For the conductive layers (conductive layer 220, conductive layer 240, conductive layer 255, conductive layer 265, etc.) of the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0186] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.

[0187] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0188] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0189] In the case where a metal oxide is used for the channel formation region of a transistor, a conductive layer that functions as a gate electrode, such as the conductive layer 255 or the conductive layer 265, preferably has a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0190] When an oxide semiconductor is used as the semiconductor layer 230, the conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the semiconductor layer 230, and therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0191] By using a conductive material containing oxygen as the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, IZO (registered trademark), or the like.

[0192] FIG. 5 shows an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2. In this case, it is preferable to use, for example, a conductive material that is not easily oxidized or a conductive material having a function of suppressing the diffusion of oxygen as the conductive layer 220a1, a material with high conductivity as the conductive layer 220a2, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220b. Specifically, it is preferable to use, for example, titanium nitride as the conductive layer 220a1, tungsten as the conductive layer 220a2, and an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) as the conductive layer 220b. In this case, titanium nitride contacts the insulating layer 210, and the oxide conductor contacts the semiconductor layer 230 which is an oxide semiconductor. In addition, an oxide conductor is used in the layer closest to the channel formation region of the semiconductor layer 230. Compared with tungsten, an oxide conductor has a lower contact resistance with the semiconductor layer 230, and therefore the current path between the source and drain can be shortened, and the on-current of the transistor can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230. When an oxide insulating layer is used for the insulating layer 210, the insulating layer 210 can suppress excessive oxidation of the conductive layer 220. When a metal material (here, tungsten) having a higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220a2, the conductivity of the conductive layer 220 can be increased.

[0193] 5 shows an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, for example, it is preferable to use a conductive material containing oxygen as the conductive layer 240b and a material having a higher conductivity than the conductive layer 240b as the conductive layer 240a. Specifically, for example, it is preferable to use an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) as the conductive layer 240b and tungsten as the conductive layer 240a. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used as the conductive layer 240a.

[0194] Of the conductive layer 240, a layer that is mainly in contact with the semiconductor layer 230 is the conductive layer 240b. When an oxide semiconductor is used for the semiconductor layer 230, it is preferable to use an oxide conductor for the conductive layer 240b, since the contact resistance with the semiconductor layer 230 can be reduced. In addition, it is preferable to use a material having a higher conductivity than an oxide conductor for the layer constituting the conductive layer 240, since the conductivity of the conductive layer 240 can be increased.

[0195] Note that the conductive layer 240a may be made of a conductive material containing oxygen, and the conductive layer 240b may be made of a material having higher conductivity than that of the conductive layer 240a. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the semiconductor layer 230. As a result, the current path between the source and drain can be shortened, and the on-current of the transistor can be increased.

[0196] The conductive layer 255 and the conductive layer 265 are preferably made of a material having high conductivity, such as tungsten. In addition, the conductive layer 255 and the conductive layer 265 are preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 255 and the conductive layer 265.

[0197] In addition, the conductive layer 265 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen (for example, titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an outer insulating layer may be captured.

[0198] 5 shows an example in which the conductive layer 265 has a two-layer structure including a conductive layer 265a and a conductive layer 265b over the conductive layer 265a. In this case, for example, it is preferable to use titanium nitride as the conductive layer 265a and tungsten as the conductive layer 265b. Alternatively, it is preferable to use tantalum nitride as the conductive layer 265a and copper as the conductive layer 265b. With such a structure, the conductivity of the conductive layer 265 can be increased.

[0199] The conductive layer 265 may have a stacked structure of three or more layers. For example, the conductive layer 265 may have a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0200] The conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265. For example, a two-layer structure of titanium nitride and tungsten may be used.

[0201] The conductive layer 255 is preferably made of, for example, tungsten or tantalum nitride.

[0202] [substrate] When a semiconductor device such as a transistor, a memory cell, or a memory device is provided on a substrate, there is no significant limitation on the material used for the substrate. The substrate can be determined in consideration of the presence or absence of light transmittance and heat resistance to a degree that can withstand heat treatment, depending on the purpose. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. As the insulating substrate, for example, a glass substrate such as barium borosilicate glass and aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), or the like may be used. In addition, a semiconductor substrate, a flexible substrate, a resin substrate, or the like may also be used.

[0203] Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. In addition, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI substrate. The semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

[0204] Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc., a substrate having a metal nitride, a substrate having a metal oxide, etc., and further include a substrate in which a conductive layer or a semiconductor layer is provided on an insulator substrate, a substrate in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and a substrate in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0205] Examples of materials that can be used for the flexible substrate or resin substrate include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0206] By using the above materials for the substrate, a lightweight semiconductor device can be provided. In addition, by using the above materials for the substrate, a semiconductor device that is resistant to shocks can be provided. In addition, by using the above materials for the substrate, a semiconductor device that is not easily damaged can be provided.

[0207] Alternatively, a substrate having elements provided thereon may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0208] <Memory cell configuration example> FIG. 6(A) shows an example of a circuit configuration of a memory cell 10 included in a memory string 100. FIG. 6(B) is a schematic plan view of the memory cell 10 shown in FIG. 6(A) viewed from the Z direction. FIG. 6(C) is a schematic perspective view of the memory cell 10 shown in FIG. 6(A). FIG. 6(D) is a schematic view of the memory cell 10 shown in FIG. 6(A) viewed from the Y direction. FIG. 6(E) is a schematic view of the memory cell 10 shown in FIG. 6(A) viewed from the X direction. The memory cell 10 shown in FIG. 6(A) is a "2Tr1C type" memory cell composed of two transistors and one capacitance element.

[0209] Fig. 7(A) shows an example of a cross-sectional configuration between B1 and B2 shown by a dashed line in Fig. 6(B), and Fig. 7(B) shows an example of a cross-sectional configuration between B3 and B4 shown by a dashed line in Fig. 4(B).

[0210] As described above, the transistor 200 can be used for the transistors WTr and RTr included in the memory cell 10. By using the transistor 200, which is a vertical transistor, for the transistors WTr and RTr, it is possible to reduce the area occupied by the memory cell 10. Furthermore, by providing the transistors WTr and RTr so as to overlap each other, it is possible to further reduce the area occupied by the memory cell 10.

[0211] Figures 7(A) and 7(B) show examples of the configuration of a memory cell 10 in which a transistor 200 is applied to each of the transistors WTr and RTr. In Figures 6(A) to 6(E), 7(A) and 7(B), "W" and "R" are added to the reference symbols shown in Figures 4(A) to 4(E) and 5 to facilitate comparison with the configuration of the transistor 200. Specifically, "W" is added to the reference symbols of the transistor WTr and parts mainly related to the transistor WTr, and "R" is added to the reference symbols of the transistor RTr and parts mainly related to the transistor RTr.

[0212] The conductive layer 220R functions as one of the source electrode or drain electrode (first terminal) of the transistor RTr. The conductive layer 240R functions as the other of the source electrode or drain electrode (second terminal) of the transistor RTr. The conductive layer 265R functions as the gate electrode of the transistor RTr, and the conductive layer 255R functions as the backgate electrode of the transistor RTr. The conductive layer 255R also functions as the wiring RBG.

[0213] Moreover, a conductive layer 241R is provided on the insulating layer 280bR. The conductive layer 241R has the same configuration as the conductive layer 240R. The conductive layer 241R can be formed at the same time as the conductive layer 240R using the same material in the same process. The conductive layer 241R functions as a wiring COM. A region where the conductive layer 241R and the conductive layer 265R overlap each other via the insulating layer 250R functions as a capacitance element Cs. The conductive layer 265R functions as a retention node SN. Thus, a part of the conductive layer 241R functions as one electrode of the capacitance element Cs, and a part of the conductive layer 265R functions as the other electrode of the capacitance element Cs. By providing the capacitance element Cs, the retention node SN becomes less susceptible to the effects of an external electric field and a leakage current, and the information written in the memory cell 10 can be stably retained. That is, the reliability of the memory cell 10 can be improved.

[0214] The conductive layer 265R functions as the gate electrode of the transistor RTr, and also functions as one of the source electrode or drain electrode (first terminal) of the transistor WTr. The conductive layer 265R serves both as the gate electrode of the transistor RTr and as one of the source electrode or drain electrode of the transistor WTr, so that the conductive layers constituting the memory cell 10 can be reduced. This allows the area occupied by the memory cell 10 to be reduced. Also, the manufacturing cost of the memory cell 10 can be reduced. Also, the productivity of the memory cell 10 can be improved.

[0215] The conductive layer 240W functions as the other of the source electrode or drain electrode (second terminal) of the transistor WTr. The conductive layer 265W functions as the gate electrode of the transistor WTr, and the conductive layer 255W functions as the backgate electrode of the transistor WTr. The conductive layer 255W also functions as the wiring WBG.

[0216] 7(A) and 7(B), the insulating layer 210 is shown divided into insulating layer 210R and insulating layer 210W, but both may be the same layer. For example, insulating layer 210W provided in the i-th stage and insulating layer 210R provided in the (i+1)-th stage may be the same layer.

[0217] In addition, the conductive layer 240W (conductive layer 240W[1]) functioning as the second terminal of the transistor WTr[1] included in the first-stage memory cell 10[1] is connected to the conductive layer 240W (conductive layer 240W[2]) functioning as the second terminal of the transistor WTr[2] included in the second-stage memory cell 10[2] via the conductive layer 245.

[0218] 7A, the conductive layer 245 is provided penetrating the insulating layer 280bW, the insulating layer 280aW, the insulating layer 280bR, the insulating layer 280aR, the insulating layer 210R (insulating layer 210W), the insulating layer 250W, and the semiconductor layer 230W along the Z direction. The conductive layer 240W provided in the i-th stage and the conductive layer 240W provided in the i-1-th stage are connected via the conductive layer 245 provided in the i-th stage. Note that, although the conductive layer 245 is shown as one conductive layer in this embodiment, the conductive layer 245 may be composed of a plurality of conductive layers.

[0219] 7(A), the conductive layer 246 is provided penetrating the insulating layer 210W (insulating layer 210R), the insulating layer 280bW, the insulating layer 280aW, the insulating layer 250R, and the semiconductor layer 230R along the Z direction. The conductive layer 240R provided in the i-th stage and the conductive layer 240R provided in the (i+1)-th stage are connected via the conductive layer 246 provided in the i-th stage. Note that, although the conductive layer 246 is shown as one conductive layer in this embodiment, the conductive layer 246 may be composed of multiple conductive layers.

[0220] In order to retain data written to the retention node SN for a long period of time, it is preferable that the off-current of the transistor WTr is as small as possible. By increasing the channel length of the transistor WTr, the off-current of the transistor WTr can be reduced. Also, in order to increase the speed at which data written to the retention node SN can be read, it is preferable that the on-current of the transistor RTr is as large as possible. By shortening the channel length of the transistor RTr, the on-current of the transistor RTr can be increased. Therefore, it is preferable to increase the channel length of the transistor WTr and shorten the channel length of the transistor RTr. In other words, it is preferable that the channel length of the transistor WTr is longer than the channel length of the transistor RTr. For the same reason, it is preferable that the channel width of the transistor WTr is shorter than the channel width of the transistor RTr.

[0221] FIG. 8 is a cross-sectional view corresponding to FIG. 7(A). In FIG. 8, the channel length of the transistor WTr is indicated as the channel length WL, and the channel length of the transistor RTr is indicated as the channel length RL. When the transistor 200, which is a vertical transistor, is used as the transistor WTr and the transistor RTr, the channel length WL can be controlled by the thicknesses of the insulating layer 280aW, the insulating layer 280bW, and the conductive layer 255W. The channel length RL can be controlled by the thicknesses of the insulating layer 280aR, the insulating layer 280bR, and the conductive layer 255R. Therefore, it is preferable that the total thickness of the insulating layer 280aW, the conductive layer 255W, and the insulating layer 280bW in the region where the conductive layer 240W and the conductive layer 265R overlap when viewed from the Z direction is thicker than the total thickness of the insulating layer 280aR, the conductive layer 255R, and the insulating layer 280bR in the region where the conductive layer 240R and the conductive layer 220R overlap when viewed from the Z direction.

[0222] Each of the conductive layers 245 provided in the first to nth stages and each of the conductive layers 240W provided in the first to nth stages function as a part of the wiring WBL. Therefore, the wiring WBL extends along the Z direction. Moreover, the wiring WWL, the wiring WBG, and the wiring RBG extend in the X direction.

[0223] As described above, by using an OS transistor as the transistor WTr, data written to the retention node SN can be retained for a long period of time. For this reason, it is possible to configure the circuit without the capacitive element Cs, as in the circuit configuration example shown in FIG. 9(A). FIG. 9(B) is a schematic plan view of the memory cell 10 shown in FIG. 9(A) as viewed from the Z direction. FIG. 9(C) is a schematic perspective view of the memory cell 10 shown in FIG. 9(A). FIG. 9(D) is a schematic view of the memory cell 10 shown in FIG. 9(A) as viewed from the Y direction. FIG. 9(E) is a schematic view of the memory cell 10 shown in FIG. 9(A) as viewed from the X direction.

[0224] By adopting a configuration without the capacitance element Cs, the capacitance of the retention node SN is reduced, and the time required for writing information can be shortened. In other words, the writing speed can be increased. Furthermore, by adopting a configuration without the capacitance element Cs, the formation of the wiring COM is also unnecessary. Furthermore, the size of the conductive layer 265R as viewed from the Z direction can be reduced. Therefore, the area occupied by the memory cell 10 can be reduced. As a result, a memory device with high memory density can be provided.

[0225] 10(A) and 10(B) are plan views of a plurality of memory cells 10 in the i-th row arranged in a matrix. Fig. 10(A) is a plan view in the case where the memory cell 10 has a capacitive element Cs. Fig. 10(B) is a plan view in the case where the memory cell 10 does not have a capacitive element Cs. When the memory cell 10 does not have the capacitive element Cs, the wiring COM is not required, and therefore the memory density can be increased compared to when the memory cell 10 has the capacitive element Cs.

[0226] In addition, when the potential of the wiring WBG is a fixed potential, the other electrode of the capacitance element Cs can be connected to the wiring WBG as in the circuit configuration example shown in FIG. 11(A). Or, a part of the wiring WBG can be used as the other electrode of the capacitance element Cs. FIG. 11(B) is a plan schematic diagram of the memory cell 10 shown in FIG. 11(A) seen from the Z direction. FIG. 11(C) is a perspective schematic diagram of the memory cell 10 shown in FIG. 11(A). FIG. 11(D) is a schematic diagram of the memory cell 10 shown in FIG. 11(A) seen from the Y direction. FIG. 11(E) is a schematic diagram of the memory cell 10 shown in FIG. 11(A) seen from the X direction. The region where the wiring WBG and the conductive layer 265R overlap with an insulating layer interposed therebetween functions as the capacitance element Cs.

[0227] FIG. 12(A) is a plan view of a plurality of memory cells 10 in the i-th row arranged in a matrix. FIG. 12(B) is a cross-sectional view between C1 and C2 indicated by a dashed line in FIG. 12(A). FIG. 12(C) is an equivalent circuit diagram of FIG. 12(B). In the memory cell 10 according to one embodiment of the present invention, two adjacent memory cells 10 can share one wiring WBL. That is, two adjacent memory strings 100 can share one wiring WBL. By using one wiring WBL in two memory strings 100, the number of wiring WBLs used can be reduced by half. Therefore, the area occupied by the memory device is further reduced, and a memory device with higher storage density can be provided.

[0228] By using an OS transistor for the transistor WTr, the memory cell 10 can be a 2Tr1C OS memory. Alternatively, by using OS transistors for the transistors WTr and RTr, the memory cell 10 can be a 2Tr1C OS memory.

[0229] The memory cell 10, which is an OS memory, can retain written information for one year or more, or even ten years or more, even if the power supply is stopped. Therefore, the memory cell 10 can be considered as a non-volatile memory.

[0230] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0231] In addition, the memory cell 10, which is an OS memory, writes charge to a retention node via an OS transistor, so that the high voltage required in conventional flash memories is not necessary, and high-speed write operations can be realized. In addition, the erase operation before data rewriting, which is performed in flash memories, is not necessary in OS memories. In addition, since no charge is injected or extracted from the floating gate or charge trapping layer, there is virtually no limit to the number of times data can be written or read in OS memories. Compared to conventional flash memories, OS memories are less susceptible to deterioration, and are highly reliable.

[0232] Moreover, the memory cell 10 does not involve structural changes at the atomic level, as occurs in ferroelectric memories (FeRAM: Ferroelectric Random Access Memory) or resistive random access memories (ReRAM: Resistive Random Access Memory), etc. Therefore, the memory cell 10 has a higher rewrite resistance than ferroelectric memories and resistive random access memories.

[0233] Also, as shown in the circuit diagram of FIG. 13(A), the gate and back gate of the transistor WTr may be connected. In this case, the wiring WBG may be unnecessary. Also, when the Vth of the transistor WTr is large in the positive direction, it is possible to use a transistor without a back gate as the transistor WTr, as shown in the circuit diagram of FIG. 13(B). In this case, the wiring WBG may also be unnecessary. Also, as shown in the circuit diagram of FIG. 13(C), a ferroelectric capacitance element using a ferroelectric material as a dielectric may be used as the capacitance element Cs. Also, as shown in the circuit diagram of FIG. 13(D), a ferroelectric transistor (FeFET: Ferroelectric FET) using a ferroelectric material as a gate insulating layer may be used as the transistor RTr.

[0234] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0235] (Embodiment 2) An operation example of the memory string 100 according to one embodiment of the present invention will be described. In this embodiment, an operation example of the memory string 100 in the case of n=3 will be described. Fig. 14 is a timing chart illustrating the operation of the memory string 100. Figs. 15 to 21 are circuit diagrams illustrating the operation of the memory string 100.

[0236] <Write operation> In this embodiment, an example of operation will be described in which, of the two pieces of information, potential H and potential L, potential H is written to memory cell 10[2]. Specifically, an example of operation will be described in which an amount of charge corresponding to potential H is written to retention node SN[2]. By making potential H correspond to a logical value of "1" and potential L correspond to a logical value of "0", one bit of information can be stored in one memory cell 10. When one memory string 100 has n stages of memory cells 10, a maximum of n bits of information can be stored in one memory string 100.

[0237] In an initial state, a potential L is written to the memory cell 10[1] and the memory cell 10[3]. Also, the transistors 121 and 122 are off, and the potential L is supplied to the wirings WWL[1] to WWL[3], the wirings WBG[1] to WBG[3], the retention nodes SN[1] to SN[3], the wirings RBL, and the wiring SL.

[0238] In addition, a potential L is supplied to the wirings RBG[1] to RBG[3]. When a potential H is supplied to the gate of an n-type transistor and a potential L is supplied to the backgate, the potential on the gate side and the potential on the backgate side are offset, and 0 V is applied to the semiconductor layer. Therefore, the n-type transistor is turned off.

[0239] In order to reliably turn off an n-type transistor, a potential LL may be supplied to the gate or back gate. The potential LL is lower than the potential L. For example, when the Vth variation of a transistor is large, some transistors may not be completely turned off even when the potential L is supplied to the back gate. In that case, for example, by supplying the potential LL to the back gate of an n-type transistor, the n-type transistor can be reliably turned off even if the potential H is supplied to the gate of the n-type transistor.

[0240] In this manner, in this embodiment, when a potential L or a potential LL is supplied to wirings RBG[1] to RBG[3], the transistors RTr[1] to RTr[3] are turned off regardless of the potentials of the retention nodes SN[1] to SN[3].

[0241] [Period T1] In a period T1, a potential H is supplied to the wiring WWL[2] and the wiring WBG[2]. A potential R is supplied to the wiring RBG[2]. The potential R is a potential between the potential H and the potential L. In this embodiment, the potential R is set to 0 V. A potential H is supplied to the wiring SL. The transistor 121 is turned on. Then, the potential of the retention node SN[2] becomes the potential H (see FIGS. 14 and 15).

[0242] Data to be written to the memory cell 10 is supplied from the wiring SL to the memory cell 10 through the source and drain of the transistor 121. By supplying a potential H to both the wiring WWL[2] and the wiring WBG[2], the on-state current of the transistor WTr[2] is increased more than when the potential H is supplied only to the wiring WWL[2], thereby increasing the data writing speed.

[0243] [Period T2] In the period T2, a potential L is supplied to the wiring WWL[2] and the wiring WBG[2]. Then, the transistor WTr[2] is turned off, and the charge written to the retention node SN[2] is retained. Here, an amount of charge equivalent to the potential H is retained (see FIGS. 14 and 16). The potential of the wiring RBG[2] is set to the potential L.

[0244] In this manner, information can be stored in the memory cell 10[2]. Information to be written to the memory cell 10 is supplied from the wiring SL to the memory cell 10 via the source and drain of the transistor 121. When writing information to the memory cell 10[1], a potential L is supplied to the wirings WWL[2], WBG[2], WWL[3], and WBG[3], and a potential H is supplied to the wirings WWL[1] and WBG[1]. Similarly, when writing information to the memory cell 10[3], a potential L is supplied to the wirings WWL[1], WBG[1], WWL[2], and WBG[2], and a potential H is supplied to the wirings WWL[3] and WBG[3].

[0245] <Read operation> An example of an operation for reading information stored in the memory cell 10[2] will be described. In an initial state, a potential L is held in the memory cell 10[1] and the memory cell 10[3]. The transistors 121 and 122 are in an off state, and the potential L is supplied to the wirings WWL[1] to WWL[3], the wirings WBG[1] to WBG[3], the holding node SN[1], the holding node SN[3], the wiring RBL, and the wiring SL. The potential L is supplied to the wirings RBG[1] to RBG[3].

[0246] <<When potential H is maintained>> First, a read operation when the potential H is held in the memory cell 10[2] will be described.

[0247] [Period T3] In the period T3, the transistor 122 is turned on, and a potential HH is supplied to the wirings RBG[1] to RBG[3]. The potential HH is higher than the potential H. By supplying the potential HH to the back gates of the n-type transistors, the transistors can be reliably turned on even if the potential L is supplied to the gates of the transistors. Therefore, the transistors RTr[1] to RTr[3] are turned on regardless of the potentials of the retention nodes SN[1] to SN[3] (see FIGS. 14 and 17). In addition, the potential H is precharged to the wiring RBL. That is, the potential of the wiring RBL is set to the potential H, and then the wiring RBL is put into a floating state.

[0248] [Period T4] In a period T4, a potential R that is a read potential is supplied to the wiring RBG connected to the memory cell 10 to be read. The potential R is a potential between the potential H and the potential L. In this embodiment, the potential R is set to 0 V. Therefore, 0 V is supplied as the potential R to the wiring RBG[2].

[0249] The potential of the retention node SN[2] is the potential H and the potential of the wiring RBG[2] is the potential R, so that the transistor RTr[2] is turned on (see FIGS. 14 and 18). In addition, the potential L is supplied to the wiring SL.

[0250] [Period T5] In the period T5, the transistor 121 is turned on. At this time, the transistors RTr[1] to RTr[3] and the transistor 122 are on, so that the wiring RBL and the wiring SL are connected through these transistors. Then, the potential of the wiring RBL, which has been precharged to the potential H, becomes the potential L (see FIGS. 14 and 19).

[0251] It can be seen that the potential of the wiring RBL becomes the potential L in the period T5, and thus the potential H is held in the memory cell 10[2].

[0252] [Period T6] In the period T6, the potentials of the transistor 121, the transistor 122, and the wirings RBG[1] to RBG[3] are set to a potential L (see FIGS. 14 and 20). Note that in the read operation, the information written to the retention node SN is retained without being erased. Thus, the memory cell 10 is a memory element capable of non-destructive reading.

[0253] <<When potential L is maintained>> Next, a read operation when the potential L is held in the memory cell 10[2] will be described. When the potential L is held in the memory cell 10[2], the potential change in the period T5 is different. In addition, even if the potential of the wiring RBG[2] is set to the potential R in the period T4, the potential of the holding node SN[2] is the potential L, so that the transistor RTr[2] remains in the off state.

[0254] [Period T5x] In the period T5x, the transistor 121 is turned on. At this time, the transistors RTr[1], RTr[3], and 122 are on, but the transistor RTr[2] is off; therefore, the wiring RBL and the wiring SL are not connected. Therefore, the potential of the wiring RBL, which is precharged to the potential H, remains at the potential H (see FIG. 14 and FIG. 21).

[0255] It can be seen that the potential of the wiring RBL remains at the potential H in the period T5x, and therefore the potential L is held in the memory cell 10[2].

[0256] In this manner, information can be written to and read from the memory cell 10.

[0257] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0258] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0259] [Oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having crystallinity. Examples of the structure of the metal oxide having crystallinity include a c-axis aligned crystal (CAAC) structure, a polycrystalline (polycrystal) structure, and a nanocrystalline (nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thus, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a memory device including the transistor can be improved.

[0260] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the ab-plane. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can be said to have a structure having layered crystal parts.

[0261] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or the analysis may be performed by combining a plurality of these techniques.

[0262] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0263] Examples of the metal oxide contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and even more preferably gallium. When the element M of the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably has one or more selected from indium, gallium and zinc. In this specification, etc., metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification, etc. may include metalloid elements.

[0264] Examples of metal oxides according to an embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc., or indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0265] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0266] The metal oxide may have one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field effect mobility of the transistor may be increased. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0267] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0268] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0269] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0270] In the present embodiment, an In-Ga-Zn oxide may be taken as an example of the metal oxide.

[0271] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0272] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed by using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0273] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using a first film formation method, and then forming a metal oxide as a second layer over the first layer by using a second film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface to be formed as compared with the second film formation method as the first film formation method. By using a film formation method that causes less damage to a surface to be formed as the first film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer that is a surface to be formed of the oxide semiconductor layer can be suppressed. Furthermore, impurities such as silicon can be suppressed from being mixed into the second layer, and thus the crystallinity of the oxide semiconductor layer can be increased.

[0274] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of the CVD method include plasma enhanced CVD (PECVD), thermal CVD, photo CVD, and metal organic CVD (MOCVD). Examples of the wet method include spray coating. Compared with the sputtering method described later, the ALD and CVD methods are suitable as the first film formation method because they can suppress damage to the surface to be formed.

[0275] Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0276] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The PEALD method may be preferable because it uses plasma, which allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amount of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. In this method, a high substrate temperature condition and / or an impurity removal treatment is adopted during film formation. Therefore, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without these conditions.

[0277] The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target or the like are deposited. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0278] The plasma CVD method can produce high-quality films at relatively low temperatures. Thermal CVD is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. In addition, thermal CVD does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0279] Examples of the second film formation method include a sputtering method, a pulsed laser deposition (PLD) method, etc. The metal oxide formed by using the second film formation method is likely to have a CAAC structure.

[0280] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased with the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0281] In addition, a third layer can be further formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to give crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0282] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using a first film formation method, forming a metal oxide as a second layer by using a second film formation method, and forming a metal oxide as a third layer by using the first film formation method. Specifically, an ALD method can be used as the first film formation method, and a sputtering method can be used as the second film formation method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the film formation method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Thus, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0283] [Method for producing oxide semiconductor layer] The semiconductor layer 230 which is an oxide semiconductor layer can be manufactured, for example, by forming a semiconductor layer 230a on the layer 229 which is a surface to be formed by an ALD method, forming a semiconductor layer 230b which is an oxide semiconductor layer on the semiconductor layer 230a which is an oxide semiconductor layer by a sputtering method, and forming a semiconductor layer 230c which is an oxide semiconductor layer on the semiconductor layer 230b by an ALD method. After forming the semiconductor layer 230 which is an oxide semiconductor layer, it is preferable to perform heat treatment. By performing the heat treatment, the crystallinity of the semiconductor layer 230 can be improved. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during a manufacturing process.

[0284] The layer 229 corresponds to the insulating layer 235 or the insulating layer 280 described in the above embodiment. The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide of the semiconductor layer 230.

[0285] An example of a method for manufacturing the semiconductor layer 230 will be described with reference to FIGS. 22A to 22D and 23A to 23D.

[0286] When a metal oxide film is formed by a sputtering method, the components contained in the metal oxide film may be alloyed with the components contained in the layer on which the film is formed due to damage caused by sputtering particles on the surface on which the film is formed or energy given to the substrate by the sputtering particles or the like. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when a heat treatment described below is performed. In addition, there is a concern that the use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between the components contained in the metal oxide film and the components contained in the layer on which the film is formed.

[0287] Therefore, first, a semiconductor layer 230a is formed on the layer 229 by ALD (FIG. 22(A)). Then, a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering (FIG. 22(B)).

[0288] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 by a deposition method that causes little damage to a surface on which the semiconductor layer 230a is formed. This can suppress alloying of components contained in the semiconductor layer 230 and components contained in the layer 229, thereby making it possible to further improve the crystallinity of the semiconductor layer 230.

[0289] By using the above-mentioned configuration, the thickness of the alloyed region can be made thin, or can be made thin enough that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be made 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Fig. 22(A) and Fig. 22(B) show an example in which no alloyed region is formed between the layer 229 and the semiconductor layer 230a.

[0290] In addition, the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0291] For example, the EDX line analysis is performed on the above region and its periphery with the direction perpendicular to the surface of the semiconductor layer 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a and is not the main component of the layer (here, layer 229) that will be the surface to be formed becomes half-value is defined as the depth (position) of the interface between the above region and the semiconductor layer 230a. Also, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will be the surface to be formed and is not the main component of the semiconductor layer 230a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that will be the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0292] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0293] For example, when a silicon oxide layer is used as the layer 229 and a SIMS analysis is performed on the semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which the thickness decreases to the interface and the depth is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0294] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0295] By reducing the alloyed region, it becomes possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region from more than 0 nm to 3 nm or less, preferably more than 0 nm to 2 nm or less, more preferably 1 nm to 2 nm or less, approximately perpendicularly from the formation surface of the semiconductor layer 230.

[0296] The CAAC structure near the formation surface may be confirmed by observation using a TEM. For example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0297] When the semiconductor layer 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than that of a CAAC structure may be formed. That is, at the manufacturing stage shown in FIG. 22A, the semiconductor layer 230a may have a region with lower crystallinity than the semiconductor layer 230b.

[0298] The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure.

[0299] When the semiconductor layer 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. In addition, when the semiconductor layer 230b is formed, a minute crystal region may be formed in the mixed layer 231 due to sputtering particles or energy given to the substrate side by the sputtering particles or the like. In a subsequent heat treatment process, the mixed layer 231 or the minute crystal region formed in the mixed layer 231 may become a nucleus, and at least a part of the semiconductor layer 230a may be crystallized.

[0300] In forming the semiconductor layer 230b by the sputtering method, it is preferable to heat the substrate. In forming the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, a metal oxide with high crystallinity may be formed.

[0301] Next, the semiconductor layer 230c is formed on the semiconductor layer 230b by the ALD method (FIG. 22C). For the formation of the semiconductor layer 230c by the ALD method, the method for forming the semiconductor layer 230a can be referred to.

[0302] When the semiconductor layer 230c is formed on the semiconductor layer 230b having the CAAC structure by the ALD method, the semiconductor layer 230c may grow epitaxially with the semiconductor layer 230b as a nucleus. Therefore, when the semiconductor layer 230c is formed, the semiconductor layer 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire semiconductor layer 230c.

[0303] Next, a heat treatment process may be performed. The heat treatment process may increase the crystallinity of the region having the CAAC structure in the semiconductor layer 230c. In addition, if the region is formed only below the semiconductor layer 230c after the film formation by the ALD method, the heat treatment process may cause the region to expand upward (FIG. 22(D)). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire semiconductor layer 230c.

[0304] It is also preferable that at least a part of the semiconductor layer 230a is converted into CAAC by the heat treatment process (FIG. 22(D)). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the semiconductor layer 230a during the deposition of the semiconductor layer 230b acts as a nucleus or seed. It is preferable that the region in the semiconductor layer 230a that is converted into CAAC is large, and it is preferable that the CAAC is converted to CAAC up to the vicinity of the layer 229.

[0305] Furthermore, because the CAAC process is performed from the top to the bottom of the semiconductor layer 230a, the CAAC process can be performed up to the vicinity of the layer 229 without being limited to the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the semiconductor layer 230a can be formed with high crystallinity. Thus, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0306] 22(A) to 22(D) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIG. 22(A) to FIG. 22(D) can be regarded as conceptual diagrams illustrating a model for forming a metal oxide film according to one embodiment of the present invention. As shown in FIG. 22(A) to FIG. 22(D), the semiconductor layer 230a and the semiconductor layer 230c each have high crystallinity using the highly crystalline semiconductor layer 230b as a nucleus or seed. Specifically, the crystallinity of the semiconductor layer 230a may be increased by heat treatment during the formation of the semiconductor layer 230b or after the formation of the semiconductor layer 230c. The crystallinity of the semiconductor layer 230c may be increased by heat treatment during the formation of the semiconductor layer 230c or after the formation of the semiconductor layer 230c. The heat treatment has an assisting effect for increasing the crystallinity.

[0307] In this manner, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the semiconductor layer 230a and the semiconductor layer 230c here) can be increased by using the semiconductor layer 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This can increase the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the semiconductor layer 230b as a nucleus or seed to form an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that, although the structures including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are illustrated in FIGS. 23A to 23D, the present invention is not limited thereto. For example, a structure including the semiconductor layer 230a and the semiconductor layer 230b can also be referred to as an AG CAAC.

[0308] In the semiconductor layer 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. FIG. 23(A) shows the state in which the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are crystallized. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Also, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. The semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observed. The semiconductor layer 230 may be expressed as a single layer.

[0309] Also, there are cases where a portion of the semiconductor layer 230a or the semiconductor layer 230c is not crystallized. The example shown in Fig. 23(B) shows a state in which the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. Fig. 23(C) shows a state in which the vicinity of the surface in the semiconductor layer 230c is not crystallized. Fig. 23(D) shows a state in which the vicinity of the interface with the layer 229 of the semiconductor layer 230a and the vicinity of the surface of the semiconductor layer 230c are not crystallized.

[0310] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of a transistor using the oxide semiconductor layer can be suppressed or initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be increased, and the on-state current can be increased.

[0311] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the semiconductor layer 230, the boundaries between the stacked films of the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c may not be visible. In particular, after heat treatment, it may be difficult to confirm the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed by using, for example, a TEM or the like.

[0312] As described above, by using a metal oxide with a high In content for a transistor, the field effect mobility of the transistor can be increased. On the other hand, an oxide semiconductor with a high In content tends to be polycrystalline. Using a metal oxide with a polycrystalline structure for a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content for one or both of the semiconductor layer 230a and the semiconductor layer 230c, crystals that reflect the crystal orientation of the semiconductor layer 230b are formed, and polycrystallization can be suppressed.

[0313] In addition, it is preferable that the degree of lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small. This allows the semiconductor layer 230a or the semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the semiconductor layer 230b. At this time, for example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0314] As long as the degree of lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small, the crystal structure of the semiconductor layer 230a or the semiconductor layer 230c is not particularly limited. The crystal structure of the semiconductor layer 230a or the semiconductor layer 230c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0315] [Composition of oxide semiconductor layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The semiconductor layer 230b can be formed by, for example, a sputtering method. The semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the metal oxide has high crystallinity. The semiconductor layer 230b preferably contains the element M in addition to zinc. By containing the element M in the semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, it is possible to improve the reliability of a transistor to which an oxide semiconductor layer is applied. Specifically, the semiconductor layer 230b may be made of a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is also preferable to use one or more of gallium, aluminum, and tin as the element M.

[0316] The semiconductor layer 230b may be configured not to include the element M. For example, it may be an In-Zn oxide. Specifically, it may be configured to have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. It may also be configured to include a trace amount of the element M. For example, it may be configured to have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof. Also, it may be configured to have a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0317] The semiconductor layer 230a and the semiconductor layer 230c can be a metal oxide having a high ratio of In. For example, the ALD method can be used to form the semiconductor layer 230a and the semiconductor layer 230c. In particular, it is preferable to use a metal oxide having a higher ratio of In than the element M. By using a metal oxide having a high ratio of In, when the oxide semiconductor layer is applied to a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0318] Alternatively, the semiconductor layer 230a and the semiconductor layer 230c may be configured to not include the element M. For example, they may be In-Zn oxide. Specifically, they may be configured to have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. Also, the semiconductor layer 230a and the semiconductor layer 230c may be configured to include a trace amount of the element M. Specifically, they may be configured to have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0319] In addition, by increasing the composition of zinc in the oxide semiconductor, the crystallinity of the oxide semiconductor can be improved. In particular, it is preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by the ALD method and the semiconductor layer 230b is formed by the sputtering method, the zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. The diffusion may occur during sputtering or during a heat treatment thereafter. The diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to promote the formation of CAAC by the lateral growth of a crystal part having c-axis orientation.

[0320] Furthermore, the semiconductor layer 230a and the semiconductor layer 230c may be made of a metal oxide having a higher proportion of In than the semiconductor layer 230b.

[0321] For example, the semiconductor layer 230a and the semiconductor layer 230c may be made of a metal oxide having a higher Ga ratio than the semiconductor layer 230b. For example, the semiconductor layer 230a and the semiconductor layer 230c may be made of a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. By increasing the ratio of Ga, for example, the band gaps of the semiconductor layer 230a and the semiconductor layer 230c may be made larger than that of the semiconductor layer 230b. As a result, the semiconductor layer 230b is sandwiched between the semiconductor layer 230a and the semiconductor layer 230c having a larger band gap, and the semiconductor layer 230b mainly functions as a current path (channel). By sandwiching the semiconductor layer 230b between the semiconductor layer 230a and the semiconductor layer 230c, it is possible to reduce the trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof, thereby realizing a buried channel type transistor in which the channel is kept away from the insulating layer interface, and thus it is possible to increase the field effect mobility.

[0322] In the oxide semiconductor layer of one embodiment of the present invention, even when the semiconductor layers 230a and 230c are formed using compositions that make it difficult to form a CAAC structure when they are formed as a single layer, crystal growth occurs with the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the semiconductor layers 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the semiconductor layers 230a and 230c and the semiconductor layer 230b.

[0323] In particular, even when the semiconductor layers 230a and 230c have a composition with a high In content, the semiconductor layers can have suitable crystallinity for use as semiconductor layers of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the CAAC structure with high crystallinity can improve reliability.

[0324] The semiconductor layer 230a and the semiconductor layer 230c may have different compositions.

[0325] The semiconductor layer 230a and the semiconductor layer 230c may be made of a metal oxide having the same composition as the semiconductor layer 230b.

[0326] By using an oxide semiconductor layer having a CAAC structure formed by using the above-described two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0327] The composition of the metal oxide used in the semiconductor layer 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0328] [c-axis orientation rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation, for example.

[0329] The crystal orientation can be obtained from the Fast Fourier Transform (FFT) pattern obtained by FFT processing of the TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of the electron diffraction pattern.

[0330] By performing FFT processing for each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystal part. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0331] The c-axis orientation rate can be calculated by calculating the ratio of c-axis oriented regions in a map showing crystal orientation. Note that the c-axis oriented regions are defined here as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0332] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0333] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0334] The c-axis orientation rates of the region formed as the semiconductor layer 230a, the region formed as the semiconductor layer 230b, and the region formed as the semiconductor layer 230c are Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0335] After the semiconductor layer 230 is fabricated, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0336] The semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, in this order from the top of the layer 229. Each region is a layer-like region.

[0337] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the second region and the third region is each 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0338] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the semiconductor layer 230 .

[0339] Or, the layer thickness in each region may be approximately the same, for example.

[0340] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0341] (Embodiment 4) In this embodiment, a configuration example of a memory device 300 including a memory string 100 according to one embodiment of the present invention will be described.

[0342] <Storage device 300> 24A is a block diagram illustrating a configuration example of a memory device 300 including a memory string 100 of one embodiment of the present invention. The memory device 300 illustrated in FIG.

[0343] The memory cell array 310 has a plurality of memory strings 100 arranged in a matrix of p rows and q columns (each of p and q is an integer equal to or greater than 1). By arranging a plurality of memory strings 100 in a matrix, a memory device with a large storage capacity can be realized.

[0344] In Figure 24 (A), memory string 100 in the first row, first column is indicated as memory string 100[1,1], memory string 100 in the pth row, qth column is indicated as memory string 100[p,q], memory string 100 in the pth row, first column is indicated as memory string 100[p,1], memory string 100 in the 1st row, qth column is indicated as memory string 100[1,q], and memory string 100 in the rth row, sth column (r is an integer greater than 1 and less than p indicating an arbitrary row, and s is an integer greater than 1 and less than q indicating an arbitrary column) is indicated as memory string 100[r,s].

[0345] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction (direction along the X axis) is referred to as the "rows" and the Y direction (direction along the Y axis) is referred to as the "columns", but the X direction may be referred to as the "columns" and the Y direction as the "rows".

[0346] The drive circuit 21 includes a power switch 22, a power switch 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generating circuit 33.

[0347] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0348] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 32.

[0349] The control circuit 32 is a logic circuit having a function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0350] The voltage generating circuit 33 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when a signal of potential H is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a voltage.

[0351] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory string 100. The peripheral circuit 41 includes a row decoder , a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, a sense amplifier , and an output circuit .

[0352] The row decoder 42 and the column decoder 44 have a function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has a function of selecting a wiring (a wiring WWL, a wiring WBG, a wiring RBG) specified by the row decoder 42. The column driver 45 has a function of supplying data to be stored in the memory string 100 to a wiring WBL specified by the column decoder 44. The column driver 45 also has a function of supplying a potential H to a wiring RBL specified by the column decoder 44. The sense amplifier 46 has a function of detecting a change in potential of the wiring RBL specified by the column decoder 44 and reading out the data stored in the memory string 100.

[0353] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory string 100. The data (Dout) read from the memory string 100 by the sense amplifier 46 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.

[0354] The power switch 22 has a function of controlling the supply of a potential VDD to the peripheral circuit 31. The power switch 23 has a function of controlling the supply of a potential VHM to the row driver 43. Here, the high power supply potential of the memory device 300 is the potential VDD, and the low power supply potential is the potential GND (ground potential). The potential VHM is a power supply potential used to set a word line (for example, a wiring WWL) to a potential H, and is a potential higher than the potential VDD. The on / off of the power switch 22 is controlled by a signal PON1, and the on / off of the power switch 23 is controlled by a signal PON2. In FIG. 24(A), the number of power supply domains to which the potential VDD is supplied in the peripheral circuit 31 is one, but it may be multiple. In this case, a power switch may be provided for each power supply domain.

[0355] 24B, the driver circuit 21 may be provided in the layer 50, and the layer 20 having the memory cell array 310 may be provided on the layer 50. The layer 50 may be a single crystal semiconductor substrate, an SOI substrate, or the like. By separately forming the layer 50 including the driver circuit 21 and the layer 20 including the memory cell array 310, the operation of the driver circuit 21 included in the layer 50 can be confirmed before the layer 20 is formed on the layer 50. Therefore, only non-defective layers 50 can be used, and the manufacturing yield of the memory device 300 can be improved.

[0356] By stacking the layer 50 including the driving circuit 21 and the layer 20 including the memory cell array 310, the signal propagation distance between the driving circuit 21 and the memory cell array 310 can be shortened. Therefore, the parasitic resistance and parasitic capacitance between the driving circuit 21 and the memory cell array 310 are reduced, and the power consumption and signal delay can be reduced. In addition, the memory device 300 can be made smaller. In addition, the memory capacity per unit area can be increased.

[0357] <Example of stacked configuration of storage device> FIG. 25 shows an example of a stacked configuration of a memory device 300, which is a type of semiconductor device. The memory device 300 shown in FIG. 25 has a layer 20 including a memory cell array 310 above a layer 50 including a driver circuit 21. FIG. 25 shows a memory cell 10[i] and a memory cell 10[i+1] included in a memory string 100[r,s] as an example. In FIG. 25, [i] is attached to a part of the layer that constitutes the memory cell 10[i]. In addition, [i+1] is attached to a part of the layer that constitutes the memory cell 10[i+1].

[0358] In order to reduce repetition, the description of the memory cell 10 will be omitted here.

[0359] 25 illustrates a transistor 400 as an example of a transistor included in the driver circuit 21. The transistor 400 is provided over a substrate 371 and includes a conductive layer 376 functioning as a gate, an insulating layer 375 functioning as a gate insulating layer, a semiconductor region 373 formed of a part of the substrate 371, and a low-resistance region 374a and a low-resistance region 374b functioning as a source region or a drain region. The transistor 400 can be a p-channel transistor or an n-channel transistor. As the substrate 371, for example, a single crystal silicon substrate can be used.

[0360] Here, in the transistor 400 shown in FIG. 25, a semiconductor region 373 (a part of a substrate 371) in which a channel is formed has a convex shape. A conductive layer 376 is provided so as to cover the side and upper surface of the semiconductor region 373 via an insulating layer 375. Note that the conductive layer 376 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulating layer that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.

[0361] Note that the transistor 400 illustrated in FIG. 25 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0362] The layer 50 may be provided with a wiring layer provided with an interlayer film, wiring, plugs, and the like. Also, a plurality of wiring layers may be provided according to the design. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0363] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 392 and the like are embedded in the insulating layer 390 and the insulating layer 391. A conductive layer 395 and the like are embedded in the insulating layer 393 and the insulating layer 394. The conductive layer 392 and the conductive layer 395 function as contact plugs or wirings.

[0364] In addition, the insulating layer functioning as an interlayer film may also function as a planarizing film that covers the uneven shape below it. For example, the upper surface of the insulating layer 391 may be subjected to CMP processing or the like to improve flatness.

[0365] A wiring layer may be provided over the insulating layer 394 and the conductive layer 395. For example, in FIG. 25, an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 394 and the conductive layer 395. A conductive layer 386 is formed in the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 386 functions as a contact plug or a wiring. The memory string 100[r,s] is connected to the transistor 400 through the conductive layer 386.

[0366] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0367] (Embodiment 5) In this embodiment, application examples of a memory device including a memory element according to one embodiment of the present invention (hereinafter also referred to as a "memory device according to one embodiment of the present invention") will be described.

[0368] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 26(A) shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed is required, and the lower the layer, the larger the memory capacity and the higher the memory density is required. Figure 26(A) shows, from the top layer, memories embedded as registers in arithmetic processing devices such as CPUs, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), and 3D NAND memories.

[0369] The memory embedded as a register in a processor such as a CPU is used for temporary storage of calculation results, and is accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. The register also has the function of storing setting information for the processor.

[0370] SRAM is used, for example, in caches. Caches have the function of duplicating and storing part of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate faster than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0371] DRAM is used, for example, as a main memory. The main memory has a function of storing programs and data read from storage. The memory density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 It is.

[0372] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored for a long time and various programs used in processing units. Therefore, storage requires a larger memory capacity and a higher memory density than the operating speed. The memory density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 It is.

[0373] The storage device according to one embodiment of the present invention has a high operating speed and is capable of retaining data for a long period of time. The storage device according to one embodiment of the present invention is suitable as a storage device located in a boundary area 901 including both a hierarchical level where a cache is located and a hierarchical level where a main memory is located. The storage device according to one embodiment of the present invention is also suitable as a storage device located in a boundary area 902 including both a hierarchical level where a main memory is located and a hierarchical level where a storage is located.

[0374] Moreover, the storage device according to one aspect of the present invention is suitable for both the hierarchical level where the main memory is located and the hierarchical level where the storage is located. Moreover, the storage device according to one aspect of the present invention is suitable for the hierarchical level where the cache is located. Figure 26(B) shows various hierarchical levels of storage devices different from those shown in Figure 26(A).

[0375] 26B illustrates, from the top layer, a memory integrated as a register in an arithmetic processing device such as a CPU, an SRAM used as a cache, and a storage device 300 according to one embodiment of the present invention. The storage device 300 according to one embodiment of the present invention can be used for the cache, the main memory, and the storage. Note that when a high-speed memory with a speed of 1 GHz or higher is required as the cache, the cache is integrated into an arithmetic processing device such as a CPU.

[0376] The memory device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (DCs), and various electronic devices. By using the memory device of one embodiment of the present invention, the electronic components, mainframes, space equipment, DCs, and various electronic devices can achieve low power consumption and high performance.

[0377] Examples of electronic devices include electronic devices with relatively large screens, such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0378] The electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0379] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded on a recording medium, etc.

[0380] [Electronic components] FIG. 27(A) shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 27(A) has memory device 300 in mold 711. FIG. 27(A) omits some parts in order to show the inside of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 300 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0381] The memory device 300 also has a layer 50 and a layer 20. The layer 50 includes a driving circuit 21, and the layer 20 includes a memory cell array 310. The memory cell array 310 includes a plurality of memory strings 100. The memory string 100 includes a plurality of memory cells 10. The memory device 300 can be configured as a monolithic stack of the layers 50 and 20. In the monolithic stack configuration, the layers can be connected to each other without using a through electrode technology such as TSV (Through Silicon Via) and a bonding technology such as Cu-Cu direct bonding. By configuring the layers 50 and 20 as a monolithic stack, for example, a so-called on-chip memory configuration can be configured in which a memory is formed directly on a processor. By configuring the on-chip memory, it is possible to increase the speed of the operation of the interface between the processor and the memory.

[0382] In addition, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSV, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).

[0383] It is also preferable that the memory cell array 310 in the layer 20 is formed using OS transistors, and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that in the case of a configuration using Si transistors in the layer 20, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that the OS transistor has a better structure than the Si transistor in the monolithic stacked configuration.

[0384] The storage device 300 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape in the manufacturing process of a semiconductor chip. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0385] 27B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 300 provided on the interposer 731.

[0386] In the electronic component 730, an example is shown in which the storage device 300 is used as a high bandwidth memory (HBM). Also, the semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0387] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0388] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In some cases, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV may be used as the through electrode.

[0389] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0390] In addition, in SiP and MCM using silicon interposers, the reliability is less likely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. In addition, since the surface of the silicon interposer is highly flat, connection failure between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0391] On the other hand, when a silicon interposer and TSV are used to electrically connect multiple integrated circuits having different terminal pitches, a space is required for the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacking configuration using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.

[0392] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 300 and the height of the semiconductor device 735.

[0393] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. Fig. 27(B) shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0394] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0395] [Large computer] Next, Figure 28(A) shows a perspective view of a large scale computer 5600. The large scale computer 5600 shown in Figure 28(A) has a rack 5610 housing a plurality of rack-mounted computers 5620. The large scale computer 5600 may also be called a supercomputer.

[0396] The computer 5620 can have the configuration shown in the perspective view of Fig. 28(B), for example. In Fig. 28(B), the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.

[0397] A PC card 5621 shown in Fig. 28C is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in Fig. 28C, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to for these semiconductor devices.

[0398] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0399] The connection terminals 5623, 5624, and 5625 can be interfaces for supplying power and inputting signals to the PC card 5621, for example. They can also be interfaces for outputting signals calculated by the PC card 5621, for example. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0400] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0401] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 by a reflow method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0402] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 by a reflow method. The semiconductor device 5628 can be, for example, a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0403] The mainframe 5600 can also function as a parallel computer. By using the mainframe 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0404] [Space equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0405] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor has small variations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high resistance to radiation and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0406] Fig. 28(D) shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 28(D) shows a planet 6804 in space.

[0407] 28D, a battery management system (also referred to as BMS) or a battery control circuit may be provided for the secondary battery 6805. The battery management system or the battery control circuit is preferably formed using an OS transistor because it consumes low power and has high reliability even in space.

[0408] Furthermore, outer space is an environment with radiation levels 100 times higher than on the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0409] When sunlight is irradiated onto the solar panel 6802, power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight or where the amount of sunlight irradiated onto the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 is not generated. In order to operate the satellite 6800 even under a situation where the amount of power generated is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0410] The artificial satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. As described above, the artificial satellite 6800 can constitute a satellite positioning system.

[0411] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor according to one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor is highly reliable and preferable even in an environment where radiation may be incident.

[0412] The artificial satellite 6800 can also be configured to have a sensor. For example, by configuring the artificial satellite 6800 to have a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected from an object on the ground. Or, by configuring the artificial satellite 6800 to have a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have a function as, for example, an earth observation satellite.

[0413] Note that in this embodiment, an artificial satellite is given as an example of space equipment, but the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, or a space probe.

[0414] As described above, OS transistors have the excellent advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance than Si transistors.

[0415] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring the immutability of the data. In order to manage long-term data, it is necessary to increase the size of the building, for example, to install storage and servers for storing a huge amount of data, to secure a stable power source for holding the data, or to secure cooling equipment required for holding the data.

[0416] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores data. This makes it possible to miniaturize the storage system, the power source for storing data, and the cooling equipment. As a result, it is possible to reduce the space required for the data center.

[0417] In addition, the semiconductor device of one embodiment of the present invention consumes less power, and thus heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0418] Fig. 28(E) shows a storage system applicable to a data center. A storage system 7010 shown in Fig. 28(E) has a plurality of servers 7001sb as a host 7001 (illustrated as Host Computer). It also has a plurality of storage devices 7003md as a storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0419] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0420] The storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required by DRAM that can be used as cache memory in the storage. In a storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is normally provided in the storage to reduce the time required to store and output data.

[0421] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0422] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced. In addition, by stacking memory cell arrays, the size can be reduced.

[0423] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO2). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.

[0424] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes. [Explanation of symbols]

[0425] 10 Memory Cells 100 Memory Strings 121 Transistor 122 Transistor 200 Transistors 210 Insulating layer 220 Conductive layer 230 Semiconductor layer 235 Insulating Layer 240 Conductive Layer 245 Conductive Layer 246 Conductive Layer 250 Insulation Layer 255 Conductive Layer 265 Conductive Layer 290 Opening 300 storage device 310 Memory Cell Array

Claims

1. n memory cells (n is an integer of 3 or more); a first wiring, n second wirings, n third wirings, and n fourth wirings; Each of the n memory cells includes a first transistor and a second transistor; Each of the first transistor and the second transistor is a first conductive layer, a first insulating layer on the first conductive layer, a fourth conductive layer on the first insulating layer, a second insulating layer on the fourth conductive layer, a second conductive layer on the second insulating layer, a semiconductor layer having a region along a side surface of the fourth conductive layer, and a third conductive layer having a region along a side surface of the fourth conductive layer via the semiconductor layer, a second conductive layer of a first transistor [i] included in an i-th memory cell (i is an integer not less than 2 and not more than n-1) is electrically connected to the first wiring, a first conductive layer of the first transistor [i] is electrically connected to a third conductive layer of a second transistor [i] included in the i-th memory cell; the third conductive layer of the first transistor [i] is electrically connected to the i-th second wiring, the fourth conductive layer of the first transistor [i] is electrically connected to the i-th third wiring, the fourth conductive layer of the second transistor [i] is electrically connected to the i-th fourth wiring, the first conductive layer of the second transistor [i] is electrically connected to the second conductive layer of the second transistor [i-1] included in the (i-1)th memory cell; the second conductive layer of the second transistor [i] is electrically connected to the first conductive layer of a second transistor [i+1] included in the (i+1)th memory cell; storage device.

2. In claim 1, The first transistor [i] and the second transistor [i] have regions that overlap each other in a plan view.

3. In claim 1 or 2, A memory device in which a first conductive layer of the first transistor [i] functions as a third conductive layer of the second transistor [i].

4. In claim 1 or 2, The semiconductor layer includes an oxide semiconductor.

5. In claim 1 or 2, Each of the n memory cells has a capacitance element; The storage device, wherein the capacitive element included in the i-th memory cell is electrically connected to the third conductive layer of the second transistor [i].

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