Microelectronic devices including corrosion containment features, and related electronic systems and methods

Abstract

To reduce or eliminate effects of corrosion in a microelectronic device.SOLUTION: A microelectronic device comprises a stack structure comprising a non-staircase region, a staircase region and an array region. Each of the non-staircase region, the staircase region and the array region comprises tiers of alternating conductive materials and dielectric materials. One or more pillars are in the non-staircase region and in the array region, and one or more supports are in the staircase region. A source comprises a conductive portion adjacent to the stack structure. Corrosion containment features are laterally adjacent to the conductive portion of the source in each of the non-staircase region, the staircase region and the array region. A dielectric-filled slit is in each of the non-staircase region, the staircase region and the array region, extends vertically into the conductive portion of the source, and is laterally adjacent to the corrosion containment features.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] [Priority claim] This application is a national stage entry of international patent application PCT / US2020 / 065132, filed on December 15, 2020, and published in English as International Patent Publication WO2021 / 146014A1 on July 22, 2021, designating Japan, which claims the benefit under Article 8 of the Patent Cooperation Treaty to U.S. patent application serial number 16 / 743,342, filed on January 15, 2020.

[0002] [Technical field] The disclosure, in various embodiments, relates generally to the field of microelectronic device design and manufacturing. More specifically, the disclosure relates to microelectronic device structures that include mechanisms for inhibiting corrosion, and to related microelectronic devices, electronic systems, and methods. [Background technology]

[0003] A continuing goal of the microelectronics industry is to increase the memory density (e.g., number of memory cells per memory die) of memory devices such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. A conventional vertical memory array includes transistor / memory cell pillars that extend through one or more decks (e.g., stack structures) that include tiers of alternating conductive and dielectric materials. The vertically oriented conductive materials of the tiers are configured as, for example, word lines or control gates, and a dielectric material is at each junction between the memory cell pillars and the conductive materials. This configuration allows a larger number of transistors to be placed per unit of die area by building the arrays upwards (e.g., lengthwise, vertically) on the die, as compared to structures having a conventional planar (e.g., two-dimensional) array of transistors. Such a configuration allows for a larger number of switching devices (e.g., transistors) to be placed per unit of die area (i.e., length and width of consumed active surface) by building the array upwards (e.g., vertically) on the die, as compared to structures having a conventional planar (e.g., two-dimensional) array of transistors.

[0004] To form a 3D NAND flash memory device, a so-called "replacement gate" process may be used in which a tier containing alternating dielectric and nitride materials becomes a tier containing alternating dielectric and conductive materials. The nitride material of the tier is replaced with a conductive material to produce a tier of alternating conductive and dielectric materials. During the replacement gate process, a material removal process (e.g., an etching process) is performed to form a so-called "slit" in the tier, which extends from the top surface of the top tier to the bottom surface of the bottom tier. The nitride material of the tier is then removed through the slit and replaced with a conductive material. The slit may be in different parts of the 3D NAND flash memory device, such as in the staircase region, the array region, or in a region outside the staircase region. During the formation of the slit, over-etching of the tier material may occur, extending the slit through the contact material into the source material underlying the tier in the array region and into the source material underlying the non-staircase region. Thus, the slit extends into the source material in the array region and the non-staircase region. Similarly, when forming slits in the step region, the fill material may be over-etched such that the slits extend through the fill material into the source material in the step region. When exposed to the conditions of the etch process (e.g., etch chemistry, etch time), corrosion of the source material and contact material may occur in the step region, array region, or non-step region. The corrosion may lift tears in the array region and steps in the step region, leading to arcing and other performance issues in the 3D NAND flash memory device including corrosion. Summary of the Invention

[0005] A microelectronic device is disclosed that includes a stack structure including a non-step region, a step region, and an array region. Each of the non-step region, the step region, and the array region includes tiers of alternating conductive and dielectric materials. One or more pillars are in the non-step region and in the array region, and one or more support posts are in the step region. A conductive material is in each of the non-step region, the step region, and the array region and extends vertically into a source adjacent the tiers. The source includes a corrosion inhibition feature in each of the non-step region, the step region, and the array region adjacent the conductive material in the source.

[0006] A microelectronic device is also disclosed that includes a stack structure including a non-step region, a step region, and an array region. Each of the non-step region, the step region, and the array region includes tiers of alternating conductive and dielectric materials. A source includes portions adjacent the stack structure and separated by a corrosion inhibition mechanism in the source. The source includes a bridge between adjacent portions of the source in the array region. Another conductive material extends vertically into the source from a top surface of the tiers.

[0007] A method of forming a microelectronic device is further disclosed. The method includes forming a source including a corrosion inhibition feature therein. Tiers of alternating nitride and dielectric material are formed adjacent to the source. One or more slits are formed extending from an uppermost one of the tiers into the source. The corrosion inhibition feature is adjacent to the one or more slits in the source. Nitride material of the tiers is removed through the one or more slits to form voids between adjacent dielectric material of the tiers. A conductive material is formed in the voids and in the slits.

[0008] Also disclosed is an electronic system including an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes at least one microelectronic device including a stack structure including tiers of alternating conductive and dielectric materials in a non-step region, a step region, and an array region. A source includes a portion adjacent the stack structure and separated by a corrosion inhibition feature. Top surfaces of the source and the corrosion inhibition feature are substantially coplanar with each other. Another conductive material extends vertically into the source from a top surface of the tiers. [Brief description of the drawings]

[0009] [Figure 1A] 1 is a simplified partial top view of a non-step region of a microelectronic device structure in an early stage of processing the microelectronic device structure according to a disclosed embodiment; FIG. [Figure 1B] FIG. 1B is a simplified partial cross-sectional view of the microelectronic device structure of FIG. 1A. [Figure 2A] 1 is a simplified partial top view of an array region of a microelectronic device structure according to an embodiment of the disclosure at an early stage of processing the microelectronic device structure. [Figure 2B] FIG. 2B is a simplified partial cross-sectional view of the microelectronic device structure of FIG. 2A taken along line AA. [Figure 2C] FIG. 2B is a simplified partial cross-sectional view of the microelectronic device structure of FIG. 2A taken along line BB. [Figure 3A] 1 is a simplified partial top view of a staircase region of a microelectronic device structure in an early stage of processing the microelectronic device structure according to an embodiment of the disclosure; FIG. [Figure 3B] FIG. 3B is a simplified partial cross-sectional view of the microelectronic device structure of FIG. 3A. [Figure 4] A process for forming a microelectronic device structure according to disclosed embodiments is described. [Diagram 5]A process for forming a microelectronic device structure according to disclosed embodiments is described. [Figure 6] A process for forming a microelectronic device structure according to disclosed embodiments is described. [Figure 7] A process for forming a microelectronic device structure according to disclosed embodiments is described. [Figure 8] FIG. 1 is a partial cross-sectional perspective view of a microelectronic device including a microelectronic device structure according to an embodiment of the disclosure. [Figure 9] FIG. 1 is a schematic block diagram illustrating an electronic system including a microelectronic device structure according to an embodiment of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Disclosed is a mechanism (e.g., corrosion inhibition mechanism) for reducing or substantially eliminating the effects of corrosion in a microelectronic device. The microelectronic device includes a microelectronic device structure including one or more materials (e.g., source material, contact material) susceptible to corrosion (e.g., oxidation) during material removal operations performed during formation of the microelectronic device. The corrosion inhibition mechanism and the material susceptible to corrosion are present in one or more regions of the microelectronic device structure, including in a step region, in an array region, or proximate (e.g., outside) the step region (e.g., a non-step region). The corrosion inhibition mechanism reduces or substantially eliminates the effects of corrosion in the microelectronic device. By forming a corrosion inhibition mechanism in a source of the microelectronic device structure, corrosion of the material susceptible to corrosion is inhibited to a small region of the microelectronic device structure and the effects of corrosion do not affect other regions of the microelectronic device structure. The corrosion inhibition mechanism insulates (e.g., electrically insulates) the region affected by corrosion from other regions of the microelectronic device structure. Bridges of material of the source join (e.g., connect) adjacent portions of the source in the array region of the microelectronic device structure. Methods of forming microelectronic device structures that include the corrosion-inhibiting features and bridges are also disclosed, as well as microelectronic devices and electronic systems that include the corrosion-inhibiting features and bridges.

[0011] The following description provides specific details such as material compositions, shapes, and sizes to provide a complete description of the disclosed embodiments. However, one of ordinary skill in the art will understand that the disclosed embodiments may be practiced without these specific details. Indeed, the disclosed embodiments may be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Additionally, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary to understand the disclosed embodiments are described in detail below. Additional actions to form a complete microelectronic device from the structure may be performed by conventional manufacturing techniques.

[0012] The drawings presented herein are for illustrative purposes only and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from shapes depicted in the drawings are expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes or regions as described, including, for example, deviations in shapes resulting from manufacturing. For example, a region illustrated or described as a box shape may have rough and / or non-linear features, and a region illustrated or described as a circle may include some rough and / or linear features. Furthermore, sharp angles described may be rounded, and vice versa. Thus, the regions depicted in the figures are schematic in nature, and their shapes are not intended to describe the exact shape of the regions and do not limit the scope of the claims. The figures are not necessarily drawn to scale. Additionally, elements common between the figures may retain the same numerical designations.

[0013] As used herein, "memory device" means and includes, but is not limited to, a microelectronic device that exhibits memory functionality.

[0014] As used herein, the terms "vertical", "longitudinal", "horizontal" and "transverse" refer to the major plane of a structure, not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction that is substantially parallel to the major plane of the structure, while a "vertical" or "longitudinal" direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of a structure is defined by the surface of the structure that has a relatively large area compared to other surfaces of the structure.

[0015] As used herein, "vertically adjacent" or "vertically adjacent" features (e.g., regions, structures, devices) mean and include those features that are in closest vertical proximity (e.g., vertically closest) to one another, and as used herein, "horizontally adjacent" or "laterally adjacent" features (e.g., regions, structures, devices) mean and include those features that are in closest horizontal proximity (e.g., horizontally closest) to one another.

[0016] As used herein, spatially relative terms such as "under", "lower", "bottom", "upper", "top", "top", "front", "rear", "left", and "right" may be used for ease of description to describe the relationship of an element or feature to another element or feature as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures were inverted, an element described as "under" or "under" or "below" or "at the bottom of" the other element or feature would then be oriented "above" or "on top" of the other element or feature. Thus, the term "under" can encompass both an orientation of above and below, depending on the context in which the term is used, as would be apparent to one of ordinary skill in the art. The materials may be otherwise oriented (eg, rotated 90 degrees, flipped, inverted) and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0018] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] As used herein, the term "configured" refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates the operation of one or more of the structures and devices in a predetermined manner.

[0020] As used herein, the phrase "coupled" refers to structures that are operably connected to one another, such as being electrically connected through a direct ohmic connection or through an indirect connection (e.g., via another structure).

[0021] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition meets some degree of variation, such as within an acceptable tolerance. By way of example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9% met, or even 100.0 percent met.

[0022] As used herein, "about" or "approximately" with respect to a numerical value for a particular parameter includes the numerical value, and the degree of variation from the numerical value that one of ordinary skill in the art would understand is within the acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value can include additional numerical values ​​in the range of 90.0 percent to 110.0 percent of the numerical value, such as in the range of 95.0 percent to 105.0 percent of the numerical value, in the range of 97.5 percent to 102.5 percent of the numerical value, in the range of 99.0 percent to 101.0 percent of the numerical value, in the range of 99.5 percent to 100.5 percent of the numerical value, or in the range of 99.9 percent to 100.1 percent of the numerical value.

[0023] 1A and 1B are respectively a simplified top view and a simplified partial cross-sectional view of a non-staircase region 105 of a microelectronic device structure 100 of a microelectronic device (e.g., a semiconductor device, a memory device such as a 3D NAND flash memory device) at an early processing stage of forming the microelectronic device. The non-staircase region 105 is outside of the array region 110 (FIGS. 2A-2C) and the staircase region 115 (FIGS. 3A and 3B) of the microelectronic device structure 100 according to disclosed embodiments. The non-staircase region 105 may be positioned proximal to an edge of the staircase region 115 and distal to the staircase structure of the staircase region 115. The microelectronic device structure 100 may include, for example, a portion of a memory device (e.g., a multi-deck 3D NAND flash memory device such as a dual-deck 3D NAND flash memory device).

[0024] The non-step region 105 of the microelectronic device structure 100 includes tiers 120 of alternating dielectric material 125 and nitride material 130, slits 135, sources 140, pillars 145, cell material 150, plug material 155, and corrosion inhibition features 160. The tiers 120 form a stack structure 165. One or more materials of the sources 140 in the non-step region 105 form tiers 120' of vertically alternating dielectric material 125 and conductive material 170 (see FIG. 7 ) and may be susceptible to corrosion during replacement of the nitride material 130 with the conductive material 170 during subsequent process operations (e.g., material removal operations, replacement gate process operations). The sources 140 are adjacent (e.g., above and vertically adjacent) to a base material (not shown), and the tiers 120 of alternating dielectric material 125 and nitride material 130 are adjacent (e.g., above and vertically adjacent) to the sources 140. The source 140 and the tier 120 extend in the x-direction. The slit 135 and the pillar 145 extend in the z-direction, with the cell material 150 surrounding the pillar 145 and the plug material 155 adjacent to (e.g., above) the pillar 145. The tier 120 and the source 140 are oriented perpendicular to the slit 135 and the pillar 145.

[0025] The source 140 and the slit 135 are illustrated in combination in a top view of FIG. 1A, with the slit 135 located above the source 140. The corrosion inhibition mechanism 160 is partially visualized in the perspective of FIG. 1A. In the non-step region 105 illustrated in FIG. 1A, adjacent portions of the source 140 are insulated (e.g., electrically isolated) from one another by the slit 135. The slit 135 forms a so-called "T-shape" in the x-direction and the y-direction, with adjacent portions of the source 140 being separated from one another by the slit 135. In the perspective of FIG. 1A, the slit 135 appears to be so-called "floating" in that the slit 135 does not appear to contact (e.g., connect) the source 140. However, the bridge 180 (FIG. 2A) of the source 140 interconnects adjacent portions of the source 140, as discussed below.

[0026] The slits 135 (e.g., trenches, openings) may extend vertically (e.g., in the Z direction) through the tiers 120 and into the source 140. The slits 135 may interrupt the horizontal continuity of the dielectric material 125 and the nitride material 130 of the tiers 120. The slits 135 may be high aspect ratio openings, such as having an aspect ratio in a range of about 10:1 to about 200:1. The aspect ratio of the slits 135 may depend on the number of tiers 120 in the microelectronic device structure 100. By way of example only, the microelectronic device structure 100 may have 10 or more tiers 120, 25 or more tiers 120, 50 or more tiers 120, 100 or more tiers 120, 150 or more tiers 120, or 200 or more tiers 120. The critical dimension (CD) (e.g., diameter) of the top of the slits 135 may be greater than the CD of the bottom of the slits 135. 1B, a first slit 135A extends through the tier 120 into the source 140, and a second slit 135B extends through the tier 120 to a top surface of the source 140. The slits 135A may expose one or more materials of the source 140 that are susceptible to corrosion (e.g., oxidation) during subsequent processing operations. Although FIG. 1B illustrates two slits 135 in the non-step region 105, there may be more than two slits 135.

[0027] The source 140 includes one or more conductive materials formed on a base material. The conductive materials are susceptible to corrosion (e.g., oxidation) during replacement gate process operations performed during the formation of the microelectronic device structure 100. The conductive materials may include, but are not limited to, polysilicon, tungsten silicide, cobalt silicide, nickel silicide, tungsten, other conductive materials, combinations thereof, or other conductive materials susceptible to corrosion. Although FIG. 1B illustrates the source 140 as including two vertically adjacent materials 140A, 140B, a single material or more than two materials may be used as the source 140. Although the disclosed embodiments illustrate the source 140 as including polysilicon 140B above tungsten silicide 140A, the source 140 may include other conductive materials susceptible to corrosion when replacement gate process operations are performed. In some embodiments, the source 140 includes polysilicon 140B above tungsten silicide 140A. The thickness of the source 140 may vary depending on the current and voltage requirements of the microelectronic device including the microelectronic device structure 100.

[0028] The dielectric material 125 of the tier 120 is a dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium dioxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ), and magnesium oxide (MgO x )), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )), and at least one dielectric carboxynitride material (e.g., silicon carboxynitride (SiO x Cz N y ))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) x , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C z N y ) represents a material that includes an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) to every atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because a formula represents relative atomic ratios and not a strict chemical structure, the dielectric material 125 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, where the values ​​of "x", "y", and "z" (if present) may be integers or non-integer. As used herein, the term "non-stoichiometric compounds" refers to and includes compounds that have elemental compositions that cannot be expressed in a clearly defined ratio of whole numbers and that defy the law of definite proportions. In some embodiments, the dielectric material 125 is formed of or includes silicon oxide (e.g., SiO2). The dielectric materials 125 of each of the tiers 120 of the stack structure 165 may each be substantially planar and each individually exhibit a desired thickness.

[0029] The nitride material 130 of the tier 120 is SiN y(e.g., Si3N4), and may include a dielectric nitride material. The nitride material 130 of the tier 120 is selectively etchable relative to the dielectric material 125 of the tier 120. As used herein, a material is "selectively etchable" relative to another material if the material exhibits an etch rate that is at least about 5 times greater than the etch rate of the other material, such as about 10 times greater, about 20 times greater, or about 40 times greater. The nitride materials 130 of each of the tiers 120 of the stack structure 165 may each be substantially planar and each individually exhibit a desired thickness. Materials other than dielectric nitride materials may be used, so long as the selected dielectric material exhibits a desired etch selectivity relative to the dielectric material 125.

[0030] The pillars 145, cell material 150, and plug material 155 may be formed of or include different materials. The pillars 145 extend through the tiers 120 of the non-step region 105 to the top surface of the source 140. The pillars 145 may provide one or more of mechanical support (e.g., structural support) or electrical coupling (e.g., electrical connection) within the microelectronic device structure 100, depending on the material used to form the pillars 145. In some embodiments, the pillars 145 are formed of a conductive material. In other embodiments, the pillars 145 are formed of a dielectric material. In yet other embodiments, the pillars 145 are formed of a channel material. The pillars 145 contact (e.g., physically contact, electrically connect) the top surface of the source 140. The conductive material of the pillars 145 may include, but is not limited to, one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), a conductively doped semiconductor material (e.g., conductively doped Si, conductively doped Ge, conductively doped SiGe).

[0031] The cell material 150 is present on the sidewalls of the pillars 145 between the pillars 145 and the tiers 120 and may be a dielectric material, a conductive material, or the like. The cell material 150 may include one or more of an oxide material, a storage material, a tunnel dielectric material, or a channel material known in the art. The cell material 150 substantially surrounds (e.g., substantially covers horizontally and vertically) each sidewall of the pillars 145. The plug material 155 is present on the top of the pillars 145 (e.g., above the pillars 145) and may be formed of a conductive material. The plug material 155 may be electrically connected to other conductive materials of the microelectronic device structure 100.

[0032] The corrosion-inhibiting feature 160 is present within (e.g., internal to) the source 140 and adjacent to one or more of the slits 135A in the non-step region 105 of the microelectronic device structure 100. As shown in FIG. 1B, the corrosion-inhibiting feature 160 is adjacent (e.g., laterally adjacent) to the slits 135A that extend into the source 140, but not adjacent to the slits 135B that do not extend into the source 140. The corrosion-inhibiting feature 160 may substantially surround the lower portion of the slit 135A (e.g., the portion of the slit 135A within the source 140) and may exhibit a height H that substantially corresponds to the thickness of the source 140. The upper and lower surfaces of the corrosion-inhibiting feature 160 may therefore be substantially coplanar with the upper and lower surfaces of the source 140. The corrosion-inhibiting feature 160 is disposed adjacent (e.g., laterally adjacent) to the portion of the slit 135A where corrosion occurs, such as the lower portion of the slit 135A. The corrosion inhibition feature 160 may extend from the top surface of the source 140 to the bottom surface of the source 140. Without being bound by any theory, it is believed that the corrosion inhibition feature 160 limits (e.g., inhibits) the corrosion 175 of the material in the source 140 to a smaller area than would occur in the absence of the corrosion inhibition feature 160. The corrosion inhibition feature 160 is formed of a dielectric material, such as a dielectric oxide material, that is not substantially removed during the replacement gate process action used to remove the nitride material 130 of the tier 120. In other words, the nitride material 130 of the tier 120 is selectively etchable relative to the material of the corrosion inhibition feature 160 and the dielectric material 125 of the tier 120. In some embodiments, the corrosion inhibition feature 160 is formed of a silicon oxide, such as silicon dioxide. However, other selectively etchable dielectric materials may also be used.

[0033] The dimensions of the corrosion inhibition features 160 may be selected based on the electric field and voltage requirements of the microelectronic device, including the microelectronic device structure 100. The height H of the corrosion inhibition features 160 may correspond to the thickness of the source 140, and the width W of the corrosion inhibition features 160 may be from about 20 nm to about 100 nm. By way of example only, the desired breakdown voltage of the microelectronic device may influence the dimensions of the corrosion inhibition features 160. Each of the corrosion inhibition features 160 in one or more of the non-staircase region 105, the staircase region 115, and the array region 110 may exhibit the same size or different sizes.

[0034] FIG 2A is a simplified top view of the array region 110 of the microelectronic device structure 100 at an initial processing stage, including slits 135 superimposed above the sources 140. FIG 2B and FIG 2C are simplified partial cross-sectional views of the array region 110 at an initial processing stage along lines AA and BB, respectively, of FIG 2A. In the array region 110, the alternating tiers 120 of dielectric material 125 and nitride material 130, slits 135, sources 140, pillars 145, cell material 150, plug material 155, and corrosion inhibition features 160 are as discussed above with reference to FIG 1A and FIG 1B. The array region 110 of the microelectronic device structure 100 differs from the non-step region 105 and the step region 115 in that so-called "bridges" 180 of the sources 140 interconnect adjacent portions of the sources 140, as shown in the perspective of FIG 2A. Adjacent portions of the source 140 are insulated from one another in the non-step region 105 ( FIG. 1A ) of the microelectronic device structure 100 by the corrosion inhibition mechanism 160, while portions of the source 140 in the array region 110 are connected to one another (e.g., electrically connected) by the bridge 180. The bridge 180 allows a voltage to be applied to the source 140 in the array region 110. No voltage is applied to the non-step region 105 and the step region 115, and thus the portions of the source 140 in these regions of the microelectronic device may be insulated from one another, such as by the corrosion inhibition mechanism 160. Without the bridge 180 in the array region 110, the portions of the source 140 would be substantially insulated from one another and from other components of the microelectronic device. The corrosion inhibition mechanism 160 in the source 140 insulates some portions of the source 140 from one another, while other portions of the source 140 are connected to one another by the bridge 180 in the array region 110. The bridges 180 therefore function to bypass the portions of the source 140 that are insulated by the corrosion inhibition mechanism 160. The desired spacing between adjacent bridges 180 may be determined by the resistance of the source 140 and the string current requirements of the microelectronic device.

[0035] As shown in FIG. 2B, the erosion suppression feature 160 is present in the array region 110 of the microelectronic device structure 100 adjacent to two slits 135A that extend into the source 140. The erosion suppression feature 160 substantially surrounds a lower portion of the slits 135A (e.g., the portion of the slits 135A in the source 140) and exhibits a height H. Although two slits 135A are shown in FIG. 2B, there may be additional slits 135A, and the erosion suppression feature 160 may be adjacent to (e.g., surround) the slits 135A. Although FIG. 2B illustrates the slits 135A as extending into the source 140 by the same amount, one or more of the slits 135A may extend into the source 140 by different distances. Although not illustrated in FIG. 2B for simplicity, the array region 110 also includes contact structures (not shown) at the bottom of the pillars 145 and proximate to the sources 140 to provide electrical coupling (e.g., electrical connection) to the sources 140.

[0036] As shown in the perspective of Figure 2C, the source 140, when viewed along line BB in Figure 2A, does not include the corrosion-inhibiting feature 160. Rather, the source 140 is substantially continuous and is not separated into segments by the corrosion-inhibiting feature 160.

[0037] 3A and 3B are simplified top and partial cross-sectional views, respectively, of the staircase region 115 of the microelectronic device structure 100 at an initial processing stage. In the staircase region 115, the alternating layers 120 of dielectric material 125 and nitride material 130, the slits 135, the source 140, and the corrosion inhibition features 160 are as discussed above with reference to FIGS. 1A and 1B. The staircase region 115 also includes support posts 185 that may provide one or more of mechanical support or electrical connection to a staircase structure (not shown) in the staircase region 115 of the microelectronic device structure 100. The staircase structure may be positioned in the center of the staircase region 115 and not proximate to the illustrated edges of the staircase region 115. The support posts 185 may be in physical contact or electrical contact with the source 140. The staircase region 115 includes steps (e.g., contact regions) defined by edges of the tiers 120 (not shown in the perspective of FIGS. 3A and 3B ). Contacts (not shown) may physically and electrically contact the steps in the staircase region 115 to provide electrical access to the source 140 of the microelectronic device structure 100.

[0038] The step region 115 of the microelectronic device structure 100 differs from the non-step region 105 in that the slits 135 of the step region 115 do not form a T-shape as shown in FIG. 3A , which includes slits 135 stacked above the sources 140. Instead, the slits 135 of the step region 115 run substantially parallel to one another. The step region 115 of the microelectronic device structure 100 also differs from the array region 110 in that there are no bridges 180 to connect adjacent portions of the sources 140. As discussed above, the bridges 180 of the sources 140 are only present in the array region 110.

[0039] As shown in FIG. 3B, the corrosion suppression features 160 are present in the step region 115 of the microelectronic device structure 100 adjacent to the four slits 135A that extend into the source 140. The corrosion suppression features 160 substantially surround the lower portions of the slits 135A and exhibit a height H. Although four slits 135A are shown in FIG. 3B, there may be a fewer number of slits 135A or a greater number of slits 135A, with the corrosion suppression features 160 adjacent to the slits 135A. Although FIG. 3B illustrates the slits 135A as extending into the source 140 by the same amount, one or more of the slits 135A may extend into the source 140 by a different distance.

[0040] To form the microelectronic device structure 100 shown in FIGS. 1A-3B, the source 140 is formed adjacent to (e.g., on) a base material (not shown) and patterned to form an opening (not shown) at a location where the corrosion inhibition feature 160 will ultimately be formed. The opening extends at least partially into the source 140. The source 140 may include one or more conductive materials formed adjacent to (e.g., on) the base material. The source 140 is formed and patterned by conventional techniques. The dielectric material (e.g., oxide material) of the corrosion inhibition feature 160 may be formed in the opening by conventional techniques, as shown in FIG. 4. The upper and lower surfaces of the corrosion inhibition feature 160 are substantially coplanar with the upper and lower surfaces of the source 140. The corrosion inhibition feature 160 is formed at a location of the source 140 proximate to the location of the slit 135 (e.g., 135A) that will ultimately be formed.

[0041] Alternating dielectric material 125 and nitride material 130 are then formed adjacent (e.g., over) source 140 by conventional techniques and patterned to form pillars 145, cell material 150, and plug material 155 in non-step region 105 and array region 110, with additional openings (not shown) in which pillars 185 are formed in step region 115. Step region 115 may also include fill material 190 between adjacent pillars 185. For simplicity, FIG. 4 includes non-step region 105, step region 115, and array region 110 combined in a single drawing, with the individual regions separated by vertical dashed lines. The patterning of tier 120, the formation of fill material 190, and the formation of pillars 145, cell material 150, plug material 155, and support posts 185 may be performed by conventional processes (e.g., conventional material deposition processes, conventional photolithography processes, conventional material removal processes) and conventional processing equipment, which will not be described in detail herein.

[0042] As shown in FIG. 5, slits 135 (e.g., 135A, 135B) are formed in the step region 115, array region 110, and non-step region 105 by exposing the tiers 120 and fill material 190 to a material removal process (e.g., an etch process) that removes portions of the alternating dielectric material 125 and nitride material 130 in the non-step region 105 and array region 110, as well as portions of the fill material 190 in the step region 115. Conventional etch chemistries may be used to form the slits. Etch conditions (e.g., etch chemistry, etch time) of the material removal process may be selected to remove desired portions of the tiers 120 and fill material 190 without substantially removing other exposed material. Some of the source 140, however, may be removed depending on the etch conditions used, extending one or more of the slits 135 into at least a portion of the source 140 to form one or more slits 135A. As discussed above, the erosion suppression feature 160 is disposed within the source 140 adjacent the slit 135A. The material removal process may form the slit 135 extending from the top tier 120 to the top surface of the source 140, and optionally over-etching into the source 140 occurs to form the slit 135A. Over-etching into one or more materials of the source 140 may occur due to differences in etch selectivity between materials of the microelectronic device structure 100 exposed to the etching conditions.

[0043] After forming the slits 135, 135A, the nitride material 130 of tier 120 may be removed, forming voids 195, as shown in FIG. 6, and replaced with conductive material 170, as shown in FIG. 7, to form tier 120' of vertically alternating dielectric material 125 and conductive material 170. The conductive material 170 of the tier 120′ of the stack structure 165 may be a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe and Ni-based alloy, or an Al-based alloy). The slit 135, 135A may be formed of or may include at least one conductive material such as gold, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low carbon steel, stainless steel), conductively doped semiconductor materials (e.g., conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)), conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), or combinations thereof. In some embodiments, the conductive material 170 is formed of or includes tungsten. The slit 135, 135A may also include a conductive material 170 extending from the top surface of the tier 120′ to the top surface of the source 140 or into the source 140. The conductive material 170 may eventually be removed from the slit 135, 135A and replaced with a dielectric.

[0044] Removal of the nitride material 130 and formation of the conductive material 170 in the voids 195 between adjacent dielectric materials 125 may be performed through the slits 135, 135A using a material removal process (e.g., a replacement gate process) selective to the nitride material 130. The replacement gate process operation removes the nitride material 130 and forms the voids 195, while other exposed materials such as the dielectric material 125, pillars 145, cell material 150, plug material 155, support posts 185, or fill material 190 are substantially unaffected by the etching conditions of the replacement gate process operation. During the replacement gate process operation, the support posts 185 may provide mechanical strength to the stack structures 165 in the staircase region 115, while the pillars 145 may provide mechanical strength to the stack structures 165 in the non-staircase region 105 and array region 110.

[0045] Depending on the material used as the source 140 and the etching conditions (e.g., etch chemistry, etch time) used to remove the nitride material 130, the source 140 in one or more of the step region 115, the array region 110, or the non-step region 105 may be subject to erosion 175. In some embodiments, erosion of the source 140 and the pillars 185 may occur in the step region 115, the array region 110, and the non-step region 105. The degree of erosion 175 in the source 140 may vary depending on the degree of overetching of material into the source 140. By way of example only, if the source 140 includes polysilicon 140B and tungsten silicide 140A, the replacement gate process action may include a wet etch process action in which the nitride material 130 is exposed to a phosphorus-based wet etch chemistry. The phosphorus-based wet etch chemistry may erode (e.g., oxidize) such material of the source 140 and extend the slit 135 into the material of one or more of the sources 140A, 140B. With the corrosion inhibition feature 160 adjacent the bottom of the slit 135A, any corrosion 175 occurring during the replacement gate process operation may be contained (e.g., confined) within a small region of the source 140 defined by the sidewalls of the corrosion inhibition feature 160. Because the slit 135A is surrounded by the corrosion inhibition feature 160, the corrosion 175 of the material of the source 140 does not propagate (e.g., diffuse) throughout the source 140. Undesirable effects of the corrosion 175 during use and operation of the microelectronic device are therefore confined to the region of the source 140 defined by the corrosion inhibition feature 160. Thus, performance characteristics of the microelectronic device, including the microelectronic device structure 100 according to the disclosed embodiments, may be maintained. A conductive material 170 may then be formed within the slit 135, 135A, and within the location previously occupied by the nitride material 130, forming the conductive material 170 of the tier 120′ in addition to filling the voids 195 with the conductive material 170.The conductive material 170 within the void 195 may function, for example, as an interconnect to electrically couple (e.g., electrically connect) the source 140 and additional components connected thereto (e.g., conductive interconnects, conductive routing structures) to other components of the microelectronic device including the microelectronic device structure 100 (e.g., additional components vertically above the stack structure 165).

[0046] Additional processing operations may then be performed by conventional techniques to form a microelectronic device including the microelectronic device structure 100. By way of example only, conductive structures such as access line structures (e.g., word line structures), select lines, and data lines (e.g., bit lines) may be formed above the stack structure 165 and electrically coupled (e.g., electrically connected) to the source 140. One or more additional microelectronic device structures (not shown) similar to the microelectronic device structure 100 may then be formed above the microelectronic device structure 100 to form a multi-deck memory device, such as a dual-deck 3D NAND flash memory device.

[0047] The corrosion inhibition features 160 according to the disclosed embodiments may be formed without adding time-consuming and costly process actions and without affecting the integrity of the microelectronic device. Because the corrosion inhibition features 160 are easily formed in the source 140 during the formation of the microelectronic device structure 100, the microelectronic device structure 100 according to the disclosed embodiments may be formed without extensive process modifications. For example, a photoresist material (not shown) already utilized in the formation of the microelectronic device structure 100 may be used to pattern the source 140 to form openings in which the corrosion inhibition features 160 will ultimately be formed. Therefore, there is little additional cost to produce the microelectronic device structure 100 according to the disclosed embodiments.

[0048] Additionally, by reducing the effects of corrosion 175 (e.g., lifting, arcing) on ​​microelectronic devices including the microelectronic device structure 100, the yield of microelectronic devices formed in accordance with disclosed embodiments may be increased as compared to the yield of conventional microelectronic devices in the absence of the corrosion inhibition mechanism 160. Illustratively, by reducing the degree of lifting of the tier 120', arcing may be reduced in microelectronic devices including the microelectronic device structure 100 in accordance with disclosed embodiments. Reducing the lifting of the tier 120' reduces any cross-contamination in the etch chemistry used in the replacement gate process as well as subsequent processes.

[0049] Accordingly, embodiments of a microelectronic device are disclosed that include a stack structure including a non-step region, a step region, and an array region. Each of the non-step region, the step region, and the array region includes tiers of alternating conductive and dielectric materials. One or more pillars are in the non-step region and in the array region, and one or more support posts are in the step region. A conductive material is in each of the non-step region, the step region, and the array region and extends vertically into a source adjacent the tiers. The source includes a corrosion inhibition feature in each of the non-step region, the step region, and the array region adjacent the conductive material in the source.

[0050] Thus, in another embodiment, a microelectronic device is disclosed that includes a stack structure including a non-staircase region, a staircase region, and an array region. Each of the non-staircase region, the staircase region, and the array region includes tiers of alternating conductive and dielectric materials. A source includes portions adjacent the stack structure and separated by a corrosion inhibition mechanism in the source. The source includes a bridge between adjacent portions of the source in the array region. Another conductive material extends vertically into the source from a top surface of the tiers.

[0051] Accordingly, an embodiment of a method of forming a microelectronic device is disclosed. The method includes forming a source including a corrosion inhibition feature therein. Tiers of alternating nitride and dielectric material are formed adjacent to the source. One or more slits are formed extending from an uppermost one of the tiers into the source. The corrosion inhibition feature is adjacent to the one or more slits in the source. Nitride material of the tiers is removed through the one or more slits to form voids between adjacent dielectric material of the tiers. A conductive material is formed in the voids and in the slits.

[0052] 8 illustrates a partial cross-sectional perspective view of a portion of a microelectronic device 800 (e.g., a memory device such as a dual deck 3D NAND flash memory device) including a microelectronic device structure 100 according to an embodiment of the disclosure. The microelectronic device structure 100 may be substantially similar to the microelectronic device structures 100 previously described with reference to FIGS. 1-7. For example, as shown in FIG. 8, the microelectronic device structure 100 may include a stack structure 802 including tiers 808 of conductive material 170 and dielectric material 125, a staircase structure 810 having a step 812 defined by an edge of the tier 808, a conductive contact structure 814 electrically connected to the step 812 of the staircase structure 810, a source 140 vertically below the stack structure 802, and a conductive pillar structure 824 extending vertically through the stack structure 802 to the source 140. The stack structure 802, tier 808, and source 140 may be substantially similar to the stack structure 165, tier 120, and source 140, respectively, previously described with reference to Figures 1A-7. The staircase structure 802, step 812, and conductive contact structure 814 may be formed by conventional techniques.

[0053] 8, the microelectronic device 800 may further include strings 830 of memory cells 832 vertically coupled to one another in series, data lines 834 (e.g., bit lines), access lines 836, and select lines 838. The strings 830 of memory cells 832 extend vertically orthogonal to the conductive lines and tiers of the microelectronic device 800 (e.g., data lines 834, source 140, tiers 808 of the stack structure 802, access lines 836, select lines 838), and conductive contact structures 814 may electrically couple the components to one another (e.g., access lines 836 and select lines 838 to tiers 808 of the stack structure 802 of the microelectronic device 800) as shown.

[0054] 8, the microelectronic device 800 may also include a control unit 840 (e.g., a control device) positioned vertically below the string 830 of memory cells 832, which may include one or more of string driver circuitry, pass gates, circuitry for selecting gates, circuitry for selecting conductive lines (e.g., data line 834, access line 836, select line 838, additional data line, additional access line, additional select line), circuitry for amplifying signals, and circuitry for sensing signals. In some embodiments, the control unit 840 is positioned at least partially (e.g., substantially) within the horizontal boundaries (e.g., in the X-direction and Y-direction) of the horizontal area occupied by the string 830 of memory cells 832. The control unit 840 may be electrically coupled to, for example, the data line 834, the source 140, the access line 836, and the select line 838. In some embodiments, the control unit 840 includes CMOS (complementary metal oxide semiconductor) circuitry. In such an embodiment, the control unit 840 may be characterized as having a "CMOS under array" ("CuA") configuration.

[0055] Microelectronic device structures (e.g., the microelectronic device structure 100 described with reference to FIGS. 1-7) and microelectronic devices (e.g., the microelectronic device 800 previously described with reference to FIG. 8) according to disclosed embodiments may be used in electronic systems according to disclosed embodiments. FIG. 9 is a block diagram of an exemplary electronic system 900 according to disclosed embodiments. The electronic system 900 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a mobile phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet, such as an iPad® or a SURFACE® tablet, an e-book, a navigation device, and the like. The electronic system 900 includes at least one memory device 902. The memory device 902 may include, for example, one or more embodiments of the microelectronic device structures (e.g., the microelectronic device structure 100 described with reference to FIGS. 1-7) and microelectronic devices (e.g., the microelectronic device 800 described with reference to FIG. 8) previously described herein. The electronic system 900 may further include at least one electronic signal processor device 904 (often referred to as a "microprocessor"). The electronic signal processor device 904 may optionally include one or more embodiments of a microelectronic device structure (e.g., the microelectronic device structure 100 described with reference to FIGS. 1-7) and a microelectronic device (e.g., the microelectronic device 800 described with reference to FIG. 8). Although the memory device 902 and the electronic signal processor device 904 are depicted in FIG. 9 as two (2) separate devices, in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of the memory device 902 and the electronic signal processor device 904 is included within the electronic system 900.In such an embodiment, the memory / processor device may include one or more of the microelectronic device structures (e.g., the microelectronic device structure 100 described with reference to FIGS. 1-7) and microelectronic devices (e.g., the microelectronic device 800 described with reference to FIG. 8) previously described herein. The electronic system 900 may further include one or more input devices 906 for inputting information into the electronic system 900 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 900 may further include one or more output devices 908 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, a display, a printer, an audio output jack, and a speaker. In some embodiments, the input device 906 and the output device 908 may include a single touch screen device that may be used to both input information into the electronic system 900 and output visual information to a user. The input device 906 and the output device 908 may be in electrical communication with one or more of the memory device 902 and the electronic signal processor device 904 .

[0056] Accordingly, an embodiment of an electronic system is disclosed, comprising an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes at least one microelectronic device including a stack structure including tiers of alternating conductive and dielectric materials in a non-step region, a step region, and an array region. A source includes a portion adjacent the stack structure and separated by a corrosion inhibition feature. Top surfaces of the source and the corrosion inhibition feature are substantially coplanar with one another. Another conductive material extends vertically from a top surface of the tiers into the source.

[0057] Additional non-limiting exemplary embodiments of the disclosure are described below.

[0058] Embodiment 1. A microelectronic device comprising: a stack structure including a non-staircase region, a staircase region, and an array region, each of the non-staircase region, the staircase region, and the array region including tiers of alternating conductive and dielectric material; one or more pillars in the non-staircase region and in the array region; one or more support posts in the staircase region; and a conductive material in each of the non-staircase region, the staircase region, and the array region extending vertically into a source adjacent the tiers, the source including a corrosion inhibition feature adjacent the conductive material in the source in each of the non-staircase region, the staircase region, and the array region.

[0059] Embodiment 2. The microelectronic device of embodiment 1, wherein the source comprises tungsten silicide adjacent to the base material and polysilicon adjacent to the tungsten silicide.

[0060] Embodiment 3. The microelectronic device of embodiment 1 or embodiment 2, wherein the conductive material extends vertically from the top surface of the tier into the top of the source.

[0061] Embodiment 4. The microelectronic device of embodiment 1 or embodiment 2, wherein the conductive material extends vertically from the top surface of the tier into the bottom of the source.

[0062] Embodiment 5. The microelectronic device of any one of embodiments 1 to 4, wherein the corrosion-inhibiting mechanism comprises a dielectric material.

[0063] Embodiment 6. A microelectronic device according to any one of embodiments 1 to 5, wherein the corrosion inhibition mechanism comprises a silicon oxide material.

[0064] Embodiment 7. The microelectronic device of any one of embodiments 1 to 6, wherein the corrosion inhibition mechanism laterally surrounds the conductive material in the source.

[0065] Embodiment 8. The microelectronic device of any one of embodiments 1 to 7, wherein the height of the corrosion-inhibiting feature is substantially the same as the thickness of the source.

[0066] Embodiment 9. A microelectronic device according to any one of embodiments 1 to 8, wherein the source and the pillar are electrically connected in the step region and in the non-step region.

[0067] Embodiment 10. A microelectronic device according to any one of embodiments 1 to 9, wherein adjacent portions of the source in the array region are electrically connected by a bridge.

[0068] Embodiment 11. A microelectronic device described in any one of embodiments 1 to 10, wherein adjacent portions of the source in the non-step region are electrically insulated from each other.

[0069] Embodiment 12. A microelectronic device comprising: a stack structure including a non-staircase region, a staircase region, and an array region, each of which includes tiers of alternating conductive and dielectric material; a source adjacent the stack structure and including portions separated by a corrosion inhibition mechanism in the source, the source including a bridge between adjacent portions of the source in the array region; and another conductive material extending vertically into the source from an upper surface of the tiers.

[0070] Embodiment 13. The microelectronic device of embodiment 12, wherein only the array region includes a bridge between adjacent portions of the source.

[0071] Embodiment 14. A microelectronic device as described in embodiment 12 or embodiment 13, wherein the corrosion inhibition mechanism is laterally adjacent to another conductive material in the source.

[0072] Embodiment 15. A microelectronic device according to any one of embodiments 12 to 14, wherein the corrosion inhibition mechanism is configured to electrically insulate portions of the source from the non-step region and the step region.

[0073] Embodiment 16. An electronic system including an input device, an output device, a processor device operably coupled to the input device and the output device, a stack structure operably coupled to the processor device and including tiers of alternating conductive and dielectric material in non-staircase regions, staircase regions, and array regions, and a memory device including at least one microelectronic device including a source adjacent the stack structure and including a portion separated by a corrosion inhibition feature, wherein top surfaces of the source and the corrosion inhibition feature are substantially coplanar with each other, and another conductive material extending vertically from the top surface of the tier into the source.

[0074] Embodiment 17. A method of forming a microelectronic device comprising forming a source including a corrosion inhibition feature therein; forming tiers of alternating nitride and dielectric material adjacent the source; and forming one or more slits extending from a topmost one of the tiers into the source, the corrosion inhibition feature being adjacent to the one or more slits in the source; removing nitride material of the tiers through the one or more slits to form voids between adjacent dielectric material of the tiers; and forming a conductive material in the voids and in the slits.

[0075] Embodiment 18. The method of embodiment 17, wherein forming a source including a corrosion-inhibiting mechanism therein comprises patterning the source and forming a dielectric material in openings between portions of the source.

[0076] Embodiment 19. The method of embodiment 17 or embodiment 18, wherein forming one or more slits extending from an uppermost one of the tiers into the source includes forming one or more slits extending into a lower portion of the source.

[0077] Embodiment 20. The method of embodiment 17 or embodiment 18, wherein forming one or more slits extending from an uppermost one of the tiers into the source includes forming one or more slits extending into an upper portion of the source.

[0078] Embodiment 21. A method as described in any one of embodiments 1 to 20, wherein forming one or more slits extending from a topmost one of the tiers into the source includes forming one or more slits in one or more of a non-staircase region, a staircase region, or an array region of the microelectronic device.

[0079] Embodiment 22. The method of any one of embodiments 1 to 21, wherein forming one or more slits extending from an uppermost one of the tiers into the source includes forming one or more slits that include a wider diameter at an upper portion of the one or more slits and a narrower diameter at a lower portion of the one or more slits.

[0080] Embodiment 23. The method of any one of embodiments 1 to 22, wherein forming one or more slits extending from an uppermost one of the tiers into the source includes forming a portion of the one or more slits laterally adjacent a corrosion inhibition feature in the source.

[0081] Embodiment 24. The method of any one of embodiments 1 to 23, wherein removing nitride material of the tier through the one or more slits includes extending the one or more slits further into the source.

[0082] Embodiment 25. The method of any one of embodiments 1 to 24, wherein forming a conductive material in the voids and in the slits includes forming a conductive material surrounded by a corrosion-inhibiting mechanism in the source.

[0083] While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. The disclosure is not, however, limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives that come within the scope of the following appended claims and their legal equivalents.

Claims

[Claim 1] a stack structure including a non-staircase region, an array region, and a staircase region sandwiched laterally between the non-staircase region and the array region, the non-staircase region, the staircase region, and the array region each including tiers of alternating conductive and dielectric material; one or more pillars in the non-staircase region and in the array region; one or more columns in the staircase region; a source including a conductive portion adjacent to the stack structure; a corrosion inhibition feature laterally adjacent the conductive portion of the source within each of the non-step region, the step region, and the array region; a dielectric filled slit in each of the non-step region, the step region, and the array region, the dielectric filled slit extending vertically into the conductive portion of the source, the dielectric filled slit laterally adjacent the corrosion inhibition feature; Microelectronic devices including:

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